Dual transistor capacitorless dynamic random access memory and method of manufacturing the same

Abstract

The application discloses a dual-transistor capacitorless dynamic random access memory, which integrates a long retention time storage array composed of a plurality of first type 2T0C storage units and a short retention time storage array composed of a plurality of second type 2T0C storage units with significantly different charge retention times on the same chip, and has a dual-mode storage array with differentiated charge retention times, which can provide reliable core device support for realizing the multi-functional cooperation of safety, calculation and storage on the same hardware platform. The application also discloses a manufacturing method of the dual-transistor capacitorless dynamic random access memory, wherein a simple selective plasma process is used to process the write transistors of part of the storage units in a specified area, so that the systematic shortening of the charge retention time of part of the storage units in the specified area is realized, and the method has high control precision, good repeatability, simple process and good compatibility.

Description

Technical Field

[0001] This invention relates to integrated circuit technology, specifically to a dual-transistor capacitorless dynamic random access memory and its manufacturing method. Background Technology

[0002] Conventional Dynamic Random Access Memory (DRAM) storage cells, such as Figure 1 As shown, the memory cell structure of a 1T1C (1 Transistor 1 Capacitor) DRAM consists of a single transistor and a single capacitor. With the continuous development of memory products towards higher capacity and higher density, the number of capacitors in conventional DRAM memory arrays has increased dramatically, making it difficult to further shrink the process size.

[0003] The 2T0C (2 Transistor 0 Capacitor) DRAM (Dynamic Random Access Memory) cell architecture avoids the presence of capacitors in the memory cell, overcoming a series of problems that arise when scaling up the process size of conventional DRAM memory cells. A typical 2T0C DRAM memory cell is shown below. Figure 2 As shown, it consists of two transistors (one write transistor and one read transistor) without independent capacitors. Data is stored as charge in the gate capacitance of the read transistor, and read and write operations are achieved by controlling the gate voltage of the read transistor. The 2T0C DRAM has a simple memory cell structure and inherent physical randomness, making it an ideal candidate for applications such as physically unclonable functions and neuromorphic computing.

[0004] The charge retention time of 2T0C DRAM cells is typically determined by the materials and manufacturing process. Existing 2T0C DRAM manufacturing methods cannot systematically and selectively control the charge retention characteristics of specific regions of 2T0C DRAM cells in back-end or mid-end processes. This makes it impossible to achieve precise and controllable differentiation of the charge retention time of different 2T0C DRAM cells on a single chip, thus limiting the realization of multifunctional integrated architectures based on retention time differences.

[0005] With the development of the Internet of Things (IoT) and edge computing, the demand for hardware primitives is increasing, with a growing expectation that single hardware components can integrate multiple functions such as security, computing, and storage. Two-dimensional semiconductor materials (such as MoS2 and black phosphorus) exhibit great potential in constructing novel electronic devices due to their atomic-level thickness, excellent electrostatic controllability, and high mobility, making them ideal channel materials for 2TOCDRAM, which can further improve performance and integration. For example, hybrid-gate 2TOCDRAM based on monolayer MoS2 can achieve a hold time of over 100 seconds and an ultra-low write voltage of 0.2V. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a dual-transistor capacitorless (2T0C) dynamic random access memory (DRAM) and its manufacturing method, which systematically shortens the charge retention time of some memory cells in a specified area, and has a simple process and good compatibility.

[0007] To solve the above-mentioned technical problems, the present invention provides a dual-transistor capacitorless dynamic random access memory, which includes a plurality of first-type 2T0C memory cells and a plurality of second-type 2T0C memory cells integrated on a single chip. The 2T0C memory cell consists of one write transistor and one read transistor; The write transistor has its gate connected to the write word line, one end of its source and drain connected to the write bit line, and the other end connected to the gate of the read transistor and used as a storage node. The read transistor has one end of its source and drain connected to the read bit line and the other end connected to the read word line. The first type of 2T0C memory cell has a first average charge retention time; The second type of 2T0C memory cell has a second average charge retention time; The second average charge retention time is less than 1 / 10 of the first average charge retention time; Multiple Type I 2T0C memory cells form a long-retention time memory array; Multiple Type II 2T0C memory cells form a short hold time memory array.

[0008] Preferably, both the write transistor and the read transistor are N-channel transistors; The write transistor has its source connected to the write bit line and its drain connected to the gate of the read transistor. The read transistor has its source terminal connected to the read bit line and its drain terminal connected to the read word line.

[0009] Preferably, the off-state leakage current of the write transistor of the second type of 2T0C memory cell is higher than the off-state leakage current of the write transistor of the first type of 2T0C memory cell.

[0010] Preferably, the off-state leakage current of the write transistor of the second type 2T0C memory cell is 4 to 5 times the off-state leakage current of the write transistor of the first type 2T0C memory cell.

[0011] Preferably, the standard deviation of the threshold voltage distribution of the write transistor of the second type 2T0C memory cell is greater than the standard deviation of the threshold voltage distribution of the write transistor of the first type 2T0C memory cell.

[0012] Preferably, the channel of the transistor in the 2T0C memory cell is a two-dimensional semiconductor; The channel two-dimensional semiconductor of the write transistor in the second type of 2T0C memory cell has more defects than the channel two-dimensional semiconductor of the write transistor in the first type of 2T0C memory cell.

[0013] Preferably, the output current of the second type 2T0C memory cell in the subthreshold region has more significant periodic to periodic random fluctuations than the output current of the first type 2T0C memory cell in the subthreshold region.

[0014] Preferably, the two-dimensional semiconductor material is a transition metal sulfide; The defects in the channel two-dimensional semiconductor are sulfur vacancies.

[0015] Preferably, the two-dimensional semiconductor material is MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, GeS2, GeSe2, GeTe2, SnS2, SnSe2, SnTe2, SnO, PbS2, PbSe2, PbTe2, GaS, GaSe, GaTe, InS, InSe, InTe, graphene, black phosphorus, arsenene, antimonene, germanene, tinene, or silene.

[0016] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing the dual-transistor capacitor-free dynamic random access memory, comprising the following steps: S1. Forming a two-dimensional semiconductor layer on a substrate; S2. The two-dimensional semiconductor layer is etched according to the dimensions of the write transistor and read transistor of the 2T0C memory cell to form a two-dimensional semiconductor channel region for at least four 2T0C memory cell transistors; S3. Implement a selective plasma processing process to perform plasma processing on the two-dimensional semiconductor of the channel region of the write transistor of a portion of the 2T0C memory cells in a designated area, thereby controllingly introducing defects on the surface of the two-dimensional semiconductor of the channel region. The two-dimensional semiconductor of the channel region of the write transistor of a portion of the 2T0C memory cells in a non-designated area is not subjected to plasma processing. This results in more defects in the two-dimensional semiconductor of the channel region of the write transistor of the 2T0C memory cells in the designated area than in the non-designated area, thus systematically increasing the off-state leakage current of the write transistor of the 2T0C memory cells in the designated area, thereby shortening its charge retention time. The 2T0C memory cells in the designated area are designated as second-type 2T0C memory cells, and the 2T0C memory cells in the non-designated area are designated as first-type 2T0C memory cells. S4. Proceed with subsequent processes to form a dual-mode dual-transistor capacitor-free dynamic random access memory with a long hold time memory array and a short hold time memory array.

[0017] Preferably, in step S1, an insulating dielectric layer is formed on the substrate, and the two-dimensional semiconductor layer is formed on the insulating dielectric layer.

[0018] Preferably, after step S1, a source-drain contact layer is formed on the two-dimensional semiconductor layer in the region where the source and drain electrodes of the write transistor and read transistor of the 2TOC memory cell are located, and then step S2 is performed.

[0019] Preferably, in step S4, the subsequent processes include depositing a seed layer, depositing a gate dielectric layer, depositing a top gate electrode layer, etching and filling vias, and depositing interconnect metal to form the source, drain, and gate electrodes of the transistors of each 2T0C memory cell.

[0020] Preferably, the top gate electrode layer of the write transistor is gold deposited by electron beam physical vapor deposition, the top gate electrode layer of the read transistor is aluminum deposited by electron beam physical vapor deposition, and the gate dielectric layer is aluminum oxide deposited by atomic layer deposition.

[0021] Preferably, the plasma is O2 plasma; The two-dimensional semiconductor is MoS2.

[0022] Preferably, the processing power, processing time, and distance from the channel region of the two-dimensional semiconductor of the write transistor in a portion of the designated 2T0C memory cell to the plasma ignition location of the selective plasma processing process are all related to the defect density to be increased.

[0023] Preferably, the selective plasma processing is carried out in an oxygen atmosphere with a gas flow rate of 50 sccm, a power range of 40W to 60W, and a processing time of 20 to 40 seconds. The plasma is ignited in a quartz tube and transported by gas flow to the channel region of the write transistor of a portion of the 2T0C memory cell in the designated area to be processed at a distance of 20 to 50 cm from the ignition position.

[0024] Preferably, in step S1, a MoS2 thin film is grown on the substrate using chemical vapor deposition. In step S2, a two-dimensional semiconductor channel region of at least four 2T0C memory cells is formed by dry etching and patterning.

[0025] Preferably, in step S3, photoresist is used to protect the non-designated area, exposing the channel region of the two-dimensional semiconductor of the write transistor of a portion of the 2T0C memory cell in the designated area; plasma treatment is performed for 30 seconds in a reactive ion etching apparatus under an oxygen atmosphere and a power of 50W.

[0026] The dual-transistor capacitorless (2T0C) dynamic random access memory (DRAM) of the present invention integrates a long-hold-time memory array composed of multiple first-type 2T0C memory cells and a short-hold-time memory array composed of multiple second-type 2T0C memory cells on the same chip. The dual-mode memory array with differentiated charge hold-time can provide reliable core device support for realizing multi-functional collaboration of security, computing and storage on the same hardware platform.

[0027] The manufacturing method of the dual-transistor capacitorless (2T0C) dynamic random access memory (DRAM) of the present invention uses a simple selective plasma process to process the write transistors of a portion of the memory cells in a specified area, thereby systematically shortening the charge retention time of the portion of the memory cells in the specified area. This method has high control precision, good repeatability, and is simple and compatible. It is easy to integrate into the standard two-dimensional device fabrication process without introducing complex additional steps, and has good manufacturability. Attached Figure Description

[0028] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a typical 1T1C memory cell circuit diagram; Figure 2 This is a typical 2T0C memory cell circuit diagram; Figure 3 This is a circuit structure diagram of an embodiment of the 2TOC DRAM of the present invention; Figure 4 This is a cross-sectional view of the formation of a two-dimensional semiconductor layer according to an embodiment of the manufacturing method of the 2TOC DRAM of the present invention; Figure 5 This is a cross-sectional view of the formation of the source / drain contact layer in an embodiment of the manufacturing method of the 2TOC DRAM of the present invention; Figure 6 This is a cross-sectional view of a two-dimensional semiconductor layer etched to form a channel region, according to an embodiment of the manufacturing method of the 2TOC DRAM of the present invention. Figure 7 This is a cross-sectional view of the two-dimensional semiconductor channel region of the write transistor of a portion of the 2TOC memory cell in a designated area, as an embodiment of the manufacturing method of the 2TOC DRAM of the present invention, showing plasma processing.

[0030] Explanation of reference numerals in the attached figures 11 Substrate; 12 Insulating dielectric layer; 13 Two-dimensional semiconductor layer; 130 Two-dimensional semiconductor in the channel region; 14 Source / drain contact layer; T1 Write transistor; T2 Read transistor; WWL Write word line; WBL Write bit line; SN Memory node; RBL Read bit line; RWL Read word line. Detailed Implementation

[0031] The technical solutions of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0032] Example 1: A dual-transistor capacitor-free (2T0C) dynamic random access memory (DRAM) includes multiple first-type 2T0C memory cells and multiple second-type 2T0C memory cells integrated on a single chip, such as... Figure 3 As shown ( Figure 3 The image shows a first-type 2T0C memory cell and a second-type 2T0C memory cell. The 2T0C memory cell consists of a write transistor T1 and a read transistor T2; The write transistor T1 has its gate connected to the write word line WWL, one end of its source and drain connected to the write bit line WBL, and the other end connected to the gate of the read transistor T2 and used as the storage node SN. The read transistor T2 has one end of its source and drain connected to the read bit line RBL and the other end connected to the read word line RWL. The first type of 2T0C memory cell has a first average charge retention time; The second type of 2T0C memory cell has a second average charge retention time; The second average charge retention time is less than 1 / 10 of the first average charge retention time; Multiple Type I 2T0C memory cells form a long-retention time memory array; Multiple Type II 2T0C memory cells form a short hold time memory array.

[0033] Preferably, both the write transistor T1 and the read transistor T2 are N-channel transistors; The write transistor T1 has its source connected to the write bit line WBL and its drain connected to the gate of the read transistor T2. The read transistor T2 has its source terminal connected to the read bit line RBL and its drain terminal connected to the read word line RWL.

[0034] Preferably, the off-state leakage current of the write transistor T1 of the second type 2T0C memory cell is higher than the off-state leakage current of the write transistor T1 of the first type 2T0C memory cell.

[0035] Preferably, the off-state leakage current of the write transistor of the second type 2T0C memory cell is 4 to 5 times the off-state leakage current of the write transistor of the first type 2T0C memory cell.

[0036] Preferably, the standard deviation of the threshold voltage distribution of the write transistor of the second type 2T0C memory cell is greater than the standard deviation of the threshold voltage distribution of the write transistor of the first type 2T0C memory cell.

[0037] The dual-transistor capacitorless (2T0C) dynamic random access memory (DRAM) of Embodiment 1 integrates a long-hold-time memory array composed of multiple first-type 2T0C memory cells and a short-hold-time memory array composed of multiple second-type 2T0C memory cells on the same chip. The dual-mode memory array with differentiated charge hold-time can provide reliable core device support for realizing multi-functional collaboration of security, computing and storage on the same hardware platform.

[0038] Example 2: A dual-transistor capacitorless (2T0C) dynamic random access memory (DRAM) based on Example 1, wherein the channel of the transistor in the 2T0C memory cell is a two-dimensional semiconductor; The channel two-dimensional semiconductor of the write transistor T1 of the second type 2T0C memory cell has more defects than the channel two-dimensional semiconductor of the write transistor T1 of the first type 2T0C memory cell.

[0039] Preferably, the two-dimensional semiconductor material is a transition metal sulfide (TMD). The defects in the channel two-dimensional semiconductor are sulfur vacancies.

[0040] Preferably, the two-dimensional semiconductor material is MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, GeS2, GeSe2, GeTe2, SnS2, SnSe2, SnTe2, SnO, PbS2, PbSe2, PbTe2, GaS, GaSe, GaTe, InS, InSe, InTe, graphene, black phosphorus, arsenene, antimonene, germanene, tinene, or silene, etc.

[0041] The second type of 2TOC memory cell exhibits more significant cycle-to-cycle (C2C) random fluctuations in its subthreshold output current compared to the first type of 2TOC memory cell. Cycle-to-cycle (C2C) random fluctuations refer to the unpredictable, non-repetitive random fluctuations in the output electrical parameters (such as subthreshold read current) of the same device under identical operating conditions (same programming voltage, timing, and environment) during multiple consecutive write-hold-read cycles. These fluctuations originate from dynamic microscopic processes such as the random capture / release of charge traps and the random activation of defect states within the device. The C2C fluctuations are significantly enhanced in the second type of 2TOC memory cell (SRA) after plasma treatment due to the introduction of more defect states into its channel. Specifically, during subthreshold readout, the period-to-period fluctuation amplitude (standard deviation) of the output current is significantly increased compared to the first type 2T0C memory cell (LRA). Based on the principle of plasma processing enhancing low-frequency noise (1 / f noise), the noise power spectral density of the second type 2T0C memory cell is increased by 5 times compared to the first type, and the amplitude of C2C fluctuations also increases accordingly. Therefore, it can be qualitatively described that the C2C fluctuation amplitude of the output current of the second type 2T0C memory cell is more significant than that of the first type, and the proportion of its fluctuation magnitude is related to the enhancement factor of low-frequency noise.

[0042] Example 3: A method for manufacturing a dual-transistor capacitor-free (2T0C) dynamic random access memory (DRAM) according to Example 2, comprising the following steps: S1. A two-dimensional semiconductor layer 13 is formed on the substrate 11, such as Figure 4 As shown; S2. The two-dimensional semiconductor layer 13 is etched according to the dimensions of the write transistor T1 and read transistor T2 of the 2T0C memory cell to form the channel region of the two-dimensional semiconductor 130 of at least four 2T0C memory cell transistors, such as... Figure 6 As shown; S3. For example Figure 7 As shown, a selective plasma processing technology is implemented to perform plasma processing on the two-dimensional semiconductor 130 of the channel region of the write transistor of a portion of the 2T0C memory cells in a designated area. Defects are controlled to be introduced on the surface of the two-dimensional semiconductor 130 of the channel region of the processed two-dimensional semiconductor 130. The two-dimensional semiconductor 130 of the channel region of the write transistor of the non-designated area of ​​the 2T0C memory cells is not subjected to plasma processing. This results in more defects in the two-dimensional semiconductor 130 of the channel region of the write transistor of the 2T0C memory cells in the designated area than in the two-dimensional semiconductor 130 of the channel region of the write transistor of the non-designated area of ​​the 2T0C memory cells. This systematically increases the off-state leakage current of the write transistor of the 2T0C memory cells in the designated area, thereby shortening its charge retention time. The 2T0C memory cells in the designated area are designated as second-type 2T0C memory cells, and the 2T0C memory cells in the non-designated area are designated as first-type 2T0C memory cells. S4. Proceed with subsequent processes to form a dual-mode dual-transistor capacitor-free dynamic random access memory with a long hold time memory array and a short hold time memory array.

[0043] Selective plasma treatment introduces defects into the surface of the treated two-dimensional semiconductor channel through physical bombardment and chemical reactions. These defects form defect states within the band gap of the two-dimensional semiconductor material, serving as efficient carrier tunneling paths. When the write transistor (T1) is in the off state (negative gate voltage), the charge on the storage node SN leaks through the tunneling paths formed by these defect states, thereby systematically increasing the off-state leakage current Ioff. This process is controllable, thus enabling a systematic reduction in charge retention time.

[0044] The manufacturing method of the dual-transistor capacitorless (2T0C) dynamic random access memory (DRAM) in Example 3 produces a 2T0C DRAM that includes a long hold time memory cell array and a short hold time memory cell array. The long hold time memory array is composed of 2T0C memory cells that have not undergone plasma treatment, while the short hold time memory array is composed of 2T0C memory cells that have undergone plasma treatment. This allows for the integration of 2T0C memory cell arrays with significantly different hold times and different randomness characteristics on the same chip.

[0045] The manufacturing method of the dual-transistor capacitorless (2T0C) dynamic random access memory (DRAM) in Example 3 involves performing a selective plasma processing process on the basic memory cell of the two-dimensional semiconductor-based dual-transistor capacitorless (2T0C) DRAM. This process precisely targets the write transistor of a specific basic memory cell, systematically increasing its off-state leakage current without significantly altering the average threshold voltage of the write transistor. This achieves a precise and controllable reduction in the charge retention time of the write transistor for the specified basic memory cell. Simultaneously, this selective plasma processing effectively introduces additional threshold voltage and transconductance random fluctuations, and enhances the low-frequency noise characteristics of the device.

[0046] The manufacturing method of the dual-transistor capacitorless (2T0C) dynamic random access memory (DRAM) in Example 3 uses a simple selective plasma process to process the write transistors of a portion of the memory cells in a specified area, thereby systematically shortening the charge retention time of the specified memory cells. This method has high control precision, good repeatability, and is simple and compatible, making it easy to integrate into standard two-dimensional device fabrication processes without introducing complex additional steps, thus exhibiting good manufacturability.

[0047] Example 4: A method for manufacturing a dual-transistor capacitor-free (2T0C) dynamic random access memory (DRAM) based on Example 3. The plasma is O2 plasma; The two-dimensional semiconductor is MoS2; The defect is a sulfur vacancy.

[0048] Preferably, the processing power, processing time, and distance from the channel region of the two-dimensional semiconductor 130 of the write transistor in a portion of the designated 2T0C memory cell to the plasma ignition location of the selective plasma processing process are related to the defect density to be increased.

[0049] Preferably, the processing power, processing time, and distance from the substrate containing multiple two-dimensional semiconductor 2TOC DRAM memory cells to the plasma ignition location in the selective plasma processing process are all related to the defect density to be increased.

[0050] Example 5: A method for manufacturing a dual-transistor capacitorless (2T0C) dynamic random access memory (DRAM) based on Example 3, wherein the selective plasma processing is performed in an oxygen atmosphere, the gas flow rate is 50 sccm, the power range is 40W to 60W (e.g., 50W), and the processing time is 20 seconds to 40 seconds (e.g., 30 seconds). The plasma is ignited in a quartz tube and transported by gas flow to the channel region of the two-dimensional semiconductor 130 of the write transistor of a portion of the designated area of ​​the 2T0C memory cell on the sample stage 20 to 50 cm away from the ignition position.

[0051] The process conditions (lower power, shorter duration) are sufficient to introduce randomly distributed micro-defects (such as sulfur vacancies) on the surface of the two-dimensional semiconductor. These defects mainly act as charge scattering centers and sources of random local potential fluctuations. They do not systematically and consistently change the average carrier concentration or gate control capability of the entire channel, thus maintaining the average threshold voltage (Vth) of the device. However, these randomly distributed defects significantly exacerbate the inherent process variations in device-to-device (D2D) critical parameters (such as local electric field and mobility), leading to enhanced random fluctuations in the threshold voltage of the processed write transistor group, manifested as an increase in the standard deviation (σ) of the statistical distribution. In addition, the defects introduced by this process (such as sulfur vacancies) act as additional carrier scattering centers and random telegraph noise (RTN) traps in the channel. These traps can randomly capture and release carriers, and their time constants are widely distributed, especially in the low-frequency range. This random fluctuation in the number of carriers caused by defects directly manifests as a significant increase in the 1 / f noise (flicker noise) power spectral density. Therefore, the low-frequency noise amplitude of the write transistor after plasma treatment is systematically increased, and 2T0C memory cell arrays with significantly different retention times and different randomness characteristics can be integrated on the same chip.

[0052] Example 6: A method for manufacturing a dual-transistor capacitor-free (2T0C) dynamic random access memory (DRAM) based on Example 3, wherein in step S1, a MoS2 thin film is grown on substrate 11 by chemical vapor deposition. In step S2, a two-dimensional semiconductor 130 with a channel region of at least three 2T0C memory cells is formed by dry etching and patterning.

[0053] Preferably, in step S3, photoresist is used to protect the non-designated area, exposing the channel region of the two-dimensional semiconductor 130 of the write transistor of a portion of the designated area of ​​the 2T0C memory cell; plasma treatment is performed for 30 seconds in a reactive ion etching apparatus under an oxygen atmosphere and a power of 50W.

[0054] Example 7: A method for manufacturing a dual-transistor capacitor-free (2T0C) dynamic random access memory (DRAM) based on Example 3. In step S1, an insulating dielectric layer 12 is formed on the substrate 11, and the two-dimensional semiconductor layer 13 is formed on the insulating dielectric layer 12, as follows: Figure 4 As shown.

[0055] Preferably, after step S1, a source / drain contact layer 14 is formed on the two-dimensional semiconductor layer 13 in the region where the source and drain electrodes of the write transistor and read transistor of the 2TOC memory cell are located, such as... Figure 5 As shown, proceed to step S2.

[0056] Preferably, in step S4, the subsequent processes include depositing a seed layer, depositing a gate dielectric layer, depositing a top gate electrode layer, etching and filling vias, and depositing interconnect metal to form the source, drain, and gate electrodes of the transistors of each 2T0C memory cell.

[0057] Preferably, the top gate electrode layer of the write transistor is gold deposited by electron beam physical vapor deposition, the top gate electrode layer of the read transistor is aluminum deposited by electron beam physical vapor deposition, and the gate dielectric layer is aluminum oxide deposited by atomic layer deposition.

[0058] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A dual-transistor capacitor-free dynamic random access memory, characterized in that, It includes multiple Type I 2T0C memory cells and multiple Type II 2T0C memory cells integrated on a single chip; The 2T0C memory cell consists of a write transistor (T1) and a read transistor (T2); The write transistor (T1) has its gate connected to the write word line (WWL), one end of its source and drain connected to the write bit line (WBL), and the other end connected to the gate of the read transistor (T2) and used as a storage node (SN). The read transistor (T2) has one end of its source and drain connected to the read bit line (RBL) and the other end connected to the read word line (RWL). The first type of 2T0C memory cell has a first average charge retention time; The second type of 2T0C memory cell has a second average charge retention time; The second average charge retention time is less than 1 / 10 of the first average charge retention time; Multiple Type I 2T0C memory cells form a long-retention time memory array; Multiple Type II 2T0C memory cells form a short-hold-time memory array; The channels of the transistors in the 2T0C memory cell are two-dimensional semiconductors; The channel two-dimensional semiconductor of the write transistor (T1) of the second type 2T0C memory cell has more defects than the channel two-dimensional semiconductor of the write transistor (T1) of the first type 2T0C memory cell. The channel two-dimensional semiconductor of the write transistor (T1) of the first type 2T0C memory cell was not subjected to plasma treatment; The channel two-dimensional semiconductor of the write transistor (T1) of the second type 2T0C memory cell has undergone plasma treatment.

2. The dual-transistor capacitorless dynamic random access memory according to claim 1, characterized in that, Both the write transistor (T1) and the read transistor (T2) are N-channel transistors; The write transistor (T1) has its source connected to the write bit line (WBL) and its drain connected to the gate of the read transistor (T2). The read transistor (T2) has its source terminal connected to the read bit line (RBL) and its drain terminal connected to the read word line (RWL).

3. The dual-transistor capacitorless dynamic random access memory according to claim 1, characterized in that, The off-state leakage current of the write transistor (T1) of the second type of 2T0C memory cell is higher than that of the write transistor (T1) of the first type of 2T0C memory cell.

4. The dual-transistor capacitorless dynamic random access memory according to claim 1, characterized in that, The off-state leakage current of the write transistor of the second type of 2T0C memory cell is 4 to 5 times that of the off-state leakage current of the write transistor of the first type of 2T0C memory cell.

5. The dual-transistor capacitorless dynamic random access memory according to claim 1, characterized in that, The standard deviation of the threshold voltage distribution of the write transistor in the second type of 2T0C memory cell is greater than the standard deviation of the threshold voltage distribution of the write transistor in the first type of 2T0C memory cell.

6. The dual-transistor capacitorless dynamic random access memory according to claim 1, characterized in that, The output current of the second type of 2T0C memory cell in the subthreshold region has more significant periodic to periodic random fluctuations than the output current of the first type of 2T0C memory cell in the subthreshold region.

7. The dual-transistor capacitorless dynamic random access memory according to claim 1, characterized in that, The two-dimensional semiconductor material is a transition metal sulfide; The defects in the channel two-dimensional semiconductor are sulfur vacancies.

8. The dual-transistor capacitorless dynamic random access memory according to claim 6, characterized in that, The two-dimensional semiconductor material is MoS2, MoSe2, MoTe2, WS2, WSe2, WTe2, GeS2, GeSe2, GeTe2, SnS2, SnSe2, SnTe2, SnO, PbS2, PbSe2, PbTe2, GaS, GaSe, GaTe, InS, InSe, InTe, graphene, black phosphorus, arsenene, antimonene, germanene, tinene, or silene.

9. A method for manufacturing the dual-transistor capacitor-free dynamic random access memory according to claim 1, characterized in that, Includes the following steps: S1. A two-dimensional semiconductor layer (13) is formed on the substrate (11); S2. The two-dimensional semiconductor layer (13) is etched according to the size of the write transistor (T1) and read transistor (T2) of the 2T0C memory cell to form a two-dimensional semiconductor (130) of the channel region of at least 4 transistors of the 2T0C memory cell. S3. A selective plasma processing process is implemented to perform plasma processing on the two-dimensional semiconductor (130) of the channel region of the write transistor of a portion of the 2T0C memory cells in a designated area, thereby controllingly introducing defects on the surface of the two-dimensional semiconductor (130) of the channel region. The two-dimensional semiconductor (130) of the channel region of the write transistor of a portion of the 2T0C memory cells in a non-designated area is not subjected to plasma processing, so that the defects in the two-dimensional semiconductor (130) of the channel region of the write transistor of the portion of the 2T0C memory cells in the designated area are more than the defects in the two-dimensional semiconductor (130) of the channel region of the write transistor of the portion of the 2T0C memory cells in the non-designated area are more than the defects in the channel region of the write transistor (T1) of the portion of the 2T0C memory cells in the non-designated area. This systematically increases the off-state leakage current of the write transistor of the portion of the 2T0C memory cells in the designated area, thereby shortening its charge retention time. The portion of the 2T0C memory cells in the designated area are designated as second-type 2T0C memory cells, and the portion of the 2T0C memory cells in the non-designated area are designated as first-type 2T0C memory cells. S4. Proceed with subsequent processes to form a dual-mode dual-transistor capacitor-free dynamic random access memory with a long hold time memory array and a short hold time memory array.

10. The method for manufacturing a dual-transistor capacitorless dynamic random access memory according to claim 9, characterized in that, In step S1, an insulating dielectric layer (12) is formed on the substrate (11), and the two-dimensional semiconductor layer (13) is formed on the insulating dielectric layer (12).

11. The method for manufacturing a dual-transistor capacitorless dynamic random access memory according to claim 10, characterized in that, After step S1, a source-drain contact layer (14) is formed on the two-dimensional semiconductor layer (13) in the region where the source and drain electrodes of the write transistor and read transistor of the 2T0C memory cell are located, and then step S2 is performed.

12. The method for manufacturing a dual-transistor capacitorless dynamic random access memory according to claim 10, characterized in that, In step S4, subsequent processes include depositing a seed layer, depositing a gate dielectric layer, depositing a top gate electrode layer, etching and filling vias, and depositing interconnect metal to form the source, drain, and gate electrodes of the transistors in each 2T0C memory cell.

13. The method for manufacturing a dual-transistor capacitorless dynamic random access memory according to claim 12, characterized in that, The top gate electrode layer of the write transistor is gold deposited by electron beam physical vapor deposition, while the top gate electrode layer of the read transistor is aluminum deposited by electron beam physical vapor deposition, and the gate dielectric layer is aluminum oxide deposited by atomic layer deposition.

14. The method for manufacturing a dual-transistor capacitorless dynamic random access memory according to claim 10, characterized in that, The plasma is O2 plasma; The two-dimensional semiconductor is MoS2.

15. The method for manufacturing a dual-transistor capacitorless dynamic random access memory according to claim 10, characterized in that, The processing power, processing time, and distance from the channel region of the two-dimensional semiconductor (130) of the write transistor in a portion of the designated area to be processed to the plasma ignition location of the selective plasma processing technology are all related to the defect density to be increased.

16. The method for manufacturing a dual-transistor capacitorless dynamic random access memory according to claim 10, characterized in that, The selective plasma processing is carried out in an oxygen atmosphere with a gas flow rate of 50 sccm, a power range of 40W to 60W, and a processing time of 20 to 40 seconds. The plasma is ignited in a quartz tube and transported by gas flow to the channel region of the two-dimensional semiconductor (130) of the write transistor of a portion of the 2T0C memory cell in the designated area to be processed at a distance of 20 to 50 cm from the ignition position.

17. The method for manufacturing a dual-transistor capacitorless dynamic random access memory according to claim 10, characterized in that, In step S1, a MoS2 thin film is grown on the substrate (11) by chemical vapor deposition. In step S2, a two-dimensional semiconductor (130) with a channel region of at least four 2T0C memory cells is formed by dry etching and patterning.

18. The method for manufacturing a dual-transistor capacitorless dynamic random access memory according to claim 10, characterized in that, In step S3, photoresist is used to protect the non-designated area, exposing the channel region of the two-dimensional semiconductor (130) of the write transistor of a portion of the designated area of ​​the 2T0C memory cell; plasma treatment is performed for 30 seconds in a reactive ion etching apparatus under an oxygen atmosphere and a power of 50W.

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