Memory circuit and method of operation thereof

Abstract

A memory circuit includes a first memory array including a plurality of first memory cells each configured to operate at a first supply voltage, a second memory array including a plurality of second memory cells each configured to operate at a second supply voltage, the first supply voltage and the second supply voltage being different from each other, and a driver operatively coupled to the plurality of first memory cells and the plurality of second memory cells by a first access line and to the plurality of second memory cells by a second access line, respectively. The driver is configured to selectively provide a negative voltage on one of the first access line or the second access line based on an address signal. Embodiments of the present application also provide a method for operating a memory circuit.

Description

Technical Field

[0001] Embodiments of this application relate to memory circuits and methods of operation thereof. Background Technology

[0002] Static Random Access Memory (SRAM) is a type of semiconductor memory used in computing applications that require high-speed data access. For example, cache memory applications use SRAM to store frequently accessed data, such as data accessed by the central processing unit.

[0003] The cell structure and architecture of SRAM enable high-speed data access. An SRAM cell includes a bistable flip-flop structure, for example, comprising four to eight transistors. An SRAM architecture may include one or more memory cell arrays and supporting circuitry. Each SRAM array is arranged in rows and columns, referred to as "word lines" and "bit lines," respectively. The supporting circuitry includes address and drive circuitry for accessing each SRAM cell via word lines and bit lines to perform various SRAM operations. Summary of the Invention

[0004] According to one aspect of the embodiments of this application, a memory circuit is provided, comprising: a first memory array including a plurality of first memory cells, each first memory cell being configured to operate at a first power supply voltage; a second memory array including a plurality of second memory cells, each second memory cell being configured to operate at a second power supply voltage, the first power supply voltage and the second power supply voltage being different from each other; and a driver operatively coupled to the plurality of first memory cells via a first access line and to the plurality of second memory cells via a second access line, respectively; wherein the driver is configured to selectively provide a negative voltage on one of the first access line or the second access line based on an address signal.

[0005] According to another aspect of the embodiments of this application, a memory circuit is provided, comprising: a first memory array including a plurality of first memory cells coupled to each other via a first bit line; a second memory array including a plurality of second memory cells coupled to each other via a second bit line; and a driver operatively coupled to the first memory cells via the first bit line and to the second memory cells via the second bit line, wherein the first memory array and the second memory array are each physically positioned relative to the driver in a lateral direction; wherein the driver is configured to: decouple from the first bit line when the first memory array is configured as an idle memory group based on an address signal; and apply a negative voltage to the second bit line when the second memory array is configured as a working memory group based on an address signal.

[0006] According to another aspect of the embodiments of this application, a method for operating a memory circuit is provided, comprising: receiving an address signal indicating that a first memory array is a free memory group and a second memory array is a working memory group, wherein the free memory group is configured to operate at a lower power supply voltage and the working memory group is configured to operate at a higher power supply voltage; providing a selection signal based on the address signal to turn off a first multiplexer and trigger a second multiplexer; and decoupling a driver from the free memory group through the turned-off first multiplexer to allow the first bit line of the free memory group to float, while coupling the driver to the working memory group through the triggered second multiplexer to provide a negative voltage on the second bit line of the working memory group. Attached Figure Description

[0007] The following detailed description, taken in conjunction with the accompanying drawings, will best provide a comprehensive understanding of the various aspects of this disclosure. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A block diagram of a memory device including write-assist circuitry according to some embodiments is shown.

[0009] Figure 2 Illustrations are shown according to some embodiments Figure 1 A schematic diagram of a memory cell in a memory device.

[0010] Figure 3 Illustrations are shown according to some embodiments Figure 1 An example schematic diagram of a portion of a memory device.

[0011] Figure 4 Illustrations are shown according to some embodiments Figure 1 A circuit diagram of a portion of a memory device, which is based on Figure 3 The schematic diagram is implemented.

[0012] Figure 5 Illustrations are shown according to some embodiments Figure 1 Another example schematic diagram of a portion of a memory device.

[0013] Figure 6 Illustrations are shown according to some embodiments Figure 1 Another example schematic diagram of a portion of a memory device.

[0014] Figure 7 Operation according to some embodiments of this disclosure is illustrated. Figure 1 Example waveforms of various signals when using memory devices.

[0015] Figure 8Some embodiments according to this disclosure are shown. Figure 1 A schematic diagram of an example of a write auxiliary circuit for a memory device.

[0016] Figure 9 A cross-sectional view of an example semiconductor device according to some embodiments is shown. The semiconductor device may be... Figure 1 It is part of the implementation of memory devices.

[0017] Figure 10 The following are examples of methods for manufacturing, according to some embodiments. Figure 1 An example flowchart of a method for a part of a memory device.

[0018] Figure 11 The following are illustrations of operation according to some embodiments. Figure 1 Example flowchart of a method for a memory device. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a second feature above or on a first feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0021] The following disclosure describes various aspects of a memory device or circuitry, such as a static random access memory (SRAM) device. For example, this disclosure describes different embodiments related to SRAM memory write operations. Certain SRAM circuitry and control logic are disclosed for ease of explanation to facilitate the description of the different embodiments. It should be understood that SRAM devices also include other circuitry and control logic. These other circuitry and control logic are within the spirit and scope of this disclosure.

[0022] Typically, SRAM devices comprise an array of individual SRAM cells. Each SRAM cell stores a binary voltage value representing a logic data bit (e.g., "0" or "1"). One existing configuration of an SRAM cell includes a pair of cross-coupled devices, such as inverters. Utilizing complementary metal-oxide-semiconductor (CMOS) technology, each inverter typically includes a pull-up PFET (p-channel) transistor connected to a complementary pull-down NFET (n-channel) transistor. The inverters, connected in a cross-coupled configuration, act as latches that store data bits as long as power is supplied to the memory array. In a conventional six-transistor (6T) cell, a pair of access transistors or transmission gates (when triggered by a word line) selectively couple the inverter to a pair of complementary bit lines. Other SRAM cell designs may include different numbers of transistors, such as 4T, 8T, etc.

[0023] The design of SRAM cells traditionally involves trade-offs between read and write operations to maintain cell stability, read performance, and write performance. The transistors that make up the cross-coupled latch are typically weak enough to be overdriven during write operations, but strong enough to maintain their data value while driving the bit lines during read operations. Connecting the cross-coupled cell node to the true bit line and complementary bit line via access transistors impacts cell stability and performance. In single-port SRAM cells, a single pair of access transistors is typically used for both read and write access to the cell. The gate is driven to a digital value to switch the transistor between on and off states. Optimizing access for write operations will drive a reduction in the device's on-resistance (R0). on On the other hand, R is added to optimize the access transistor driver for read operations. on This is to isolate the cell from the bit line capacitor and prevent cell interference.

[0024] One proposed method to improve the write performance of SRAM devices is to use a so-called "negative boost" technique to discharge the bit lines to a voltage level below the nominal low supply rail value (e.g., ground). In other words, when written to, the corresponding bit line of the SRAM cell can present a negative voltage. This bit line is typically discharged to a negative voltage via write-assist circuitry, which typically includes a capacitor (sometimes called a boost capacitor). In this way, the transfer gate of the SRAM cell coupled to the discharged bit line sees an increase in both gate-to-source and drain-to-source voltages. This negative boost allows for an increase of 3σ or more (in terms of anticipated device failures) compared to more conventional write techniques where the bit lines are only discharged to the nominal low supply rail value (e.g., ground).

[0025] Despite the advantages of negative boost, existing SRAM devices with negative boost may still be less than ideal in some respects. For example, as transistor sizes continue to shrink in advanced technology nodes, multiple memory banks are typically coupled to write-aided circuitry, some of which can operate at relatively high supply voltages, while others can operate at relatively low supply voltages in terms of power consumption. Typically, for example, memory banks selected to operate at high supply voltages are configured for high-speed read / write operations, while memory banks selected to operate at low supply voltages are configured for data retention.

[0026] In one configuration, where a first memory bank (operating at a low supply voltage) is physically located closer to a write assist circuit than a second memory bank (operating at a high supply voltage), the write assist circuit typically provides a "deeper" negative voltage on the bit line to ensure the first memory bank receives a sufficiently negative voltage on its bit line in order to effectively write to the first memory bank with a negative bit line. As a non-limiting example, where the high and low supply voltages are approximately 1.1V and 0.5V respectively, the write assist circuit can apply a negative voltage of approximately -250 mV on the discharge bit line connected to the first (far) memory bank and the second (near) memory bank. Therefore, the first memory bank can see a negative voltage of approximately -50 mV on its bit line, which may cause the second memory bank to see a negative voltage close to -250 mV on its bit line. This causes the access transistors of the second memory bank to unexpectedly turn on because the V0 of the access transistors... gs Too close to its V th Therefore, the second memory bank may disadvantageously lose its ability to retain stored data.

[0027] This disclosure provides various embodiments of a memory circuit including a (write) driver that can provide a negative voltage, sometimes referred to as a negative bit line voltage, on a bit line. The memory circuit may include an SRAM device or circuitry. The negative bit line voltage can be selectively coupled (or applied) to a first bit line of a first memory group of the disclosed memory circuit, which is selected as a working memory group, while the negative bit line voltage can be selectively isolated from a second bit line of a second memory group of the disclosed memory circuit, which is selected as an idle memory group. For example, as disclosed herein, the memory circuit may include logic gates, at least a first multiplexer (e.g., a first transistor), and at least a second multiplexer (e.g., a second transistor). The first multiplexer is coupled between the write driver and the first bit line, and the second multiplexer is coupled between the write driver and the second bit line. Based on a received address signal, the logic gates can trigger one of the first or second multiplexers while simultaneously turning off the other of the first or second multiplexers. In some embodiments, the working memory bank can be configured for high-speed read / write operations or to operate at a relatively high power supply voltage, while the idle memory bank can be configured for data retention or to operate at a relatively low power supply voltage. In some embodiments, the idle memory bank (operating at a lower power supply voltage) can be physically located closer to the write driver than the working memory bank (operating at a higher power supply voltage). In this arrangement, the first line coupling the write driver to the working memory bank can be physically constructed across the idle memory bank using multiple metal tracks in multiple metallization layers.

[0028] According to various embodiments of this disclosure Figure 1 A block diagram of an example static random access memory (SRAM) device / circuit 100 is shown, which includes a write driver 110 with write assistance circuitry. The SRAM device 100 may further include a row decoder 120, a word line driver 130, a memory bank decoder 140, a memory bank multiplexer circuit 150, and a memory array 180. It should be understood that... Figure 1 The block diagram is provided for illustrative purposes and has been simplified; therefore, the SRAM device 100 may include a variety of other suitable components while still remaining within the scope of this disclosure.

[0029] Memory array 180 includes multiple memory cells 190. The memory cells 190 can be arranged into multiple memory groups, some of which can be configured as working memory groups and others as free memory groups, as will be discussed in further detail below. Figure 1 In the example, memory array 180 has "M" rows (e.g., ROW1 to ROW2). M) and "N" columns (COL1 to COL) N As a non-limiting example, M can be equal to 256, therefore, memory array 180 can include a first memory group with 128 rows and a second memory group with 128 rows. Each memory cell 190 can be located at the intersection of the corresponding row and the corresponding column. Therefore, the symbol "190" 11 "Refers to a memory cell 190 located at ROW1 and COL1, symbol "190" MN "refers to the location in ROW" M and COL N Another memory unit 190, and so on.

[0030] According to various embodiments of this disclosure, based on an address (ADDR) signal, the memory group decoder 140 can provide a memory group select (SEL) signal to the memory group multiplexer circuit 150. Using the SEL signal, the memory group multiplexer circuit 150 can select at least one memory group of the memory array 180 as a working memory group and select at least one memory group of the memory array 180 as an idle memory group. The working memory group can be powered by a relatively high supply voltage for high-speed write / read operations, while the idle memory group can be powered by a relatively low supply voltage for retaining previously written data. The memory cells 190 of the working memory group selected by the memory group multiplexer circuit 150 can be accessed (e.g., written) by the write driver 110. The write assist circuitry of the write driver 110 can provide a negative bit line voltage and apply it to one or more bit line pairs of the working memory group. The bit line pairs are commonly referred to as BL and BLB, where the symbol "BL" refers to a bit line and the symbol "BLB" refers to the two's complement of BL, sometimes referred to as bit line inversion.

[0031] On the other hand, the memory cells 190 of the free memory bank selected by the memory bank multiplexer circuit 150 can be operatively isolated from the write driver 110, causing the bit line pairs of the free memory bank to float (e.g., after pre-charging to the corresponding supply voltage). Each memory cell 190 can be accessed using the ADDR signal before, during, or after the selection of the working memory bank, for example, to perform read or write operations. Based on the ADDR signal, the row decoder 120 can select rows of memory cells in the working memory bank (e.g., ROW1 to ROW). M One of them), to be transmitted via word line driver 130 (e.g., multiple word line drivers 1301…130). M Access the corresponding one in the middle.

[0032] The memory cell 190 can have various circuit topologies. For example, the memory cell 190 can have a "6T" circuit topology. Figure 2 An example 6T circuit topology for memory cell 190 is shown. The 6T circuit topology includes n-channel metal-oxide-semiconductor (NMOS) transmission gate devices 220 and 230, NMOS pull-down devices 240 and 250, and p-channel metal-oxide-semiconductor (PMOS) pull-up devices 260 and 270. Voltage from word line driver 130 controls (e.g., turns on / off) NMOS devices 220 and 230 via word line WL to deliver voltage from bit line pairs BL and BLB to a bistable flip-flop structure formed by NMOS devices 240 and 250 and PMOS devices 260 and 270. NMOS device 240 and PMOS device 260 form a first inverter, and NMOS device 250 and PMOS device 270 form a second inverter, wherein the first and second inverters are cross-coupled, operatively forming the flip-flop structure. Voltage applied to bit line pairs BL and BLB can be used for write operations.

[0033] For example, when the voltage applied to word line WL (or to the gate terminals of NMOS transmission gates 220 and 230) is at a sufficient voltage level, the logic values ​​of BL and BLB can be propagated to the bistable flip-flop structure. As a non-limiting example, when NMOS transmission gates 220 and 230 are turned on, if the inverted bit line BLB is provided with a '1' or a logic high value (e.g., a supply voltage CVDD, such as 0.4V, 0.5V, 0.6V, 0.7V, 1.0V, 1.1V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, or any combination thereof), and the bit line BL is provided with a '0' or a logic low value (e.g., ground or 0V), then the logic low value of BL and the logic high value of BLB can be propagated to the internal nodes X and Y of the bistable flip-flop structure, respectively. As a result, these logic values ​​are written (or programmed) into the bistable flip-flop structure.

[0034] According to some embodiments of this disclosure Figure 3 SRAM device 100 is shown. Figure 1 Example diagram of a part of ) Figure 4 It shows the basis Figure 3 The circuit diagram is constructed from the schematic diagram. In Figures 3-4 In the example, memory array 180 includes two memory groups, such as 180A and 180B, one of which can be selected as active and the other as idle. For example, memory array 180 may include 256 rows (or 256 word lines), where memory group 180A with 128 rows is selected as the active memory group (e.g., operating at approximately 1.1V CVDD), and memory group 180B with 128 rows is selected as the idle memory group (e.g., operating at approximately 0.5V CVDD).

[0035] According to some embodiments, the write assist circuitry of write driver 110 can provide a vBL signal to memory array 180. For example, write driver 110 can selectively provide the vBL signal as a negative bit line voltage to the working memory bank (e.g., 180A) based on the ADDR signal. The write assist circuitry of write driver 110 may include one or more boost capacitors to provide this negative vBL signal, which will be discussed below. Figure 8 The negative vBL signal can be applied to at least one bit line BL (e.g., 340), which is coupled to multiple memory cells 190 of the working memory bank 180A via multiplexer 320 of memory bank multiplexer circuit 150. Multiplexer 320 (e.g., implemented as an NMOS device) can be turned on by a SEL signal generated by logic gate 310 of memory bank decoder 140. For example, logic gate 310 may include a NOR gate having a first input configured to receive an ADDR signal, a second input configured to receive a control (YMUXB) signal, and an output configured to generate a SEL signal by performing a NOR operation on the ADDR signal and the YMUXB signal. Multiplexer 320 has a gate terminal connected to the output of logic gate 310, a first source / drain terminal connected to write driver 110, and a second source / drain terminal connected to bit line BL 340.

[0036] Although not shown, when a negative vBL signal is applied to bit line BL 340, the corresponding inverted bit line BLB in the same column can be floating (e.g., held at the precharge voltage level). This can be applied when logic low and logic high values ​​are programmed to internal nodes X and Y respectively. Figure 2 In another case, when logic high and logic low values ​​are programmed to internal nodes X and Y respectively, the negative vBL signal can be applied to the corresponding inverted bit line BLB, while bit line BL 340 is floating.

[0037] While write driver 110 is coupled to bit line BL 340 via multiplexer 320, the negative vBL signal can be isolated from bit lines BL (e.g., 350) coupled to multiple memory cells 190 of free memory bank 180B. Bit line BL 350 can be isolated from write driver 110 by turning off multiplexer 330 of memory bank multiplexer circuit 150. Multiplexer 330 (e.g., implemented as another NMOS device) can be turned off by SEL signal. For example, multiplexer 330 has an output with gate terminal connected to logic gate 310, a first source / drain terminal connected to write driver 110, and a second source / drain terminal connected to bit line BL 350. Although not shown, the corresponding inverted bit line BLB in the same column can also be isolated from write driver 110. Therefore, bit line pair BL (350) and BLB can be floating or held at precharge voltage level.

[0038] exist Figure 3 In the example, memory array 180 has 256 rows, and the ADDR signal can be provided or input in 8-bit form, such as ADDR[7:0]. One of these 8 bits can be used to identify whether the corresponding memory group is configured as a working memory group. For example, when a column of memory array 180 is selected, the YMUXB signal can be provided as an inverted pulse, i.e., when a column is selected, the YMUXB signal is pulled down to logic 0. Furthermore, when ADDR[7] provides logic 0 and ADDR[6] provides logic 1, logic gate 310 can perform a NOR operation on the ADDR signal and the YMUXB signal to output a SEL signal including a first bit as logic 1 and a second bit as logic 0. The first bit can be received by the gate terminal of multiplexer 320, and the second bit can be received by the gate terminal of multiplexer 330. Therefore, multiplexer 320 is turned on and multiplexer 330 is turned off, thereby coupling write driver 110 to bit line BL 340 and decoupling it from bit line BL 350.

[0039] According to some embodiments, memory bank 180A may be physically located further away from write driver 110 than memory bank 180B. Therefore, bit line BL 340 may be formed across multiple metallization layers to span memory bank 180A. As a non-limiting example, memory cells of both memory banks 180A-B may be formed along the main surface of the substrate, sometimes referred to as part of a front-end process (FEOL) network. Bit line BL 350 may be formed based on at least one first metal track disposed in a first metallization layer (e.g., M0 layer) among multiple metallization layers disposed above the main surface of the substrate, sometimes referred to as part of a back-end process (BEOL) network. Bit line BL 340 may be formed based on a second metal track in at least a second higher metallization layer (e.g., M2 layer) among multiple metallization layers, a third metal track disposed in the first metallization layer (M0 layer), and one or more via structures connecting the second and third metal tracks.

[0040] Next reference Figure 4 (combined) Figure 3 Two memory cells, such as 190A1, 190A2, 190B1, and 190B2, are shown in each memory group 180A and 180B. Continuing with the example above, memory groups 180A and 180B are selected as active and idle, respectively, and bit line BL 350 is applied with a logic low value. Bit line 350 can be applied with a negative bit line voltage of approximately -100mV (e.g., applied by write driver 110), while BLB 340' (of active memory group 180A) and bit line pairs BL 350 and BLB 350' are floating (e.g., maintained at a precharge voltage level of approximately 1.1V). Therefore, the memory cell 190A1, which is closer to the write driver 110, can see a vBL signal of about -100mV on the corresponding portion of its bit line BL 340, while the memory cell 190A2, which is further away from the write driver 110, can see a vBL signal of about -50mV on the corresponding portion of its bit line BL 340 (e.g., due to the IR drop and / or leakage of the transmission gate device arranged between the memory cell 190A2 and the write driver 110).

[0041] Since the corresponding portions of bit line 340 each present a negative bit line voltage, each of memory cells 190A1 and 190A2 can more efficiently program logic low values ​​into its X node. On the other hand, each of memory cells 190B1 and 190B2 sees its corresponding portion of bit line BL 350 held at approximately 1.1V (precharge voltage level). Since the free memory bank 180B is powered by approximately 0.5V of CVDD, the X node of each of memory cells 190B1 and 190B2 is latched at approximately 0.5V. Because no negative bit line voltage is applied to bit line 350, each of memory cells 190B1 and 190B2 can therefore safely retain its previously stored data.

[0042] According to some embodiments of this disclosure Figure 5 SRAM device 100 is shown. Figure 1 An example diagram of a portion of ( ). In Figure 5 In the example, memory array 180 includes three memory groups, such as 180A, 180B, and 180C, one of which can be selected as active and each of the other two can be selected as idle. For example, memory array 180 may include 256 rows (or 256 word lines), where memory group 180B with 128 rows is selected as the active memory group (e.g., operating at approximately 1.1V CVDD), and each of memory group 180B with 64 rows and memory group 180C with 64 rows is selected as an idle memory group (e.g., operating at approximately 0.5V CVDD).

[0043] Similar to Figure 3 The schematic diagram shows that the memory group decoder 140 also includes a NOR gate 310 configured to perform a NOR operation on the received ADDR signal and MUXB signal to provide a SEL signal to the memory group multiplexer circuit 150. Figure 5 In this circuit, the memory bank multiplexer circuit 150 includes three multiplexers 510, 520, and 530, which are coupled between the write driver 110 and the corresponding memory bank (or its bit line BL). Each multiplexer 510 to 530 can be implemented as an NMOS device, with its gate terminal configured to receive the SEL signal. Furthermore, multiplexer 510 may have its first source / drain terminal connected to the write driver 110 and its second source / drain terminal connected to the bit line BL 540 of memory bank 180A; multiplexer 520 may have its first source / drain terminal connected to the write driver 110 and its second source / drain terminal connected to the bit line BL 550 of memory bank 180B; and multiplexer 530 may have its first source / drain terminal connected to the write driver 110 and its second source / drain terminal connected to the bit line BL 550 of memory bank 180C.

[0044] According to some embodiments, memory group 180A may be physically located further away from write driver 110 than memory groups 180B and 180C, and memory group 180B may be physically located further away from write driver 110 than memory group 180C. Therefore, bit line BL 540 may be formed across multiple metallization layers to traverse memory groups 180B-C, and bit line BL 550 may also be formed across multiple metallization layers to traverse memory group 180C.

[0045] As a non-limiting example, the memory cells of all memory groups 180A-C can be formed along the main surface of the substrate. Bit line BL 560 can be formed based on at least one first metal track disposed in a first metallization layer (e.g., M0 layer) among a plurality of metallization layers disposed above the main surface of the substrate. Bit line BL 550 can be formed based on a second metal track in at least a second higher metallization layer (e.g., M2 layer) among a plurality of metallization layers, a third metal track disposed in the first metallization layer (M0 layer), and one or more via structures connecting the second and third metal tracks. Bit line BL 550 can be formed based on a fourth metal track in at least a third higher metallization layer (e.g., M4 layer) among a plurality of metallization layers, a fifth metal track disposed in the first metallization layer (M0 layer), and one or more via structures connecting the fourth and fifth metal tracks.

[0046] According to some embodiments of this disclosure Figure 6 SRAM device 100 is shown. Figure 1 An example diagram of a portion of ( ). In Figure 5 In the example, memory array 180 includes four memory groups, such as 180A, 180B, 180C, and 180D, one of which can be selected as active and each of the other three can be selected as idle. For example, memory array 180 may include 256 rows (or 256 word lines), where memory group 180C with 64 rows is selected as the active memory group (e.g., operating at approximately 1.1V CVDD), and each of memory groups 180A, 180B, and 180D with 64 rows is selected as an idle memory group (e.g., operating at approximately 0.5V CVDD).

[0047] Similar to Figure 3 The schematic diagram shows that the memory group decoder 140 also includes a NOR gate 310 configured to perform a NOR operation on the received ADDR signal and MUXB signal to provide a SEL signal to the memory group multiplexer circuit 150. Figure 6In this circuit, the memory bank multiplexer circuit 150 includes four multiplexers 610, 620, 630, and 640, which are coupled between the write driver 110 and the corresponding memory bank (or its bit line BL). Each multiplexer 610 to 640 can be implemented as an NMOS device, with its gate terminal configured to receive the SEL signal. Furthermore, multiplexer 610 may have a first source / drain terminal connected to write driver 110 and a second source / drain terminal connected to bit line BL 650 of memory group 180A; multiplexer 620 may have a first source / drain terminal connected to write driver 110 and a second source / drain terminal connected to bit line BL 660 of memory group 180B; multiplexer 630 may have a first source / drain terminal connected to write driver 110 and a second source / drain terminal connected to bit line BL 670 of memory group 180C; multiplexer 640 may have a first source / drain terminal connected to write driver 110 and a second source / drain terminal connected to bit line BL 680 of memory group 180D.

[0048] According to some embodiments, memory group 180A may be physically located further away from write driver 110 than memory groups 180B-D, memory group 180B may be physically located further away from write driver 110 than memory groups 180C-D, and memory group 180C may be physically located further away from write driver 110 than memory group 180D. Therefore, bit line BL650 may be formed across multiple metallization layers to traverse memory groups 180B-D, bit line BL660 may also be formed across multiple metallization layers to traverse memory groups 180C-D, and bit line BL670 may also be formed across multiple metallization layers to traverse memory group 180D.

[0049] As a non-limiting example, the memory cells of all memory banks 180A-D can be formed along the main surface of the substrate. Bit line BL 680 can be formed based on at least one first metal track disposed in a first metallization layer (e.g., M0 layer) among a plurality of metallization layers disposed above the main surface of the substrate. Bit line BL 670 can be formed based on a second metal track in at least a second higher metallization layer (e.g., M2 layer) among a plurality of metallization layers, a third metal track disposed in the first metallization layer (M0 layer), and one or more via structures connecting the second and third metal tracks. Bit line BL 680 can be formed based on a fourth metal track in at least a third higher metallization layer (e.g., M4 layer) among a plurality of metallization layers, a fifth metal track disposed in the first metallization layer (M0 layer), and one or more via structures connecting the fourth and fifth metal tracks. The bit line BL 650 can be formed based on a sixth metal track in a fourth higher metallization layer (e.g., M6 layer) arranged in at least a plurality of metallization layers, a seventh metal track arranged in a first metallization layer (M0 layer), and one or more via structures connecting the sixth metal track and the seventh metal track.

[0050] According to some embodiments of this disclosure Figure 7 Example waveforms for one bit of the aforementioned vBL and ADDR signals are shown. This bit of the ADDR signal can be configured to indicate whether the corresponding memory bank is configured to be active (e.g., ready to be written to). For example, when this bit of the ADDR signal is provided as logic 1, the corresponding memory bank is configured to be idle, causing vBL to be provided at a precharge voltage level (e.g., approximately 1.1V); when this bit of the ADDR signal is provided as logic 0, the corresponding memory bank is configured to be active, causing vBL to be provided at a negative voltage level (e.g., approximately -100mV).

[0051] According to some embodiments of this disclosure Figure 8 An example circuit diagram of the aforementioned write auxiliary circuitry (hereinafter referred to as "write auxiliary circuitry 800") of the write driver 110 is shown. Typically, write auxiliary circuitry 800 can selectively provide a negative voltage to the vBL signal. It should be understood that... Figure 8 The circuit diagram has been simplified for illustrative purposes. Therefore, the write auxiliary circuit 800 may include various other suitable components, while still remaining within the scope of this disclosure.

[0052] As shown, the write assist circuit 800 includes an NMOS device 810 (used as a switch) and a boost capacitor 820. The NMOS device 810 is coupled between ground and node A, and the boost capacitor 820 is coupled between node A and node B, with node B connected to the gate terminal of the NMOS device 810. A bit-line boost enable control signal 801 can be provided at node B by logic circuitry 830, which is configured to receive a write enable signal 803 (e.g., a logically inverted YMUXB signal). Logic circuitry 830 may include multiple delay elements connected in series with one or more inverters to provide a delay to the write enable signal 803. Therefore, the write enable signal 803 can be delayed and inverted to provide a boost signal 805 at node B. The boost signal 805 is high before the write enable signal 803 goes high (at the start of a write operation / cycle), which turns on the NMOS device 810 and charges the boost capacitor 820. When boost signal 805 is high, node A is also connected to ground via NMOS device 810. After a delay, boost signal 805 goes low, which turns off NMOS device 810 and causes boost capacitor 820 to discharge, thereby driving node A from ground (low) to a negative value. This negative voltage is then provided as the vBL signal and supplied to the working memory bank as described above.

[0053] Figure 9 A cross-sectional view of a semiconductor device 900 is shown, which may be implemented as at least a portion of an SRAM device 100. For example, the semiconductor device 900 may include various components of write auxiliary circuitry configured as a write driver 110. Figure 9 The cross-sectional view is cut along the longitudinal direction of the channels of the plurality of transistors of the semiconductor device 900, each transistor being implemented as a gate-all-around field-effect transistor (GAA FET) device. However, it should be understood that the transistors of the semiconductor device 900 can be implemented as various other transistor structures (e.g., fin field-effect transistors, planar field-effect transistors, or other nanostructure transistors, etc.) while still within the scope of this disclosure.

[0054] On the front side of the substrate (surrounded by dashed lines, as it was removed during the formation of the back interconnect structure), the semiconductor device 900 includes an active region 902, a portion of which is formed as a channel 904 and a portion as a source / drain structure 906. In various embodiments, each of the channels 904 may include one or more vertically spaced nanostructures (e.g., nanosheets, nanowires), and each of the source / drain structures 906 may include one or more epitaxial structures. The semiconductor device 900 includes a plurality of active (e.g., metal) gate structures 908, each gate structure 908 surrounding the nanostructure of the corresponding channel 904. Above the source / drain structures 906, the semiconductor device 900 includes a plurality of source / drain interconnect structures (sometimes referred to as MD) 910, some of which are coupled to contact via structures (sometimes referred to as VD) 912 formed thereon. Above the gate structures 908, the semiconductor device 900 includes a plurality of gate via structures (sometimes referred to as VG) 914.

[0055] VD 912 couples MD 910 to a first metal track 916 in the first front-side metallization layer (M0 layer). Metal track 916 is sometimes referred to as M0 track 916. VG 914 couples gate structure 908 to a second M0 track 918. Above M0 tracks 916 and 918 (and various other metal tracks in the M0 layer), semiconductor device 900 includes a plurality of via structures (sometimes referred to as V0) 920 and 922 to couple M0 tracks 916 and 918 to corresponding metal tracks (sometimes referred to as M1 tracks) 924 and 926 in the next front-side metallization layer (M1 layer) away from the substrate, respectively. Furthermore, above M1 orbitals 924 and 926 (and various other metal orbitals in the M1 layer), semiconductor device 900 includes a plurality of via structures (sometimes referred to as V1) 928 and 930 to couple M1 orbitals 924 and 926 to corresponding metal orbitals (sometimes referred to as M2 orbitals) 932 and 934 in the next front metallization layer (M2 layer) away from the substrate, respectively. Although three front metallization layers are shown, it should be understood that semiconductor device 900 may include any number of front metallization layers.

[0056] According to various embodiments, the metal tracks formed across these front-side metallization layers can be configured to electrically couple different components of the SRAM device 100 (in order to route signals and / or provide power). Figure 3As a representative example, the bit line BL 340 of the fly-through memory group 180B can be formed by at least one M0 track and one M2 track. In another example, bit line 350 can be formed by at least one M0 track. According to some embodiments of this disclosure, at least one of the channels 904, together with the corresponding gate structure 908 and the corresponding source / drain structure 906 pair surrounding the channel, can form an NMOS device 810 of the write auxiliary circuit 800. M0 tracks 916 and 918 can form one of a plurality of parallel-connected sub-capacitors of the boost capacitor 820. M0 tracks 916 and 918 can each serve as a terminal of such a sub-capacitor.

[0057] According to some embodiments, Figure 10 A flowchart of a method 1000 for forming or manufacturing a semiconductor device is shown. Some operations of method 1000 can be configured to form at least a portion of the aforementioned SRAM device 100, such as memory cells 190 of different memory groups 180A-B, write drivers 110, and bit lines BL 340-350 coupling the write drivers 110 to the memory groups 180A-B. Figure 3 and Figure 4 ), memory cells 190 of different memory groups 180A-C, write drivers 110, and bit lines BL 540-560 that couple write drivers 110 to memory groups 180A-C ( Figure 5 ), or memory cells 190 of different memory groups 180A-D, write drivers 110, and bit lines BL 650-680 that couple write drivers 110 to memory groups 180A-D ( Figure 6 It should be understood that it is possible to... Figure 10 Additional operations are performed before, during, and / or after the method shown in 1000.

[0058] For example, method 1000 begins at operation 1010, providing a substrate including a first region, a second region, and a third region. Method 1000 proceeds to operation 1020, forming a channel layer and a sacrificial layer on the substrate, alternately stacked on top of each other. Method 1000 proceeds to operation 1030, defining a plurality of first semiconductor fins, each including a corresponding first portion of the channel layer and the sacrificial layer; a plurality of second semiconductor fins, each including a corresponding second portion of the channel layer and the sacrificial layer; and a plurality of third semiconductor fins, each including a corresponding third portion of the channel layer and the sacrificial layer. In some embodiments, the first semiconductor fins may be disposed in the first region, the second semiconductor fins may be disposed in the second region, and the third semiconductor fins may be disposed in the third region.

[0059] Method 1000 proceeds to operation 1040, forming a plurality of first source / drain structures in each first semiconductor fin, a plurality of second source / drain structures in each second semiconductor fin, and a plurality of third source / drain structures in each third semiconductor fin. Method 1000 may proceed to operation 1050, forming a plurality of first active (e.g., metal) gate structures across the first semiconductor fin; a plurality of second active (e.g., metal) gate structures across the second semiconductor fin; and a plurality of third active (e.g., metal) gate structures across the third semiconductor fin. The first active gate structures may replace the remaining portion of the sacrificial layer in the first semiconductor fin to surround the remaining portion of the channel layer in the first semiconductor fin; the second active gate structures may replace the remaining portion of the sacrificial layer in the second semiconductor fin to surround the remaining portion of the channel layer in the second semiconductor fin; and the third active gate structures may replace the remaining portion of the sacrificial layer in the third semiconductor fin to surround the remaining portion of the channel layer in the third semiconductor fin.

[0060] In some embodiments, a first semiconductor fin, a first source / drain structure, and a first active gate structure can operatively form a first memory cell of a first memory group; a second semiconductor fin, a second source / drain structure, and a second active gate structure can operatively form a second memory cell of a second memory group; and a third semiconductor fin, a third source / drain structure, and a third active gate structure can operatively form a write driver. Furthermore, the first region can be located between the second and third regions; therefore, the first memory group in the first region may sometimes be referred to as a near memory group (relative to the write driver), and the second memory group in the second region may sometimes be referred to as a far memory group (relative to the write driver).

[0061] Method 1000 proceeds to operation 1060, forming at least a first metal track located in a first metallization layer, configured to couple a write driver to a first memory group; and at least a second metal track located in a second higher metallization layer, and a third metal track located in the first metallization layer, the second and third metal tracks being configured to couple a write driver to a second memory group. In some embodiments, the first metal track operatively serves as one of a plurality of first bit lines of the first memory group, and the second and third metal tracks may operatively serve as one of a plurality of second bit lines of the first memory group.

[0062] According to some embodiments, Figure 11A flowchart of a method 1100 for operating a memory device is shown. For example, at least some operations of method 1100 can be configured to selectively couple write auxiliary circuitry to one or more of various memory groups in a memory array, the write auxiliary circuitry providing a negative bit-line voltage while decoupling the negative bit-line voltage from other memory groups. It should be noted that method 1100 is merely an example and is not intended to limit the scope of this disclosure. Therefore, it should be understood that... Figure 11 Additional operations are provided before, during, and / or after Method 1100, and this document may only briefly describe some of these other operations.

[0063] Method 1100 begins with operation 1110, receiving an address signal indicating that the first memory array is a free memory group and the second memory array is a working memory group. According to some embodiments, the free memory group is configured to operate at a lower supply voltage, and the working memory group is configured to operate at a higher supply voltage. Figure 3 The implementation shown is a representative example. The memory group decoder 140 can receive an ADDR signal, which includes one or more bits, each configured to indicate whether the corresponding memory group is configured as a working or idle memory group. Based on the ADDR signal, memory group 180A can be indicated as a working memory group, and memory group 180B can be indicated as an idle memory group. According to some embodiments, the working memory group is configured to perform read / write operations, while the idle memory group is configured to retain previously written data.

[0064] Method 1100 continues to operation 1120, providing an address-based selection signal to disable the first multiplexer and trigger the second multiplexer. Continuing the example above, the memory bank decoder 140 can provide a SEL signal to control (e.g., trigger) multiplexer 320 to selectively couple write driver 110 to memory bank 180A based on an ADDR signal, and to control multiplexer 330 to selectively couple write driver 110 to memory bank 180B based on an ADDR signal. The SEL signal may include a first bit and a second bit, which are logically opposite. When the first bit is provided as logic 1 (and the second bit is provided as logic 0), multiplexer 320 is triggered, and multiplexer 330 is disabled.

[0065] Method 1100 continues to operation 1130, decoupling the driver from the free memory bank by disabling the first multiplexer to allow the first bit line of the free memory bank to float, while simultaneously coupling the driver to the working memory bank by triggering the second multiplexer to provide a negative voltage on the second bit line of the working memory bank. Continuing the example above, when multiplexer 320 is triggered and multiplexer 330 is disabled, write driver 110 can be configured to provide a negative bit line voltage and coupled to memory bank 180A via triggering multiplexer 320. When write driver 110 is configured to provide a negative bit line voltage, write driver 110 can simultaneously be decoupled from memory bank 180B via disabling multiplexer 330.

[0066] In one aspect of this disclosure, a memory circuit is disclosed. The memory circuit includes a first memory array comprising a plurality of first memory cells, each first memory cell configured to operate at a first power supply voltage; a second memory array comprising a plurality of second memory cells, each second memory cell configured to operate at a second power supply voltage, the first and second power supply voltages being different from each other; and a driver operatively coupled to the plurality of first memory cells via first access lines and to the plurality of second memory cells via second access lines. The driver is configured to selectively provide a negative voltage on either the first or second access lines based on an address signal.

[0067] In some embodiments, the first memory unit and the second memory unit each include a static random access memory unit.

[0068] In some embodiments, the driver is physically closer to one of the first or second memory arrays in the lateral direction than the other of the first or second memory arrays.

[0069] In some embodiments, the driver is configured to apply a negative voltage to a first access line via a first transistor turned on by an address signal, while decoupling from a second access line via a second transistor turned off by an address signal.

[0070] In some embodiments, where the first memory array is located between the driver and the second memory array in the lateral direction, the first access line is formed by a first metal track that physically extends at least in the lateral direction, and the second access line is formed by both a second metal track and a third metal track that physically extend at least in the lateral direction.

[0071] In some embodiments, the first metal orbital and the third metal orbital are formed in the first metallization layer, while the second metal orbital is formed in the second and higher metallization layers.

[0072] In some embodiments, both the first metal track and the second metal track extend across the first memory array.

[0073] In some embodiments, the first memory array is configured as a working memory group based on an address signal, causing the first access line to receive a negative voltage, while the second memory array is configured as an idle memory group based on an address signal, causing the second access line to float.

[0074] In some embodiments, the memory circuitry further includes: a logic gate configured to provide a selection signal based on an address signal, wherein the address signal indicates whether a second memory array is selected as a working memory group; a first transistor configured to decouple a driver from a first access line based on the selection signal; and a second transistor configured to couple a driver to a second access line based on the selection signal.

[0075] In some embodiments, the logic gate is configured to perform a NOR operation on address signals and control signals.

[0076] In some embodiments, the first transistor and the second transistor are turned on alternately based on an address signal.

[0077] In another aspect of this disclosure, a memory circuit is disclosed. The memory circuit includes a first memory array comprising a plurality of first memory cells coupled to each other via a first bit line; a second memory array comprising a plurality of second memory cells coupled to each other via a second bit line; and a driver operatively coupled to the first memory cells via the first bit line and to the second memory cells via the second bit line, wherein the first and second memory arrays are each physically positioned laterally relative to the driver. The driver is configured to decouple from the first bit line when the first memory array is configured as an idle memory group based on an address signal; and to apply a negative voltage to the second bit line when the second memory array is configured as a working memory group based on an address signal.

[0078] In some embodiments, the driver is physically closer to one of the first or second memory arrays in the lateral direction than the other of the first or second memory arrays.

[0079] In some embodiments, where the first memory array is located between the driver and the second memory array in the lateral direction, the first bit line is formed by a first metal track that physically extends at least in the lateral direction, and the second bit line is formed by both a second metal track and a third metal track that physically extend at least in the lateral direction.

[0080] In some embodiments, the first metal orbital and the third metal orbital are formed in the first metallization layer, while the second metal orbital is formed in the second and higher metallization layers.

[0081] In some embodiments, both the first metal track and the second metal track extend across the first memory array.

[0082] In some embodiments, the memory circuitry further includes: a logic gate configured to provide a selection signal based on an address signal; a first transistor selectively coupled between a driver and a first bit line based on the selection signal; and a second transistor selectively coupled between a driver and a second bit line based on the selection signal.

[0083] In another aspect of this disclosure, a method for operating memory circuitry is disclosed. The method includes receiving an address signal indicating that a first memory array is a free memory group and a second memory array is a working memory group, wherein the free memory group is configured to operate at a lower supply voltage and the working memory group is configured to operate at a higher supply voltage. The method includes providing a selection signal based on the address signal to disable a first multiplexer and trigger a second multiplexer. The method includes decoupling a driver from the free memory group via the disabled first multiplexer to allow a first bit line of the free memory group to float, while coupling the driver to the working memory group via the triggered second multiplexer to provide a negative voltage on a second bit line of the working memory group.

[0084] In some embodiments, the first memory array is physically located between the second memory group and the driver in the lateral direction.

[0085] In some embodiments, the first line is formed by a first metal track that physically extends at least in the lateral direction, and the second line is formed by both a second metal track and a third metal track that physically extend at least in the lateral direction, wherein the first metal track and the third metal track are formed in a first metallization layer, and the second metal track is formed in a second, higher metallization layer.

[0086] As used herein, the terms “about” and “approximately” generally refer to the value of a given quantity that can vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term “about” can mean that the value of a given quantity varies within, for example, 10-30% of that value (e.g., +10%, ±20%, or ±30% of that value).

[0087] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis to design or modify other processes and structures to perform the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A memory circuit, comprising: A first memory array includes a plurality of first memory cells, each first memory cell being configured to operate at a first power supply voltage; The second memory array includes a plurality of second memory cells, each second memory cell being configured to operate at a second power supply voltage, the first power supply voltage and the second power supply voltage being different from each other; as well as The driver is operatively coupled to the plurality of first memory cells via a first access line and to the plurality of second memory cells via a second access line, respectively; The driver is configured to selectively provide a negative voltage on either the first access line or the second access line based on an address signal.

2. The memory circuit according to claim 1, wherein, The driver is physically closer to one of the first or second memory arrays in the lateral direction than the other of the first or second memory arrays.

3. The memory circuit according to claim 1, wherein, The driver is configured to apply the negative voltage to the first access line via a first transistor turned on by the address signal, while decoupling from the second access line via a second transistor turned off by the address signal.

4. The memory circuit according to claim 1, wherein, When the first memory array is located between the driver and the second memory array in the lateral direction, the first access line is formed by a first metal track that physically extends at least in the lateral direction, and the second access line is formed by both a second metal track and a third metal track that physically extend at least in the lateral direction.

5. The memory circuit according to claim 4, wherein, The first metal orbital and the third metal orbital are formed in the first metallization layer, while the second metal orbital is formed in the second and higher metallization layers.

6. The memory circuit according to claim 1, wherein, The first memory array is configured as a working memory group based on the address signal, causing the first access line to receive the negative voltage, while the second memory array is configured as an idle memory group based on the address signal, causing the second access line to float.

7. The memory circuit according to claim 1, further comprising: A logic gate is configured to provide a selection signal based on the address signal, wherein the address signal indicates whether the second memory array is selected as the working memory group; A first transistor is configured to decouple the driver from the first access line based on the selection signal; and The second transistor is configured to couple the driver to the second access line based on the selection signal.

8. A memory circuit, comprising: A first memory array includes a plurality of first memory cells coupled to each other via a first bit line; The second memory array includes a plurality of second memory cells coupled to each other via second bit lines; as well as A driver is operatively coupled to the first memory cell via the first bit line and to the second memory cell via the second bit line, wherein the first memory array and the second memory array are each physically positioned in a lateral direction relative to the driver; The driver is configured to decouple from the first bit line when the first memory array is configured as an idle memory group based on the address signal, and to apply a negative voltage to the second bit line when the second memory array is configured as a working memory group based on the address signal.

9. The memory circuit according to claim 8, wherein, When the first memory array is located between the driver and the second memory array in the lateral direction, the first bit line is formed by a first metal track that physically extends at least in the lateral direction, and the second bit line is formed by both a second metal track and a third metal track that physically extend at least in the lateral direction.

10. A method for operating a memory circuit, comprising: Receive an address signal indicating that the first memory array is a free memory group and the second memory array is a working memory group, wherein the free memory group is configured to operate with a lower power supply voltage and the working memory group is configured to operate with a higher power supply voltage. Based on the address signal, a selection signal is provided to disable the first multiplexer and trigger the second multiplexer; and The driver is decoupled from the free memory group by the first multiplexer that is turned off, so that the first bit line of the free memory group floats, while the driver is coupled to the working memory group by the second multiplexer that is triggered, so that a negative voltage is provided on the second bit line of the working memory group.

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