Low-voltage high-robustness 2t1r rram array structure and control method thereof

Abstract

The application relates to a low-voltage high-robustness 2T1R RRAM array structure, which is composed of k*n*m 2T1R units, each k*n 2T1R unit forms a sub-block, and each sub-block contains k rows and n columns of 2T1R units; in order to ensure multi-bit parallel read-write access of the array, each sub-block is additionally provided with k gating tubes, that is, in the row direction, every n 2T1R units share one gating tube S0; finally, each subarray (Subarray) is composed of one 2T1R sub-block and a group of gating tubes; through improvement of the array structure and increase of the gating tubes and peripheral computing tubes, the RRAM array can establish a reliable read operation path under low power voltage bias. The cross-coupled read structure can ensure that, within fixed access time, the high and low resistance states of the RRAM are converted into nearly rail-to-rail voltages at the input end of the sensitive amplifier, so that the read margin is improved.

Description

Technical Field

[0001] This invention proposes a low-voltage, high-robust 2T1R (two transistors and one RRAM device) RRAM array architecture and its control method. This array, by introducing a novel topology connection and bias strategy between the selector and the memory cell, aims to solve the reliability problems of traditional RRAM in low-power applications, such as reduced read / write tolerance and increased bit error rate due to lower operating voltage. This enables efficient and stable non-volatile data storage in ultra-low-power System-on-Chip (SoC). Background Technology

[0002] In the post-Moore's Law era, with the explosive growth of the Internet of Things (IoT), edge computing, and wearable devices, the energy efficiency ratio of chips has become a key indicator for measuring their core competitiveness. As an important carrier of in-memory computing and non-volatile memory, resistive random access memory (RRAM) is regarded as an effective solution to break through the "memory wall" due to its high integration, low power consumption for erasing and writing, and high compatibility with CMOS technology.

[0003] However, when applications shift to near-threshold or low-voltage supply environments, the robustness of RRAM (Resistive Random Access Memory) faces severe challenges. Currently, while the traditional 1T1R (one transistor and one RRAM device) architecture offers area advantages, it is highly susceptible to device resistance variation and interconnect parasitic voltage drop (IR drop) at low voltages. With process advancements, traditional 1T1R structures facing severe voltage headroom challenges when using current-based readout methods become extremely limited in voltage headroom. As supply voltage decreases, the voltage space for external sense amplifiers and bit line voltage drops becomes extremely restricted. This minimal voltage headroom makes it difficult for the readout circuit to accurately capture signals under noise interference, resulting in extremely poor robustness of the readout path to power supply fluctuations. Secondly, if voltage-based readout is used, the on-resistance of the transistor in the 1T1R interferes with resistance differentiation. Since its gate overdrive voltage also decreases with the supply voltage, the transistor is no longer in an ideal short-circuit state; its magnitude may even be similar to the low-resistance state (LRS) or even high-resistance state (HRS) of RRAM. This series resistance effect means that the overall resistance of the read branch may be dominated by the transistor, resulting in a contraction of the voltage swing at the detection end and a severe deterioration of the high-low configuration switching ratio of the array unit.

[0004] While the industry has attempted to enhance the robustness of low-voltage memory by introducing high-precision readout circuits or special array readout strategies, these methods typically come at the cost of complex circuit structures and additional power consumption. Therefore, achieving efficient reading of cells with limited switching ratios at the physical level by improving cell structure while maintaining array integration has become a key technology for realizing low-power, high-reliability non-volatile memory. Summary of the Invention

[0005] The purpose of this invention is to propose a low-voltage, high-robustness 2T1R RRAM array structure and its control method. This invention improves the array topology of the traditional 1T1R, changing its detection method during read operations. This structure can reliably read cells with limited switching ratios under lower power supply voltages. Furthermore, the cross-coupled positive feedback structure introduced into the read operation path further expands the read window and improves its read speed under low voltage.

[0006] This invention proposes a low-voltage, high-robust 2T1R RRAM array structure. This RRAM array consists of k*n*m 2T1R cells, with each k*n 2T1R cell forming a sub-block. Each sub-block contains k rows and n columns of 2T1R cells. To ensure multi-bit parallel read / write access, each sub-block is additionally equipped with k select transistors; that is, in the row direction, every n 2T1R cells share one select transistor S0. Finally, each subarray consists of a 2T1R sub-block and a set of select transistors. Specifically, the 2T1R sub-block is formed by connecting an RRAM device (R0) and two transistors (first transistor T0 and second transistor T1) in series. The series connection node between the RRAM device R0 and the first transistor T0 is connected to the drain of the second transistor T1. Within each subarray, the drain of the select transistor S0 in the row direction... The first transistor T0 of all 2T1R units is connected to the source; in the entire array, the gates of the second transistor T1 of all 2T1R units in the row direction are connected together to form the row word line signal RWL[0:k-1], and the gates of all the gate transistors S0 are connected together to form the row gating signal RSEL[0:k-1]; in the column direction, the gates of the T0 of all 2T1R units are connected together to form the column word line signal CWL[0:n*m-1], the sources of the second transistors T1 of all 2T1R units are connected together to form the column calculation signal RL[0:n*m-1], the non-serial nodes of the RRAM devices R0 of all 2T1R units are connected together to form the column bit line signal BL[0:n*m-1], and the sources of all the gate transistors S0 are connected together to form the column signal SL[0:m-1];

[0007] When accessing the array, the 2T1R RRAM array needs to work with a set of external compute transistors to distinguish between high and low impedance configurations. For each column cell of the 2T1R unit, the column word line CWL signal is connected to the drain of the compute transistor C0, and the column compute signal RL is connected to the gate of the compute transistor C0. At the same time, the source of the compute transistor C0 is grounded. The external circuit determines whether the selected RRAM cell is in a low impedance state or a high impedance state based on the degree of discharge of the compute transistor C0 to the column word line CWL.

[0008] The present invention proposes a control method for a low-voltage, high-robust 2T1R RRAM array structure, the specific steps of which are as follows:

[0009] When the array enters a read operation, all column line signals SL[0:m-1] are clamped to 0 level; the column word line signal CWL of the selected cell is pre-charged to the power supply voltage. After charging, the row word line signal RWL and the row strobe signal RSEL generate read pulses, and the column word line signal BL is pulled high to the power supply voltage. Under the above signal configuration, the second transistor T1 and the strobe transistor S0 act as enable switches, selecting one RRAM device in each subarray for access according to the column address. At this time, the read operation path of each RRAM device is simplified to a cross-coupled structure composed of RRAM device R0, T0 and computing transistor C0. After the CWL and RSEL signals arrive, the voltage division result between the first transistor T0 and RRAM device R0 determines the conduction state of computing transistor C0, thereby enabling the pre-charged column word line signal. The line signal CWL discharges to different degrees: If the RRAM device R0 has low resistance, the voltage value obtained by voltage division across the RRAM is low, causing the gate of the computing transistor C0 to be driven by a higher voltage, thus starting to discharge CWL; on the other hand, the gradually decreasing voltage of CWL will in turn weaken the conduction state of the first transistor T0, thus forming a positive feedback loop to further raise the gate voltage of the computing transistor C0; finally, within a certain read time, the voltage of CWL will be pulled to ground; if the RRAM device R0 has high resistance, a low voltage will be applied to the gate of the computing transistor C0, preventing it from completing the discharge of CWL within a given time; finally, the column word line CWL will be output to the input of the sensitive amplifier and the current resistance state of the RRAM will be determined based on the voltage sampled at the falling edge of the read pulse.

[0010] When the array enters a write operation, all row word line signals RWL[0:k-1] and column calculation signals RL[0:n*m-1] are clamped to 0 level, all calculation transistors C0 and all first transistors T1 are turned off; the gate transistor S0 of the selected cell remains on; each memory cell is configured as a conventional 1T1R structure: cell operation supports applying set and reset pulses to BL0 and SL0, while applying gate voltage to WL0.

[0011] The beneficial effects of this invention are as follows: By improving the array structure and adding selector transistors and peripheral computing transistors, the RRAM array can establish a reliable read operation path under low power supply voltage bias. The cross-coupled read structure ensures that within a fixed access time, the high and low impedance states of the RRAM are converted into near rail-to-rail voltages at the input of the sensitive amplifier, thereby improving its read margin.

[0012] With the common requirements of edge devices and neural computing for ultra-low power consumption, high reliability and biocompatible voltage windows, this low-voltage, high-robust RRAM array provides effective hardware support for building self-powered edge sensing systems, biomimetic neuromorphic computing cores and implantable brain-computer interface storage and processing units. Attached Figure Description

[0013] Figure 1 The structural diagram of the 2T1R RRAM array is given;

[0014] Figure 2 The circuit structure diagrams and related principles for reading and writing operations of the unit are given; (a) the circuit structure of the read / write operation cycle; (b) the cross-detection principle of the read operation cycle;

[0015] Figure 3 The results of 1000 Monte Carlo simulations are presented to compare the readings of the 2T1R cell and the 1T1R cell under low voltage conditions; high impedance 60K, low impedance 20K, (a) voltage mode reading, (b) current mode reading and (c) voltage of 2T1R cell (high impedance 60K, low impedance 20K);

[0016] Figure 4 Visualizations of the resistance programming and reading results for a 16x32 memristor array are presented. (a) Visualization of the resistance value of each cell after programming the memristor array (quantized by ADC), (b) Visualization of the resistance value after reading the memristor array. Detailed Implementation

[0017] The present invention will be further illustrated by the following examples.

[0018] Example 1:

[0019] like Figure 1As shown, each 2T1R cell consists of two gate transistors, where the first transistor T0 is connected in series with the RRAM device, and its series node is led out and connected to the second transistor T1. In the row direction: the gate interconnect of the second transistor T1 in each 2T1R cell forms the RWL signal; the source of the first transistor in every n 2T1R cells is connected to the drain of transistor S0; simultaneously, the gate interconnect of all gate transistors S0 in the row direction forms the RSEL signal. In the column direction: the RRAM terminals not connected to the first transistor T0 in each 2T1R cell are interconnected to form the BL signal; the gate interconnect of the first transistor T0 in each 2T1R cell forms the CWL signal; the source interconnect of the second transistor T1 in each 2T1R cell forms the RL signal; and the source interconnect of each gate transistor S0 forms the SL signal. At the array periphery, each column is equipped with a computing transistor C0. The gate of computing transistor C0 is connected to the column signal line RL, the drain of computing transistor C0 is connected to the column signal line CWL, and the source of computing transistor C0 is connected to ground.

[0020] like Figure 2 As shown, when entering a read operation, the array will be configured as follows: Figure 2 (a) In the top structure, all column line signals SL[0:m-1] are clamped to 0 level. The column signal CWL of the selected cell is pre-charged to the power supply voltage. After charging is complete, the row signal RWL and row signal RSEL generate read pulses, while the column signal BL is pulled high to the power supply voltage. At this time, the second transistor T1 and the gate transistor S0 act as enable switches, selecting one RRAM device in each subarray for access according to the column address. Figure 2 (b) The read operation path of each RRAM device is simplified to a cross-coupled structure consisting of RRAM device R0, first transistor T0, and computing transistor C0. After the CWL and RSEL signals arrive, the voltage division result between the first transistor T0 and RRAM device R0 determines the conduction state of computing transistor C0, thereby discharging the pre-charged column signal CWL to different degrees: if RRAM device R0 has low resistance, the voltage of CWL will be quickly pulled down to ground within a certain read time; if RRAM device R0 has high resistance, CWL cannot be completely discharged within the limited read time. Finally, the column signal CWL will be output to the input of the external sensitive amplifier, and the current resistance state of the RRAM will be determined based on the voltage sampled at the falling edge of the read pulse.

[0021] like Figure 3 As shown, the readout window of a traditional 1T1R array under low voltage is compared with that of the 2T1R array proposed in this invention. Through 1000 Monte Carlo simulations for low impedance 20KΩ and high impedance 60KΩ, the two readout methods of the 1T1R array are analyzed. Figure 3 (a) and Figure 3(b) exhibits poor margin, based on voltage readout mode. Figure 3 (a) Only a voltage window of less than 50mV, based on current readout mode Figure 3 (b) It has a current window of less than 1 μA. In contrast, Figure 3 (c) The reading window, which is close to the power supply voltage of 520mV, further illustrates that the 2T1R unit proposed in this invention has better robustness at low voltage.

[0022] like Figure 4 As shown, read and write operations are performed on 512 devices in a 2T1R array. Figure 4 (a) First, write operations are performed on all cells, and their resistance states are read through an off-chip analog-to-digital converter (ADC) circuit to output a visual interface. Due to process variations in RRAM, the specific resistance distribution varies, resulting in the output visual graphic text "RRAM" exhibiting a mixture of light and dark areas. Figure 4 (b) Visual output is performed using the 2T1R cell reading method proposed in this invention. Due to the expansion of the reading window and the enhanced robustness of cell reading, the output results are clearer.

Claims

1. A low-voltage, high-robust 2T1R RRAM array structure, characterized in that... The RRAM array consists of k*n*m 2T1R cells, with each k*n 2T1R cell forming a sub-block. Each sub-block contains k rows and n columns of 2T1R cells. To ensure multi-bit parallel read and write access, each sub-block is additionally equipped with k select transistors, meaning that in the row direction, every n 2T1R cells share one select transistor S0. Ultimately, each subarray consists of one 2T1R sub-block and a set of select transistors. Specifically, the 2T1R sub-block is formed by connecting one RRAM device (R0) and two transistors (first transistor T0 and second transistor T1) in series. The series connection node between the RRAM device R0 and the first transistor T0 is connected to the drain of the second transistor T1. Within each subarray, the drain of the row-direction select transistor S0 is connected to all... The source of the first transistor T0 of the 2T1R unit; in the entire array, the gates of the second transistors T1 of all 2T1R units in the row direction are connected together to form the row word line signal RWL[0:k-1], and the gates of all the gate transistors S0 are connected together to form the row gating signal RSEL[0:k-1]; in the column direction, the gates of the T0 of all 2T1R units are connected together to form the column word line signal CWL[0:n*m-1], the sources of the second transistors T1 of all 2T1R units are connected together to form the column calculation signal RL[0:n*m-1], the non-serial nodes of the RRAM devices R0 of all 2T1R units are connected together to form the column bit line signal BL[0:n*m-1], and the sources of all the gate transistors S0 are connected together to form the column signal SL[0:m-1]; When accessing the array, the 2T1R RRAM array needs to work with a set of external compute transistors to distinguish between high and low impedance configurations. For each column cell of the 2T1R unit, the column word line CWL signal is connected to the drain of the compute transistor C0, and the column compute signal RL is connected to the gate of the compute transistor C0. At the same time, the source of the compute transistor C0 is grounded. The external circuit determines whether the selected RRAM cell is in a low impedance state or a high impedance state based on the degree of discharge of the compute transistor C0 to the column word line CWL.

2. A control method for a low-voltage, high-robustness 2T1R RRAM array structure as described in claim 1, characterized in that... The specific steps are as follows: When the array enters a read operation, all column line signals SL[0:m-1] are clamped to 0 level; the column word line signal CWL of the selected cell is pre-charged to the power supply voltage. After charging is complete, the row word line signal RWL and the row strobe signal RSEL generate a read pulse, while the column bit line signal BL is pulled high to the power supply voltage; under the above signal configuration, the second transistor T1 and the strobe transistor S0 act as enable switches, selecting one RRAM device in each subarray for access according to the column address; at this time, the read operation path of each RRAM device is simplified to a cross-coupled structure composed of RRAM devices R0, T0 and computing transistor C0; After the CWL and RSEL signals arrive, the voltage division result between the first transistor T0 and the RRAM device R0 determines the conduction state of the computing transistor C0, thereby discharging the pre-charged column word signal CWL to different degrees: if the RRAM device R0 has low resistance, the voltage value obtained by the voltage division across the RRAM is low, causing the gate of the computing transistor C0 to be driven by a higher voltage, thus starting to discharge CWL; on the other hand, the gradually decreasing voltage of CWL will in turn weaken the conduction state of the first transistor T0, thus forming a positive feedback loop to further raise the gate voltage of the computing transistor C0; finally, within a certain read time, the voltage of CWL will be pulled to ground; if the RRAM device R0 has high resistance, a low voltage will be applied to the gate of the computing transistor C0, preventing it from completing the discharge of CWL within a given time; finally, the column word CWL will be output to the input of the sensitive amplifier and the current resistance state of the RRAM will be determined based on the voltage sampled at the falling edge of the read pulse. When the array enters a write operation, all row word line signals RWL[0:k-1] and column calculation signals RL[0:n*m-1] are clamped to 0 level, all calculation transistors C0 and all first transistors T1 are turned off; the gate transistor S0 of the selected cell remains on; each memory cell is configured as a conventional 1T1R structure: cell operation supports applying set and reset pulses to BL0 and SL0, while applying gate voltage to WL0.

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