Memory built-in self-test structure for specific soc platform
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NAT INNOVATION INST OF DEFENSE TECH PLA ACAD OF MILITARY SCI
- Filing Date
- 2026-04-14
- Publication Date
- 2026-08-07
AI Technical Summary
[0004]然而，超大规模集成电路一般使用嵌入式存储器模块，在此类电路外部可直接接触嵌入式存储器的管脚几乎没有，导致ATE很难通过外部管脚将测试激励写入存储器和由存储器读出测试数据
[0015]本发明提供的面向特定SoC平台的存储器内建自测试结构，通过联合测试工作组接口，建立自动测试设备与测试访问端口控制器模块间通路并转换信号，使得各模块协同工作，实现让特定系统级芯片平台集成的所有嵌入式存储器借助自动测试设备测试机台测试，提高测试效率。
Smart Images
Figure CN122531445A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of digital circuit testing technology, and more particularly to a memory-built-in self-test structure for a specific SoC platform. Background Technology
[0002] With the increasing integration and complexity of chips, complex and large-scale integrated circuit design projects must consider how to test the circuits in advance during the design phase. Design for testability requires that while the chip can perform normal functions, some circuitry should be added to achieve the purpose of testing, and the test circuitry module should not occupy too much power consumption and area.
[0003] Existing testing methods use automated test equipment (ATE) to write and read test stimuli to the internal circuitry of the chip via external pins. By comparing the written and read data, the correctness of the circuit function and the stability of its performance are determined.
[0004] However, very large-scale integrated circuits (VLSIs) typically use embedded memory modules. There are almost no external pins that can directly access the embedded memory, making it difficult for test equipment (ATE) to write test stimuli to and read test data from the memory using external pins. Furthermore, due to the large memory capacity, ATEs struggle to process the massive amounts of test data within a controllable timeframe, increasing the chip's testing time cost. Therefore, there is an urgent need for a memory-integrated self-test structure for specific SoC platforms to address these issues. Summary of the Invention
[0005] To address the problems existing in the prior art, this invention provides a memory-built-in self-test structure for a specific SoC platform.
[0006] This invention provides a memory-in-memory self-test architecture for a specific SoC platform, comprising a joint test workgroup interface, a test access port controller module, a memory-in-memory self-test control module, and a memory packaging module, wherein: The joint test workgroup interface is used to establish a test path between the automatic test equipment and the test access port controller module, and to convert the test signals sent by the automatic test equipment into corresponding joint test workgroup signals. The test access port controller module is used to determine the test mode to be executed or the data register information to be accessed based on the joint test working group signal. The memory has a built-in self-test control module, which is used to perform corresponding state machine control on the memory according to the control signal of the debug module interface, and to receive the test feedback results generated by the memory packaging module. The debug module interface control signal is obtained based on the signal conversion of the joint test working group. The memory encapsulation module is used to execute the corresponding memory built-in self-test function based on the data register information in the debug module interface control signal when the current state is determined to be the memory built-in self-test function start state.
[0007] According to the present invention, a memory-in-memory self-test structure for a specific SoC platform is provided, wherein the test access port controller module and the memory-in-memory self-test control module are connected via a clock domain conversion module, wherein: The clock domain conversion module is used to convert the joint test workgroup signal into the debug module interface control signal based on the debug module interface handshake protocol, and to convert the first clock signal into the second clock signal, wherein the first clock signal represents the slow clock signal output by the test access port controller module; and the second clock signal represents the high-speed clock signal of the chip's main frequency.
[0008] According to the present invention, a memory-built-in self-test structure for a specific SoC platform is provided, wherein the clock domain conversion module is specifically used for: During a read operation, when the debug module interface request valid signal and the debug module interface ready signal are both 1, the test access port controller module is allowed to send the corresponding read request data, and after one clock cycle, the debug module interface request valid signal is pulled low. When the debug module interface response valid signal and the debug module interface response ready signal are both 1, the built-in self-test control module of the memory is allowed to return the read status response result and read data.
[0009] According to a memory-built-in self-test structure for a specific SoC platform provided by the present invention, the clock domain conversion module is further used for: During a write operation, when the debug module interface request valid signal and the debug module interface ready signal are both 1, the test access port controller module is allowed to send the corresponding write request data, and after one clock cycle, the debug module interface request valid signal is pulled low.
[0010] According to the present invention, a memory-built-in self-test structure for a specific SoC platform is provided, wherein the test access port controller module includes a finite state machine, an instruction register, and a data register, wherein: The finite state machine is used to execute the corresponding state transition based on the mode selection signal; The instruction register is used to store the address of the data register and to determine the data register information based on the joint test working group signal; The data register is used to store test data or configuration parameters.
[0011] According to the present invention, a memory-in-memory self-test structure for a specific SoC platform is provided, wherein the memory-in-memory self-test control module is specifically used for: When the current state is determined to be the memory built-in self-test function start state, the debug module interface request valid signal is pulled high; when the debug module interface ready signal is 1, the debug module interface request valid signal is pulled low, and the data register information is sent to the corresponding memory encapsulation module to start the memory built-in self-test function.
[0012] According to the present invention, a memory-in-memory self-test structure for a specific SoC platform is provided, wherein the memory-in-memory self-test control module is further configured to: When the current state is determined to be the start state of the built-in self-test function of the memory, if the debug module interface request valid signal is 1, the built-in self-test enable signal of the memory is pulled high; and based on the data register information, the memory package module to be started in the current test is determined. When the current state is determined to be the waiting state of the built-in self-test function in the memory, the received test completion status signal or test not started signal is written to the corresponding target register. When the test completion status signal or the test not started signal is 1, the debug module interface ready signal is pulled high, and reading new test request addresses is stopped. The memory built-in self-test function waiting for return status is switched to the memory built-in self-test function waiting for upload status. When the current state is determined to be the waiting state for the built-in self-test function of the memory to upload, if the debug module interface responds with a ready signal of 1, the value corresponding to the test result is written into the target register. The test results of all the memory packaging modules in the current test are received as the test feedback results and sent to the clock domain conversion module. The memory built-in self-test function is switched from the waiting upload state to the start state of the memory built-in self-test function.
[0013] According to the present invention, a memory-in-memory self-test structure for a specific SoC platform is provided. The memory packaging module includes a multiplexer, a test stimulus generator, an address generator, and a response comparator, wherein: The multiplexer is used to switch the data path between test mode and normal operation mode; The test stimulus generator is used to generate a pseudo-random test sequence based on the March algorithm, wherein the pseudo-random test sequence is used to trigger the corresponding fault type of the memory. The address generator is used to traverse the address sequence of all memory cells in the memory and perform corresponding read and write operations on each memory cell. The response comparator is used to compare the actual test output of the memory with the preset test response, and to determine the fault test status of the memory based on the comparison result.
[0014] According to the present invention, a memory-built-in self-test structure for a specific SoC platform is provided, wherein the fault types include fixed faults, transition faults, write interference faults, read destruction faults, erroneous read faults, pseudo-read destruction faults, state coupling faults, interference coupling faults, transition coupling faults, read destruction coupling faults, pseudo-read destruction coupling faults, and erroneous read coupling faults.
[0015] The present invention provides a built-in self-test structure for memory on a specific SoC platform. Through the joint test workgroup interface, it establishes a path between the automatic test equipment and the test access port controller module and converts signals, enabling the modules to work together. This allows all embedded memories integrated into a specific system-on-a-chip platform to be tested using an automatic test equipment test bench, thereby improving test efficiency. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0017] Figure 1 This is a schematic diagram of a memory-built-in self-test structure for a specific SoC platform provided by the present invention. Figure 2 This is a schematic diagram of the overall architecture of the memory-built-in self-test structure provided by the present invention. Figure 3 This invention provides a timing diagram for the clock domain conversion module's cross-clock processing. Figure 4 A schematic diagram of the internal structure of the test access port controller module provided by the present invention; Figure 5 This is a schematic diagram of the state transition of the built-in self-test control module in the memory provided by the present invention. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0019] Embedded memory modules are widely used in very large-scale integrated circuits (VLSI). However, these circuits have significant drawbacks: the pins of the embedded memory are almost impossible to access directly from the outside, making it difficult for test equipment (ATE) to write test stimuli to the memory via external pins or read test data from it. Furthermore, due to the enormous memory capacity, the ATE struggles to process the massive amounts of test data within a manageable timeframe, significantly increasing the chip's testing time cost. Therefore, for embedded memories in VLSI, the Memory Built-in Self-test (MBIST) technique can be employed.
[0020] This invention targets the aforementioned specific System-on-Chip (SoC) platform. The testing sequence for embedded memory conforms to the design structure from top to bottom, significantly reducing testing time. Furthermore, it employs fully custom embedded memory modules during the design phase to meet the high-frequency requirements of the specific SoC platform.
[0021] Figure 1 This is a schematic diagram of a memory-built-in self-test structure for a specific SoC platform provided by the present invention, as shown below. Figure 1 As shown, this invention provides a memory-in-memory self-test structure for a specific SoC platform, including a joint test workgroup interface 101, a test access port controller module 102, a memory-in-memory self-test control module 103, and a memory packaging module 104, wherein: The joint test workgroup interface 101 is used to establish a test path between the automatic test equipment and the test access port controller module 102, and to convert the test signals sent by the automatic test equipment into corresponding joint test workgroup signals. The test access port controller module 102 is used to determine the test mode to be executed or the data register information to be accessed based on the joint test work group signal. The memory has a built-in self-test control module 103, which is used to perform corresponding state machine control on the memory according to the debug module interface control signal, and to receive the test feedback result generated by the memory packaging module 104. The debug module interface control signal is obtained based on the signal conversion of the joint test working group. The memory encapsulation module 104 is used to execute the corresponding memory built-in self-test function based on the data register information in the debug module interface control signal when the current state is determined to be the memory built-in self-test function start state.
[0022] In this invention, the Joint Test Action Group (JTAG) interface 101 with built-in self-test structure in the memory adopts the functions of the standard JTAG protocol interface and is responsible for establishing the test path between the Automated Test Equipment (ATE) and the Test Access Port (TAP) controller module 102.
[0023] In certain SoC platforms (such as VLSI), data can be input from the JTAG pin through the standard JTAG protocol interface, converting the test signals sent by the ATE into corresponding joint test workgroup signals. This enables signal interaction between the ATE and subsequent modules, building a bridge for signal transmission for the entire test process and ensuring that the test signals can be accurately transmitted to the test access port controller module 102.
[0024] In this invention, the test access port controller module 102 determines the test mode to be executed or the data register information to be accessed based on the received joint test workgroup signals. The test access port controller module 102 internally includes a finite state machine (FSM), an instruction register (IR), and a data register (DR), where the value of the IR register determines the data register or other path to be accessed. By analyzing and processing the joint test workgroup signals, the test access port controller module 102 accurately locates the test requirements, clarifying which test mode to execute or which data register to access, thereby providing clear instructions and direction for subsequent test operations.
[0025] The memory has a built-in MBIST Control (MBC) module 103, which executes corresponding state machine control on the memory based on the control signals from the debug module interface (these signals are derived from the joint test working group signal conversion and are MBIST logic control signals). Furthermore, the built-in MBIST control module 103 is also responsible for receiving test feedback results generated by the memory packaging module 104.
[0026] The memory wrapper module 104 (i.e., the SRAM_Wrapper module, which can be abbreviated as SW) includes circuits such as a multiplexer, a test stimulus generator, an address generator, and a response comparator. Figure 2 This is a schematic diagram of the overall architecture of the memory-built-in self-test structure provided by the present invention, which can be referred to. Figure 2 As shown, when the current state is determined to be the memory built-in self-test function start state, the memory packaging module 104 executes the corresponding memory built-in self-test function based on the data register information in the debug module interface control signal. For example, the test stimulus generator generates the stimulus signal required for the test, the address generator generates the corresponding address signal, the multiplexer selects the appropriate signal path, and the response comparator compares the actual response of the memory with the expected response, thereby realizing the testing of various functions of the memory, completing the main function of MBIST testing, and ensuring that the memory can work normally and stably in the SoC platform.
[0027] For reference Figure 2 As shown, the built-in self-test structure of the memory includes multiple memory package modules (such as SW_0, SW_1, ..., SW_N and SW_0', SW_1', ..., SW_N'), which belong to different chains (chain 0 and chain n). Each memory package module receives control signals from the MBC, executes the test function, and returns the test feedback results to the MBC. Furthermore, each memory package module has interface signals such as mb_en (enable signal), mb_start (start signal), mb_done (completion signal), and mb_fail (failure signal) for communication with the MBC.
[0028] The present invention provides a built-in self-test structure for memory on a specific SoC platform. Through the joint test workgroup interface, it establishes a path between the automatic test equipment and the test access port controller and converts signals, enabling the modules to work together. This allows all embedded memories integrated into a specific system-on-a-chip platform to be tested using an automatic test equipment test bench, thereby improving test efficiency.
[0029] Based on the above embodiments, the test access port controller module and the memory-built-in self-test control module establish a connection through a clock domain conversion module, wherein: The clock domain conversion module is used to convert the joint test workgroup signal into the debug module interface control signal based on the debug module interface handshake protocol, and to convert the first clock signal into the second clock signal, wherein the first clock signal represents the slow clock signal output by the test access port controller module; and the second clock signal represents the high-speed clock signal of the chip's main frequency.
[0030] In this invention, reference may be made to Figure 2 As shown, in the built-in self-test structure of the system-on-a-chip platform's memory, the test access port controller module (TAP) is tested. Figure 2 (Not specifically shown in the text) The memory built-in self-test control module (MBC) is not directly connected, but rather established through a clock domain conversion module (i.e., dtm_mbist_ctrl). This connection method is to solve the problems of clock signal mismatch and signal protocol conversion between different modules, ensuring that test signals can be transmitted accurately and stably in different clock domains and different protocol environments, thereby guaranteeing the normal implementation of the memory built-in self-test function.
[0031] Specifically, the clock domain conversion module employs the Debug Module Interface (DMI) handshake protocol. This protocol defines the rules and procedures for signal interaction between the Test Access Port Controller (TAP) module and the Memory Built-in Self-Test (MBIST) control module. When the TAP receives joint test workgroup signals from the Joint Test Workgroup Interface (JIT) interface, these signals contain information such as test modes and test commands. The clock domain conversion module, according to the DMI handshake protocol, parses and processes these JIT signals, converting them into DMI control signals—specifically, MBIST logic control signals—that can be recognized and executed by the MBIST control module.
[0032] For example, when initiating a memory test, the test access port controller module receives a joint test workgroup signal indicating the start of the test. The clock domain conversion module identifies this signal via a handshake protocol and converts it into the control signal required by the memory's built-in self-test control module to start the test, thereby triggering the memory's built-in self-test control module to initiate the corresponding test process.
[0033] The slow clock signal output by the test access port controller module typically originates from the Joint Test Workgroup interface (such as the JTAG interface). Since the JTAG interface is primarily used for connecting external test equipment and transmitting test signals, its operating frequency is relatively low to meet the operational requirements of external devices. Therefore, the clock signal (the first clock signal) corresponding to the signal received by the test access port controller module from the JTAG interface is a slow clock signal.
[0034] The high-speed clock signal of the chip's main frequency is the clock signal used by all modules inside the chip to operate normally. Its high frequency ensures that the chip can process various data and instructions quickly and efficiently. The built-in self-test control module in the memory, as an important module inside the chip, needs to operate under the high-speed clock signal of the chip's main frequency to ensure the real-time performance and accuracy of the test.
[0035] In this invention, the clock domain conversion module, while performing signal protocol conversion, is also responsible for converting the first clock signal (slow clock signal) into the second clock signal (high-speed clock signal). This conversion process requires consideration of matching parameters such as the frequency and phase of the clock signal to avoid problems such as clock jitter and clock skew, ensuring stable signal transmission between different clock domains. This enables the built-in self-test control module of the memory to quickly and accurately execute various test operations under the drive of the high-speed clock signal, improving test efficiency.
[0036] Based on the above embodiments, the clock domain conversion module is specifically used for: During a read operation, when the debug module interface request valid signal and the debug module interface ready signal are both 1, the test access port controller module is allowed to send the corresponding read request data, and after one clock cycle, the debug module interface request valid signal is pulled low. When the debug module interface response valid signal and the debug module interface response ready signal are both 1, the built-in self-test control module of the memory is allowed to return the read status response result and read data.
[0037] In this invention, the clock domain conversion module undertakes the crucial task of coordinating signal interaction and clock domain conversion between the test access port controller module and the memory-built-in self-test control module. Since the test access port controller module operates in a slow clock domain, while the memory-built-in self-test control module uses a full-speed clock (the high-speed clock of the main frequency), the clock domain conversion module needs to implement cross-clock domain processing to ensure accurate data transmission and correct execution of operations under different clock domains, especially in controlling relevant signals during read and write operations.
[0038] During a read operation, when both the debug module interface request valid signal (dmi_req_valid) and the debug module interface ready signal (dmi_req_ready) are 1, it indicates that the debug module interface is ready to receive data, and the test access port controller module has data to send. At this time, the clock domain conversion module allows the test access port controller module to send the corresponding read request data, which typically includes information such as address (addr) and operation type (op). After one clock cycle, the debug module interface request valid signal is pulled low to ensure signal stability and operational correctness. For example, data transmission is completed within one clock cycle, and then the request valid signal is promptly pulled low to avoid timing issues that might arise from a continuously valid signal, while also preparing for the next operation.
[0039] When both the debug module interface response valid signal (dmi_resp_valid) and the debug module interface response ready signal (dmi_resp_ready) are 1, it indicates that the memory-built-in self-test control module is ready to return data, and the debug module interface can receive data. At this time, the clock domain conversion module allows the memory-built-in self-test control module to return the read status response result (e.g., SUCCESS indicates successful operation) and the read data. This process ensures that the result of the read operation can be accurately transmitted from the memory-built-in self-test control module to the test access port controller module, completing the feedback loop of the read operation.
[0040] Based on the above embodiments, the clock domain conversion module is further used for: During a write operation, when the debug module interface request valid signal and the debug module interface ready signal are both 1, the test access port controller module is allowed to send the corresponding write request data, and after one clock cycle, the debug module interface request valid signal is pulled low.
[0041] In this invention, when both the debug module interface request valid signal and the debug module interface ready signal are 1, similar to a read operation, it indicates that the system is in a state where data can be sent. The clock domain conversion module allows the test access port controller module to send the corresponding write request data, including information such as address (addr), data to be written (data), and operation type (op). Similarly, the debug module interface request valid signal is pulled low after one clock cycle to ensure correct timing. Unlike a read operation, a write operation does not require waiting for data return. That is, after the test access port controller module sends the write request data, it does not need to pay attention to the return information from the memory's built-in self-test control module. The clock domain conversion module can end the relevant signal processing flow for this write operation after completing the control of sending the write request data.
[0042] Figure 3 The timing diagram for cross-clock processing of the clock domain conversion module provided by this invention can be referred to. Figure 3 As shown, during a read operation, in the request phase: when both dmi_req_valid and dmi_req_ready are high, it indicates that the debug module interface is ready to receive data, and the test access port controller module has read request data to send. At this time, dmi_req.op is "READ", and dmi_req.addr is the requested address (e.g., "0x12").
[0043] After one clock cycle, the dmi_req_valid signal is pulled low to ensure signal stability and operational correctness, avoid timing issues that may be caused by a continuously valid signal, and prepare for the next operation.
[0044] Response Phase: When both dmi_resp_valid and dmi_resp_ready are high, it indicates that the memory's built-in self-test control module is ready to return data, and the debug module interface can receive data. At this time, dmi_resp.resp is "SUCCESS", indicating that the read operation was successful, and dmi_resp.data is the data read (such as "0x1234").
[0045] During the write operation, in the request phase: When both dmi_req_valid and dmi_req_ready are high, it indicates that the system is ready to send data. At this time, dmi_req.op is "WRITE", dmi_req.addr is the address to be written (e.g., "0x34"), and dmi_req.data is the data to be written (e.g., "0xabcd"). After one clock cycle, the dmi_req_valid signal is also pulled low to ensure correct timing.
[0046] No-response phase: Unlike read operations, write operations do not require waiting for data to return. After the test access port controller module sends the write request data, it does not need to pay attention to the return information from the memory's built-in self-test control module. The clock domain conversion module can end the relevant signal processing flow for this write operation after completing the control of sending the write request data.
[0047] In this invention, the clock domain conversion module, through the DMI handshake protocol, strictly follows the interaction of the aforementioned timing control signals to achieve data transmission and operation control between the test access port controller module (operating in the slow clock domain) and the memory-built-in self-test control module (operating in the high-speed clock domain). This mechanism ensures stable signal transmission between different clock domains, enabling the memory-built-in self-test function to execute normally and accurately, thus improving testing efficiency and reliability.
[0048] Based on the above embodiments, the test access port controller module includes a finite state machine, an instruction register, and a data register, wherein: The finite state machine is used to execute the corresponding state transition based on the mode selection signal; The instruction register is used to store the address of the data register and to determine the data register information based on the joint test working group signal; The data register is used to store test data or configuration parameters.
[0049] In this invention, the finite state machine plays a core control role in the test access port controller module, driving the various components of the TAP and simultaneously directing the instruction register and data register. To implement a standard TAP controller, this invention employs a 16-state finite state machine.
[0050] Finite state machines (FSMs) use the Test Mode Select (TMS) signal to execute corresponding state transitions. The TMS signal provides different instructions at different times, and the FSM transitions from one state to another based on these instructions. For example, during JTAG testing, by changing the level of the TMS signal, the FSM can switch between 16 states in a predetermined logical sequence, thereby controlling the progress of the entire test process. This includes transitions from the idle state to the instruction register scan state, and then to the instruction register capture state. Each state transition corresponds to a specific test operation stage, ensuring the test process proceeds smoothly.
[0051] In this invention, the primary function of the instruction register is to store the addresses of the data registers. The test access port controller module contains multiple data registers, each with its own specific address. The instruction register stores this address information to provide a basis for subsequently selecting the data register to access. The instruction register determines the data register information based on signals from the joint test workgroup.
[0052] Upon receiving a signal from the joint test workgroup, the instruction register parses the corresponding data register address information based on the instruction content in the signal. For example, when an external test device sends a specific test instruction via the JTAG interface, the instruction register receives the instruction and converts it into the corresponding data register address, thereby determining the data register to be accessed subsequently for appropriate test operations or data read / write.
[0053] Data registers are used to store test data or configuration parameters. During the built-in memory self-test, test data is used to stimulate the memory for testing; for example, a specific binary sequence is written to the memory to check if its storage and retrieval functions are normal. Configuration parameters are used to set parameters for the test environment or test method, such as the selection of the test mode (all 0 test, all 1 test, etc.) and the test address range.
[0054] During testing, once the instruction register determines the data register to be accessed, the test access port controller module will, based on specific test requirements, read test data from the data register and send it to the memory for testing, or write external configuration parameters to the data register to adjust the test parameter settings. For example, during memory read / write tests, the test data stored in the data register will be sent to the memory, and the memory's response data may also be read and stored in the data register for subsequent analysis and determination of whether the memory is functioning correctly.
[0055] Figure 4 This is a schematic diagram of the internal structure of the test access port controller module provided by the present invention, which can be referred to. Figure 4 As shown, the Finite State Machine (FSM), as the core control unit of the TAP controller, executes corresponding state transitions based on the Test Mode Select (TMS) signal, Test Clock (TCK), and Reset Signal (TRST). The FSM drives the various components of the TAP, directing the operations of the instruction register and data register. Based on the level changes of the TMS signal, the FSM switches between 16 states in a predetermined logical sequence. For example, it transitions from the idle state to the instruction register scan state, and then to the instruction register capture state. Each state transition corresponds to a specific test operation stage, ensuring the test process proceeds smoothly.
[0056] In this invention, the finite state machine receives the TMS signal, TCK and TRST, and outputs control signals to the instruction register and data register to coordinate the entire TAP controller's workflow.
[0057] The Instruction Register stores the address of the data register and determines the data register information based on the Joint Test Team (JTAG) signal (input via the Test Data Input Interface (TDI)). Related operation instructions include Capture-IR, Shift-IR, and Update-IR.
[0058] Furthermore, the instruction information output from the instruction register is decoded and converted into specific control signals to select the corresponding data register or execute specific test operations.
[0059] The data register, including the DTMCS-32-bit register and the Debug Register-1-bit register, is used to store test data or configuration parameters. Data is received via TDI and output via the Test Data Output (TDO) interface, the operation of which is controlled by the instruction decoding module.
[0060] The TAP controller interacts with the DMI0 module via a data register. During testing, the data register can store data read from or written to the DMI0 module, including configuration parameters and test data. For example, during memory testing, the data register can retrieve test configuration information from the DMI0 module or send the memory test results to the DMI0 module for further processing.
[0061] Through the above structure and process, the TAP controller realizes the processing of test commands and test data, providing basic control and data transmission functions for test operations such as memory-built-in self-test, and uses the test data or configuration parameters to complete the precise control of the memory-built-in self-test function.
[0062] Based on the above embodiments, the built-in self-test control module of the memory is specifically used for: When the current state is determined to be the memory built-in self-test function start state, the debug module interface request valid signal is pulled high; when the debug module interface ready signal is 1, the debug module interface request valid signal is pulled low, and the data register information is sent to the corresponding memory encapsulation module to start the memory built-in self-test function.
[0063] In this invention, the Memory Built-in Self-Test Control Module (MBC) is the control module for the memory built-in self-test structure. It connects to the Test Access Port Controller Module (TAP) via a Clock Domain Conversion Module (dtm_mbist_ctrl) to receive DMI signals and feedback test results. These signals and feedback test results are implemented by a state machine converted from an algorithm, controlling the entire memory built-in self-test structure's read / write operations, address generation, and multiplexing signals.
[0064] Figure 5 The state transition diagram of the built-in self-test control module in the memory provided by this invention can be referred to. Figure 5 As shown, when the built-in self-test control module determines that the current state is the built-in self-test function start state (START state), it will pull up the debug module interface request valid signal (dmi_req_valid) to inform the relevant module (such as the corresponding memory packaging module) that data transmission and test start operations are about to begin. In one embodiment, pulse_1=1 (a pulse signal used to trigger a specific operation or event) between "START" and "WAIT_done" represents a trigger condition or signal used to control the transition of the state machine. Specifically, pulse_1=1 is the condition for transitioning from the "START" state to the "WAIT_done" state. When this condition is met, i.e., the pulse_1 signal is 1, the state machine will transition from the "START" state to the "WAIT_done" state.
[0065] When the debug module interface ready signal (dmi_req_ready) is 1, it indicates that the debug module interface is ready to receive data. At this time, the built-in memory self-test control module pulls low the debug module interface request valid signal and sends the data register information to the corresponding memory package module (SRAM_Wrapper). The data register information contains key information such as register addresses. In this way, the memory package module to be activated for the built-in memory self-test function is precisely specified, thereby initiating the corresponding test function. For example, a specific address in the data register information corresponds to an SRAM_Wrapper on a certain scan chain. When this address information is sent to the corresponding memory package module, that module will start running the built-in memory self-test function according to the preset procedure.
[0066] Based on the above embodiments, the built-in self-test control module of the memory is also used for: When the current state is determined to be the start state of the built-in self-test function of the memory, if the debug module interface request valid signal is 1, the built-in self-test enable signal of the memory is pulled high; and based on the data register information, the memory package module to be started in the current test is determined. When the current state is determined to be the waiting state of the built-in self-test function in the memory, the received test completion status signal or test not started signal is written to the corresponding target register. When the test completion status signal or the test not started signal is 1, the debug module interface ready signal is pulled high, and reading new test request addresses is stopped. The memory built-in self-test function waiting for return status is switched to the memory built-in self-test function waiting for upload status. When the current state is determined to be the waiting state for the built-in self-test function of the memory to upload, if the debug module interface responds with a ready signal of 1, the value corresponding to the test result is written into the target register. The test results of all the memory packaging modules in the current test are received as the test feedback results and sent to the clock domain conversion module. The memory built-in self-test function is switched from the waiting upload state to the start state of the memory built-in self-test function.
[0067] In this invention, reference may be made to Figure 5 As shown, when the current state is determined to be the start state of the built-in self-test function (IDLE state), if the debug module interface request valid signal is 1, the built-in self-test control module will pull up the built-in self-test enable signal, and the address data will be directly pulled from the port.
[0068] Based on the data register information, the built-in self-test control module of the memory can determine the memory package module to be started for the current test. The signal (dmi_req_i==mb_start[i]) is 10 bits wide. Each bit in the data register information may correspond to a memory package module SRAM_Wrapper on the scan chain. By judging the value of the data bit (when it is set to 1, it corresponds to the SRAM_Wrapper enabling the MBIST function), the memory package module that needs to be started for the test can be accurately identified, thus preparing for subsequent test operations.
[0069] When the current state is determined to be the WAIT_done state (waiting for return from the built-in self-test function), the built-in self-test control module will write the received test completion status signal (done[i]) or test not started signal (not start[i]) into the corresponding target register (MBC0 register). These signals reflect the test status of each memory package module, and writing them into the register facilitates the unified management and analysis of the test results later.
[0070] When the test completion status signal or test not started signal is 1, it indicates that a memory packaging module has completed the test or has not started the test. At this time, the built-in self-test control module will raise the debug module interface ready signal and stop reading new test request addresses. It will switch the built-in self-test function waiting for return status to the built-in self-test function waiting to upload status (WAIT_resp), indicating that the system has entered the stage of preparing to upload test results from the stage of waiting for test results to return.
[0071] When the current state is determined to be the memory built-in self-test function waiting to upload, if the debug module interface responds with a ready signal (dmi_resp_ready) of 1, the memory built-in self-test control module will write the value corresponding to the test result into the target register (MBC0 register), thereby organizing and storing the test results of each memory package module. Further, the memory built-in self-test control module will send the received test results of all memory package modules in the current test as test feedback results to the clock domain conversion module. Then, the memory built-in self-test function waiting to upload state will be switched to the memory built-in self-test function start state, returning the system to its initial state and preparing for the next test, forming a complete test cycle.
[0072] Through the operations in each of the above states, the built-in self-test control module of the memory achieves precise control over the built-in self-test process of the memory, ensuring that the test can proceed smoothly according to the predetermined logic and sequence, and providing timely feedback on the test results.
[0073] Based on the above embodiments, the memory packaging module includes a multiplexer, a test stimulus generator, an address generator, and a response comparator, wherein: The multiplexer is used to switch the data path between test mode and normal operation mode; The test stimulus generator is used to generate a pseudo-random test sequence based on the March algorithm, wherein the pseudo-random test sequence is used to trigger the corresponding fault type of the memory. The address generator is used to traverse the address sequence of all memory cells in the memory and perform corresponding read and write operations on each memory cell. The response comparator is used to compare the actual test output of the memory with the preset test response, and to determine the fault test status of the memory based on the comparison result.
[0074] In this invention, the multiplexer in the memory packaging module acts as a data path switcher, enabling flexible switching between test mode and normal operation mode. In normal operation mode, the multiplexer connects the memory to other normal data paths of the SoC system, allowing the memory to perform regular data storage and retrieval operations according to design requirements, thus serving the normal functional operation of the SoC.
[0075] When entering test mode, the multiplexer quickly switches the data path to the test-related path, connecting test modules such as the test stimulus generator and address generator to perform comprehensive testing of the memory. For example, upon receiving a test start signal, the multiplexer switches the path originally connected to the external data bus to the path connected to the test stimulus generator according to the control signal, allowing test data to be successfully input into the memory.
[0076] In this invention, the test stimulus generator (test_data_generation) is based on the March algorithm and can generate various pseudo-random test sequences. The March algorithm is a series of classic algorithms used for memory testing, and different variants of the March algorithm correspond to different test requirements and fault coverage. The test stimulus generator automatically generates the corresponding pseudo-random test sequences according to the specific March algorithm used and the logic and steps specified by the algorithm.
[0077] In this invention, the generated pseudo-random test sequences have specific patterns and characteristics, designed to stimulate various types of potential memory faults. For example, certain test sequences can detect fixed faults (memory cells are always 0 or 1), transition faults (memory cells cannot transition normally during read / write operations), and coupling faults (the state of one memory cell affects the state of another). By writing these test sequences into the memory, hidden faults can be effectively exposed, providing a basis for subsequent fault diagnosis and repair.
[0078] The address generator (BIST_March_C_plus module and BIST_March_LR module) is used to traverse the address sequence of all memory cells in the memory, generating the address of each memory cell sequentially according to a certain order and pattern, ensuring that the test can cover every corner of the memory. For example, a linear increment method can be used, starting from the starting address of the memory and gradually increasing the address value until the maximum address of the memory is reached.
[0079] While generating the address of each memory cell, the address generator also performs corresponding read and write operations on each memory cell according to the test requirements. During the write operation, the test data generated by the test stimulus generator is written to the corresponding memory cell; during the read operation, data is read from the memory cell for subsequent comparison with the preset test response. In this way, the read and write functions of the memory at different addresses are comprehensively tested to ensure they are functioning correctly.
[0080] The response comparator compares the actual test output of the memory with a preset test response. The preset test response is a theoretical output result predetermined based on the adopted test algorithm and test sequence. After the memory completes a read / write operation, its output data is transmitted to the response comparator and compared bit by bit with the preset test response. Based on the comparison result, the response comparator can determine the memory's fault test status. If the actual test output is completely consistent with the preset test response, it indicates that the memory is working normally under that test item; if there is a difference, it indicates that the memory may be faulty. The response comparator feeds back the comparison result to the memory's built-in self-test control module for further analysis and recording of memory fault information, providing important reference for subsequent fault location and repair.
[0081] This invention achieves comprehensive and effective built-in self-test functionality for embedded memory through the coordinated operation of multiplexers, test stimulus generators, address generators, and response comparators in the memory packaging module, ensuring that the memory can work stably and reliably in the SoC system.
[0082] In this invention, two March algorithms (March C+ and March LR) are implemented to test and cover various fault types in fully custom memories. The covered fault types specifically include fixed faults, transition faults, write interference faults, read corruption faults, erroneous read faults, pseudo-read corruption faults, state coupling faults, interference coupling faults, transition coupling faults, read corruption coupling faults, pseudo-read corruption coupling faults, and erroneous read coupling faults. For example, a fixed fault manifests as a memory cell or signal line remaining fixed in a logic 0 or logic 1 state, unable to change its state during normal write operations. This fault leads to errors in data storage and retrieval, compromising data integrity and causing inconsistencies between the data obtained and the actual data written. A transition fault manifests as a fault occurring when a memory cell transitions from one state to another, affecting the read / write speed and accuracy of the memory. In operations requiring frequent changes to memory cell states, this can lead to data errors or operation failures.
[0083] These fault types cover a variety of abnormal situations that may occur in memory. By designing corresponding test sequences and algorithms in the built-in self-test of memory, these faults can be effectively detected to ensure the reliability and stability of memory.
[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A memory-built-in self-test structure for a specific SoC platform, characterized in that, This includes a joint test workgroup interface, a test access port controller module, a memory-built-in self-test control module, and a memory encapsulation module, among which: The joint test workgroup interface is used to establish a test path between the automatic test equipment and the test access port controller module, and to convert the test signals sent by the automatic test equipment into corresponding joint test workgroup signals. The test access port controller module is used to determine the test mode to be executed or the data register information to be accessed based on the joint test working group signal. The memory has a built-in self-test control module, which is used to perform corresponding state machine control on the memory according to the control signal of the debug module interface, and to receive the test feedback results generated by the memory packaging module. The debug module interface control signal is obtained based on the signal conversion of the joint test working group. The memory encapsulation module is used to execute the corresponding memory built-in self-test function based on the data register information in the debug module interface control signal when the current state is determined to be the memory built-in self-test function start state.
2. The memory-built-in self-test structure for a specific SoC platform according to claim 1, characterized in that, The test access port controller module and the memory-built-in self-test control module are connected via a clock domain conversion module, wherein: The clock domain conversion module is used to convert the joint test workgroup signal into the debug module interface control signal based on the debug module interface handshake protocol, and to convert the first clock signal into the second clock signal, wherein the first clock signal represents the slow clock signal output by the test access port controller module; and the second clock signal represents the high-speed clock signal of the chip's main frequency.
3. The memory-built-in self-test structure for a specific SoC platform according to claim 2, characterized in that, The clock domain conversion module is specifically used for: During a read operation, when the debug module interface request valid signal and the debug module interface ready signal are both 1, the test access port controller module is allowed to send the corresponding read request data, and after one clock cycle, the debug module interface request valid signal is pulled low. When the debug module interface response valid signal and the debug module interface response ready signal are both 1, the built-in self-test control module of the memory is allowed to return the read status response result and read data.
4. The memory-built-in self-test structure for a specific SoC platform according to claim 2, characterized in that, The clock domain conversion module is also used for: During a write operation, when the debug module interface request valid signal and the debug module interface ready signal are both 1, the test access port controller module is allowed to send the corresponding write request data, and after one clock cycle, the debug module interface request valid signal is pulled low.
5. The memory-built-in self-test structure for a specific SoC platform according to claim 2, characterized in that, The test access port controller module includes a finite state machine, an instruction register, and a data register, wherein: The finite state machine is used to execute the corresponding state transition based on the mode selection signal; The instruction register is used to store the address of the data register and to determine the data register information based on the joint test working group signal; The data register is used to store test data or configuration parameters.
6. The memory-built-in self-test structure for a specific SoC platform according to claim 2, characterized in that, The built-in self-test control module of the memory is specifically used for: When the current state is determined to be the memory built-in self-test function start state, the debug module interface request valid signal is pulled high; when the debug module interface ready signal is 1, the debug module interface request valid signal is pulled low, and the data register information is sent to the corresponding memory encapsulation module to start the memory built-in self-test function.
7. The memory-built-in self-test structure for a specific SoC platform according to claim 6, characterized in that, The built-in self-test control module of the memory is also used for: When the current state is determined to be the start state of the built-in self-test function of the memory, if the debug module interface request valid signal is 1, the built-in self-test enable signal of the memory is pulled high; and based on the data register information, the memory package module to be started in the current test is determined. When the current state is determined to be the waiting state of the built-in self-test function in the memory, the received test completion status signal or test not started signal is written to the corresponding target register. When the test completion status signal or the test not started signal is 1, the debug module interface ready signal is pulled high, and reading new test request addresses is stopped. The memory built-in self-test function waiting for return status is switched to the memory built-in self-test function waiting for upload status. When the current state is determined to be the waiting state for the built-in self-test function of the memory to upload, if the debug module interface responds with a ready signal of 1, the value corresponding to the test result is written into the target register. The test results of all the memory packaging modules in the current test are received as the test feedback results and sent to the clock domain conversion module. The memory built-in self-test function is switched from the waiting upload state to the start state of the memory built-in self-test function.
8. The memory-built-in self-test structure for a specific SoC platform according to claim 2, characterized in that, The memory packaging module includes a multiplexer, a test stimulus generator, an address generator, and a response comparator, wherein: The multiplexer is used to switch the data path between test mode and normal operation mode; The test stimulus generator is used to generate a pseudo-random test sequence based on the March algorithm, wherein the pseudo-random test sequence is used to trigger the corresponding fault type of the memory. The address generator is used to traverse the address sequence of all memory cells in the memory and perform corresponding read and write operations on each memory cell. The response comparator is used to compare the actual test output of the memory with the preset test response, and to determine the fault test status of the memory based on the comparison result.
9. The memory-built-in self-test structure for a specific SoC platform according to claim 8, characterized in that, The fault types include fixed faults, transition faults, write interference faults, read destruction faults, erroneous read faults, pseudo-read destruction faults, state coupling faults, interference coupling faults, transition coupling faults, read destruction coupling faults, pseudo-read destruction coupling faults, and erroneous read coupling faults.