Memory and electronic device

Abstract

The application provides a memory and an electronic device; the memory comprises a logic chip and at least one storage chip stacked on the logic chip; the storage chip and the logic chip are connected through a plurality of interconnection structures and realize signal transmission; the logic chip comprises a plurality of data transmission ends and a plurality of read data detection modules corresponding to the data transmission ends one by one; in a test mode, the logic chip receives a read command, and the read data detection module reads a plurality of first test data stored in the storage chip through a plurality of interconnection structures; the read data detection module comprises an operation unit; the operation unit is used for performing at least one operation processing on the plurality of first test data to obtain operation data and storing the operation data.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a memory and electronic device. Background Technology

[0002] With the development of 3D stacked memory technology, logic chips and at least one memory chip in the memory are vertically interconnected through multiple interconnect structures such as through-silicon vias (TSVs), and data is transmitted between the logic chips and memory chips through the interconnect structures. To ensure the reliability of data transmission, it is necessary to detect the state of the interconnect structures in the memory.

[0003] In related technologies, testing interconnect structures typically requires the acquisition, transmission, and analysis of multiple test data streams one by one. The test results depend on multiple data outputs and external judgments. For stacked memories with high parallelism, this testing method results in long test data processing links, large data transmission volumes, and time-consuming testing processes, leading to low overall testing efficiency and making it difficult to meet the rapid testing requirements of high-density interconnect structures. Summary of the Invention

[0004] This disclosure provides a memory and an electronic device.

[0005] In a first aspect, embodiments of this disclosure provide a memory, the memory including a logic chip and at least one storage chip stacked on the logic chip; the storage chip and the logic chip are connected through multiple interconnect structures to realize signal transmission; The logic chip includes: multiple data transmission terminals and multiple read data detection modules corresponding one-to-one with each of the data transmission terminals; The read data detection module is configured such that, in test mode, the logic chip receives a read command, and the read data detection module reads multiple first test data stored in the storage chip through multiple interconnect structures; The read data detection module includes: a processing unit; The computation unit is used to perform at least one computation on multiple sets of the first test data to obtain computation data and to store the computation data.

[0006] In some embodiments, the logic chip further includes a test interface circuit connected to the arithmetic unit, which is used to read the arithmetic data and compare the arithmetic data with expected data. If the arithmetic data is consistent with the expected data, a first comparison result is output, indicating that there is no fault. If the arithmetic data is inconsistent with the expected data, a second comparison result is output, indicating that there is a fault.

[0007] In some embodiments, the read data detection module further includes a clock processing unit connected to the input terminal corresponding to the arithmetic unit. The clock processing unit is used to generate a clock signal so that the arithmetic unit outputs the arithmetic data to the test interface circuit according to the clock signal.

[0008] In some embodiments, the clock processing unit is an up-frequency clock unit used to generate an up-frequency clock signal.

[0009] In some embodiments, the up-frequency clock unit includes a first edge generating circuit, a second edge generating circuit, and a pulse synthesis circuit; The output of the first edge generating circuit is connected to the first input of the pulse synthesis circuit, and is used to generate a first pulse signal based on the first transition edge of the reference clock signal. The output of the second edge generating circuit is connected to the second input of the pulse synthesis circuit, and is used to generate a second pulse signal based on the second transition edge of the reference clock signal; The pulse synthesis circuit is used to synthesize the first pulse signal and the second pulse signal to obtain the up-frequency clock signal.

[0010] In some embodiments, the read data detection module further includes a data receiving and processing module for receiving the first test data and outputting multiple multiplexed signals.

[0011] In some embodiments, the data receiving and processing module includes multiple demultiplexing units and corresponding signal multiplexing units; The demultiplexing unit is used to perform multi-phase demultiplexing on the corresponding first test data to obtain multiple demultiplexed signals; The signal multiplexing unit is used to perform time-series multiplexing of multiple demultiplexed signals to obtain the multiplexed signal; The arithmetic unit is also used to receive multiple multiplexed signals and perform arithmetic processing to obtain the arithmetic data.

[0012] In some embodiments, the multiple input terminals of the arithmetic unit are used to receive multiple multiplexed signals and perform arithmetic processing on them respectively to obtain the arithmetic data. The arithmetic unit includes multiple cascaded arithmetic subunits, and the arithmetic subunits correspond one-to-one with the multiplexed signals. Each of the above-level operation subunits receives the corresponding multiplexed signal at its input terminal. In the case of having a previous-level operation subunit, each operation subunit also receives the initial operation data output by the previous-level operation subunit, and performs another operation on the corresponding multiplexed signal and the initial operation data output by the previous-level operation subunit to obtain the initial operation data of the current operation subunit.

[0013] In some embodiments, the read data detection module is further configured to convert multiple parallel initial operation data into serial operation data.

[0014] In some embodiments, the computation unit is a compression unit, the computation data is compressed data, and the compression unit is used to perform at least one non-carry superposition of multiple first test data to obtain the compressed data.

[0015] In some embodiments, the compression unit includes a serial conversion subunit; The serial conversion subunit includes multiple parallel input interfaces, which are respectively connected to the output terminals of multiple arithmetic subunits. The serial conversion subunit is used to receive the initial arithmetic data output by the multiple arithmetic subunits and combine the received initial arithmetic data into serial compressed data.

[0016] In some embodiments, the serial conversion subunit includes cascaded selection transmission circuits, each of the selection transmission circuits including a selector and a transmission circuit, and the selector corresponds one-to-one with the operation subunit; The first input terminal of the selector is connected to the output terminal of the corresponding operation subunit, and the second input terminal of the selector is connected to the output terminal of the previous stage transmission circuit. When the selector receives a selection signal at the selection input terminal, the selector is used to output the initial operation data output by the current operation subunit indicated by the selection signal to the current transmission circuit, or to output the initial operation data output by the previous stage transmission circuit indicated by the selection signal. The initial operation data output by the last transmission circuit is used as the compressed data.

[0017] In some embodiments, the operation subunit is a superposition subunit, and each level of the superposition subunit includes a superposition circuit and an operation data output circuit; The first input terminal of the superposition circuit is connected to the output terminal of the previous-level computational data output circuit, the second input terminal of the superposition circuit is connected to the output terminal of the data receiving and processing module, and the output terminal of the superposition circuit is connected to the input terminal of the current-level computational data output circuit. The superposition circuit is used to receive the multiplexed signal, and, in the case of having the previous-level computational data output circuit, to receive the initial computational data output by the previous-level computational data output circuit, and to perform computational processing on the corresponding multiplexed signal and the initial computational data output by the previous-level superposition subunit to obtain the initial computational data of the current superposition circuit. The output terminal of the computational data output circuit is connected to the first input terminal of the next-level superposition circuit, and is used to receive the clock signal and output the initial computational data according to the clock signal.

[0018] In some embodiments, the superimposed circuit includes a first logic gate, a second logic gate, and a third logic gate, wherein the output terminal of the first logic gate is connected to the first input terminal of the third logic gate, and the output terminal of the second logic gate is connected to the second input terminal of the third logic gate. The first logic gate is used to receive the initial operation data output by the previous operation data output circuit through the first input terminal, and when the first indication signal is received at the second input terminal at the first level, output the inverted signal of the initial operation data output by the previous superposition subunit to obtain the first superposition data; The second logic gate is used to receive the corresponding multiplexed signal through the first input terminal, and when the second indication signal received at the second input terminal is at the first level, output the inverted signal of the corresponding multiplexed signal to obtain the second data to be superimposed; The third logic gate is used to output the initial operation data of the current superposition circuit when the first data to be superimposed is different from the second data to be superimposed.

[0019] In some embodiments, the logic chip further includes: The write data module, connected to the data transmission terminal, is configured to write the first test data to the memory chip through the interconnect structure when a write command is received in the test mode.

[0020] In some embodiments, the memory chip further includes a data temporary storage unit; The read data detection module is further configured such that, in normal mode, when the logic chip receives a read command, the read data detection module reads the data in the data temporary storage unit through multiple interconnect structures; The write data module is also configured such that, in normal mode, the logic chip receives a write command, and the write data module writes data to the data temporary storage unit through multiple interconnect structures.

[0021] In a second aspect, embodiments of this disclosure provide an electronic device including a memory as described in the first aspect; and a test module connected to the memory via a test interface for testing at least one interconnect structure in the memory.

[0022] This disclosure provides a memory and an electronic device that, in test mode, receives a read command through a logic chip, enabling a read data detection module to read multiple first test data stored in the memory chip via multiple interconnect structures, and then processes the data to obtain computational data for verifying the state of each path in the memory chip. This reduces the external transmission and path-by-path analysis of multiple test data, shortens the detection link, and thus improves the efficiency of detecting interconnect structures. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a memory architecture provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the structure of a logic chip and a memory chip in a memory provided in an embodiment of this disclosure; Figure 3 This is a circuit diagram of a logic chip provided in an embodiment of this disclosure; Figure 4 This is a circuit diagram of a logic chip with an added data receiving and processing module and a clock processing unit provided in an embodiment of this disclosure; Figure 5 This is a circuit diagram of a data receiving and processing module provided in an embodiment of this disclosure; Figure 6 This is a circuit diagram of an operational subunit provided in an embodiment of this disclosure; Figure 7 This is a circuit diagram of a serial conversion subunit provided in an embodiment of this disclosure; Figure 8 This is a circuit diagram of a clock processing unit provided in an embodiment of this disclosure; Figure 9 This is a waveform diagram of the signals within the logic chip provided in an embodiment of this disclosure. Detailed Implementation

[0024] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the relevant applications and are not intended to limit the scope of this disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0026] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0027] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0028] In particular, the illustrations presented in this disclosure are not intended to be actual views of any particular microelectronic device or its components, but are merely idealized representations for describing illustrative embodiments, and therefore the illustrations are not necessarily drawn to scale.

[0029] In the description of the embodiments of this disclosure, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0030] In this disclosure, "electrical connection" or "electrical connection" refers to the ability of corresponding modules to transmit information via electrical signals. In specific implementations, "electrical connection" can be a direct connection between corresponding modules via wires, or an indirect connection between corresponding modules via other circuit structures.

[0031] In related technologies, in memory-integrated self-test (WBT) or integrated circuit testing, test data is typically read from the memory and sent to a Multiple-Input Signature Register (MISR). The MISR performs a signature generation operation on the test data and compares the result with a preset signature to determine if there are any functional abnormalities in the memory. However, since the MISR itself does not have a read function, this detection method requires pre-collected data for subsequent signature analysis and result determination, making it difficult to quickly process data on the read path. Especially in stacked memories with high parallelism, test data corresponding to multiple interconnect structures often needs to be collected and processed separately, resulting in a long overall test process, low test efficiency, and difficulty in meeting the rapid testing requirements of high-density interconnect structures.

[0032] See Figure 1 This illustrates a schematic diagram of the structure of a memory provided in an embodiment of this disclosure. Figure 1 As shown, the memory includes a logic chip 100 and at least one memory chip 200 stacked on the logic chip 100; the memory chip 200 and the logic chip 100 are connected through multiple interconnect structures 300 to realize signal transmission.

[0033] The interconnect structure 300 may be a through-silicon via (TSV) for transmitting read and write data between the logic chip 100 and the memory chip 200. The memory chip 200 includes a core array 210. The core array 210 is used to store service data, and in this embodiment, it is also used to store test data for testing (the first test data presented below).

[0034] See Figure 2 The logic chip 100 includes: multiple data transmission terminals 120 and multiple read data detection modules 110 corresponding to each data transmission terminal 120.

[0035] In some embodiments, each data transmission terminal 120 can be electrically connected to the memory cell array 210 in the memory chip 200 through a corresponding interconnect structure 300 to receive data output by the memory chip 200. Each read data detection module 110 can operate in parallel or in groups according to a preset timing sequence to adapt to detection requirements with different parallel bit widths or different test frequencies. The number of data transmission terminals 120 can be set according to the amount of data that the memory cell array 210 can store; for example, one data transmission terminal 120 and a corresponding read data detection module 110 can be set for each byte.

[0036] The read data detection module 110 is configured such that, in test mode, when the logic chip 100 receives a read command, the read data detection module 110 reads multiple first test data stored in the storage chip 200 through multiple interconnect structures 300.

[0037] It should be noted that the test mode can be a Multiple Input Signature Register (MISR) mode. MISR mode refers to a specific working mode that uses MISR to compress and sign test results. The read data detection module 110 can perform calculations on the first test data based on the MISR. The MISR typically only has data reception and compression functions and does not have the function of actively reading data. In this embodiment, by responding to a read command in test mode, the read data detection module 110 (which includes an internal MISR architecture) adds an active read function. The read data detection module 110 can capture multiple channels of first test data from the interconnect structure 300 and determine whether there is a fault in the memory on the read data path based on the first test data.

[0038] In some embodiments, the logic chip 100 further includes: The write data module 130, connected to the data transmission terminal 120, is configured to write first test data to the memory chip 200 through the interconnect structure 300 when a write command is received in test mode.

[0039] The data reading and detection module 110 includes: a processing unit 111.

[0040] The arithmetic unit 111 is used to perform at least one arithmetic operation on multiple first test data to obtain arithmetic data and to store the arithmetic data.

[0041] See Figure 3 The diagram illustrates a circuit diagram of a memory provided in an embodiment of this disclosure. The data transmission terminal 120 includes a write bus driver 122 and a read bus driver 121. When the logic chip 100 receives a write command, the write bus driver 122 writes the data (such as first test data) to the memory chip 200 via the interconnect structure 300. When the logic chip 100 receives a read command, the read bus driver 121 receives the data (such as the first test data) read from the memory chip 200 via the interconnect structure 300, shapes and drives it, and then sends it to the arithmetic unit 111.

[0042] Furthermore, under the Loopback Test Mode specified in relevant storage standards (such as the JEDEC standard), when the mode opcode (e.g., mode register MR7 OP[5:3] bits) is configured to indicate a specific value for the Multiple Input Signature Register Mode (MISR mode), the MISR circuit only performs operations and compression on the data generated by the write command. Since the main function of MISR is to train and verify the data link between the host and the memory device, rather than verifying the correctness of the contents of the memory storage unit, this process does not require the participation of read operations. Additionally, the data source for write operations is deterministic (generated by the host), while the data for read operations originates from the storage unit and may be affected by changes in the storage unit's state (such as read corruption, data retention errors, etc.). If the read data is also compressed into the MISR, the uncertainty of the signature will increase significantly, making it difficult to distinguish between link problems and storage unit problems, thus losing the efficiency of MISR as a link testing method. In the JEDEC standard, the MISR mode usually exists as an independent test mode. Its design goal is to achieve fast link integrity detection with minimal hardware overhead. Supporting both read and write compression simultaneously requires additional selectors and control logic, and necessitates waiting for data return after the read operation before compression, increasing test latency and hardware complexity. Supporting only write-direction compression allows for simpler test instructions and more efficient execution. Therefore, existing technologies intentionally limit MISR mode design to write operation compression to achieve rapid training and testing of the link.

[0043] In this embodiment, an additional test interface signal (e.g., setting the 1500WDR Config signal to an active state, such as setting it to the number 1) can be configured as a read command, enabling the arithmetic unit 111 to not only process write data but also add the function of reading commands in multi-input signature register mode. Upon receiving a read command, the arithmetic unit 111 can receive the data read by each read command, directly perform superposition operations on the read data, compress it, and store it in the arithmetic unit 111. Thus, further analysis can detect the transmission of data in the read path direction.

[0044] See Figure 3In test mode, write commands and read commands can be sent to logic chip 100 sequentially. For example, the host sends write and read commands to logic chip 100. When logic chip 100 receives a write command, write data module 130 transmits the first test data to write bus driver 122. Write bus driver 122 drives the first test data to the corresponding location in memory chip 200 via interconnect structure 300. Specifically, the first test data can be driven to memory cell array 210 in memory chip 200. When the logic chip 100 receives a read command, it parses the read command and transmits the parsed read instruction signal to the memory chip 200. Then, it reads the first test data from the memory chip 200. The read bus driver 121 in the logic chip 100 reads the first test data from multiple locations in the memory chip 200 via the interconnect structure 300 and transmits it to the corresponding arithmetic unit 111. Specifically, when the logic chip 100 receives a read command, transmitting the read instruction signal to the memory chip 200 can be done by transmitting it to the memory cell array 210 of the memory chip 200, and then reading the first test data from the memory cell array 210.

[0045] In some embodiments, see Figure 3 The arithmetic unit 111 also includes a data selector 112. The first input of the data selector 112 is electrically connected to the output of the read bus driver 121, the second input is electrically connected to the write data module 130, and the output is electrically connected to the input of the arithmetic subunit 410. The data selector 112 receives a configuration signal and selects one of the written data and read data to input into the arithmetic subunit 410 according to the configuration signal. In test mode, the data selector 112 can select to input read data (first test data) into the arithmetic subunit 410.

[0046] It should be noted that, since the interface of the interconnect structure 300 typically operates at extremely high data rates, directly processing the raw, high-speed "first test data" can easily lead to timing violations or sampling errors. Therefore, a demultiplexing and remultiplexing mechanism can be implemented on the first test data to ensure accurate data processing. The circuit of the read data detection module 110 after adding the demultiplexing and remultiplexing mechanism on the first test data is as follows: Figure 4 As shown, it includes a data receiving and processing module 420, a clock processing unit 440, and an arithmetic unit 111, wherein the arithmetic unit 111 includes an arithmetic subunit 410 and a serial conversion subunit 430.

[0047] In some embodiments, the read data detection module 110 further includes a data receiving and processing module 420, which is used to receive the first test data and output multiple multiplexed signals.

[0048] In some embodiments, the multiplexed signal can be obtained by first down-processing and then up-processing: First, the high-speed read first test data is demultiplexed in real time in multiple phases to ensure accurate signal capture. For example, the first test data is sampled by odd-even cross-sampling to obtain odd-phase demultiplexed signals and even-phase demultiplexed signals. However, demultiplexing inevitably causes the first test signal to split into multiple parallel branch signals. If one-to-one parallel operation is performed on multiple branch signals, the required processing unit 111 will be too large, occupying too much chip area. Therefore, after the demultiplexed signal capture is completed, the branch signals are multiplexed at the time level to re-aggregate the multiple parallel signals into a multiplexed signal on a limited number of lines, which can balance the reliable sampling of high-speed data and the area occupied by the test circuit. Alternatively, the multiplexed signal can be obtained by first up-processing and then down-processing, or by obtaining a multiplexed signal with a constant frequency; no limitation is made here.

[0049] For example, the input terminal of the data receiving and processing module 420 is electrically connected to the output terminal of the read bus driver 121, and the output terminal of the data receiving and processing module 420 is electrically connected to the input terminal of the data selector 112.

[0050] In some embodiments, the data receiving and processing module 420 includes a plurality of demultiplexing units 421 and corresponding signal multiplexing units 422; Demultiplexing unit 421 is used to perform multi-phase demultiplexing on the corresponding first test data to obtain multiple demultiplexed signals; Signal multiplexing unit 422 is used to perform time-sequential multiplexing of multiple demultiplexed signals to obtain multiplexed signals; The arithmetic unit 111 is also used to receive multiple multiplexed signals and perform arithmetic processing to obtain arithmetic data.

[0051] by Figure 5 For example, multiple demultiplexed signals can be odd-phase demultiplexed signals and even-phase demultiplexed signals. Demultiplexing unit 421 includes an even-phase processing branch and an odd-phase processing branch.

[0052] The even-phase processing branch includes a first XOR gate 501 and a first flip-flop 502. The first flip-flop 502 can be a D flip-flop with a reset terminal (the port receiving RstN). The output of the first XOR gate 501 is connected to the input of the first flip-flop 502. Since the memory chip 200 can perform Data Bus Inversion (DBI) on the read data during high-speed data reading to reduce losses, a data bus inversion module (not shown in the figure) can be included in the peripheral link of the memory chip. Therefore, the first test data may have undergone data bus inversion before reaching the demultiplexing unit 421. The inversion flag signal generated during data bus inversion needs to restore the first test data to its original state. Therefore, the first input of the first XOR gate 501 receives the even-phase demultiplexing signal RdDq_E, and the second input of the first XOR gate 501 receives the even-phase demultiplexing inversion flag signal Rdbi_E. The first XOR gate 501 performs data toggling decoding on the even-phase demultiplexed signal RdDq_E and the even-phase demultiplexed toggle flag signal Rdbi_E. Subsequently, the clock terminal of the first flip-flop 502 receives the even clock signal RCLKE and, triggered by the even clock signal RCLKE, performs stable sampling on the decoded data, outputting the first demultiplexed signal DataE, which is aligned in the internal clock domain due to frequency reduction.

[0053] The odd-phase processing branch includes a second XOR gate 503 and a second flip-flop 504, wherein the output of the second XOR gate 503 is connected to the input of the second flip-flop 504. The first input of the second XOR gate 503 receives the odd-phase demultiplexed signal RdDq_O, and the second input receives the odd-phase demultiplexed toggle flag signal Rdbi_O. The second XOR gate 503 performs data toggle decoding on the odd-phase demultiplexed signal RdDq_O and the odd-phase demultiplexed toggle flag signal Rdbi_O. Subsequently, the clock input of the second flip-flop 504 receives the odd clock signal RCLKO, and under the trigger of the odd clock signal RCLKO, it performs stable sampling on the decoded data and outputs the second demultiplexed signal DataO, which is aligned in the internal clock domain due to frequency downsampling.

[0054] It should be noted that the even-phase demultiplexing toggle flag signal Rdbi_E and the odd-phase demultiplexing toggle flag signal Rdbi_O are two phase flag signals formed by sampling the toggle flag signal in even and odd phases respectively after receiving the toggle flag signal generated by the data bus toggle module. The demultiplexing unit 421 performs toggle recovery on the even-phase demultiplexing signal RdDq_E and the odd-phase demultiplexing signal RdDq_O through the first XOR gate 501 and the second XOR gate 503 respectively, which can simultaneously test the data bus toggle function in the memory chip.

[0055] SeeFigure 5 The signal multiplexing unit 422 includes a first NAND gate 505, a second NAND gate 506 and a third NAND gate 507.

[0056] Specifically, the first input of the first NAND gate 505 is connected to the output of the first flip-flop 502 to receive the first demultiplexed signal DataE, the second input of the first NAND gate 505 receives the first gating control signal RCLKE_d, and the output of the first NAND gate 505 is connected to the first input of the third NAND gate 507. The first gating control signal RCLKE_d can be obtained by precisely delaying the dual clock signal RCLKE.

[0057] The first input of the second NAND gate 506 is connected to the output of the second flip-flop 504 to receive the second demultiplexed signal DataO. The second input of the second NAND gate 506 receives the second gating control signal RCLKEN_d. The output of the second NAND gate 506 is connected to the second input of the third NAND gate 507. The second gating control signal RCLKEN_d can be the inverted signal of the first gating control signal RCLKE_d.

[0058] By alternately enabling the first gating control signal RCLKE_d and the second gating control signal RCLKEN_d, the signal multiplexing unit 422 alternately samples and splices the parallel first demultiplexed signal DataE and the second demultiplexed signal DataO in timing, and performs logic synthesis through the third NAND gate 507. The third NAND gate 507 outputs the rearranged multiplexed signal MisrIn.

[0059] It should be noted that, since the multiple demultiplexed signals are sorted into a standard timing pulse stream for single-wire transmission through the demultiplexing unit 421 and the signal multiplexing unit 422, the arithmetic unit 111 can perform continuous arithmetic processing on the multiplexed signals without having to set up a corresponding hardware architecture for each demultiplexed signal, thus reducing the chip area required for high-speed interface testing.

[0060] In some embodiments, the multiple input terminals of the arithmetic unit 111 are used to receive multiple multiplexed signals and perform arithmetic processing on them respectively to obtain arithmetic data. The arithmetic unit 111 includes multiple cascaded arithmetic subunits 410, and the arithmetic subunits 410 correspond one-to-one with the multiplexed signals. Each operation subunit 410 receives a corresponding multiplexed signal at its input terminal. In the case of a previous operation subunit 410, each operation subunit 410 also receives the initial operation data output by the previous operation subunit 410, and performs the corresponding multiplexed signal and the initial operation data output by the previous operation subunit 410 for further operation processing to obtain the initial operation data of the current operation subunit 410.

[0061] In some embodiments, the arithmetic unit 111 receives multiple multiplexed signals. The arithmetic unit 111 includes multiple cascaded arithmetic subunits 410. The input terminals of each arithmetic subunit 410 receive their respective multiplexed signals and perform arithmetic processing to obtain arithmetic data. To achieve compression of multiplexed signals and save hardware overhead, the arithmetic unit 111 includes multiple cascaded arithmetic subunits 410 in its physical structure, that is, the number of arithmetic subunits 410 is the same as the number of multiplexed signals. Each arithmetic subunit 410 receives multiplexed signals. When it has a previous-level arithmetic subunit 410, the current-level arithmetic subunit 410 also receives the initial arithmetic data output by the previous-level arithmetic subunit 410. When it does not have a previous-level arithmetic subunit 410, it receives the initial arithmetic data output by the last-level arithmetic subunit 410 (for simplicity, it will be referred to as the previous-level initial arithmetic data). In other words, the multiple cascaded operation subunits 410 include a first operation subunit 410, a second operation subunit 410, a third operation subunit 410, ..., an Nth operation subunit 410 connected sequentially. The first operation subunit 410 is the parent operation subunit 410 of the second operation subunit 410, the second operation subunit 410 is the parent operation subunit 410 of the third operation subunit 410, ..., the (N-1)th operation subunit 410 is the parent operation subunit 410 of the Nth operation subunit 410, and so on. Therefore, the Nth operation subunit 410 is the parent operation subunit 410 of the first operation subunit 410. The operation subunit 410 performs logical-dimensional reprocessing on the multiplexed signal MisrIn it receives and the initial operation data Shiftbit from the previous level, thereby integrating the information from these two paths to obtain the initial operation data for the current-level operation subunit 410, which is then passed to the next-level operation subunit 410 for execution.

[0062] In some embodiments, the operation subunit 410 is a superposition subunit, and each superposition subunit includes a superposition circuit 411 and an operation data output circuit 412. The first input terminal of the superposition circuit 411 is connected to the output terminal of the previous level operation data output circuit 412, the second input terminal of the superposition circuit 411 is connected to the output terminal of the data receiving and processing module 420, and the output terminal of the superposition circuit 411 is connected to the input terminal of the current level operation data output circuit 412. The superposition circuit 411 is used to receive multiplexed signals, and when the previous level operation data output circuit 412 is present, to receive the initial operation data output by the previous level operation data output circuit 412, and to perform operation processing on the corresponding multiplexed signals and the initial operation data output by the previous level superposition subunit to obtain the initial operation data of the current superposition circuit 411. The output terminal of the computation data output circuit 412 is connected to the first input terminal of the next stage superposition circuit 411 to receive the clock signal and output the initial computation data according to the clock signal.

[0063] In some embodiments, the superposition circuit 411 performs calculations on the multiplexed signal MisrIn and the initial operation data Shiftbit from the previous stage to obtain the initial operation data for the current stage. Subsequently, the initial operation data is synchronized by the operation data output circuit 412. The operation data output circuit 412 receives the MISR clock signal CkMisr, which is matched with the operation subunit 410, through its clock input, and transitions according to the effective edge of the clock signal, stably latching and outputting the calculated initial operation data MisrQ to the next stage.

[0064] See Figure 6 The operational data output circuit 412 includes a third flip-flop 511. The third flip-flop 511 receives the MISR clock signal CkMisr via a clock input. At the moment the MISR clock signal CkMisr transitions, the initial operational data MisrQ received at the first input is captured and refreshed to the output (Q input) to avoid crosstalk between the previous and next data, thus ensuring high fidelity in long-distance cascaded transmission. It should be noted that the third flip-flop 511 is also configured with independent set input SetN and reset input RstN. Before testing, the data in the operational subunit 410 can be cleared by pulling all reset inputs RstN low, or specific initial test data can be burned in by controlling the level of the set input SetN in the third flip-flop 511 of a specific operational subunit 410.

[0065] In some embodiments, the superposition circuit 411 includes a first logic gate, a second logic gate and a third logic gate, wherein the output terminal of the first logic gate is connected to the first input terminal of the third logic gate, and the output terminal of the second logic gate is connected to the second input terminal of the third logic gate. The first logic gate is used to receive the initial operation data output by the previous operation data output circuit 412 through the first input terminal, and when the first indication signal is received at the second input terminal at the first level, output the inverted signal of the initial operation data output by the previous superposition subunit to obtain the first superposition data; The second logic gate is used to receive the corresponding multiplexed signal through the first input terminal, and when the second indicator signal received at the second input terminal is at the first level, output the inverted signal of the corresponding multiplexed signal to obtain the second data to be superimposed; The third logic gate is used to output the initial operation data of the current superposition circuit 411 when the first data to be superimposed is different from the second data to be superimposed.

[0066] byFigure 6 For example, the circuit structure of the arithmetic subunit 410 is shown. Each arithmetic subunit 410 can be implemented using a built-in multi-input signature register (MISR). Specifically, the first logic gate in the superposition circuit 411 is a fourth NAND gate 508, the second logic gate is a fifth NAND gate 509, and the third logic gate is a third XOR gate 510. The arithmetic data output circuit 412 includes a third flip-flop 511. The first input of the fourth NAND gate 508 serves as the first input of the superposition circuit 411, connected to the output of the third flip-flop 511 in the previous arithmetic subunit 410, and is used to receive the initial arithmetic data Shiftbit from the previous stage. The second input of the fourth NAND gate 508 receives the first mode configuration signal M0. The first input of the fifth NAND gate 509 serves as the second input of the superposition circuit 411, connected to the output of the data receiving and processing module 420, and is used to receive the multiplexed signal MisrIn. The second input of the fifth NAND gate 509 receives the second mode configuration signal M1.

[0067] It should be noted that the first mode configuration signal M0 and the second mode configuration signal M1 are received from the global combination control word of the chip test status controller (e.g., the IEEE 1500 test access port). By configuring the level combination of (M0, M1), different operating modes of the operation subunit 410 can be switched. For example, when both the first mode configuration signal M0 and the second mode configuration signal M1 are at the first level, i.e., M0=1, M1=1, the initial operation data Shiftbit and the multiplexed signal MisrIn of the previous stage are both selected and sent to the third XOR gate 510 for operation. This mode is used for data collection for dynamic fault testing of the interconnect structure 300. When the test sampling period ends and the test results need to be read, the second mode configuration signal M1 can be switched to the second level (logic 0). At this time, the multiple operation subunits 410 are serial shift registers. In this mode, the initial operation data latched in each operation subunit 410 can be output through the end-to-end shift path.

[0068] As an example, we will use three operational subunits 410 for illustration. For ease of description, Q2 will be referred to as the next-level operational subunit 410 above Q0. This indicates a no-carry addition operation, and the output of each operation subunit 410 is represented as: new Q0 = old Q2. New D0, New Q1 = Old Q0 New D1, New Q2 = Old Q1 New D2, where Q0, Q1, and Q2 are the outputs of different operation sub-units 410, and D0, D1, and D2 are the inputs (i.e., multiplexed signals) of different operation sub-units 410. Assume that the ideal 4-step multiplexed signals are [1,0,1], [0,1,1], [1,1,0], and [0,0,1]. The data stored in the third flip-flop 511 of each operation sub-unit 410 for the first step signal is [1,0,1]. The data stored in the third flip-flop 511 for the second, third, and fourth steps are [1,0,1], [0,0,0], and [0,0,1], respectively.

[0069] Taking the example that the multiplexed signal received by the first operation subunit 410 in the second phase changes from 0 to 1, the multiplexed signal in the second phase is [1,1,1]. The data stored in the third flip-flop 511 in each operation subunit 410 in the first phase is [0,0,1]. Since there is no abnormality in the multiplexed signal in the first phase, it is consistent with the ideal state. The data stored in the register in the second phase is [0,0,1]. It can be seen that when the multiplexed signal is abnormal, the data stored in the third flip-flop 511 in the operation subunit 410 will change. In addition, since the data stored in the third flip-flop 511 in the second phase has changed, the data stored in the second phase will be used as the input data for the third phase operation (the initial operation data of the previous level). At this time, the data stored in each third flip-flop 511 in the third phase is [1,0,0], and the data stored in each third flip-flop 511 in the fourth phase is [0,1,1].

[0070] As can be seen, if any multiplexed signal experiences a timing or level abnormality in any phase, the abnormality will propagate and recursively accumulate in multiple operation subunits 410. Therefore, it is only necessary to detect the output of one bit of initial operation data from each third flip-flop 511 to determine whether the multiplexed signal MisrIn has changed. If one operation subunit 410 processes 1 byte (i.e., 8 bits) of the first test data, then only the 1 bit of initial operation data needs to be confirmed to determine whether the multiplexed signal MisrIn has changed, thus achieving compression of the first test data. Even when facing a multi-phase ultra-high-speed read stream, after the entire read / write test process is completed, the operation subunit 410 of this embodiment only needs to queue and output the last bit of initial operation data stored in its third flip-flop 511 to verify with the standard signature, which can accurately infer whether there is a physical fault in the entire high-speed data flow path (including the interconnect structure 300 and the memory chip 200). This mechanism compresses the spatial channel width and temporal test depth into a tiny initial operation data.

[0071] In some embodiments, the read data detection module 110 is further configured to convert multiple parallel initial operation data into serial operation data.

[0072] It should be noted that each operation subunit 410 outputs its initial operation results in parallel. In order to transmit these initial operation results output in parallel from multiple physical channels and perform subsequent efficient comparisons, the initial operation data (e.g., data distributed on multiple spatial structures in parallel) can be processed. Figure 7 MisrQ< >、MisrQ <1> and MisrQ <0> This is converted into serial computational data over a one-bit time series to reduce the number of pins required for the chip test interface, thereby improving the utilization of test communication bandwidth.

[0073] In some embodiments, the operation unit 111 is a compression unit, the operation data is compressed data, and the compression unit is used to perform at least one non-carry superposition of multiple first test data to obtain compressed data.

[0074] It should be noted that the compression unit uses a non-carry superposition method to repeatedly superimpose discrete test data with historical states within the long chain of triggers, thereby compressing it into a set of test signature results with a certain length, thus obtaining compressed data. As long as the test data undergoes a slight change, the compressed data will be significantly different from the expected data.

[0075] In some embodiments, the compression unit includes a serial conversion subunit 430; The serial conversion subunit 430 includes multiple parallel input interfaces, which are respectively connected to the output terminals of multiple arithmetic subunits 410. The serial conversion subunit 430 is used to receive the initial arithmetic data output by the multiple arithmetic subunits 410 and combine the received initial arithmetic data into serial compressed data.

[0076] It should be noted that the serial conversion subunit 430 first receives a large batch of initial calculation data that has been calculated and output by multiple calculation subunits 410, and then uses the shift channel to intercept multiple initial calculation data, and sorts and combines them into serial compressed data for single-line pin output according to a predetermined rhythm.

[0077] In some embodiments, the serial conversion subunit 430 includes cascaded selection transmission circuits 431, each selection transmission circuit 431 including a selector 512 and a transmission circuit 513, and the selector 512 corresponds one-to-one with the operation subunit 410. The first input terminal of selector 512 is connected to the output terminal of the corresponding arithmetic subunit 410, and the second input terminal of selector 512 is connected to the output terminal of the previous stage transmission circuit 513. Selector 512 is used to output the initial arithmetic data output by the current arithmetic subunit 410 as indicated by the selection signal to the current transmission circuit 513 when a selection signal is received at the selection input terminal, or to output the initial arithmetic data output by the previous stage transmission circuit 513 as indicated by the selection signal. The initial arithmetic data output by the last transmission circuit 513 is used as compressed data. It should be noted that the cascaded selection transmission circuit 431 is a chain structure consisting of multiple selection transmission circuits 431 connected sequentially. The second input terminal (packaged serial input terminal WSI) of selector 512 in the first selection transmission circuit 431 in the chain structure can receive compressed data output by another serial conversion subunit 430, or a fixed placeholder. The selection transmission circuit 431 without a next-stage selection transmission circuit 431 in the chain structure is the last selection transmission circuit 431, which outputs the compressed data of the current serial conversion subunit 430.

[0078] See Figure 7 This illustrates the circuit structure of the serial conversion subunit 430. The serial conversion subunit 430 includes multiple cascaded selection transmission circuits 431, each corresponding one-to-one with an operation subunit 410. Each selection transmission circuit 431 receives two data streams through its internal selector 512: one stream is the current initial operation data (e.g., MisrQ) output side-by-side from the corresponding operation subunit 410. <0> The other path is the pre-processed data (such as MisrQ) transmitted via shifting from the previous stage transmission circuit 513 through the cascaded link. <1> Selector 512 selects one of the channels based on the selection signal CaptureWR in a time-division manner and sends it to the subsequent transmission circuit (such as transmission circuit 513, which can be implemented by a D flip-flop with an independent clock terminal WRCK and a test reset terminal WRst_N) for latching output.

[0079] Taking the last-stage selection transmission circuit 431 at the very end of the chain as an example, it includes a first selector 512a and a first transmission circuit 513a. The first input terminal (high-level gating port) of the first selector 512a is connected to the output terminal of the corresponding operation subunit 410, and its second input terminal (low-level gating port) is connected to the output terminal of the second transmission circuit 513b in the previous stage selection transmission circuit 431. The selection terminal of the first selector 512a is used to receive the selection signal CaptureWR.

[0080] When the selection terminal of the first selector 512a receives the selection signal CaptureWR indicating the capture state, it selects its first input terminal and displays the initial operation data MisrQ received from the corresponding operation subunit 410. <0> The data input terminal (D terminal) of the first transmission circuit 513a is transmitted to the control. Simultaneously, the second selector 512b in the non-last stage serial conversion subunit 430 of the entire link also performs the same synchronization action, each intercepting the initial operation data of its corresponding upper-level operation subunit 410. Subsequently, utilizing the latching mechanism within the transmission circuit 513, under the unified drive of the valid test clock edge received at the independent clock terminal WRCK, the first transmission circuit 513a and its corresponding preceding transmission circuits 513 (such as the second transmission circuit 513b) simultaneously and stably capture these spatially parallel data, and solidify the output at their respective output terminals (Q terminals). This action is equivalent to using the entire transmission circuit 513 chain to complete a one-time interception of the parallel initial operation data.

[0081] After interception, the selection signal CaptureWR toggles, preventing the first selector 512a from receiving the capture command. At this point, the first selector 512a (and all selectors 512 in the link) disconnects the first input, instead maintaining selection of the second input (pin 0). With the second input selected, the various transmission circuits 513 are connected end-to-end to form a continuous one-dimensional channel. Under the control of the clock tick WRCK, the cascaded selection transmission circuit 431 shifts to the right, realizing the initial calculation data MisrQ that was previously temporarily stored in the previous stage's second transmission circuit 513b and earlier stages. <1> It is laterally shifted through the first selector 512a, refreshed, and enters the final stage first transmission circuit 513a; simultaneously, the MisrQ originally stored in the first transmission circuit 513a... <0> The data is then shifted and output to obtain serial compressed data, which is then output to the serial output port (Wrapper Serial Output, WSO).

[0082] In some embodiments, the read data detection module 110 further includes a clock processing unit 440, which is connected to the input terminal of the arithmetic unit 111. The clock processing unit 440 is used to generate a clock signal so that the arithmetic unit 111 outputs arithmetic data to the test interface circuit according to the clock signal.

[0083] It should be noted that, because the front-end data receiving and processing module 420 demultiplexes the first test data through timing multiplexing and then superimposes and aggregates the demultiplexed data onto the single-line multiplexed signal MisrIn, the data toggle density within the multiplexed signal MisrIn has changed compared to a single physical line. However, the third flip-flop 511, as a state latching element, is only sensitive to a single clock edge (such as a rising edge). If the unprocessed reference clock is used to drive it directly, stable sampling cannot be completed within one reference cycle, which may result in more than half of the initial computation data being truncated. This can be addressed by introducing a specially customized clock signal to make the operating sampling frequency of the third flip-flop 511 keep up with the data update frequency of the multiplexed signal MisrIn waveform.

[0084] In some embodiments, the clock processing unit 440 is an up-frequency clock unit used to generate an up-frequency clock signal.

[0085] It should be noted that because the data receiving and processing module 420 transmits the first test data, which was originally transmitted at double the data rate, through multiplexing and splicing into a single bus, the multiplexing signal flip density is doubled. The third flip-flop 511, upon which the arithmetic subunit 410 relies, only has the ability to "grab" data on a clock transition edge in one fixed direction. To resolve the mismatch between the data and the sampling clock, an up-frequency clock unit can be used to double the original lower reference test clock in the memory, generating an up-frequency clock signal twice the size of the reference clock signal, which serves as the MISR clock signal CKMisr, thereby increasing the sampling throughput of the third flip-flop 511.

[0086] In some embodiments, the up-frequency clock unit includes a first edge generating circuit 441, a second edge generating circuit 442, and a pulse synthesis circuit 443; The output of the first edge generating circuit 441 is connected to the first input of the pulse synthesis circuit 443, and is used to generate a first pulse signal based on the first transition edge of the reference clock signal. The output of the second edge generating circuit 442 is connected to the second input of the pulse synthesis circuit 443, and is used to generate a second pulse signal based on the second transition edge of the reference clock signal. The pulse synthesis circuit 443 is used to synthesize the first pulse signal and the second pulse signal to obtain the up-frequency clock signal.

[0087] In some embodiments, the second pulse signal and the first pulse signal have a preset interval.

[0088] See Figure 8The first edge generating circuit 441 in the upsampling clock unit includes a first inverter 514, a first delay 515, and a sixth NAND gate 516. The second edge generating circuit 442 includes a second inverter 517, a second delay 518, and a seventh NAND gate 519. The input terminals of the first inverter 514 and the first input terminal of the sixth NAND gate 516 are connected to the input terminals of the first edge generating circuit 441 to obtain the first transition edge by receiving a reference clock signal. In this embodiment, an odd clock signal RCLKO can be used as the reference clock signal. The first inverter 514 is connected to the second input terminal of the sixth NAND gate 516 via the first delay 515 to obtain the inverted signal nRCLKO_del of the reference clock signal with a set delay. The sixth NAND gate 516 performs a NAND operation on the odd clock signal RCLKO and the inverted signal nRCLKO_del with the set delay to obtain the first pulse signal nRCLKO_del_pwl, which is then output. The set delay is the pulse width of the first pulse signal nRCLKO_del_pwl. The input of the second inverter 517 and the first input of the seventh NAND gate 519 are connected to the input of the second edge generating circuit 442 to obtain the second transition edge of the reference clock. In this embodiment, the second transition edge can be obtained by obtaining the inverted odd clock signal RCLKO_N. The second inverter 517 is connected to the second input of the seventh NAND gate 519 via the second delay unit 518 to obtain the inverted reference clock signal nRCLKO_N_del with the set delay. The seventh NAND gate 519 performs a NAND operation on the inverted odd clock signal RCLKO_N and the inverted reference clock signal nRCLKO_N_del with the set delay to obtain the second pulse signal nRCLKO_N_del output.

[0089] See Figure 8 The pulse synthesis circuit 443 includes an eighth NAND gate 520. The first input of the eighth NAND gate 520 is connected to the output of the sixth NAND gate 516, and the second input of the eighth NAND gate 520 is connected to the output of the seventh NAND gate 519. It is used to synthesize the first pulse signal nRCLKO_del_pwl and the second pulse signal nRCLKO_N_del_pwl into an up-frequency clock signal as the MISR clock signal CKMisr.

[0090] In the first edge generating circuit 441 described above, when the odd clock signal RCLKO has a first transition edge (such as a rising edge), the signal at the first input terminal of the sixth NAND gate 516 becomes high. However, due to the delay effect of the first delay unit 515, the signal at the second input terminal of the sixth NAND gate 516 has not yet flipped to low and remains at a short high level. At this time, both input terminals of the sixth NAND gate 516 are at high levels, and a brief low-level pulse is emitted at the output terminal of the sixth NAND gate 516, which is the first pulse signal nRCLKO_del_pwl.

[0091] In the second edge generating circuit 442 described above, when the inverted odd clock signal RCLKO_N experiences its second transition edge (corresponding to the falling edge of the odd clock signal RCLKO), the signal at the first input of the seventh NAND gate 519 becomes high. However, due to the delay effect of the second delay unit 518, the signal at the second input of the seventh NAND gate 519 has not yet flipped to low and remains at a short high level. At this time, both inputs of the seventh NAND gate 519 are high, thus generating a brief low-level pulse at the output of the seventh NAND gate 519, which is the second pulse signal nRCLKO_N_del_pwl.

[0092] In the pulse synthesis circuit 443 described above, the low-level pulses of the first pulse signal nRCLKO_del_pwl and the second pulse signal nRCLKO_N_del_pwl are time-divisionally entered into the eighth NAND gate 520. Each time the eighth NAND gate 520 receives a low-level pulse, a polarity reversal occurs at the output terminal of the eighth NAND gate 520, and a regular positive high-level pulse is output. This transforms the odd clock signal, which has only undergone one cycle of rotation, into two equidistant pulse waveforms, thus obtaining the up-frequency clock signal.

[0093] See Figure 9The diagram illustrates the signal schematics of each interface within the chip. First, the even clock signal RCLKE and the odd clock signal RCLKO appear in alternating phases, serving as trigger references for two independent branches. Under the influence of the even clock signal RCLKE, the circuit samples and outputs the first demultiplexed signal DataE, maintaining a wide data window of the first data 1th_E and the second data 2th_E in the diagram. Similarly, under the influence of the odd clock signal RCLKO, the circuit obtains the second demultiplexed signal DataO, which has a time lag, and outputs the first data 1th_O and the second data 2th_O accordingly. At this point, DataE and DataO are parallel, down-frequency signals. Subsequently, to regroup the parallel signals, a gating control signal RCLKE_d is introduced. This signal alternates between high and low levels, acting as a timing trimming window. Under the alternating high and low level control of the gating control signal RCLKE_d, the circuit sequentially extracts the effective portions of DataE and DataO and concatenates them end-to-end, ultimately splicing the two signals into a single-line multiplexed signal MisrIn. As shown in the figure, a tightly connected serial data stream of 1th_E, 1th_O, 2th_E, and 2th_O is formed on the multiplexed signal MisrIn, significantly doubling its data update density. Finally, to match the doubled data rate of the multiplexed signal MisrIn, a higher-frequency upsampling clock signal is provided as the MISR clock signal CkMisr. Each rising edge of the MISR clock signal CkMisr is aligned with each bit of data in the multiplexed signal MisrIn (such as 1th_E, 1th_O, etc.). Furthermore, each transition edge of the upsampling clock signal CkMisr is precisely aligned with the stable data region of the multiplexed signal MisrIn (such as 1th_E, 1th_O, etc.). Under the triggering of consecutive valid edges of the MISR clock signal CkMisr, the internal flip-flop accurately captures the high-speed data of MisrIn and drives the initial operational data MisrQ to undergo corresponding state transitions. MisrQ starts from the initial preset state Preset, and then updates the calculations sequentially in strict accordance with the clock beat, gradually evolving into the stable output initial calculation data Q_1, Q_2, Q_3 and Q_4.

[0094] In some embodiments, the logic chip 100 further includes a test interface circuit connected to the arithmetic unit 111, which is used to read arithmetic data and compare the arithmetic data with expected data. If the arithmetic data and expected data are consistent, a first comparison result is output, indicating that there is no fault. If the arithmetic data and expected data are inconsistent, a second comparison result is output, indicating that there is a fault.

[0095] In some embodiments, to achieve final closed-loop determination of test results and external interaction, the logic chip 100 also integrates a test interface circuit (e.g., a kernel test wrapper interface conforming to the IEEE 1500 standard). Physically, the test interface circuit is directly connected to the output of the aforementioned arithmetic unit 111 (e.g., the final serial output WSO of the serial conversion subunit 430 composed of multiple D flip-flops). That is, the test interface circuit reads the serially output arithmetic data from the arithmetic unit 111 and compares the arithmetic data with expected data. Expected data can come from an algorithm preset issued by an external test machine or be generated by the logic chip 100 using a write path.

[0096] It should be noted that any minor open circuit, short circuit, bridging, or transient timing misalignment event occurring on the interconnect structure 300 or the memory chip 200 will be retained and amplified by the arithmetic unit 111, causing a change in the final read data. That is, if the processed data matches the expected data bit-for-bit, the test interface circuit outputs a first comparison result, indicating that the multi-channel memory interconnect structure 300 covered in the current batch maintains data fidelity under high-speed throughput and is free of faults. If a level inconsistency is found between the processed data and the expected data during the comparison process, the test interface circuit outputs a second comparison result (e.g., forcing a specified pin level low, or sending an alarm signal to the host). This second comparison result indicates a physical or timing fault in the measured cross-chip interconnect data path.

[0097] In some embodiments, the memory chip 200 further includes a data temporary storage unit; The read data detection module 110 is also configured such that, in normal mode, when the logic chip 100 receives a read command, the read data detection module 110 reads the data in the data temporary storage unit through multiple interconnect structures 300; The write data module 130 is also configured such that, in normal mode, when the logic chip 100 receives a write command, the write data module 130 writes data to the data temporary storage unit through multiple interconnect structures 300.

[0098] It should be noted that when transmitting signals across chip layers, since there is usually a phase difference between the clock domain of the logic chip 100, the clock domain of the cross-layer bus, and the clock domain of the memory array in the memory chip 200, physical or timing faults of the data temporary storage unit and the interconnect structure 300 can also be detected by writing data to the data temporary storage unit and reading the written data from the data temporary storage unit through the read data detection module 110.

[0099] In another embodiment of this disclosure, an electronic device is provided, which includes the memory of the foregoing embodiments and a test module connected to the memory via a test interface for testing at least one interconnect structure 300 in the memory.

[0100] In summary, this disclosure provides a memory and an electronic device, wherein the logic chip 100, by setting a read data detection module 110, can read, down-frequency capture, multiplex and synthesize, and internally perform non-carry superposition compression of high-speed first test data within the memory chip 200 in test mode, to obtain a computational result that can be used to detect whether there are abnormalities in the interconnect structure 300. Compared with the prior art, this solution has the following significant advantages: (1) In this embodiment, through specific mode configuration (such as 1500WDR Config combined with MR7 OP parameters), the computing unit actively captures and processes the data read by the read command. This eliminates the need for lengthy external transmission and path-by-path analysis of test data, shortens the data processing link, and improves testing efficiency.

[0101] (2) By first reducing the frequency of the high-speed parallel read stream to stabilize it in the internal clock domain, and then using alternating sampling and splicing aggregation to gather it into a single-line high-speed multiplexed signal, the operation unit can process data in a pipeline manner, avoiding the need to set up a complicated one-to-one hardware operation architecture for the parallel bus and reducing the area occupied by the test circuit in the logic chip.

[0102] (3) For high-speed data streams with doubled density after multiplexing and aggregation, a dedicated clock pulse with double the sampling frequency is synthesized in place by utilizing the edge delay characteristics of the reference clock. Since the sampling clock dynamically follows the update frequency of the data waveform, it avoids the phenomena of incorrect sampling, missed sampling and timing violations caused by excessive data stream density, and ensures the fidelity of massive concurrent test data in the process of cascading operation.

[0103] (4) Through the non-carry cyclic logic operation of the cascaded superposition circuit, any minor occasional anomalies (such as open circuit, short circuit, timing misalignment, etc.) that may occur in the multi-path physical interconnection structure within different timing steps are amplified and superimposed without omission and retained; in conjunction with the serial conversion subunit, the operation results that were originally scattered on multiple parallel physical channels are converted into a single-line serial stream. The number of dedicated pins required for testing is reduced, which is suitable for the test communication bandwidth under high-density packaging.

[0104] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0105] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0106] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0107] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0108] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0109] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory, characterized in that, include: A logic chip and at least one memory chip stacked on the logic chip; The memory chip and logic chip are connected through multiple interconnect structures to achieve signal transmission; The logic chip includes: multiple data transmission terminals and multiple read data detection modules corresponding one-to-one with each of the data transmission terminals; The read data detection module is configured such that, in test mode, the logic chip receives a read command, and the read data detection module reads multiple first test data stored in the storage chip through multiple interconnect structures; The read data detection module includes: a processing unit; The computation unit is used to perform at least one computation on multiple sets of the first test data to obtain computation data and to store the computation data.

2. The memory according to claim 1, characterized in that, The logic chip also includes a test interface circuit connected to the arithmetic unit. The test interface circuit is used to read the arithmetic data and compare the arithmetic data with expected data. If the arithmetic data is consistent with the expected data, a first comparison result is output, indicating that there is no fault. If the arithmetic data is inconsistent with the expected data, a second comparison result is output, indicating that there is a fault.

3. The memory according to claim 2, characterized in that, The data reading detection module further includes a clock processing unit, which is connected to the input terminal of the arithmetic unit. The clock processing unit is used to generate a clock signal so that the arithmetic unit outputs the arithmetic data to the test interface circuit according to the clock signal.

4. The memory according to claim 3, characterized in that, The clock processing unit is an up-frequency clock unit used to generate up-frequency clock signals.

5. The memory according to claim 4, characterized in that, The up-frequency clock unit includes a first edge generating circuit, a second edge generating circuit, and a pulse synthesis circuit; The output of the first edge generating circuit is connected to the first input of the pulse synthesis circuit, and is used to generate a first pulse signal based on the first transition edge of the reference clock signal. The output of the second edge generating circuit is connected to the second input of the pulse synthesis circuit, and is used to generate a second pulse signal based on the second transition edge of the reference clock signal; The pulse synthesis circuit is used to synthesize the first pulse signal and the second pulse signal to obtain the up-frequency clock signal.

6. The memory according to claim 1, characterized in that, The read data detection module further includes a data receiving and processing module, which is used to receive the first test data and output multiple multiplexed signals.

7. The memory according to claim 6, characterized in that, The data receiving and processing module includes multiple demultiplexing units and corresponding signal multiplexing units; The demultiplexing unit is used to perform multi-phase demultiplexing on the corresponding first test data to obtain multiple demultiplexed signals; The signal multiplexing unit is used to perform time-series multiplexing of multiple demultiplexed signals to obtain the multiplexed signal; The arithmetic unit is also used to receive multiple multiplexed signals and perform arithmetic processing to obtain the arithmetic data.

8. The memory according to claim 6, characterized in that, The multiple input terminals of the arithmetic unit are used to receive multiple multiplexed signals and perform arithmetic processing on them respectively to obtain the arithmetic data. The arithmetic unit includes multiple cascaded arithmetic subunits, and each arithmetic subunit corresponds to one of the multiplexed signals. Each of the above-level operation subunits receives the corresponding multiplexed signal at its input terminal. In the case of having a previous-level operation subunit, each operation subunit also receives the initial operation data output by the previous-level operation subunit, and performs another operation on the corresponding multiplexed signal and the initial operation data output by the previous-level operation subunit to obtain the initial operation data of the current operation subunit.

9. The memory according to claim 8, characterized in that, The read data detection module is also used to convert multiple parallel initial operation data into serial operation data.

10. The memory according to claim 8, characterized in that, The calculation unit is a compression unit, and the calculation data is compressed data. The compression unit is used to perform at least one non-carry superposition of multiple first test data to obtain the compressed data.

11. The memory according to claim 10, characterized in that, The compression unit includes a serial conversion subunit; The serial conversion subunit includes multiple parallel input interfaces, which are respectively connected to the output terminals of multiple arithmetic subunits. The serial conversion subunit is used to receive the initial arithmetic data output by the multiple arithmetic subunits and combine the received initial arithmetic data into serial compressed data.

12. The memory according to claim 11, characterized in that, The serial conversion subunit includes cascaded selection transmission circuits, each of which includes a selector and a transmission circuit, and the selector corresponds one-to-one with the operation subunit. The first input terminal of the selector is connected to the output terminal of the corresponding operation subunit, and the second input terminal of the selector is connected to the output terminal of the previous stage transmission circuit. When the selector receives a selection signal at the selection input terminal, the selector is used to output the initial operation data output by the current operation subunit indicated by the selection signal to the current transmission circuit, or to output the initial operation data output by the previous stage transmission circuit indicated by the selection signal. The initial operation data output by the last transmission circuit is used as the compressed data.

13. The memory according to any one of claims 8 to 12, characterized in that, The operation subunit is a superposition subunit, and each level of the superposition subunit includes a superposition circuit and an operation data output circuit; The first input terminal of the superposition circuit is connected to the output terminal of the previous-level computational data output circuit, the second input terminal of the superposition circuit is connected to the output terminal of the data receiving and processing module, and the output terminal of the superposition circuit is connected to the input terminal of the current-level computational data output circuit. The superposition circuit is used to receive the multiplexed signal, and, in the case of having the previous-level computational data output circuit, to receive the initial computational data output by the previous-level computational data output circuit, and to perform computational processing on the corresponding multiplexed signal and the initial computational data output by the previous-level superposition subunit to obtain the initial computational data of the current superposition circuit. The output terminal of the computational data output circuit is connected to the first input terminal of the next-level superposition circuit, and is used to receive the clock signal and output the initial computational data according to the clock signal.

14. The memory according to claim 13, characterized in that, The superimposed circuit includes a first logic gate, a second logic gate, and a third logic gate. The output terminal of the first logic gate is connected to the first input terminal of the third logic gate, and the output terminal of the second logic gate is connected to the second input terminal of the third logic gate. The first logic gate is used to receive the initial operation data output by the previous operation data output circuit through the first input terminal, and when the first indication signal is received at the second input terminal at the first level, output the inverted signal of the initial operation data output by the previous superposition subunit to obtain the first superposition data; The second logic gate is used to receive the corresponding multiplexed signal through the first input terminal, and when the second indication signal received at the second input terminal is at the first level, output the inverted signal of the corresponding multiplexed signal to obtain the second data to be superimposed; The third logic gate is used to output the initial operation data of the current superposition circuit when the first data to be superimposed is different from the second data to be superimposed.

15. The memory according to claim 1, characterized in that, The logic chip also includes: The write data module, connected to the data transmission terminal, is configured to write the first test data to the memory chip through the interconnect structure when a write command is received in the test mode.

16. The memory according to claim 15, characterized in that, The storage chip also includes a data temporary storage unit; The read data detection module is further configured such that, in normal mode, when the logic chip receives a read command, the read data detection module reads the data in the data temporary storage unit through multiple interconnect structures; The write data module is also configured such that, in normal mode, the logic chip receives a write command, and the write data module writes data to the data temporary storage unit through multiple interconnect structures.

17. An electronic device, characterized in that, include: The memory as described in any one of claims 1 to 16; The test module is connected to the memory via a test interface and is used to test at least one interconnect structure in the memory.

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