Interface test circuit, system, memory and electronic device

Abstract

The present disclosure provides an interface test circuit, system, memory and electronic device, relating to the technical field of semiconductor. The interface test circuit comprises: a clock control module configured to receive an input clock signal, adjust the input clock signal by using a plurality of gear signals to obtain a plurality of first clock signals, and obtain a plurality of second clock signals based on the input clock signal, wherein a preset phase difference exists between each first clock signal and the corresponding second clock signal; a loopback test module coupled with the clock control module, the first interface circuit and the second interface circuit, configured to generate test data in a data generation stage, and in a loopback test stage, the first interface circuit and the second interface circuit are tested based on the test data by using each group of corresponding first clock signals and second clock signals, which can realize the measurement of data eye diagram and improve the reliability and stability of interface test.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to an interface test circuit, system, memory, and electronic device. Background Technology

[0002] During the development of Dynamic Random Access Memory (DRAM), it is necessary to test the DQ interface inside the DRAM. As the data rate of the DQ interface increases, existing test equipment can no longer meet the testing requirements.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides an interface test circuit, system, memory, and electronic device that enables, to at least partially, testing of the DQ interface in DRAM.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part by practice of this disclosure.

[0006] According to one aspect of this disclosure, an interface test circuit is provided, comprising: a clock control module configured to receive an input clock signal, adjust the input clock signal using multiple level signals to obtain multiple first clock signals, and obtain multiple second clock signals based on the input clock signal, wherein a preset phase difference exists between each first clock signal and its corresponding second clock signal; and a loopback test module coupled to the clock control module, a first interface circuit, and a second interface circuit, configured to generate test data during a data generation phase, and perform loopback tests on the first interface circuit and the second interface circuit based on the test data using each set of corresponding first and second clock signals during a loopback test phase.

[0007] According to another aspect of this disclosure, an interface testing system is also provided, comprising: a frequency multiplier module configured to receive an external reference clock signal, multiply the reference clock signal, and output a multiplied clock signal; and a memory including an interface testing circuit of any one of the above, the interface testing circuit being coupled to the frequency multiplier module and configured to obtain an input clock signal based on the multiplied clock signal, and to test the interface of the memory based on the input clock signal.

[0008] According to another aspect of this disclosure, a memory is also provided, including an interface test circuit as described in any of the foregoing.

[0009] According to another aspect of this disclosure, an electronic device is also provided, which includes the memory as described above.

[0010] The interface testing circuit provided in this embodiment receives an input clock signal and uses multiple level signals to adjust the input clock signal to generate multiple first clock signals. Based on the input clock signal, it generates multiple second clock signals. These multiple sets of first and second clock signals with different phase differences simulate the phase relationship between the first and second interface circuits. Using the generated first and second clock signals, actual data reading and writing are performed on the DQ interface of the memory, and matching is performed to obtain multiple sets of matching results. By analyzing each set of matching results, it is possible to evaluate whether the DQ interface meets the design requirements and the eye diagram width of the DQ interface. This enables the measurement of the data eye diagram, improving the reliability and stability of interface testing.

[0011] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0013] Figure 1 A schematic diagram of an exemplary interface test circuit according to an embodiment of this disclosure is shown; Figure 2 A schematic diagram of another exemplary interface test circuit in an embodiment of this disclosure is shown; Figure 3 A schematic diagram of another exemplary interface test circuit in an embodiment of this disclosure is shown; Figure 4 A schematic diagram of another exemplary interface test circuit in an embodiment of this disclosure is shown; Figure 5 A schematic diagram of an exemplary enable control circuit according to an embodiment of this disclosure is shown; Figure 6 A schematic diagram of another exemplary interface test circuit in an embodiment of this disclosure is shown; Figure 7 A schematic diagram of an exemplary random sequence generation circuit and comparison circuit in an embodiment of this disclosure is shown; Figure 8 A schematic diagram of an exemplary target matrix is ​​shown in an embodiment of this disclosure; Figure 9 A schematic diagram illustrating a data transmission timing example from an embodiment of this disclosure is shown. Figure 10 A schematic diagram of an exemplary second clock signal in an embodiment of this disclosure is shown; Figure 11 The electrical schematic of the trigger signal of an exemplary second conversion circuit in an embodiment of this disclosure is shown; Figure 12 A schematic diagram of an exemplary verification process in an embodiment of this disclosure is shown; Figure 13 A schematic diagram illustrating an exemplary eye diagram width analysis according to an embodiment of this disclosure is shown; Figure 14 A flowchart illustrating the operation of an exemplary interface test circuit in an embodiment of this disclosure is shown. Detailed Implementation

[0014] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0015] It should be noted that, unless otherwise specified, the embodiments of the present invention and the technical features thereof can be combined with each other.

[0016] In semiconductor manufacturing and packaging testing, the DQ interface is tested using Automatic Test Equipment (ATE) and High Speed ​​ATE (HS ATE). Current ATE and HS ATE can meet the testing requirements of 9600Mbps. However, with the continuous upgrading of memory, its interface data rate has reached over 12800Mbps. The speed of HS ATE is no longer sufficient to meet the testing requirements of LPDDR6.

[0017] To meet the testing requirements of LPDDR6, ultra-high-speed automated test equipment (UHS ATE) was developed, as UHS ATE can meet the testing speed requirements of LPDDR6. However, on the one hand, the purchase and maintenance costs of UHS ATE are expensive. On the other hand, existing UHS ATEs are difficult to directly measure the eye diagram (ED).

[0018] To address this, this disclosure provides an interface testing circuit. A clock control module receives an input clock signal, adjusts it using multiple level signals to generate multiple first clock signals, and generates multiple second clock signals based on the input clock signal. These multiple sets of first and second clock signals with different phase differences simulate the phase relationship between the first and second interface circuits. Using the generated first and second clock signals, actual data reading and writing are performed on the DQ interface of the memory, and matching is performed to obtain multiple sets of matching results. By analyzing each set of matching results, it is possible to evaluate whether the DQ interface meets the design requirements and the eye diagram width of the DQ interface. This enables the measurement of the data eye diagram, improving the reliability and stability of interface testing.

[0019] The interface test circuit provided in the embodiments of this disclosure will be described in detail below with reference to specific embodiments and accompanying drawings.

[0020] like Figure 1 As shown, the interface test circuit includes: a clock control module 11, configured to receive an input clock signal, adjust the input clock signal using multiple level signals to obtain multiple first clock signals, and obtain multiple second clock signals based on the input clock signal, wherein there is a preset phase difference between each first clock signal and its corresponding second clock signal; and a loopback test module 12, coupled to the clock control module 11, the first interface circuit 21, and the second interface circuit 22, configured to generate test data during the data generation phase, and perform loopback tests on the first interface circuit and the second interface circuit based on the test data using the corresponding first and second clock signals during the loopback test phase.

[0021] The input clock signal can be provided by an external device. For example, the external device can be a high-speed test machine or an ultra-high-speed test machine. The output terminal of the external device is connected to the input terminal of the clock control module 11 to provide the input clock signal to the clock control module 11.

[0022] The first interface circuit 21 and the second interface circuit 22 can be understood as the DQ data pins in DRAM. For example, the first interface circuit 21 refers to the data read pin in DRAM, and the second interface circuit 22 refers to the memory data write pin. It should be noted that the data read pin and the data write pin appear in pairs; that is, the data read pin and the data write pin are connected via a data line used to transmit 1 bit of data. In other words, the data transmitted between the data read pin and the data write pin is serial.

[0023] The gear position signal can be understood as a control signal input from an external device or generated internally by the clock control module, used to adjust the phase of the first clock signal, ensuring a predetermined phase relationship between the first and second clock signals. Furthermore, each gear position signal corresponds to a set of preset phase difference configurations; that is, different gear position signals result in different preset phase differences between the first and second clock signals. In other words, M gear position signals adjust the input clock signal, generating M first clock signals, and the second clock signal is determined based on the input clock signal. The preset phase difference between each first clock signal and its corresponding second clock signal is unique. Each first clock signal and its corresponding second clock signal can be referred to as a set of clock signals.

[0024] The value M can be determined based on the period of an input clock signal and a preset phase difference. For example, M is 32. In this embodiment, two UI (Unit Interval) values ​​are selected to adjust the phase of the first clock signal. Therefore, the step size corresponding to the gear signal is step = 720. o / 32=22.5 o It should be noted that the number of gears M and the step size mentioned above are only illustrative examples and are not specifically limited. They can be set according to the actual situation.

[0025] The first and second clock signals have the same frequency and duty cycle, but a preset phase difference exists between them. Furthermore, as the gear position signal increases, the preset phase difference between the first and second clock signals increases. That is, the preset phase difference between the first and second clock signals is directly proportional to the gear position signal. For example, the preset phase difference could be 0°, 22.5°, etc. o , 45°, etc.

[0026] The first clock signal can be understood as the clock signal used to drive the first interface circuit of the memory to read data, and the second clock signal is used to control the second interface circuit of the memory to write data.

[0027] In this embodiment, the loopback test module 12 operates in two phases: a data generation phase and a loopback test phase. In the data generation phase, the loopback test module 12 generates a pseudo-random number sequence as the test data. In the loopback test phase, the loopback test module 12 uses M sets of clock signals provided by the clock control module 11 to sequentially perform M loopback tests on the first interface circuit 21 and the second interface circuit 22 of the memory.

[0028] Each loopback test process includes: the loopback test module 12 uses the first clock signal in the group as the driving clock to transmit the data under test to the second interface circuit 22 of the memory via the first interface circuit 21 of the memory. The loopback test module 12 uses the second clock signal in the group as the sampling clock to obtain sampled data from the second interface circuit 22. The loopback test module 12 compares the data under test with the sampled data to obtain the matching result corresponding to the signal level.

[0029] The clock control module 11 generates M gear signals sequentially, which in turn generate M sets of clock signals with different preset phase differences. The loop closure test module 12 repeats the loop closure test process M times to complete the full scan of the M gears.

[0030] Since the first clock signal and the second clock signal in each group of clock signals have different preset phase differences, the interface test circuit scans the setup time margin and hold time margin of the DQ interface under different signal levels. By analyzing the matching results of each group, it can evaluate whether the DQ interface meets the design requirements and the eye diagram width of the DQ interface.

[0031] In this embodiment, the clock control module receives an input clock signal, adjusts the input clock signal using multiple level signals to generate multiple first clock signals, and generates multiple second clock signals based on the input clock signal. These multiple sets of first and second clock signals with different phase differences simulate the phase relationship between the first interface circuit and the second interface circuit. Using the generated first and second clock signals, actual data reading and writing are performed on the DQ interface of the memory, and matching is performed to obtain multiple sets of matching results. By analyzing each set of matching results, it is possible to evaluate whether the DQ interface meets the design requirements and the eye diagram width of the DQ interface, thereby achieving data eye diagram measurement and improving the reliability and stability of interface testing.

[0032] In some embodiments, such as Figure 2 As shown, the clock control module 11 includes a frequency divider circuit 111, which is configured to receive an external frequency multiplier clock signal and divide the frequency multiplier clock signal to obtain an input clock signal.

[0033] The frequency divider circuit 111 is a component within the clock control module 11, used to divide the clock signal input to the memory. The input clock signal refers to the clock signal output by the frequency divider circuit 111 after dividing the reference clock signal. The frequency of the input clock signal conforms to the frequency corresponding to the DQ interface.

[0034] Frequency division can be understood as dividing the clock frequency of the reference clock signal by a division factor to obtain a lower frequency input clock signal. It should be noted that frequency division does not change the duty cycle or phase of the clock signal. The division factor can include, but is not limited to, 2, 4, etc. For example, if the reference clock signal is wck1T, the input clock signal after division by 2 is wck2T.

[0035] In one possible implementation, such as Figure 2 As shown, the clock control module 10 includes: a frequency divider circuit 111, which is coupled to an external device 40 through a frequency multiplier module 30; the frequency multiplier module 30 is configured to multiply the reference clock signal output by the external device and then output a multiplied clock signal to the frequency divider circuit 111; the frequency divider circuit 111 is configured to divide the multiplied clock signal to obtain an input clock signal.

[0036] The frequency multiplier module 30 is an intermediate device connected between the external device 40 and the interface test circuit 10. It is used to multiply the frequency of the reference clock signal output by the external device to obtain a higher frequency clock signal. Specifically, frequency multiplication can be understood as multiplying the clock frequency of the reference clock signal by a multiplication factor to obtain a higher frequency clock signal. It should be noted that the multiplication factor can include, but is not limited to, 2, 4, etc. The multiplication factor can be set according to actual conditions. In practical applications, the multiplication factor can be dynamically adjusted based on the clock signal frequency output by the external device and the clock frequency of the interface of the memory under test to meet testing requirements.

[0037] In one possible implementation, the frequency multiplier module 30 can be installed inside the external device 40, that is, as a built-in module of the high-speed test machine. The frequency multiplier module 30 inside the external device 40 directly outputs the multiplied clock signal.

[0038] Alternatively, the frequency multiplier module 30 can be installed as a separate chip on the connection path between the external device 40 and the memory. Furthermore, the frequency multiplier module 30 can be installed close to the memory, allowing the external device 40 to output only a low-frequency reference clock signal, which is then transmitted to the frequency multiplier module 30 via cable, multiplied, and directly fed into the memory's clock input, thus shortening the transmission path of the high-frequency clock signal.

[0039] In this embodiment, the clock output terminal of the external device 40 is connected to the input terminal of the frequency multiplier module 30, which receives the reference clock signal sent by the external device 40. The output terminal of the frequency multiplier module 30 is connected to the clock input terminal of the memory, multiplies the reference clock signal, and transmits the multiplied clock signal to the clock input terminal of the memory. The input terminal of the frequency divider circuit 111 is connected to the clock input terminal of the memory to obtain the multiplied clock signal from the clock input terminal of the memory. The output terminal of the frequency divider circuit 111 is connected to the subsequent circuit inside the clock control module 11, using the frequency-divided input clock signal as the clock signal for the subsequent circuit.

[0040] Furthermore, the frequency multiplier module 30 may internally include a phase-locked loop (PLL) for multiplying the frequency of the low-frequency reference clock signal provided by the external device 40 by a fixed multiplication factor to output a multiplied clock signal. This multiplied clock signal is transmitted to the clock input terminal of the memory via a cable or PCB trace. The frequency divider circuit 111 receives the multiplied clock signal input from the clock input terminal of the memory, divides the multiplied clock signal by a division factor, and obtains a lower frequency input clock signal.

[0041] In this embodiment, the external device only needs to provide a low-frequency reference clock signal. The frequency multiplier module converts the low-frequency reference clock signal into a multiplied clock signal to meet the testing requirements of the high-speed DQ interface. This eliminates the need for expensive ultra-high-speed testing equipment, reducing testing costs. Furthermore, the frequency multiplier module is located outside the memory, avoiding the need to place analog circuitry inside the memory and saving chip area.

[0042] In some embodiments, such as Figure 3 As shown, the clock control module 11 includes: a phase interpolation circuit 112, configured to perform phase interpolation on the input clock signal in response to the current gear signal, generating a first clock signal with a preset phase difference relative to the input clock signal; a first control circuit 113, coupled to the phase interpolation circuit 112, configured to output the first clock signal in response to a first enable signal being active; and a second control circuit 114, configured to output the input clock signal as a second clock signal in response to a second enable signal being active.

[0043] The first enable signal enables the first control circuit 113 to output a first clock signal, and the first enable signal is valid once in one loopback test. Similarly, the second enable signal enables the second control circuit 114 to output a second clock signal, and the second enable signal is valid once in one loopback test. The second enable signal appears later than the first enable signal.

[0044] like Figure 3As shown, the output terminal of the frequency divider circuit 111 is connected to the input terminal of the second control circuit 114 and the input terminal of the phase interpolation circuit 112, respectively. The second control circuit 114 and the phase interpolation circuit 112 receive the input clock signal wck2T output from the frequency divider circuit 111, respectively.

[0045] When the second enable signal is valid, the second control circuit 114 directly outputs the input clock signal wck2T as the second clock signal, which is used to control the second interface circuit 22 to sample and receive data. The second control circuit 114 does not change the phase and frequency of the input clock signal; therefore, the second clock signal has the same phase and frequency as the input clock signal. When the second enable signal is invalid, the second control circuit 114 is turned off and does not output a clock signal.

[0046] In this embodiment, the phase interpolation circuit 112 can be implemented using a phase interpolator (PI). Specifically, the phase interpolator superimposes two or more clock signals with different phases according to a certain weight to obtain a new clock signal.

[0047] In one possible implementation, an external device inputs the current gear signal to the phase interpolation circuit 112, or the phase interpolation circuit 112 automatically generates the current gear signal based on its internal circuitry. For example, the gear signal can be represented using 4 bits of binary, where gear signal

[0000] represents PI_code=0, gear signal

[0001] represents PI_code=1, ..., gear signal

[1111] represents PI_code=31.

[0048] After performing phase interpolation based on the current gear signal, the phase interpolator outputs a first clock signal corresponding to the current gear signal. It should be noted that the phase of the first clock signal and the phase of the second clock signal satisfy the formula (1).

[0049] phase_tx=phase_rx+PI_code×step(1)

[0050] Where phase_tx is the phase of the first clock signal, phase_rx is the phase of the second clock signal, PI_code is the current gear signal, and step is the step size. The step size is determined by the interpolation accuracy of the phase interpolator; in this embodiment, step is 22.5. o For example, it should be noted that the minimum value of PI_code is 0. At this time, the phase of the first clock signal is the same as the phase of the second clock signal. The maximum value of PI_code is M. At this time, the phase of the first clock signal and the phase of the second clock signal are represented by formula (1).

[0051] The phase interpolator provides M gear selections simultaneously. Based on the input from external devices or the gear selection signal automatically generated by the phase interpolation circuit 112 according to the internal circuit, the corresponding gear signal PI_code is determined.

[0052] When the first enable signal is valid, the first control circuit 113 buffers and outputs the first clock signal from the phase interpolation circuit 112 to the subsequent stage; when the first enable signal is invalid, the first control circuit 113 is turned off and does not output a clock signal.

[0053] In this embodiment, by sequentially changing the gear signal and repeatedly performing the loopback test M times, the data reception under different transmission phases can be scanned, thereby evaluating the eye diagram width of the memory DQ interface.

[0054] In some embodiments, such as Figure 4 As shown, the clock control module 11 further includes an enable control circuit 115, coupled to the first control circuit 113 and the second control circuit 114, configured to output a first enable signal after a first set period in response to the loopback enable signal being valid; and output a second enable signal after a second set period; wherein the second set period is greater than the first set period.

[0055] The loopback enable signal can be an externally input control signal used to initiate a complete loopback test. For example, a valid loopback enable signal can be a high level. During the period when the loopback enable signal is valid, data is transmitted from the first interface circuit 21 to the second interface circuit 22.

[0056] It should be noted that the loopback enable signal is used to perform one loopback test. Each time a loopback test is performed, the gear position signal increments by 1 until it reaches its maximum value (e.g., 32), at which point this round of interface testing is complete. Then, the loopback test module is controlled to regenerate new test data, set the gear position signal to 0, and re-execute the next round of interface testing.

[0057] The first set period can be understood as the pre-set delay period of the first enable signal, that is, starting from the effective period of the loopback enable signal, the first enable signal is output after the first set period. Similarly, the second set period can be understood as the pre-set delay period of the second enable signal, that is, starting from the effective period of the loopback enable signal, the second enable signal is output after the second set period.

[0058] Furthermore, the first and second set periods can be represented by reference clock periods wck2T. For example, the second set duration is 7 reference clock periods wck2T, and the first set duration is 3 reference clock periods wck2T.

[0059] In one possible implementation, the enable control circuit 115 receives a loopback enable signal cm_ts_ODLBEn from an external device. When the loopback enable signal is valid (e.g., cm_ts_ODLBEn=1), an internal counter or delay starts timing. After a first set period, it outputs a first enable signal valid (TXEn=1). After a second set period, it outputs a second enable signal valid (RXEn=1). The first and second enable signals generate only one valid pulse in one loopback test.

[0060] Figure 5 It is a circuit diagram of an enable control circuit, such as Figure 5 As shown, the input signals of the enable control circuit include a loopback enable signal cm0_ts_ODLBEn and an input clock signal wck2T. The input clock signal wck2T is input to the enable control circuit 115 by the frequency divider circuit 111. The enable control circuit 115 includes multiple cascaded D flip-flops (DFFs), and the input clock signal wck2T is input to the clock input terminal of each D flip-flop.

[0061] The loopback enable signal cm0_ts_ODLBEn first passes through two stages of D flip-flops (DFFs) and is driven by the input clock signal wck2T to synchronize the loopback enable signal cm0_ts_ODLBEn and the input clock signal wck2T, thereby improving the timing stability of subsequent circuits.

[0062] After the clock cycle, the loopback enable signal cm0_ts_ODLBEn will be shifted clockwise in a shift register composed of multiple cascaded D flip-flops (DFFs). For example, the output signal of the first-stage DFF is passed to the second-stage DFF, and the output signal of the second-stage DFF is passed to the third-stage DFF. The output signal of each stage DFF is delayed by one wck2T clock cycle compared to the previous stage DFF.

[0063] After the lap timer is applied, the loopback enable signal cm0_ts_ODLBEn is ORed with the output signal of the first-stage DFF, resulting in a high-level first enable signal. After being shifted backwards for several cycles, the loopback enable signal cm0_ts_ODLBEn is then ORed with the output signal of the last-stage DFF and its input signal, resulting in a high-level second enable signal.

[0064] After the loopback enable signal cm0_ts_ODLBEn goes low, the first enable signal and the second enable signal will also go low, thus achieving timing control for one loopback test.

[0065] In this embodiment, the second enable signal generated by the enable control circuit based on the loop-through enable signal is delayed by a certain time compared to the first enable signal, so as to avoid the second clock signal starting too early and capturing measurement errors caused by erroneous data, thereby improving the accuracy of interface testing.

[0066] In some embodiments, such as Figure 6 As shown, the loop closure test module 12 includes: a random sequence generation circuit 121; the random sequence generation circuit 121 is configured to generate data to be tested based on an initial seed signal if the test control signal is in a first state; and to cyclically shift the data to be tested based on a cyclic shift control signal to obtain a target matrix if the test control signal is in a second state; the test control signal in the first state is used to indicate that the loop closure test module is in the data generation stage, and the test control signal in the second state is used to indicate that the loop closure test module is in the loop closure test stage.

[0067] In this embodiment, the first state can be low level and the second state can be high level as an example. For example, the test control signal is cm0_ts_ODLBRdResult=0 in the first state and cm0_ts_ODLBRdResult=1 in the second state.

[0068] In one possible implementation Figure 7 This disclosure provides a random number generation circuit, such as... Figure 7 As shown, the random sequence generation circuit 121 includes a shift register consisting of eight cascaded D flip-flops.

[0069] The data input of the first-stage D flip-flop is connected to the output of the multiplexer (mux). The multiplexer has three inputs: the test control signal cm0_ts_ODLBRdResult, the output data of the last-stage D flip-flop, and a single data value obtained after multiple calculations. This single data value is obtained by XORing the output data of the last-stage D flip-flop, the fourth-stage D flip-flop, the fifth-stage D flip-flop, and the sixth-stage D flip-flop. It should be noted that... Figure 7 The multiple calculations described herein are merely illustrative and not intended to be limiting. In practical applications, the multiple calculations of the pseudo-random number generation circuit can be designed according to requirements, and the embodiments disclosed herein are not specifically limited.

[0070] The clock input of each stage of the D flip-flop receives the PRBS (Pseudo-Random Binary Sequence) clock signal cm0_ts_ODLBPRBSClk, which is used to drive the synchronous shift of all D flip-flops. Tap0-Top7 are the output data of each stage of the D flip-flop, totaling 8 bits.

[0071] Specifically, when cm0_ts_ODLBRdResult=0, the random sequence generation circuit 121 loads initial values ​​for the eight D flip-flops based on the externally input initial seed signal seed<7:0>. When the rising edge of the PRBS clock signal cm0_ts_ODLBPRBSClk arrives, the eight D flip-flops shift. Simultaneously, the output data of the fourth-stage D flip-flop, the output data of the fifth-stage D flip-flop, the output data of the sixth-stage D flip-flop, and the output data of the eighth-stage D flip-flop are XORed to update the input data of the first-stage D flip-flop. After eight PRBS clock signals cm0_ts_ODLBPRBSClk, the current 8-bit pseudo-random sequence is used as the test data.

[0072] When cm0_ts_ODLBRdResult=1, the random sequence generation circuit 121 no longer generates pseudo-random number sequences, but instead performs shift control according to the cyclic shift control signal. In this embodiment, the cyclic shift control signal uses the PRBS clock signal cm0_ts_ODLBPRBSClk. For each valid clock signal, the output data of the random sequence generation circuit is shifted one position to the right to obtain a new target data. After eight PRBS clock signals cm0_ts_ODLBPRBSClk, the eight pseudo-random number sequences are cyclically shifted once to obtain an 8×8 target matrix.

[0073] like Figure 8 As shown, the first row of the target matrix is ​​D7-D0, the second row is D0, D7-D1, ..., and the eighth row is D6-D0, D7.

[0074] It should be noted that the random sequence generation circuit 121 is implemented using an existing pseudo-random number generator inside the memory, eliminating the need for external testing equipment to provide test data. The generation and comparison of test data are both completed inside the memory, reducing the need for external high-speed equipment and lowering testing costs.

[0075] Furthermore, this embodiment uses the random sequence generation circuit 121 to generate an 8-bit pseudo-random sequence as an example for illustration. This embodiment does not limit the number of bits in the pseudo-random sequence.

[0076] Continue to refer to Figure 6As shown, the loopback test module 12 includes: a first conversion circuit 122, coupled to the clock control module 11 and the first interface circuit 21 of the memory, configured to convert the data to be tested into transmitted data; for each first clock signal, driving the transmitted data to the first interface circuit 21 based on the first clock signal, so that the first interface circuit 21 sends data to the second interface circuit 22; a second conversion circuit 123, coupled to the clock control module 11 and the second interface circuit 22 of the memory, configured to buffer multiple received data received by the second interface circuit 22 and convert them into multiple sampled data; and a comparison circuit 124, coupled to the second conversion circuit, configured to compare the multiple sampled data with a target matrix to obtain multiple sets of comparison matches, wherein the target matrix is ​​determined according to the shift of the data to be tested.

[0077] like Figure 6 As shown, the input terminal of the first conversion circuit 122 is connected to the output terminal of the random sequence generation circuit 121. The first conversion circuit 122 and the random sequence generation circuit 121 are connected by an 8-bit data bus. In response to cm0_ts_ODLBRdResult=0, the random sequence generation circuit 121 generates 8 bits of test data and transmits it to the first conversion circuit 122 through the 8-bit data bus.

[0078] The first conversion circuit 122 is a P2S (parallel to serial) circuit. After receiving 8 bits of data to be tested, the first conversion circuit 122 converts the 8 bits of data to be tested into serial data and repeats this process 3 times to obtain the data to be transmitted. For example, the data to be transmitted is 24 bits.

[0079] The clock input terminal of the first conversion circuit 122 is connected to the output terminal of the first control circuit 113, and is used to receive the first clock signal output by the first control circuit 113. In response to the first clock signal, the data to be transmitted is sent to the second interface circuit 22 through the first interface circuit 21.

[0080] In this embodiment, M=32, so there are 32 gear position signals. Each gear position signal corresponds to one loopback test, and 32 loopback tests can be performed. In this embodiment, one loopback test is used as an example for explanation.

[0081] The second control circuit 114 responds to the second enable signal and outputs the second clock signal, and the first control circuit 113 responds to the first enable signal and outputs the first clock signal. The first clock signal and the second clock signal constitute a set of clock signals, and there is a preset phase difference between the two clock signals.

[0082] The first conversion circuit 122 uses the first clock signal as the driving clock to drive the 24-bit transmission data to the first interface circuit 21, which then transmits the data to the second interface circuit 22. The second interface circuit 22 uses a second clock signal corresponding to the first clock signal to sample and receive the data.

[0083] The input of the second conversion circuit 123 is connected to the second interface circuit 22 to acquire the received data sampled by the second interface circuit 22. This received data may be 24 bits or less. In response to the buffer signal, a set number of consecutive 8 bits of data are extracted from the received data, and this consecutive 8 bits of data is converted into parallel data and then transmitted to the comparison circuit 124 through an 8-bit data bus.

[0084] In the above embodiment, taking one loopback test as an example, one 8-bit sample data is obtained. M loopback tests will yield M 8-bit sample data.

[0085] Figure 9 This is a timing diagram of the data transmission provided in the embodiments of this disclosure, such as... Figure 9 As shown, each transmitted data has a PI delay relative to the input clock signal. The PI delay is mainly determined by the process, voltage, and temperature of the phase interpolation circuit. In this embodiment, the size of the PI delay is not specifically limited.

[0086] Taking 24 bits of data to be sent as an example, when PI_code=0, the delay of sending data is the PI delay; when PI_code=1, the delay of sending data is the sum of the PI delay and 12×step; ..., when PI_code=31, the delay of sending data is the sum of the PI delay and 31×step(2UI).

[0087] like Figure 10 As shown, the phase and frequency of the second clock signal are consistent with the input clock signal and are not controlled by the gear signal, so that there is a different phase difference between the second clock signal and the first clock signal during each loopback test. Figure 10 The document shows the second clock signals triggered by different second enable signals, namely the second clock signals triggered by four second enable signals. Each second clock signal is illustrated using only six high-level pulses as an example. Each pulse collects 1 bit of data. When the transmitted data is 24 bits, the corresponding second clock signal should be 24 high-level pulses.

[0088] Figure 11 It is the clock signal for the second conversion circuit. Figure 11The diagram shows the buffer signals of the second conversion circuit triggered by different second enable signals, namely, the buffer signals triggered by four second enable signals. These buffer signals are used to instruct the second conversion circuit to buffer the received data sampled by the second interface circuit 22, and after converting the serial data into parallel data, to extract 8 bits of data at a set position as the final sampled data.

[0089] In some embodiments, the loop closure test module 12 further includes: a shift count counting circuit, configured to count the number of cyclic shifts if the test control signal is in the second state, and trigger the cyclic shift control signal to be valid when the number of cyclic shifts is less than N; and a random sequence generation circuit, configured to cyclically shift the output data of the random sequence generation circuit once in response to the cyclic shift control signal being valid if the test control signal is in the second state, to obtain the target data.

[0090] The shift count counting circuit is used to count the number of cyclic shift control signals cm0_ts_ODLBPRBSClk when the test control signal is in the second state, and use this count as the number of cyclic shifts. In this embodiment, N=8 is used as an example. If the number of cyclic shifts is less than 8, it indicates that the data under test has not completed the complete shift, that is, the target matrix cannot be formed.

[0091] The shift count counting circuit checks the internal cyclic shift count (count) against N. If the cyclic shift count is less than N, the cyclic shift control signal is activated. If the cyclic shift count is less than or equal to N, the cyclic shift control signal is deactivated. When the test control signal is in the second state, the random sequence generation circuit switches to cyclic shift mode.

[0092] Each time a valid cyclic shift control signal is detected (e.g., a rising edge), the random sequence generation circuit performs a cyclic shift operation. The currently stored parallel data (Top0-Top7) is shifted one bit to the right, and the inputs of the first-stage D flip-flops are obtained through multiple calculations. The new data obtained after the shift is the target data and is updated in the output register.

[0093] Continue to refer to Figure 7As shown, the sampled data DBUS<22:15> is compared with the test data (the first row of the target matrix) output by the random sequence generation circuit 121. If they are the same, the verification is successful; otherwise, the verification fails. Then, the cyclic shift control signal is triggered, and the random sequence generation circuit cyclically shifts the test data to the right once to obtain the target data (the second row of the target matrix). The sampled data DBUS<22:15> is compared with the target data (the second row of the target matrix) output by the random sequence generation circuit. If they are the same, the verification is successful; otherwise, the verification fails. Then, the cyclic shift control signal is triggered, and the random sequence generation circuit cyclically shifts the target data to the right once to obtain new target data (the third row of the target matrix), and so on, until the sampled data DBUS<22:15> is compared with the target data (the eighth row of the target matrix) output by the random sequence generation circuit. If they are the same, the verification is successful; otherwise, the verification fails, and the comparison ends.

[0094] In this embodiment, the data generation and cyclic shift logic are integrated into the memory. The random sequence generation circuit can automatically complete N shifts and corresponding loop tests under the control of the shift count statistics circuit, which further reduces the number of interactions between external devices and the memory, reduces test overhead, and shortens test time.

[0095] In some embodiments, the comparison circuit is configured to compare each sampled data with N rows of target data for multiple sampled data to obtain multiple sets of matching results, wherein each set of matching results includes N verification results, the verification results including verification pass or verification fail; the multiple sets of matching results are used to determine the interface test results, the interface test results including whether the interface meets the design requirements and / or the memory eye diagram width.

[0096] This embodiment uses one sampled data point as an example for explanation. Figure 12 As shown, the first interface circuit 21 sends 24 bits of data, which is the test data repeated 3 times (D7-D0); the second interface circuit 22 receives data. Due to clock data delay and other reasons, the first 4 bits of the received data RX may be empty data, and only 20 bits of received data are sampled. The last 4 bits of the sent data may not be sampled.

[0097] The second conversion circuit 123 extracts bits 1 to 8 from the 20-bit received data as sample data (D2, D1, D0, D7, D6, D5, D4, D3). The extracted 8-bit sample data must be one of the target matrix. It should be noted that the extraction position of the sample data can be set according to the actual situation.

[0098] Further, sampling data is retrieved from the target matrix. Specifically, comparison circuit 124 compares the sampling data with the first row of the target matrix, outputting a verification failure (Fail). Comparison circuit 124 compares the sampling data with the second row of the target matrix, outputting a verification failure. Comparison circuit 124 compares the sampling data with the third row of the target matrix, outputting a verification failure. Comparison circuit 124 compares the sampling data with the fourth row of the target matrix, outputting a verification success (Pass). Comparison circuit 124 compares the sampling data with the fifth row of the target matrix, outputting a verification failure. Comparison circuit 124 compares the sampling data with the sixth row of the target matrix, outputting a verification failure. Comparison circuit 124 compares the sampling data with the seventh row of the target matrix, outputting a verification failure. Comparison circuit 124 compares the sampling data with the eighth row of the target matrix, outputting a verification failure. Eight verification results form a set of matching results, meaning one loopback test corresponds to one set of matching results. Therefore, 32 gear positions correspond to 32 loopback tests, resulting in 32 × 8 verification results.

[0099] In some embodiments, whether the interface meets the design requirements includes whether the number of valid matches in multiple sets of matching results is greater than a preset threshold.

[0100] A preset threshold is a pre-defined integer threshold used to determine whether the timing performance of the memory interface is acceptable. The preset threshold is typically determined based on product specifications or eye diagram width requirements; this embodiment does not specify a particular threshold.

[0101] After completing the loopback tests corresponding to the M gear positions, the comparator circuit 124 has generated 32×8 verification results. The counter iterates through all verification results, incrementing the count by 1 when a verification pass flag is detected, thus obtaining the total number of verification pass flags. If the total number of gear positions... The preset threshold is 26. The digital comparator determines whether the total number of verified flags is greater than the set threshold of 26. If it is, the memory interface meets the design requirements and is deemed qualified. If it is not, the memory interface fails to meet the design requirements and is deemed unqualified.

[0102] In some embodiments, the eye diagram width of the memory interface is determined based on the number of target gears and the phase difference corresponding to each gear, and the number of target gears is determined based on the target data line transition corresponding to the verification pass.

[0103] Eye diagram width refers to the length of the time window during which the second interface circuit can correctly sample data under a set bit error rate. It is usually expressed in unit intervals (UI) or absolute time (ps).

[0104] like Figure 13As shown, the target data corresponding to cyclic shift 4 successfully matches the sampled data corresponding to PI0. The target data corresponding to cyclic shift 5 successfully matches the sampled data corresponding to PI1~PI15. The target data corresponding to cyclic shift 6 successfully matches the sampled data corresponding to PI17~PI31, which are in a matching state. Starting from PI1, the sampled data successfully matches the target data corresponding to cyclic shift 5, and the successfully matched target data row jumps from cyclic shift 4 to cyclic shift 5. From PI1 to PI16, all successfully matched target data rows are cyclic shift 5. Starting from PI17, the sampled data successfully matches the target data corresponding to cyclic shift 6, and the successfully matched target data row jumps from cyclic shift 5 to cyclic shift 6. The number of all gears between the two target data row jumps is counted as the target gear count.

[0105] The starting gear is PI1, the ending gear is PI6, and the target number of gears is stop-start+1=16-1+1=16.

[0106] In this embodiment, 16 gear positions constitute one unit time interval, therefore, Figure 13 The eye diagram width obtained in the matching results shown is 1 unit time interval (UI).

[0107] In one possible implementation, the above multiple sets of matching results are sent to an external device through a first interface circuit, where they can be displayed and the test results analyzed.

[0108] Based on the interface testing circuit described above, a workflow is provided, such as... Figure 14 As shown, the workflow of the interface test circuit mainly includes: The test initializes the memory, including: the external device sends a CAS (Column Address Strobe) command to the DRAM. The CAS command is used to open the DRAM's wck input register and enable the write clock path.

[0109] Set PIEn=1 to enable the phase interpolator; set PwrEn=1 to enable the CMOS transistor in the DQ region, so that it enters normal working state.

[0110] When ODLBRdResult is set to 0, the random sequence generation circuit responds by generating a pseudo-random sequence as the test data. The Loop PISel signal is used to select a range of the phase interpolator, serving as the current range signal. The Loop PISel signal is used to adjust the phase of the first clock signal, creating a phase difference between the first and second clock signals.

[0111] A complete loopback test includes the following steps: First, set LBEn=1 to initiate a data transmission and reception operation. The first interface circuit sends the transmitted data to the second interface circuit in the memory. Second, set lat=1 to latch the serial data received by the second interface circuit into the data bus latch DBUS after serial-to-parallel (S2P) conversion. At this time, DBUS stores the parallel sampled data received in this loopback. Third, set cm0_ts_ODLBRdResult=1 and initialize the shift count statistics circuit Shift=0. Fourth, enter the loop judgment: If Shift<8, based on the current Shift value, perform a cyclic shift on the data to be tested to obtain the target data. Compare the target data with the data to be tested to obtain the matching result, send the matching result to the external device, and then Shift=Shift+1, returning to the loop judgment. When Shift=8, exit the loop and end this loopback test.

[0112] Based on the same inventive concept, this disclosure also provides an interface testing system, including: a frequency multiplier module, which receives an external reference clock signal, multiplies the reference clock signal, and outputs a multiplied clock signal; and a memory, including an interface testing circuit of any one of the above, wherein the interface testing circuit is coupled to the frequency multiplier module and configured to obtain an input clock signal based on the multiplied clock signal, and test the interface of the memory based on the input clock signal.

[0113] Based on the same inventive concept, this disclosure also provides a memory, as shown in the following embodiment. Since the principle by which this memory embodiment solves the problem is similar to that of the interface test circuit embodiment described above, the implementation of this memory embodiment can refer to the implementation of the interface test circuit embodiment described above, and repeated details will not be described again.

[0114] The aforementioned memory can be a memory based on semiconductor structures or components.

[0115] Memory can be volatile memory, such as: DRAM (Dynamic Random Access Memory), SDRAM (Synchronous DRAM), DDR SDRAM (Double Data Rate SDRAM), LPDDR SDRAM (Low Power DDR SDRAM), GDDR SDRAM (Graphics DDR SDRAM), DDR2 SDRAM (second DDR SDRAM), DDR3 SDRAM (third DDR SDRAM), DDR4 SDRAM (fourth DDR SDRAM), DDR5 SDRAM (fifth DDR SDRAM), TRAM (Thyristor RAM), etc.

[0116] The memory can be non-volatile memory, such as PRAM (Phase-Change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), RRAM (Resistive Random Access Memory), etc.

[0117] Based on the same inventive concept, this disclosure also provides an electronic device, which may include the aforementioned memory. Since the principle by which this electronic device solves the problem is similar to that of the aforementioned interface test circuit embodiment, the implementation of this electronic device embodiment can refer to the implementation of the aforementioned interface test circuit embodiment, and repeated details will not be described again.

[0118] Electronic devices may include, but are not limited to, mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having the memory provided in the above embodiments.

[0119] It should be noted that the embodiments disclosed herein are merely one example of the application of the principles of this disclosure. Those skilled in the art will clearly understand that the principles of this disclosure are not limited to any details or components of the apparatus shown in the drawings or described in the specification.

[0120] It should be understood that this disclosure is not limited to the detailed structure and arrangement of the components presented in this specification. This disclosure is capable of other embodiments and can be implemented and performed in various ways. The foregoing variations and modifications fall within the scope of this disclosure. It should be understood that this disclosure, as disclosed and defined in this specification, extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of this disclosure. The embodiments described in this specification illustrate the best known mode for implementing this disclosure and will enable those skilled in the art to utilize this disclosure.

[0121] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An interface testing circuit, characterized in that, include: The clock control module is configured to receive an input clock signal, adjust the input clock signal using multiple gear signals to obtain multiple first clock signals, and obtain multiple second clock signals based on the input clock signal, wherein there is a preset phase difference between each first clock signal and the corresponding second clock signal; The loopback test module, coupled to the clock control module, the first interface circuit, and the second interface circuit, is configured to generate test data during the data generation phase and, during the loopback test phase, perform loopback tests on the first interface circuit and the second interface circuit based on the test data using the corresponding first clock signal and second clock signal of each group.

2. The interface test circuit according to claim 1, characterized in that, The loopback test module includes: A first conversion circuit, coupled to the clock control module and the first interface circuit, is configured to convert the data to be tested into data to be transmitted; for each first clock signal, the transmitted data is driven to the first interface circuit based on the first clock signal, so that the first interface circuit sends the transmitted data to the second interface circuit. The second conversion circuit, coupled to the clock control module and the second interface circuit, is configured to buffer multiple sets of received data received by the second interface circuit and convert them into multiple sets of sampled data. The comparison circuit, coupled to the second conversion circuit, is configured to compare multiple sets of the sampled data with a target matrix to obtain multiple sets of matching results, wherein the target matrix is ​​determined by shifting the data to be tested.

3. The interface test circuit according to claim 2, characterized in that, The loopback test module further includes: a random sequence generation circuit; The random sequence generation circuit is configured to generate the test data based on an initial seed signal if the test control signal is in a first state; and to perform a cyclic shift on the test data based on a cyclic shift control signal to obtain the target matrix if the test control signal is in a second state. The test control signal in the first state is used to indicate that the loopback test module is in the data generation stage, and the test control signal in the second state is used to indicate that the loopback test module is in the loopback test stage.

4. The interface test circuit according to claim 3, characterized in that, The target matrix includes N rows of target data; The loopback test module also includes: The shift count counting circuit is configured to count the number of cyclic shifts if the test control signal is in the second state, and to trigger the cyclic shift control signal to be valid when the number of cyclic shifts is less than N. The random sequence generation circuit is configured to, if the test control signal is in the second state, and in response to the valid cyclic shift control signal, cyclically shift the output data of the random sequence generation circuit once to obtain the target data.

5. The interface test circuit according to claim 4, characterized in that, The comparison circuit is configured to compare each set of sampled data with N rows of target data for multiple sets of sampled data to obtain multiple sets of matching results, wherein each set of matching results includes N verification results, and the verification results include verification passed or verification failed. The multiple sets of matching results are used to determine the interface test results, which include whether the interface meets the design requirements and / or the signal eye diagram width.

6. The interface test circuit according to claim 5, characterized in that, Whether the interface meets the design requirements includes: whether the number of valid matches in the multiple sets of matching results is greater than a preset threshold.

7. The interface test circuit according to claim 5, characterized in that, The signal eye diagram width is determined based on the number of target gears and the phase difference corresponding to each gear. The number of target gears is determined based on the corresponding target data line transitions that pass the verification.

8. The interface test circuit according to claim 1, characterized in that, The clock control module includes: A phase interpolation circuit is configured to perform phase interpolation on the input clock signal in response to the current gear signal, thereby generating a first clock signal having the preset phase difference relative to the input clock signal. A first control circuit, coupled to the phase interpolation circuit, is configured to output the first clock signal in response to a first enable signal being active. The second control circuit is configured to output the input clock signal as a second clock signal in response to the second enable signal being active.

9. The interface test circuit according to claim 8, characterized in that, The clock control module also includes: An enable control circuit, coupled to the first control circuit and the second control circuit, is configured to respond to a loopback enable signal being active, output the first enable signal after a first set period, and output the second enable signal after a second set period; wherein the second set period is greater than the first set period.

10. The interface test circuit according to claim 8, characterized in that, The clock control module also includes: The frequency divider circuit is configured to receive an external frequency multiplier clock signal, and divide the frequency multiplier clock signal to obtain the input clock signal.

11. An interface testing system, characterized in that, include: The frequency multiplier module is configured to receive an external reference clock signal, multiply the reference clock signal, and output a multiplied clock signal. The memory includes an interface test circuit as described in any one of claims 1 to 10, the interface test circuit being coupled to the frequency multiplier module and configured to obtain the input clock signal based on the frequency multiplier clock signal, and to test the interface of the memory based on the input clock signal.

12. A memory, characterized in that, Includes the interface test circuit as described in any one of claims 1 to 10.

13. An electronic device, characterized in that, The electronic device includes the memory as described in claim 12.

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