A dynamically adjusted flash memory error detection method and system

Abstract

The application discloses a kind of dynamic adjustment's flash memory error detection method and system, it is related to memory error detection technical field, including based on the check response baseline of target page belonging to page family to target page is read, and in low-density parity-check decoding fails or correction bit landing point is along decision boundary to spread, select abnormal corresponding decision boundary, current decoding result is obtained according to the reading execution order when establishing check response baseline, and compared with check response baseline forms check response difference;According to check response difference determines corresponding processing, when corresponding processing is local enhancement reading, small address range is executed to local enhancement reading, when corresponding processing is local subdivision reading, local subdivision reading level is increased, when corresponding processing is boundary correction, boundary correction direction is determined, and error detection is completed.The realization to small address range concentrated anomaly, reading response change and the difference in processing of decision boundary offset, improve the pertinence and dynamic adjustment capability of flash memory error detection.

Description

Technical Field

[0001] This invention relates to the field of memory error detection technology, and in particular to a dynamically adjusted flash memory error detection method and system. Background Technology

[0002] Flash memory, as a non-volatile storage medium, is widely used in solid-state drives, embedded storage, mobile terminals, and industrial control equipment. It can retain data after power failure and provide high storage density and access efficiency. With the development of multi-layer storage technology, flash memory uses different threshold voltage ranges to represent multiple storage states. During the reading process, the controller usually distinguishes adjacent storage states based on the read reference voltage and combines error detection and correction mechanisms to improve data reliability. Low-density parity checking has become an important error correction method in high-reliability flash memory read links due to its strong error correction capability and suitability for long code segment data processing. Existing flash memory error detection usually combines read reference voltage setting, read retry, inspection refresh, error counting, bad block management, and decoding result judgment to identify and process bit errors during the reading process, so as to meet the data retention and reliability management requirements of flash memory devices at different stages of use.

[0003] Existing flash memory error detection technologies, when using low-density parity decoding results to guide read adjustments, typically focus more on whether the decoding was successful or the change in the number of errors. They struggle to establish a stable correspondence between the decoding response and the decision boundaries between adjacent memory states, resulting in insufficient correlation between read adjustments and specific decision boundaries. When the correction bit points are concentrated in a small address range, existing processing methods cannot form independent read processing for this local range, affecting the precision of subsequent error detection. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides a dynamically adjusted flash memory error detection method to solve the problems of low-density parity decoding response being difficult to dynamically correlate with decision boundaries and lack of targeted reading and processing for locally concentrated errors.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: In a first aspect, the present invention provides a dynamically adjusted flash memory error detection method, comprising: After collecting the read results of the target page that has been written, perform center read, low-side micro-bias read and high-side micro-bias read on the decision boundary between adjacent storage states according to the page family to which the target page belongs, extract the low-density parity decoding results, and establish the parity response baseline of the page family to which the target page belongs.

[0007] The target page is read based on the parity response baseline of the page family to which the target page belongs. When the low-density parity decoding fails or the correction bit falls along the decision boundary, the decision boundary corresponding to the anomaly is selected. The current decoding result is obtained according to the reading execution order when the parity response baseline is established, and compared with the parity response baseline to form the parity response difference.

[0008] Based on the differential verification response, the corresponding processing is determined. When the corresponding processing is local enhanced read, local enhanced read is performed on a small address range. When the corresponding processing is local subdivision read, the local subdivision read level is increased. When the corresponding processing is boundary correction, the boundary correction direction is determined, and error detection is completed.

[0009] The verification response baseline of the page family to which the target page belongs is updated based on the error detection results, and the updated verification response baseline is called to read the page family to which the target page belongs in subsequent reads.

[0010] As a preferred embodiment of the dynamically adjusted flash memory error detection method of the present invention, the following steps are taken: The reading results of the target page after completion of writing are collected, and according to the page family to which the target page belongs, center reading, low-side micro-bias reading, and high-side micro-bias reading are performed on the decision boundary between adjacent storage states. Read the physical block address, word line address, page number, cumulative erase / write count, and write completion time of the target page, determine the block location, word line location, page type, erase / write stage, and retention stage, and combine them in sequence to form a page family identifier.

[0011] If the target page can be decoded by reading according to the current default decision boundary and the correction bit does not cross the adjacent low-density parity code segment to form a continuous address band corresponding to the decision boundary, the target page is included in the filing process. For the target page that enters the filing process, the center read, low-side micro-bias read and high-side micro-bias read are performed sequentially at each decision boundary between adjacent storage states.

[0012] As a preferred embodiment of the dynamically adjusted flash memory error detection method of the present invention, the step of extracting low-density parity decoding results and establishing a parity response baseline for the page family to which the target page belongs includes: After each read operation is completed, the read results are sent to the low-density parity check decoder in the code segment order corresponding to the low-density parity check. The total number of unsatisfied parity equations, the total number of decoding iterations, and the number of consecutive segments of correction bit landing points within the current decision boundary are extracted. The read response order is determined in the following order: priority of being able to complete decoding, priority of fewer total number of unsatisfied parity equations, priority of fewer total number of decoding iterations, and priority of fewer consecutive segments of correction bit landing points. When the current target page is a candidate filing page, and at least two subsequent pages that enter the filing process and belong to the same page family maintain the same read response order as the current target page on the same decision boundary, and the coverage area of ​​correction bit landing points maintains a continuous relationship corresponding to the current decision boundary, the read response order, the current decision boundary, the page family identifier, and the corresponding address range are solidified as the parity response baseline of the current page family.

[0013] As a preferred embodiment of the dynamically adjusted flash memory error detection method of the present invention, the step of reading the target page based on the parity response baseline of the page family to which the target page belongs, and selecting the abnormal corresponding judgment boundary when low-density parity decoding fails or the correction bit falls along the decision boundary, includes: When the page family to which the target page belongs has not formed a fixed verification response baseline, the process is switched to establishing the verification response baseline. When the page family to which the target page belongs has formed a fixed verification response baseline, the reading response order and corresponding address range are called, and the target page is read using the reading method with the highest order. When the reading result cannot complete the low-density parity check decoding, or when the correction bit falls across adjacent low-density parity check code segments to form a continuous address band corresponding to the decision boundary, the address range corresponding to the anomaly is determined, and the decision boundary with the most addresses covering the address range corresponding to the anomaly is taken as the decision boundary corresponding to the anomaly.

[0014] As a preferred embodiment of the dynamically adjusted flash memory error detection method of the present invention, the specific steps of obtaining the current decoding result according to the read execution order when establishing the verification response baseline and comparing it with the verification response baseline to form a verification response difference are as follows: For the exception-corresponding decision boundary, the reading execution order when establishing the verification response baseline is executed sequentially, including center reading, low-side micro-bias reading, and high-side micro-bias reading. The current decoding result is extracted and compared item by item with the verification response baseline under the same page family, the same decision boundary, and the same reading method. The relationship between the total number of non-satisfied verification equations, the total number of decoding iterations, and the number of consecutive segments of correction bit landing points and the verification response baseline is recorded. The relationship between the current reading response order and the reading response order in the verification response baseline is also recorded, forming the verification response difference.

[0015] As a preferred embodiment of the dynamically adjusted flash memory error detection method of the present invention, the steps are as follows: when the corresponding processing is local enhanced read, local enhanced read is performed on a small address range; when the corresponding processing is local subdivision read, a local subdivision read level is added. The address ranges corresponding to anomalies in the verification response differential are processed according to the target page address order. Local enhanced read, local subdivision read, and boundary correction are judged in sequence. When the results of center read, low-side micro-bias read, and high-side micro-bias read cannot complete low-density parity check decoding, the correction bit landing points are all concentrated in the same small address range, or center read takes priority but the target page is still in an abnormal read state, it is determined to be a local enhanced read. The reading results of center read, low-side micro-bias read, and high-side micro-bias read are used to form candidate replacement results for the small address range. The local replacement results are selected to complete the error detection according to the order of less total number of unsatisfied verification equations, less total number of decoding iteration rounds, and less number of consecutive segments of correction bit landing points.

[0016] When a local enhanced read is not included and both the low-side micro-bias read and the high-side micro-bias read are placed before the center read, or when the low-side micro-bias read and the high-side micro-bias read cause the address range corresponding to the anomaly to shrink on different consecutive address bands, it is determined to be a local subdivision read. One subdivision read is added between the center read and the low-side micro-bias read, and between the center read and the high-side micro-bias read, to form local subdivision candidate results. The local subdivision read results are selected to complete the error detection according to the order of fewer total number of unsatisfied check equations, fewer total number of decoding iterations, and fewer consecutive segments of correction bit landing points.

[0017] In a preferred embodiment of the dynamically adjusted flash memory error detection method of the present invention, the specific steps for determining the boundary correction direction and completing error detection when the corresponding processing is boundary correction are as follows: When a read is not local enhanced or local subdivision read, and the low-side micro-bias read is placed before the center read but the high-side micro-bias read is not placed before the center read, it is determined to be a boundary correction and the boundary correction direction is determined to be low-side. When the high-side micro-bias read is placed before the center read but the low-side micro-bias read is not placed before the center read, it is determined to be a boundary correction and the boundary correction direction is determined to be high-side.

[0018] During boundary correction, a single-step correction is performed on the decision boundary corresponding to the anomaly. If the single-step correction reverses the order of the read reference positions of the decision boundary corresponding to the anomaly and the adjacent decision boundary, then the boundary correction is not performed and local subdivision reading is performed. If the reversal does not occur, the read result of the corresponding address range is replaced with the corrected read result, and the code segments corresponding to the low-density parity check are sent to the low-density parity check decoder in the order of the code segments corresponding to the low-density parity check to obtain the error detection result. If the corresponding processing cannot be determined after sequential judgment, it is determined to be a local enhanced read, and error detection is performed on the small address range where the correction bit landing point is most concentrated.

[0019] As a preferred embodiment of the dynamically adjusted flash memory error detection method of the present invention, the specific steps of updating the verification response baseline of the page family to which the target page belongs based on the error detection result are as follows: When the low-density parity check decoding in the error detection result can be completed, and the correction bit no longer crosses the adjacent low-density parity check code segment to form a continuous address band corresponding to the decision boundary, the corresponding processing is written into the verification response baseline as a valid result.

[0020] When a valid result corresponds to boundary correction, the read reference position to be written, the boundary correction direction, and the corresponding decoding result are written to the verification response baseline, provided that the read reference position order has not been reversed. When a valid result corresponds to local subdivision read, the local subdivision read level and the corresponding replacement relationship are written to the verification response baseline. When a valid result corresponds to local enhancement read, the small address range, the read method used to generate the local replacement result, and the corresponding decoding result are written to the verification response baseline. When the same exception corresponds to a decision boundary where boundary correction, local subdivision read level, and local enhancement read small address range exist simultaneously, the verification response baseline is called in the order of the small address range of the local enhancement read, the local subdivision read level, and the read reference position used for the center read after boundary correction.

[0021] As a preferred embodiment of the dynamically adjusted flash memory error detection method of the present invention, wherein: the step of calling the updated verification response baseline to read the page family to which the target page belongs in subsequent reads includes: Determine the page family to which the current target page belongs, and invoke the updated verification response baseline. For address ranges that do not hit the corresponding address range of the local subdivision read level and do not hit the small address range of the local enhanced read, use the read method ranked first in the verification response baseline for reading. For the decision boundary that has been written to the local subdivision read level, execute the local subdivision read level within the corresponding address range and replace the read results within the corresponding address range. For the small address range that has been written to the local enhanced read, obtain the subsequent read results by center read, low-side micro-bias read, and high-side micro-bias read, and form a new local replacement result according to the read method corresponding to the small address range in the verification response baseline. If the subsequent read is still abnormal, re-form the verification response differential based on the updated verification response baseline.

[0022] Secondly, the present invention provides a dynamically adjustable flash memory error detection system, comprising: The verification response baseline module collects the read results of the target page after it has been written, and performs central read, low-side micro-bias read and high-side micro-bias read on the decision boundary between adjacent storage states according to the page family to which the target page belongs. It extracts the low-density parity decoding results and establishes the verification response baseline of the page family to which the target page belongs.

[0023] The verification response differential generation module reads the target page based on the verification response baseline of the page family to which the target page belongs. When the low-density parity decoding fails or the correction bit falls along the decision boundary, it selects the decision boundary corresponding to the anomaly, obtains the current decoding result according to the reading execution order when the verification response baseline is established, and compares it with the verification response baseline to form the verification response differential.

[0024] The differential-driven error detection module determines the corresponding processing based on the differential verification response. When the corresponding processing is local enhanced read, it performs local enhanced read on a small address range. When the corresponding processing is local subdivision read, it adds a local subdivision read level. When the corresponding processing is boundary correction, it determines the boundary correction direction and completes error detection.

[0025] The baseline update call module updates the verification response baseline of the page family to which the target page belongs based on the error detection results, and calls the updated verification response baseline to read the page family to which the target page belongs in subsequent reads.

[0026] The beneficial effects of this invention are as follows: By forming a check response differential based on the check response baseline, the corresponding comparison between the current decoding result and the read response order of the same decision boundary in the same page family is realized, and the decision boundary corresponding to the anomaly and the address range corresponding to the anomaly are determined. This allows the low-density parity decoding response to directly participate in the decision boundary level anomaly localization. By determining local enhanced read, local subdivision read, or boundary correction based on the check response differential, the different processing of concentrated anomalies in small address ranges, read response changes, and decision boundary offsets is realized. The effective results are written into the check response baseline, so that subsequent reads can call the updated check response baseline, thereby improving the pertinence and dynamic adjustment capability of flash memory error detection. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A flowchart for a dynamically adjusted flash memory error detection method.

[0029] Figure 2 A schematic diagram of a dynamically adjustable flash memory error detection system.

[0030] Figure 3 A flowchart is created to verify the response baseline.

[0031] Figure 4 This is a flowchart of differential-driven error detection. Detailed Implementation

[0032] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0033] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0034] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0035] Reference Figures 1-4 As one embodiment of the present invention, this embodiment provides a dynamically adjusted flash memory error detection method, comprising the following steps: S1. Collect the read results of the target page after it has been written. According to the page family to which the target page belongs, perform center read, low-side micro-bias read and high-side micro-bias read on the decision boundary between adjacent storage states, extract the low-density parity decoding results, and establish the parity response baseline of the page family to which the target page belongs.

[0036] After the target page is written, the physical block address, word line address, page number, cumulative erase / write count, and write completion time of the target page are read. The block location of the target page is determined by the physical block address, the word line location is determined by the word line address, the page type is determined by the page number combined with the page organization method and page programming order of the flash memory device, the erase / write phase is determined by the number range in which the cumulative erase / write count of the physical block containing the target page falls, and the retention phase is determined by the time range in which the retention duration between the current read time and the write completion time falls. The block location, word line location, page type, erase / write phase, and retention phase are combined in sequence to form a page family identifier, and the target page is assigned to its page family according to the page family identifier.

[0037] The number of erase / write cycles is determined based on the controller firmware configuration table corresponding to the flash memory device where the target page is located. The controller firmware configuration table records the erase / write cycle division results corresponding to the flash memory model, page type, process generation, and rated number of erase / write cycles. The erase / write cycle division results are determined by the read reference voltage drift, low-density parity check decoding convergence, and correction bit distribution changes under different cumulative erase / write cycles in the factory calibration or historical operation records. After reading the cumulative number of erase / write cycles of the physical block where the target page is located, the cumulative number of erase / write cycles is matched with the number range in the controller firmware configuration table to obtain the erase / write cycle corresponding to the target page.

[0038] The time interval of the retention phase is determined according to the controller firmware configuration table corresponding to the flash memory device where the target page is located. The controller firmware configuration table records the retention phase division results corresponding to the flash memory model, page type, process generation, and rated data retention time. The retention phase division results are determined by the read reference voltage drift, low-density parity check decoding convergence, and correction bit drop point distribution changes under different retention durations in the factory calibration or historical operation records. After reading the retention duration between the current read time and the write completion time, the retention duration is matched with the time interval in the controller firmware configuration table to obtain the retention phase corresponding to the target page.

[0039] When the flash memory device containing the target page cannot read the corresponding controller firmware configuration table, the factory calibration parameters that are consistent with the flash memory model, page type and process generation are called. When the factory calibration parameters cannot be read either, the current target page is not directly used to solidify the verification response baseline, but only as a transitional record, and the page family pages that enter the subsequent documentation process are called for verification.

[0040] After the target page is assigned to its page family, a read operation is performed on the target page using the current default decision boundary. The read result is then sent to the low-density parity check decoder in the order of the code segments corresponding to the low-density parity check. If the read result can complete the low-density parity check decoding, and the continuous segments of correction bit placements formed along the target page address order are all located within the same low-density parity check code segment, and there is no situation where the same continuous segment of correction bit placement simultaneously covers the boundary of two adjacent low-density parity check code segments, the target page is included in the filing process of the parity response baseline. If the read result cannot complete the low-density parity check decoding, or if there is a situation where the same continuous segment of correction bit placement simultaneously covers the boundary of two adjacent low-density parity check code segments, it is determined that the correction bit placement has crossed the adjacent low-density parity check code segments to form a continuous address band corresponding to the decision boundary, and the parity response baseline is not established with the current target page.

[0041] A continuous segment of corrected bit landing points refers to a set of consecutive positions where there are no uncorrected address breaks between corrected bit landing points after they are arranged in the order of the target page addresses.

[0042] The simultaneous coverage of the boundary position of two adjacent low-density parity check code segments by the same correction position point means that the start and end positions of the continuous position set are located within two adjacent low-density parity check code segments, or the continuous position set contains the boundary position of two adjacent low-density parity check code segments.

[0043] The code segment order corresponding to low-density parity check refers to the order in which the low-density parity check code segments are arranged in the decoding process after the target page read result is divided into multiple low-density parity check code segments according to the address within the target page. The arrangement order maintains a correspondence with the address order within the target page, so that each low-density parity check code segment corresponds to a continuous address range in the target page.

[0044] For page families that have not yet established a verification response baseline, the current target page is selected as the filing page. For page families that already have a verification response baseline but the verification response baseline has not yet been solidified, the current target page is selected as the supplementary page. For page families that already have a solidified verification response baseline, the filing process is not repeated. For the target page that enters the filing process, the reading is performed sequentially at each decision boundary between adjacent storage states in the order of center reading, low-side micro-bias reading, and high-side micro-bias reading.

[0045] Center reading refers to reading using the default reading reference voltage position of the current decision boundary.

[0046] Low-side micro-bias reading refers to moving the reading reference voltage corresponding to the current decision boundary to the lower voltage side by a minimum repeatable reading step relative to the default reading reference voltage before reading.

[0047] High-side micro-bias reading refers to moving the reading reference voltage corresponding to the current decision boundary to the high-voltage side by a minimum repeatable reading step relative to the default reading reference voltage before reading.

[0048] The minimum repeatable read step is determined by the controller reading the read reference voltage adjustment register of the flash memory device where the target page is located or the read reference voltage parameter table that matches the flash memory device during flash memory device initialization. The read reference voltage parameter table is pre-written into the controller by the correspondence between the flash memory device's standard, page type, and read reference voltage level. The minimum repeatable read step is the smallest level difference between adjacent settable read reference voltage levels that can be repeatedly written by the controller and stably executed by the flash memory device. Low-side micro-bias read, high-side micro-bias read, and boundary correction all use the minimum repeatable read step as the adjustment unit for the read reference position, and the adjusted read reference position should be within the read reference voltage adjustment range allowed by the flash memory device, and the order of read reference positions of adjacent decision boundaries should not be reversed.

[0049] After each read is completed, the read results are sent to the low-density parity check decoder in the order of the code segments corresponding to the low-density parity check. For all code segments within the current decision boundary coverage area, the low-density parity check decoding results are extracted. The low-density parity check decoding results include the total number of unsatisfied check equations, the total number of decoding iterations, and the number of consecutive segments of correction bit landing points.

[0050] The current decision boundary coverage refers to the continuous address range formed after the target page address sequence is categorized into the same low-density parity check code segment or adjacent low-density parity check code segments. This is achieved by keeping the reference position of the decision boundary between other adjacent memory states unchanged during the target page read process, and only performing center read, low-side micro-bias read, and high-side micro-bias read on the current decision boundary. The location where the read result changes relative to the current default decision boundary read result, the position of the correction bit landing point in low-density parity check decoding, and the position where the initial hard decision is flipped in the last iteration before decoding stops are all included in the target page address sequence. When the address positions within the target page form multiple non-contiguous address ranges, they are respectively used as the coverage range corresponding to the current decision boundary according to the target page address sequence.

[0051] The total number of unsatisfied parity equations is counted after the first check of the read result entering low-density parity-check decoding. This reflects the initial mismatch between the current read state and the low-density parity-check constraints. The total number of decoding iterations is counted to reflect the number of iterations each code segment undergoes from the start of decoding to successful or stopped decoding. This reflects the difficulty of decoding convergence. The number of consecutive segments with correction bit landing points is counted when the read result can complete decoding, based on the consecutive segments formed along the target page address order according to the position of the completed correction. When the read result cannot complete decoding, it is counted based on the consecutive segments formed along the target page address order according to the position of the flip relative to the initial hard decision in the last iteration before decoding stops. This reflects whether the error continues to expand along the decision boundary associated address band.

[0052] After obtaining the center read result, low-side micro-bias read result, and high-side micro-bias read result corresponding to the same decision boundary, the read response order of the current decision boundary is determined according to the following priority: priority for completing low-density parity check decoding, priority for fewer total number of unsatisfied parity equations, priority for fewer total decoding iterations, and priority for fewer consecutive segments of correction bit landing points. The priority order corresponds to whether the read result satisfies the low-density parity check constraint, the initial mismatch degree when the read result enters decoding, the difficulty of decoding convergence, and the degree to which the error continuously expands along the target page address sequence. When there is an inconsistency in the priority relationship between indicators, the reading response order is determined according to the order of priority, and the indicators are not merged for calculation. When the number of consecutive segments of the correction bit landing point is still consistent, the execution order of center reading, low-side micro-bias reading and high-side micro-bias reading remains unchanged. When none of the three reading results can complete the low-density parity check decoding, the temporary reading response order is determined according to the sum of the number of unsatisfied parity equations obtained at the time of decoding termination, the sum of the decoding iteration rounds, and the number of consecutive segments of the correction bit landing point. The temporary reading response order is only used as a transition record and is not fixed as the parity response baseline.

[0053] When the current target page is a candidate filing page, and at least two subsequent pages entering the filing process and belonging to the same page family maintain the same read response order as the current target page on the same decision boundary, and the correction bit landing range corresponding to the read response order maintains a continuous relationship with the current decision boundary, the read response order, along with the current decision boundary, page family identifier, and corresponding address range, is solidified as the verification response baseline of the current page family. If any subsequent page entering the filing process on the same page family has a different read response order on the same decision boundary, or the correction bit landing range no longer maintains a continuous relationship with the current decision boundary, the current record is retained as a transitional record, and subsequent pages entering the filing process on the same page family are re-verified.

[0054] The verification response baseline includes page families, decision boundaries between adjacent memory states, the decoding result corresponding to the center read, the decoding result corresponding to the low-side micro-bias read, the decoding result corresponding to the high-side micro-bias read, and the address range that continuously corresponds to the current decision boundary.

[0055] S2. Read the target page based on the check response baseline of the page family to which the target page belongs, and when the low-density parity check decoding fails or the correction bit falls along the decision boundary, select the decision boundary corresponding to the exception, obtain the current decoding result according to the reading execution order when the check response baseline is established, and compare it with the check response baseline to form a check response difference.

[0056] If the page family to which the target page belongs has not yet formed a solidified verification response baseline, then no verification response differential is formed, and the process is transferred to the verification response baseline filing process to determine whether the current target page is to be filed or supplemented. If the page family to which the target page belongs has already formed a solidified verification response baseline, then the read response order corresponding to the decision boundary between the adjacent storage states and the address range continuously corresponding to the current decision boundary in the verification response baseline are called.

[0057] After invoking the verification response baseline of the page family to which the target page belongs, a read based on the verification response baseline is performed on the target page. For each decision boundary between adjacent storage states in the target page, the read reference position for this read is the one with the decision boundary ranked first in the read response order of the verification response baseline.

[0058] The reading method that ranks first refers to one of the following: center reading, low-side micro-bias reading, or high-side micro-bias reading.

[0059] The read results are sent to the low-density parity check decoder in the order of the code segments corresponding to the low-density parity check. The low-density parity check decoding result is extracted. When the read result can complete the low-density parity check decoding and the correction bit does not cross the adjacent low-density parity check code segments to form a continuous address band corresponding to the decision boundary, it is determined that the current read state has not triggered the parity response differential formation process, and the read result is retained as the normal read result of the target page. When the read result cannot complete the low-density parity check decoding, or when the read result can complete the low-density parity check decoding but the correction bit crosses the adjacent low-density parity check code segments to form a continuous address band corresponding to the decision boundary, it is determined that the target page has entered an abnormal read state, and the abnormal decision boundary is selected again.

[0060] After the target page enters the abnormal read state, the address range corresponding to the abnormality is determined. When the read result can complete the low-density parity decoding, the continuous address band formed by the correction bit landing point along the target page address order is taken as the address range corresponding to the abnormality. When the read result cannot complete the low-density parity decoding, the continuous address band formed by the position that was flipped relative to the initial hard decision in the last iteration before the decoding stopped along the target page address order is taken as the address range corresponding to the abnormality. The address range corresponding to the abnormality is compared with the address range corresponding to each decision boundary in the verification response baseline. The decision boundary that covers the address range corresponding to the abnormality with the most addresses is selected as the decision boundary corresponding to the abnormality. If two adjacent decision boundaries cover the same number of addresses, both adjacent decision boundaries are taken as the decision boundaries corresponding to the abnormality, and the reading and comparison process is entered again respectively to form the corresponding verification response difference. If there are multiple non-contiguous address ranges corresponding to abnormalities in the target page, the corresponding decision boundaries corresponding to the abnormalities are selected in the order of the target page address, and the reading and comparison process is entered again respectively to form the corresponding verification response difference.

[0061] After determining the decision boundary corresponding to the anomaly, only the decision boundary corresponding to the anomaly is read again. The remaining decision boundaries continue to use the reading method with the highest order in the reading response sequence of the verification response baseline. For the decision boundary corresponding to the anomaly, the center reading, low-side micro-bias reading and high-side micro-bias reading are performed in sequence according to the reading execution order when the verification response baseline was established. After each type of reading is completed, the reading result is sent to the low-density parity check decoding according to the code segment order corresponding to the low-density parity check. The total number of unsatisfied verification equations, the total number of decoding iterations and the number of consecutive segments of correction bit landing points are extracted within the coverage area of ​​the decision boundary corresponding to the anomaly as the current decoding result.

[0062] The current decoding result is compared item by item with the decoding results of the same page family, the same decision boundary, and the same read method in the verification response baseline. The changes of the total number of unsatisfied verification equations, the total number of decoding iterations, and the number of consecutive segments of correction bit landing points relative to the verification response baseline are read respectively. When only one type of decoding result increases or decreases relative to the verification response baseline, and the current read response order is consistent with the read response order in the verification response baseline, the single increase or decrease is recorded as read fluctuation and is recorded as consistent. When at least two of the three types of decoding results change in the same direction relative to the verification response baseline, or when the current read response order changes relative to the read response order in the verification response baseline, the corresponding change is recorded as increase or decrease. When the change directions of the three types of decoding results are inconsistent, but the current read response order is consistent, the corresponding change is recorded as consistent. The comparison process does not compress the three types of decoding results into a single value, but retains the corresponding change relationship of the three types of decoding results relative to the verification response baseline.

[0063] The current read response order is re-determined for the current center read, the current low-side micro-bias read, and the current high-side micro-bias read. The current read response order is compared with the fixed read response order in the verification response baseline. When the current read response order is consistent with the read response order in the verification response baseline, the consistency of the read response order is included as an item in the verification response difference. When the current read response order is inconsistent with the read response order in the verification response baseline, the change in the read response order is included as an item in the verification response difference. When none of the three read results can complete the low-density parity check decoding, the current read response order is determined based on the sum of the number of unsatisfied parity equations obtained when decoding stops, the sum of the decoding iteration rounds, and the number of consecutive segments of correction bit landing points. The current read response order that cannot be decoded by any of the three read results and the temporarily determined current read response order are included as an item in the verification response difference.

[0064] The verification response differential includes the page family to which the target page belongs, the decision boundary corresponding to the exception, the address range corresponding to the exception, the current decoding result of the center read and the change relationship of the current decoding result relative to the verification response baseline, the current decoding result of the low-side micro-bias read and the change relationship of the current decoding result relative to the verification response baseline, the current decoding result of the high-side micro-bias read and the change relationship of the current decoding result relative to the verification response baseline, and the maintenance or change relationship of the current read response order relative to the read response order in the verification response baseline.

[0065] S3. Determine the corresponding processing based on the differential verification response. When the corresponding processing is local enhanced read, perform local enhanced read on the small address range. When the corresponding processing is local subdivision read, add local subdivision read level. When the corresponding processing is boundary correction, determine the boundary correction direction and complete error detection.

[0066] The error detection is performed sequentially according to the target page address. The error detection is performed on each of the error detection response differentials, including the decision boundary corresponding to the error, the address range corresponding to the error, the current decoding result of the center read, the current decoding result of the low-side micro-bias read, the current decoding result of the high-side micro-bias read, and the relationship between the current read response order and the read response order in the baseline of the error detection response. If there are multiple non-contiguous error address ranges in the target page, they are processed in the determined order. After the error detection of the address range corresponding to the previous error is completed, the address range corresponding to the next error is processed.

[0067] When determining the appropriate handling, the following principles are followed: from small to large anomaly range and from low to high degree of change in reference position, to determine whether it belongs to local enhanced reading, local subdivision reading, and boundary correction.

[0068] Local enhanced read is only used when the correction bit landing points are concentrated in the same small address range, or when the center read is ranked before the low-side micro-bias read and high-side micro-bias read in the current read response order, but the target page is still in an abnormal read state. Its effect is limited to a small address range and does not change the overall read reference position of the abnormal judgment boundary.

[0069] Local segmentation reads are used when both low-side micro-bias reads and high-side micro-bias reads are placed before the center read, or when low-side micro-bias reads and high-side micro-bias reads respectively shrink the address range corresponding to the exception on different consecutive address bands. Its function is to increase the local segmentation read level without moving the decision boundary corresponding to the exception.

[0070] Boundary correction is performed only when the read is not part of a local enhancement read or a local subdivision read, and when a low-side micro-bias read or a high-side micro-bias read has unilateral priority over a center read, in order to determine the direction of boundary correction.

[0071] If anomalies still exist after local enhancement reading, boundary correction is not performed directly. Instead, the verification response difference is re-formed based on the error detection results after local enhancement reading, and the corresponding processing is re-determined in sequence.

[0072] A small address range refers to a continuous address range within the same low-density parity check (LDPC) code segment, formed by consecutive correction bit placements, within the address range corresponding to an anomaly. When determining a small address range, the correction bit placements are first divided into several continuous segments according to the target page address order. Continuous segments that cross adjacent LPC code segments are removed. For continuous segments that cross adjacent LPC code segments, they are further divided into multiple candidate continuous segments according to the code segment boundaries. Within the same address range corresponding to an anomaly, the candidate continuous segment containing the most correction bit placements is determined as the small address range. If multiple candidate continuous segments contain the same number of correction bit placements, the candidate continuous segment with the larger number of non-satisfied parity check equations within its respective LPC code segment is selected. If they are still the same, the candidate continuous segment ranked first according to the target page address order is selected. When a candidate continuous segment covers the entire continuous address range of its respective LPC code segment, it is not considered a small address range. Instead, the address range corresponding to the anomaly within the LPC code segment to which the candidate continuous segment belongs continues to be used for local subdivision reading or boundary correction judgment.

[0073] When the corresponding processing is local enhanced reading, the reading level is not increased, nor is the overall reading reference position of the exception corresponding judgment boundary changed. For a small address range, the corresponding reading results obtained from the center reading, low-side micro-bias reading, and high-side micro-bias reading are read, and candidate decoding inputs are formed in the controller's reading buffer. When forming candidate decoding inputs, the reading results of other address ranges within the low-density parity code segment to which the small address range belongs remain unchanged. Only the reading results of the small address range within the same target page, the same low-density parity code segment, and the same address position within the same target page are replaced with the reading results corresponding to the center reading, low-side micro-bias reading, and high-side micro-bias reading, respectively, forming three candidate replacement results. The address order, code segment length, and code segment order corresponding to low-density parity of the candidate replacement results are consistent with the original reading results. Moreover, the replacement is only used to form low-density parity decoding inputs and does not rewrite the stored data of the target page. The three candidate replacement results are sent to the low-density parity decoding inputs respectively. The row check comparison selects the candidate replacement result that minimizes the number of unsatisfied check equations in the low-density parity check code segment as the local replacement result for the small address range. If the number of unsatisfied check equations is the same, the candidate replacement result with fewer decoding iterations is preferred. If the total number of decoding iterations is still the same, the candidate replacement result with fewer consecutive segments of correction bit landing points is preferred. After the local replacement is completed, only the local replacement result of the small address range replaces the reading result of the corresponding address range in the target page. The remaining address range still retains the reading result based on the check response baseline. The reading result of the replaced target page is sent to the low-density parity check decoder in the code segment order corresponding to the low-density parity check. When the decoding can be completed and the correction bit landing points are no longer concentrated in the small address range, the error detection result is determined to be that the error detection was completed after local enhancement reading. When the decoding cannot be completed or the correction bit landing points are still concentrated in the small address range, the error detection result is determined to be that there is still an anomaly after local enhancement reading.

[0074] When a read is not a local enhanced read and both the low-side micro-bias read and the high-side micro-bias read are placed before the central read in the current read response order, or when the low-side micro-bias read and the high-side micro-bias read cause the address range corresponding to the anomaly to shrink on different consecutive address bands, the corresponding processing will be determined as a local subdivision read.

[0075] Prioritizing reading from the center means that the reading method has fewer total unsatisfied check equations, fewer total decoding iterations when the total number of unsatisfied check equations is the same, or fewer consecutive segments of correction bit landing points when the total number of decoding iterations is the same.

[0076] Shrinkage on different continuous address bands refers to the reduction in the number of consecutive segments of correction bit landing points in different continuous address bands caused by low-side micro-bias reads and high-side micro-bias reads, and the continuous address bands corresponding to low-side micro-bias reads and high-side micro-bias reads are not exactly the same.

[0077] When processing local subdivision reading, the current reading reference position of the exception-corresponding decision boundary is not moved. Instead, an additional subdivision reading is added between the reading reference position corresponding to the center reading and the reading reference position corresponding to the low-side micro-bias reading, serving as a subdivision reading closer to the low-side micro-bias reading. Similarly, an additional subdivision reading is added between the reading reference position corresponding to the center reading and the reading reference position corresponding to the high-side micro-bias reading, serving as a subdivision reading closer to the high-side micro-bias reading. This increases the reading level formed by the center reading, low-side micro-bias reading, and high-side micro-bias reading to a local subdivision reading level containing the two newly added subdivision readings. After completing the two newly added subdivision readings, three local subdivision candidate results are formed, the first... The first local segmentation candidate result is to replace the read result of the corresponding address range within the decision boundary coverage area of ​​the anomaly with the segmentation read result closer to the low-side micro-bias read. The second local segmentation candidate result is to replace the read result of the corresponding address range within the decision boundary coverage area of ​​the anomaly with the segmentation read result closer to the high-side micro-bias read. The third local segmentation candidate result is to read each continuous address band in the address range corresponding to the anomaly in the order of the target page address. When the low-side micro-bias read causes the current continuous address band to shrink while the high-side micro-bias read does not, the read result of the current continuous address band is replaced with the segmentation read result closer to the low-side micro-bias read. If the current continuous address band is not shrunk during a read, the read result of the current continuous address band is replaced by the subdivision read result closer to the high-side micro-bias read. When both the low-side and high-side micro-bias reads shrink the current continuous address band, the subdivision read result used for the current continuous address band is determined according to the order of fewer total number of unsatisfied parity equations, fewer total number of decoding iterations, and fewer consecutive segments of correction bit landing points. Each local subdivision candidate result is sent to the low-density parity check decoder in the order of the code segments corresponding to the low-density parity check. The local subdivision read result is selected according to the order of fewer total number of unsatisfied parity equations, fewer total number of decoding iterations, and fewer consecutive segments of correction bit landing points. The read results are used to replace the read results within the decision boundary coverage area corresponding to the anomaly. The remaining decision boundaries are still read using the order of the read response sequence of the verification response baseline. The read results of the replaced target page are sent to the low-density parity check decoder in the code segment order corresponding to the low-density parity check. When the decoding can be completed and the correction bit no longer crosses the adjacent low-density parity check code segment to form a continuous address band corresponding to the decision boundary, the error detection result is determined to be an error detection completed after local subdivision reading. When the decoding cannot be completed, or the correction bit still crosses the adjacent low-density parity check code segment to form a continuous address band corresponding to the decision boundary, the error detection result is determined to be an anomaly still existing after local subdivision reading.

[0078] When a read is not a local enhanced read or a local subdivision read, and the low-side micro-bias read is placed before the center read in the current read response order but not before the center read, the corresponding processing is determined as boundary correction, and the boundary correction direction is determined to be low-side.

[0079] When the corresponding processing is boundary correction, a single-step correction is performed on the exception-corresponding decision boundary. When the boundary correction direction is low-side, the reading reference position of the exception-corresponding decision boundary is moved towards the low-voltage side relative to the current reading reference position by a minimum repeatable reading step. When the boundary correction direction is high-side, the reading reference position of the exception-corresponding decision boundary is moved towards the high-voltage side relative to the current reading reference position by a minimum repeatable reading step. The maximum offset range of the boundary correction is limited to a minimum repeatable reading step corresponding to the differential of this verification response. Multiple boundary corrections are not performed consecutively in the same error detection. If the single-step correction reverses the order of the reading reference positions of the exception-corresponding decision boundary and the adjacent decision boundary, the boundary correction is not performed, and local subdivision reading is performed instead. After the single-step correction is completed, the corrected reading result within the coverage area of ​​the exception-corresponding decision boundary is used to replace the corresponding decision boundary in the controller's reading buffer. The reading results of the address range are used to read the remaining decision boundaries using the reading response order that is first in the check response baseline. The replacement is only used to form the low-density parity decoding input and does not rewrite the stored data of the target page. The reading results of the replaced target page are sent to the low-density parity decoding according to the code segment order corresponding to the low-density parity. When the decoding can be completed and the correction bit no longer crosses the adjacent low-density parity code segment to form a continuous address band corresponding to the decision boundary, the error detection result is determined to be an error detection completed after boundary correction. When the decoding cannot be completed, or the correction bit still crosses the adjacent low-density parity code segment to form a continuous address band corresponding to the decision boundary, the error detection result is determined to be an anomaly that still exists after boundary correction. The boundary correction step size is not further expanded, and the error detection result is recorded as an ineffective processing record for subsequent re-formation of the check response differential.

[0080] If the corresponding processing cannot be determined after sequential judgment, the corresponding processing is determined to be local enhanced reading. A small address range for fallback processing is determined from the address range corresponding to the anomaly. When determining the small address range for fallback processing, each candidate small address range in the address range corresponding to the anomaly is read in the order of the target page address. The number of correction bit landing points in each candidate small address range is counted. The candidate small address range with the most correction bit landing points is determined as the small address range with the most concentrated correction bit landing points. If multiple candidate small address ranges have the same number of correction bit landing points, the candidate small address range with the shorter address span is selected first. If the address span is still the same, the candidate small address range with the larger number of unsatisfied check equations in the low-density parity check code segment is selected first. If they are still the same, the candidate small address range that is ranked first in the order of the target page address is selected, and local enhanced reading is performed on the determined small address range.

[0081] Error detection results include the page family to which the target page belongs, the decision boundary corresponding to the anomaly, the address range corresponding to the anomaly, the corresponding processing, the boundary correction direction related to the corresponding processing, the small address range of the local subdivision reading level or the local enhanced reading, whether the low-density parity check decoding can be completed, and whether the correction bit landing point still crosses the adjacent low-density parity check code segment to form a continuous address band corresponding to the decision boundary.

[0082] S4. Update the verification response baseline of the page family to which the target page belongs based on the error detection results, and call the updated verification response baseline to read the page family to which the target page belongs in subsequent reads.

[0083] Based on the error detection results, the following information is retrieved: the page family to which the target page belongs, the decision boundary corresponding to the anomaly, the address range corresponding to the anomaly, the corresponding processing, the boundary correction direction related to the corresponding processing, the small address range of the local subdivision reading level or the local enhanced reading, whether low-density parity check decoding can be completed, and whether the correction bit landing point still crosses adjacent low-density parity check code segments to form a continuous address band corresponding to the decision boundary. When low-density parity check decoding can be completed and the correction bit landing point no longer crosses adjacent low-density parity check code segments to form a continuous address band corresponding to the decision boundary, this corresponding processing is considered a valid result that can be written into the verification response baseline. When low-density parity check decoding cannot be completed, or the correction bit landing point still crosses adjacent low-density parity check code segments to form a continuous address band corresponding to the decision boundary, only the page family to which the target page belongs, the decision boundary corresponding to the anomaly, the address range corresponding to the anomaly, and the corresponding processing are retained as ineffective processing records and are not used as the basis for subsequent reading.

[0084] When the processing corresponding to the valid result is boundary correction, the write-read reference position of the exception-corresponding decision boundary is determined according to the boundary correction direction. If the boundary correction direction is low-side, the read reference position of the exception-corresponding decision boundary after single-step correction on the low-voltage side is used as the write-read reference position. If the boundary correction direction is high-side, the read reference position of the exception-corresponding decision boundary after single-step correction on the high-voltage side is used as the write-read reference position. When the write-read reference position is consistent with the read reference position of the adjacent decision boundary, it is not directly fixed as the verification response baseline. Instead, the write-read reference position, boundary correction direction, exception-corresponding decision boundary, exception-corresponding address range, and low-density parity check decoding result obtained after boundary correction are written into the unconfirmed boundary correction record. When the first target page belonging to the same page family hits the same exception-corresponding decision boundary and exception-corresponding address range again, and is read according to the boundary correction direction in the unconfirmed boundary correction record, the low-density parity check decoding can be completed and the correction bit landing point no longer crosses the formation and judgment of adjacent low-density parity check code segments. When dealing with consecutive address bands corresponding to the decision boundary, the read reference position to be written, the boundary correction direction, and the corresponding decoding result are solidified into the verification response baseline of the page family to which the target page belongs. The read reference position to be written is used as the default read reference position for subsequent execution center reads corresponding to the exception decision boundary. When the first target page belonging to the same page family does not hit the same exception decision boundary and the address range corresponding to the exception again, the boundary correction record to be confirmed is retained but not used as the solidified verification response baseline. When the first target page belonging to the same page family hits the same exception decision boundary and the address range corresponding to the exception again, but the low-density parity check decoding cannot be completed after reading according to the boundary correction record to be confirmed, or the correction bit landing point still crosses the adjacent low-density parity check code segment to form a consecutive address band corresponding to the decision boundary, the boundary correction record to be confirmed is withdrawn, and a new verification response differential is formed when the subsequent read enters the exception read state. When the order of the read reference position to be written and the read reference position of the adjacent decision boundary is reversed, the boundary correction result is not written, and the boundary correction record to be confirmed is not generated.

[0085] When the processing corresponding to the valid result is a partial subdivision read, the selected partial subdivision read level and the corresponding replacement relationship are written into the verification response baseline of the page family to which the target page belongs. A correspondence is established between the partial subdivision read level and the exception-corresponding decision boundary and the exception-corresponding address range. If the selected partial subdivision read result comes from a subdivision read close to the low-side micro-bias read, then when reading the same decision boundary of the page family to which the target page belongs in the subsequent process, a subdivision read close to the low-side micro-bias read is performed in the corresponding address range, and the subdivision read result replaces the read result in the corresponding address range. If the selected partial subdivision read result comes from a subdivision read close to the high-side micro-bias read, then when reading the same decision boundary of the page family to which the target page belongs in the subsequent process, a subdivision read close to the high-side micro-bias read is performed in the corresponding address range, and the subdivision read result obtained in the subsequent process replaces the read result in the corresponding address range. If the selected partial subdivision read result is the result of two newly added subdivision reads replacing the read results in the corresponding continuous address range, then when reading the same decision boundary of the page family to which the target page belongs in the subsequent process, two newly added subdivision reads are performed in the order of the target page address, and the two newly added subdivision read results obtained in this process replace the read results in the corresponding continuous address range.

[0086] When the processing corresponding to the valid result is a local enhanced read, the small address range of the local enhanced read and the read method used to generate the local replacement result are not directly solidified into the verification response baseline. Instead, the page family to which the target page belongs, the exception corresponding decision boundary, the small address range, the read method used to generate the local replacement result, and the corresponding low-density parity decoding result are written into the unconfirmed local enhanced record. When the first subsequent target page belonging to the same page family hits the same exception corresponding decision boundary and the same small address range again, and a new local replacement result is formed according to the read method in the unconfirmed local enhanced record, and the low-density parity decoding can be completed and the correction bit landing point is no longer concentrated in that small address range, the small address range, the read method used to generate the local replacement result, and the corresponding low-density parity decoding result are solidified into the verification response baseline of the page family to which the target page belongs. When the first subsequent target page belonging to the same page family does not hit the same exception corresponding decision boundary and the same small address range again, the unconfirmed local enhanced record is retained but not used as the solidified verification response baseline. When the first subsequent target page belonging to the same page family hits the same exception corresponding decision boundary again... If the boundary and the same small address range are involved, but the low-density parity check decoding still cannot be completed after forming a new local replacement result according to the reading method in the local enhancement record to be confirmed, or if the correction bit landing points are still concentrated in the small address range, the local enhancement record to be confirmed is withdrawn. A new parity response differential is then formed when subsequent readings enter an abnormal reading state. After the small address range of the local enhancement read is fixed, when subsequently reading the page family to which the target page belongs, if the read address hits the small address range, the reading result of the remaining address range within the low-density parity check code segment to which the small address range belongs remains unchanged. According to the read method written in the verification response baseline, a new local replacement result is formed from the center read, low-side micro-bias read, and high-side micro-bias read results obtained in this subsequent read. The read result of the small address range is replaced with the new local replacement result. The target page read result after replacement is sent to the low-density parity check decoder in the code segment order corresponding to the low-density parity check. If the read address does not hit the small address range, the read method corresponding to the small address range of the local enhanced read is not called. Instead, the read is performed in the read response order corresponding to the decision boundary in the page family verification response baseline.

[0087] When the same exception corresponds to a decision boundary where there are simultaneously boundary correction, local subdivision read level, and local enhanced read small address ranges, subsequent reads will call the verification response baseline in the order of the small address range of local enhanced read, local subdivision read level, and the read reference position used by the center read after boundary correction. The small address range of local enhanced read only applies to the corresponding continuous address range, the local subdivision read level only applies to the address range corresponding to the exception, and the read reference position used by the center read after boundary correction applies to the address range within the decision boundary that is not covered by local enhanced read and local subdivision read.

[0088] For the local enhanced read segment address range to be written to the verification response baseline, an overlap consistency check is performed. If the segment address range to be written overlaps with the segment address range already written, the non-overlapping parts are retained according to their respective reading methods. The overlapping address ranges are divided into candidate replacement results according to the reading methods to be written and the reading methods already written, and then sent to low-density parity check decoding for verification and comparison. The reading methods that can complete low-density parity check decoding are retained first. If both can complete low-density parity check decoding, the reading method for subsequent calls to the overlapping address range is determined according to the order of fewer total number of unsatisfied check equations, fewer total decoding iterations, and fewer consecutive segments of correction bit landing points. If they are still consistent, the reading method corresponding to the segment address range formed first is retained according to the target page address order. When the subsequent read hits the overlapping address range, a new local replacement result is formed based on the reading method retained in the verification response baseline and the center read, low-side micro-bias read, and high-side micro-bias read results obtained in this subsequent read.

[0089] For records that have not taken effect, when reading the page family to which the target page belongs, if the same exception is hit again at the decision boundary and the address range corresponding to the exception, the already fixed check response baseline will still be called first for reading. When low-density parity decoding fails again, or the correction bit falls across the adjacent low-density parity code segment to form a continuous address band corresponding to the decision boundary, a new check response differential will be formed instead of directly calling the records that have not taken effect.

[0090] When reading the page family to which the target page belongs in subsequent reads, first determine the page family to which the current target page belongs, and call the updated verification response baseline. For address ranges that do not hit the corresponding address range of the local subdivision read level and do not hit the small address range of the local enhanced read, use the read method with the highest order in the verification response baseline for reading. If the corresponding decision boundary has been written to the read reference position used by the boundary-corrected center read, then the center read is based on the boundary-corrected read reference position. The low-side micro-bias read and the high-side micro-bias read are both determined based on this read reference position. For decision boundaries that have been written to the local subdivision read level, the local subdivision read level is executed in the corresponding address range, and the read result in the corresponding address range is replaced with the result of this local subdivision read. For small address ranges that have been written to the local enhanced read, the read result is obtained in the small address range according to the center read, low-side micro-bias read, and high-side micro-bias read respectively. According to the read method recorded in the verification response baseline, a new local replacement result is formed from the center read, low-side micro-bias read, and high-side micro-bias read results obtained in subsequent reads. The replacement result replaces the read result of a small address range. The target page read result is then sent to the low-density parity check decoder in the order of the code segments corresponding to the low-density parity check. If the low-density parity check decoder can be completed and the correction bit does not cross adjacent low-density parity check code segments to form a continuous address band corresponding to the decision boundary, the read is completed. If the low-density parity check decoder cannot be completed, or the correction bit still crosses adjacent low-density parity check code segments to form a continuous address band corresponding to the decision boundary, the read is completed for the same target page, the same exception corresponding to the decision boundary, and the same exception corresponding to the decision boundary. For each address range, a new parity response differential is formed only once. After determining the corresponding processing based on the parity response differential, error detection is performed again. If low-density parity decoding still cannot be completed after performing error detection again, or if the correction bit still crosses the adjacent low-density parity code segment to form a continuous address band corresponding to the decision boundary, then the dynamic adjustment process is stopped, no new parity response differential is formed, the result is recorded as an ineffective processing record, not written to the parity response baseline, and the target page is transferred to the flash controller's read retry record, data migration record, or bad block management record.

[0091] The updated verification response baseline includes the page family to which the target page belongs, the decision boundary between adjacent storage states, the original read response order, the read reference position used for the center read after boundary correction when a corresponding valid result exists, the local subdivision read level, the small segment address range of the local enhanced read, the read method corresponding to the small segment address range of the local enhanced read, and the low-density parity check decoding result used to verify the validity of the corresponding read method. Records that have not taken effect are retained as records but are not used as the basis for subsequent reads.

[0092] This embodiment also provides a dynamically adjustable flash memory error detection system, including: The verification response baseline module collects the read results of the target page after it has been written, and performs central read, low-side micro-bias read and high-side micro-bias read on the decision boundary between adjacent storage states according to the page family to which the target page belongs. It extracts the low-density parity decoding results and establishes the verification response baseline of the page family to which the target page belongs. The verification response differential generation module reads the target page based on the verification response baseline of the page family to which the target page belongs. When the low-density parity check decoding fails or the correction bit falls along the decision boundary, the module selects the decision boundary corresponding to the anomaly, obtains the current decoding result according to the reading execution order when the verification response baseline is established, and compares it with the verification response baseline to form the verification response differential. The differential-driven error detection module determines the corresponding processing based on the differential verification response. When the corresponding processing is local enhanced read, it performs local enhanced read on a small address range. When the corresponding processing is local subdivision read, it adds a local subdivision read level. When the corresponding processing is boundary correction, it determines the boundary correction direction and completes error detection. The baseline update call module updates the verification response baseline of the page family to which the target page belongs based on the error detection results, and calls the updated verification response baseline to read the page family to which the target page belongs in subsequent reads.

[0093] In summary, this invention achieves the following: by forming a parity response differential based on the parity response baseline, it realizes the correspondence and comparison between the current decoding result and the read response order of the same decision boundary in the same page family, and determines the decision boundary and address range corresponding to the anomaly. This allows the low-density parity decoding response to directly participate in the decision boundary level anomaly localization. By determining local enhanced read, local subdivision read, or boundary correction based on the parity response differential, it achieves differentiated processing of concentrated anomalies in small address ranges, read response changes, and decision boundary offsets. The effective results are written into the parity response baseline, so that subsequent reads can call the updated parity response baseline, thereby improving the pertinence and dynamic adjustment capability of flash memory error detection.

[0094] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A dynamically adjusted flash memory error detection method, characterized in that, include: After collecting the read results of the target page that has been written, perform center read, low-side micro-bias read and high-side micro-bias read on the decision boundary between adjacent storage states according to the page family to which the target page belongs, extract the low-density parity decoding results, and establish the parity response baseline of the page family to which the target page belongs; The target page is read based on the verification response baseline of the page family to which the target page belongs. When the low-density parity decoding fails or the correction bit falls along the decision boundary, the corresponding decision boundary is selected. The current decoding result is obtained according to the reading execution order when the verification response baseline is established, and compared with the verification response baseline to form the verification response difference. Based on the differential verification response, the corresponding processing is determined. When the corresponding processing is local enhanced read, local enhanced read is performed on a small address range. When the corresponding processing is local subdivision read, the local subdivision read level is increased. When the corresponding processing is boundary correction, the boundary correction direction is determined and error detection is completed. The verification response baseline of the page family to which the target page belongs is updated based on the error detection results, and the updated verification response baseline is called to read the page family to which the target page belongs in subsequent reads.

2. The dynamically adjusted flash memory error detection method as described in claim 1, characterized in that, The process involves collecting the read results of the target page after it has been written, and then performing central read, low-side micro-bias read, and high-side micro-bias read on the decision boundary between adjacent storage states, according to the page family to which the target page belongs. The specific steps are as follows: Read the physical block address, word line address, page number, cumulative erase / write count, and write completion time of the target page; determine the block location, word line location, page type, erase / write stage, and retention stage; and combine them in sequence to form a page family identifier. If the target page can be decoded by reading according to the current default decision boundary and the correction bit does not cross the adjacent low-density parity code segment to form a continuous address band corresponding to the decision boundary, the target page is included in the filing process. For the target page that enters the filing process, the center read, low-side micro-bias read and high-side micro-bias read are performed sequentially at each decision boundary between adjacent storage states.

3. The dynamically adjusted flash memory error detection method as described in claim 2, characterized in that, The extraction of low-density parity-check decoding results and the establishment of a parity response baseline for the page family to which the target page belongs include: After each read operation is completed, the read results are sent to the low-density parity check decoder in the code segment order corresponding to the low-density parity check. The total number of unsatisfied parity equations, the total number of decoding iterations, and the number of consecutive segments of correction bit landing points within the current decision boundary are extracted. The read response order is determined in the following order: priority of being able to complete decoding, priority of fewer total number of unsatisfied parity equations, priority of fewer total number of decoding iterations, and priority of fewer consecutive segments of correction bit landing points. When the current target page is a candidate filing page, and at least two subsequent pages that enter the filing process and belong to the same page family maintain the same read response order as the current target page on the same decision boundary, and the coverage area of ​​correction bit landing points maintains a continuous relationship corresponding to the current decision boundary, the read response order, the current decision boundary, the page family identifier, and the corresponding address range are solidified as the parity response baseline of the current page family.

4. The dynamically adjusted flash memory error detection method as described in claim 1 or 3, characterized in that, The process of reading the target page based on the parity response baseline of the page family to which the target page belongs, and selecting the corresponding exception judgment boundary when low-density parity decoding fails or the correction bit falls along the decision boundary, includes: When the page family to which the target page belongs has not formed a fixed verification response baseline, the process is switched to establishing the verification response baseline. When the page family to which the target page belongs has formed a fixed verification response baseline, the reading response order and corresponding address range are called, and the target page is read using the reading method with the highest order. When the reading result cannot complete the low-density parity check decoding, or when the correction bit falls across adjacent low-density parity check code segments to form a continuous address band corresponding to the decision boundary, the address range corresponding to the anomaly is determined, and the decision boundary with the most addresses covering the address range corresponding to the anomaly is taken as the decision boundary corresponding to the anomaly.

5. The dynamically adjusted flash memory error detection method as described in claim 4, characterized in that, The specific steps for obtaining the current decoding result according to the reading execution order when establishing the verification response baseline and comparing it with the verification response baseline to form the verification response difference are as follows: For the exception-corresponding decision boundary, the reading execution order when establishing the verification response baseline is executed sequentially, including center reading, low-side micro-bias reading, and high-side micro-bias reading. The current decoding result is extracted and compared item by item with the verification response baseline under the same page family, the same decision boundary, and the same reading method. The relationship between the total number of non-satisfied verification equations, the total number of decoding iterations, and the number of consecutive segments of correction bit landing points and the verification response baseline is recorded. The relationship between the current reading response order and the reading response order in the verification response baseline is also recorded, forming the verification response difference.

6. The dynamically adjusted flash memory error detection method as described in claim 1 or 5, characterized in that, The specific steps are as follows: When the corresponding processing is local enhanced read, local enhanced read is performed on a small address range; when the corresponding processing is local subdivision read, a local subdivision read level is added. The address range corresponding to the anomaly in the verification response differential is processed according to the target page address order, and local enhanced reading, local subdivision reading and boundary correction are judged in sequence. When the results of center reading, low-side micro-bias reading and high-side micro-bias reading cannot complete low-density parity check decoding, the correction bit landing points are all concentrated in the same small address range, or center reading takes priority but the target page is still in an abnormal reading state, it is determined to be local enhanced reading. The reading results of center reading, low-side micro-bias reading and high-side micro-bias reading are used to form candidate replacement results for the small address range, and the local replacement results are selected to complete the error detection according to the order of less total number of unsatisfied verification equations, less total number of decoding iteration rounds and less number of consecutive segments of correction bit landing points. When a local enhanced read is not included and both the low-side micro-bias read and the high-side micro-bias read are placed before the center read, or when the low-side micro-bias read and the high-side micro-bias read cause the address range corresponding to the anomaly to shrink on different consecutive address bands, it is determined to be a local subdivision read. One subdivision read is added between the center read and the low-side micro-bias read, and between the center read and the high-side micro-bias read, to form local subdivision candidate results. The local subdivision read results are selected to complete the error detection according to the order of fewer total number of unsatisfied check equations, fewer total number of decoding iterations, and fewer consecutive segments of correction bit landing points.

7. The dynamically adjusted flash memory error detection method as described in claim 6, characterized in that, The specific steps for determining the boundary correction direction and completing error detection when the corresponding processing is boundary correction are as follows: When it does not belong to local enhancement reading and local subdivision reading, and the low-side micro-bias reading is ranked before the center reading and the high-side micro-bias reading is not ranked before the center reading, it is determined to be boundary correction and the boundary correction direction is determined to be low side. When the high-side micro-bias reading is ranked before the center reading and the low-side micro-bias reading is not ranked before the center reading, it is determined to be boundary correction and the boundary correction direction is determined to be high side. During boundary correction, a single-step correction is performed on the decision boundary corresponding to the anomaly. If the single-step correction reverses the order of the read reference positions of the decision boundary corresponding to the anomaly and the adjacent decision boundary, then the boundary correction is not performed and local subdivision reading is performed. If the reversal does not occur, the read result of the corresponding address range is replaced with the corrected read result, and the code segments corresponding to the low-density parity check are sent to the low-density parity check decoder in the order of the code segments corresponding to the low-density parity check to obtain the error detection result. If the corresponding processing cannot be determined after sequential judgment, it is determined to be a local enhanced read, and error detection is performed on the small address range where the correction bit landing point is most concentrated.

8. The dynamically adjusted flash memory error detection method as described in claim 1 or 7, characterized in that, The specific steps for updating the verification response baseline of the page family to which the target page belongs based on the error detection results are as follows: When the low-density parity check decoding in the error detection result can be completed, and the correction bit landing point no longer crosses the adjacent low-density parity check code segment to form a continuous address band corresponding to the decision boundary, the corresponding processing is written into the verification response baseline as a valid result. When a valid result corresponds to boundary correction, the read reference position to be written, the boundary correction direction, and the corresponding decoding result are written to the verification response baseline, provided that the read reference position order has not been reversed. When a valid result corresponds to local subdivision read, the local subdivision read level and the corresponding replacement relationship are written to the verification response baseline. When a valid result corresponds to local enhancement read, the small address range, the read method used to generate the local replacement result, and the corresponding decoding result are written to the verification response baseline. When the same exception corresponds to a decision boundary where boundary correction, local subdivision read level, and local enhancement read small address range exist simultaneously, the verification response baseline is called in the order of the small address range of the local enhancement read, the local subdivision read level, and the read reference position used for the center read after boundary correction.

9. The dynamically adjusted flash memory error detection method as described in claim 8, characterized in that, The step of calling the updated verification response baseline to read the page family to which the target page belongs in subsequent reads includes: Determine the page family to which the current target page belongs, and invoke the updated verification response baseline. For address ranges that do not hit the corresponding address range of the local subdivision read level and do not hit the small address range of the local enhanced read, use the read method ranked first in the verification response baseline for reading. For the decision boundary that has been written to the local subdivision read level, execute the local subdivision read level within the corresponding address range and replace the read results within the corresponding address range. For the small address range that has been written to the local enhanced read, obtain the subsequent read results by center read, low-side micro-bias read, and high-side micro-bias read, and form a new local replacement result according to the read method corresponding to the small address range in the verification response baseline. If the subsequent read is still abnormal, re-form the verification response differential based on the updated verification response baseline.

10. A dynamically adjusted flash memory error detection system, based on the dynamically adjusted flash memory error detection method according to any one of claims 1 to 9, characterized in that, include: The verification response baseline module collects the read results of the target page after it has been written, and performs central read, low-side micro-bias read and high-side micro-bias read on the decision boundary between adjacent storage states according to the page family to which the target page belongs. It extracts the low-density parity decoding results and establishes the verification response baseline of the page family to which the target page belongs. The verification response differential generation module reads the target page based on the verification response baseline of the page family to which the target page belongs. When the low-density parity check decoding fails or the correction bit falls along the decision boundary, the module selects the decision boundary corresponding to the anomaly, obtains the current decoding result according to the reading execution order when the verification response baseline is established, and compares it with the verification response baseline to form the verification response differential. The differential-driven error detection module determines the corresponding processing based on the differential verification response. When the corresponding processing is local enhanced read, it performs local enhanced read on a small address range. When the corresponding processing is local subdivision read, it adds a local subdivision read level. When the corresponding processing is boundary correction, it determines the boundary correction direction and completes error detection. The baseline update call module updates the verification response baseline of the page family to which the target page belongs based on the error detection results, and calls the updated verification response baseline to read the page family to which the target page belongs in subsequent reads.

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