A memory and electronic device

Abstract

The present disclosure provides a memory and an electronic device, the memory comprising: N test circuits, each test circuit corresponding to one test bonding point of the memory, N being a positive integer; each test bonding point being connected with a detection line, a signal on the detection line being a detection signal; an i th test circuit being configured to control a level state of an i th test bonding point to be a first level state, so that the detection signal is in the first level state; a j th test circuit being configured to control a level state of a j th test bonding point to be a second level state, so that the detection signal is in the second level state; i and j both being greater than 0 and less than or equal to N, i being an odd number, and j being an even number; the first level state and the second level state being mutually inverse, and the N test circuits sequentially controlling the level states of the corresponding test bonding points.

Description

Technical Field

[0001] This disclosure relates to semiconductor technology, and more particularly to a memory and electronic device. Background Technology

[0002] Multi-wafer bonding is one of the key technologies for achieving chip stacking and system integration, thereby improving the equivalent density of integrated circuits. Multi-wafer bonding typically refers to bonding two or more pre-fabricated wafers together using interface bonding processes, and achieving mechanical fixation and electrical connection between the wafers through vertical interconnect structures. Multi-wafer bonding often employs a combination of flip chip (FC) bonding, through silicon via (TSV) bonding, and bump / pad bonding techniques to achieve mechanical and circuit interconnection.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a memory and an electronic device thereof.

[0005] In a first aspect, embodiments of this disclosure provide a memory, including: There are N test circuits, where N is a positive integer. Each test circuit corresponds to one test bonding point of the memory. All N test bonding points are connected to a detection line, and the signal on the detection line is a detection signal. The i-th test circuit is used to control the level state of the i-th test bonding point to a first level state, so that the detection signal is in the first level state; i is an odd number greater than 0 and less than or equal to N; The j-th test circuit is used to control the level state of the j-th test bonding point to a second level state, so that the detection signal is in the second level state; j is an even number greater than 0 and less than or equal to N; Wherein, the first level state and the second level state are opposite to each other, and from the 1st to the Nth, the N test circuits sequentially control the level state of the corresponding test bonding point.

[0006] In some embodiments, each of the test circuits includes a register circuit and a level control circuit; The first register circuit is used to receive the initial flag signal and perform sampling processing, and output the first sampling flag signal and the first inverted flag signal, wherein the sampling flag signal and the inverted flag signal are inverted relative to each other; the second to the Nth register circuits are used to receive the sampling flag signal output by the previous register circuit and perform sampling processing, and output the corresponding sampling flag signal and the inverted flag signal. The i-th level control circuit is used to control the level state of the i-th test bonding point to the first level state based on one of the i-th sampling flag signal and the i-th inverted flag signal; The j-th level control circuit is used to control the level state of the j-th test bonding point to the second level state based on the other of the j-th sampling flag signal and the j-th inverted flag signal.

[0007] In some embodiments, the level control circuit is a MOSFET; The control terminal of the MOS transistor receives the corresponding sampling flag signal or the corresponding inverting flag signal; The first terminal of the i-th MOS transistor is connected to a first input signal that provides the first level state; The first terminal of the j-th MOS transistor is connected to a second input signal that provides the second level state; The second end of the MOS transistor is connected to the corresponding test bonding point.

[0008] In some embodiments, the initial flag signal and each of the sampling flag signals are both in the first level state, and each of the inverted flag signals is in the second level state; the first level state is a high level state, and the second level state is a low level state; The i-th MOS transistor is a PMOS transistor, and the control terminal of the PMOS transistor receives the corresponding inverting flag signal; the j-th MOS transistor is an NMOS transistor, and the control terminal of the NMOS transistor receives the corresponding sampling flag signal. Alternatively, the i-th MOS transistor is an NMOS transistor, and the control terminal of the NMOS transistor receives the corresponding sampling flag signal; the j-th MOS transistor is a PMOS transistor, and the control terminal of the PMOS transistor receives the corresponding inversion flag signal.

[0009] In some embodiments, the initial flag signal and each of the sampling flag signals are both in the first level state, and each of the inverted flag signals is in the second level state; the first level state is a low level state, and the second level state is a high level state; The i-th MOS transistor is a PMOS transistor, and the control terminal of the PMOS transistor receives the corresponding sampling flag signal; the j-th MOS transistor is an NMOS transistor, and the control terminal of the NMOS transistor receives the corresponding inversion flag signal. Alternatively, the i-th MOS transistor is an NMOS transistor, and the control terminal of the NMOS transistor receives the corresponding inverting flag signal; the j-th MOS transistor is a PMOS transistor, and the control terminal of the PMOS transistor receives the corresponding sampling flag signal.

[0010] In some embodiments, the register circuit is a D flip-flop; The first input terminal of the D flip-flop is used to receive the initial flag signal; The inputs of the second to Nth D flip-flops are connected to the first output of the previous D flip-flop; The clock input of each of the D flip-flops is used to receive a clock signal; The first output terminal of each of the D flip-flops is used to output the corresponding sampling flag signal; The second output terminal of each of the D flip-flops is used to output the corresponding inverted flag signal.

[0011] In some embodiments, the memory further includes a test control circuit, which is connected in series with N register circuits to form a loop, and the test control circuit is also connected to the detection line; The test control circuit is used to output the initial flag signal; The test control circuit is also used to receive the detection signal and determine the detection result based on the detection signal; The test control circuit is also used to receive the Nth sampling flag signal and determine whether the detection result is valid based on the Nth sampling flag signal.

[0012] In some embodiments, the test control circuit includes: Clock generator circuit, used to generate and output clock signals; A discrimination circuit is used to receive the detection signal and determine the detection result based on the detection signal; The logic circuit is used to output the initial flag signal; and also to receive the Nth sampling flag signal, and if the value of the Nth sampling flag signal is the expected value, determine that the detection result is valid.

[0013] In some embodiments, the discrimination circuit is configured to receive the clock signal and the detection signal, sample the detection signal based on the clock signal, and generate a first sampling signal; if the first sampling signal alternates between the first level state and the second level state according to the clock cycle of the clock signal, it is determined that there is no defect; if the first sampling signal is at the same level state for two consecutive clock cycles, it is determined that there is a defect.

[0014] In some embodiments, the test control circuit further includes a counting circuit; A counting circuit is used to receive the clock signal and count based on the clock signal to generate a count value; The discrimination circuit is also used to send an enabled defect signal to the logic circuit when a defect is determined to exist. The logic circuit is configured to receive the defect signal and the count value, and when the defect signal is in an enabled state, determine the test bonding point with a defect based on the count value at the corresponding time.

[0015] In some embodiments, the memory includes a first chip and a second chip, and the test bonding point is the bonding connection point between the first chip and the second chip.

[0016] In a second aspect, embodiments of this disclosure provide an electronic device, the electronic device including the memory described in any one of the first aspects.

[0017] This disclosure provides a memory and an electronic device. The memory includes: N test circuits, where N is a positive integer, and each test circuit corresponds to one test bonding point of the memory; all N test bonding points are connected to a detection line, and the signal on the detection line is a detection signal; the i-th test circuit is used to control the level state of the i-th test bonding point to a first level state, so that the detection signal is in the first level state; i is an odd number greater than 0 and less than or equal to N; the j-th test circuit is used to control the level state of the j-th test bonding point to a second level state, so that the detection signal is in the second level state; j is an even number greater than 0 and less than or equal to N; wherein the first level state and the second level state are inverses of each other, and from the 1st to the Nth, the N test circuits sequentially control the level state of the corresponding test bonding points.

[0018] In this memory, each test bonding point corresponds to a test circuit. The test circuit can control the voltage level of the corresponding test bonding point. During control, odd-numbered test bonding points are controlled to a first voltage level, and even-numbered test bonding points are controlled to a second voltage level. Since the test bonding points are connected to the detection lines, the voltage level of the detection signal on the detection lines is also controlled. Based on this design, when testing the test bonding points, N test circuits sequentially control the voltage level of N test bonding points. This ensures that, assuming all test bonding points are free of defects and can transmit data normally, the detection signal alternates between the first and second voltage levels. This allows for rapid determination of whether a test bonding point is defective based on the state of the detection signal, and quick location of the defect based on the appearance of abnormal signals. The testing method is simple, time-efficient, and saves on subsequent testing steps. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. Figure 1 ; Figure 2 This is a schematic diagram of a bonding point distribution provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. Figure 2 ; Figure 4 This is a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. Figure 3 ; Figure 5 This is a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. Figure 4 ; Figure 6 This is a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. Figure 5 ; Figure 7 This is a schematic diagram of a test loop provided in an embodiment of this disclosure; Figure 8 This is a signal timing diagram provided in an embodiment of the present disclosure; Figure 9 This is a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. Figure 6 . Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this disclosure clearer, the disclosure will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0021] It is understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. It should also be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit the disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict. It should be noted that the terms "first, second, third, fourth" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third, fourth" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0022] In actual manufacturing processes, multi-wafer bonding processes are susceptible to failures due to various random or systematic factors. Typical examples include: misalignment between wafers caused by bonding misalignment, excessive bonding stress leading to interconnect structure breakage or cracking, and localized bonding defects caused by particulate contaminants such as dust. Although these failures can be screened out through conventional functional and performance testing, this method is essentially a retrospective screening, resulting in a significant waste of invested manufacturing resources (including bonding, packaging, and pre-testing costs), thus significantly reducing overall production yield and cost efficiency.

[0023] Based on this, this disclosure proposes a memory, including: N test circuits, where N is a positive integer, and each test circuit corresponds to one test bonding point of the memory; all N test bonding points are connected to a detection line, and the signal on the detection line is a detection signal; the i-th test circuit is used to control the level state of the i-th test bonding point to a first level state, so that the detection signal is in the first level state; i is an odd number greater than 0 and less than or equal to N; the j-th test circuit is used to control the level state of the j-th test bonding point to a second level state, so that the detection signal is in the second level state; j is an even number greater than 0 and less than or equal to N; wherein the first level state and the second level state are inverses of each other, and from the 1st to the Nth, the N test circuits sequentially control the level state of the corresponding test bonding points.

[0024] In this memory, each test bonding point corresponds to a test circuit. The test circuit can control the voltage level of the corresponding test bonding point. During control, odd-numbered test bonding points are controlled to a first voltage level, and even-numbered test bonding points are controlled to a second voltage level. Since the test bonding points are connected to the detection lines, the voltage level of the detection signal on the detection lines is also controlled. Based on this design, when testing the test bonding points, N test circuits sequentially control the voltage level of N test bonding points. This ensures that, assuming all test bonding points are free of defects and can transmit data normally, the detection signal alternates between the first and second voltage levels. This allows for rapid determination of whether a test bonding point is defective based on the state of the detection signal, and quick location of the defect based on the appearance of abnormal signals. The testing method is simple, time-efficient, and saves on subsequent testing steps.

[0025] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0026] In one embodiment of this disclosure, see [link to embodiment]. Figure 1 It illustrates a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. Figure 1 .like Figure 1 As shown, the memory 10 includes: N test circuits 100 ( Figure 1 Only one label 100 is shown in the figure, where N is a positive integer. Each test circuit 100 corresponds to one test bonding point 101 of the memory 10. All N test bonding points 101 are connected to the detection line 102, and the signal on the detection line 102 is the detection signal test. The i-th test circuit 100 is used to control the level state of the i-th test bonding point 101 to the first level state, so that the detection signal test is in the first level state; i is an odd number greater than 0 and less than or equal to N; The j-th test circuit 100 is used to control the level state of the j-th test bonding point 101 to the second level state, so that the detection signal test is in the second level state; j is an even number greater than 0 and less than or equal to N; Among them, the first level state and the second level state are opposite to each other. From the 1st to the Nth, the N test circuits 100 sequentially control the level state of the corresponding test bonding point 101.

[0027] It should be noted that the memory 10 in this embodiment can be a memory composed of multi-wafer bonding (which can be called a bonding chip). Different chips can be connected by bonding or other means. By adding test bonding points 101 near the bonding area corresponding to the key signal, bonding defects of the bonding chip can be detected.

[0028] For example, such as Figure 2 As shown, the left dashed box shows the bonding points 103 of the critical signals. The critical signals include, but are not limited to, command / address (CA), data (DQ), and clock (CLK). There are usually multiple critical signals and their bonding points 103. The right dashed box shows the corresponding test bonding points 101. These test bonding points 101 are arranged at critical locations near the critical signals to detect whether there are bonding defects in their surrounding areas.

[0029] In semiconductor manufacturing, the bonding point 101 for testing and the bonding point 103 for other key signals can be a bonding pad, a hybrid bonding (HB), a through-silicon via (TSV), a metal via, etc., without any specific limitations.

[0030] It should be noted that, in order to achieve accurate detection of bonding defects, this embodiment introduces a test circuit 100, such as... Figure 1 As shown, all N test bonding points 101 are connected to the same detection line 102, and the detection signal test on the detection line 102 is determined by the level state of the N test bonding points 101.

[0031] Specifically, from the first test circuit 100 to the Nth test circuit 100, the odd-numbered test circuit 100 (i.e., the i-th test circuit 100) controls the level state of the corresponding i-th test bonding point 101 to a first level state, enabling the detection signal test to be in the first level state when there is no defect in the i-th test bonding point 101; the even-numbered test circuit 100 (i.e., the j-th test circuit 100) controls the level state of the corresponding j-th test bonding point 101 to a second level state, enabling the detection signal test to be in the second level state when there is no defect in the j-th test bonding point 101; wherein, the first level state and the second level state are inverses of each other. Here, the first level state can be a high level state (logic 1), and the second level state can be a low level state (logic 0); or, the first level state can be a low level state (logic 0), and the second level state can be a high level state (logic 1). This embodiment of the present disclosure does not specifically limit this.

[0032] When performing bonding defect detection, the level states of N test bonding points 101 are controlled sequentially by N test circuits 100. That is, in the same time period, the level state of the detection signal test on the detection line 102 is determined by the level state of only one test bonding point 101. Assuming the test process is divided into N sequential, non-overlapping time periods, in the first time period, the first test circuit 100 controls the voltage level of the first test bonding point 101 to a first voltage level, so that the voltage level of the detection signal test is also at the first voltage level. In the second time period, the second test circuit 100 controls the voltage level of the second test bonding point 101 to a second voltage level, so that the voltage level of the detection signal test is also at the second voltage level. In the third time period, the third test circuit 100 controls the voltage level of the third test bonding point 101 to a first voltage level, so that the voltage level of the detection signal test is also at the first voltage level. In the fourth time period, the fourth test circuit 100 controls the voltage level of the fourth test bonding point 101 to a second voltage level, and so on.

[0033] In this way, assuming no faults or defects exist in any test bonding point 101 or test circuit 100, the level state of the detection signal `test` alternates between a first level state and a second level state. For example, when the first level state is 1 and the second level state is 0, the detection signal `test` displays 101010...; conversely, when the first level state is 0 and the second level state is 1, the detection signal `test` displays 010101... Therefore, the detection signal `test` can be used to determine if there is a defect in any test bonding point 101. When the level state of the detection signal `test` exhibits a regular alternation, meaning no two adjacent test bonding points 101 have the same level state, it indicates that all test bonding points 101 are intact and undamaged. Conversely, if any pair of adjacent test bonding points 101 have the same level state in the detection signal `test`, it is considered to have a defect. Based on this method, problematic test bonding points 101 can be quickly identified, saving subsequent testing steps.

[0034] In some embodiments, see Figure 3 It illustrates a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. Figure 2 .like Figure 3 As shown, each test circuit 100 includes a register circuit 110 and a level control circuit 120; The first register circuit 110 ( Figure 1 Only one label 110 is shown, which is used to receive the initial flag signal token0 and perform sampling processing, and output the first sampling flag signal token1 and the first inverted flag signal n_token1. The sampling flag signal token and the inverted flag signal n_token are inverted. The second to Nth register circuits 110 are used to receive the sampling flag signal token output by the previous register circuit 110 and perform sampling processing, and output the corresponding sampling flag signal token and the inverted flag signal n_token. The i-th level control circuit 120 is used to control the level state of the i-th test bonding point 101 to the first level state based on one of the i-th sampling flag signal tokeni and the i-th inverted flag signal n_tokeni. The j-th level control circuit 120 is used to control the level state of the j-th test bonding point 101 to the second level state based on the other of the j-th sampling flag signal tokenj and the j-th inverted flag signal n_tokenj.

[0035] It should be noted that the initial flag signal is represented by token0, and the sampling flag signal is represented by token. Both the initial flag signal token0 and the sampling flag signal token can be referred to as flag signals. When it is necessary to distinguish between different sampling flag signals token, token1, token2, token3, etc. are used to represent each sampling flag signal in sequence.

[0036] like Figure 3 As shown in this embodiment, the first level state is controlled by the i-th level control circuit 120 based on the i-th inverted flag signal n_token, and the second level state is controlled by the j-th level control circuit 120 based on the j-th sampling flag signal tokenj. In other examples, the first level state can be controlled by the i-th level control circuit 120 based on the i-th sampling flag signal token, and the second level state can be controlled by the j-th level control circuit 120 based on the j-th inverted flag signal n_tokenj. Alternatively, each level control circuit 120 may receive a corresponding sampling flag signal token or a corresponding inverted flag signal n_token, by setting an inverter inside or before the odd-numbered or even-numbered level control circuit 120; this is not specifically limited.

[0037] In each test circuit 100, a register circuit 110 receives and samples the previous flag signal, and outputs a corresponding sampled flag signal token and an inverted flag signal n_token. In some embodiments, the sampled flag signal token has the same level as the flag signal received by the register circuit 110, and the inverted flag signal n_token has the opposite level to the received flag signal; or, in other embodiments, the sampled flag signal token has the opposite level to the flag signal received by the register circuit 110, and the inverted flag signal n_token has the same level as the received flag signal. This disclosure does not specifically limit the scope of the embodiments.

[0038] In this way, the transmission of the flag signal is realized through the cascaded register circuit 110, thereby ensuring that only one level control circuit 120 is controlled by the signal output by the register circuit 110 during each time period of the test process, and controls the level state of the detection signal test to the corresponding state, avoiding signal chaos caused by multiple test bonding points 101 controlling the level state of the detection signal test together during the same time period.

[0039] In some embodiments, for register circuit 110, such as Figure 4or Figure 5 As shown, register circuit 110 can be a D flip-flop; The first D flip-flop input (D) is used to receive the initial flag signal token0; The input terminals (D) of the second to Nth D flip-flops are connected to the first output terminal (Q) of the previous D flip-flop. The clock input (CK) of each D flip-flop is used to receive the clock signal clk; The first output (Q) of each D flip-flop is used to output the corresponding sampling flag signal token; The second output terminal ( / Q) of each D flip-flop is used to output the corresponding inverted flag signal n_token.

[0040] It should be noted that a D flip-flop (D-FF) is a sequential logic unit. When the effective edge (rising or falling edge) of the clock signal clk arrives, it transmits a flag signal to the first output terminal (Q), or inverts the flag signal and transmits it to the second output terminal ( / Q), maintaining the output state unchanged at other times. Therefore, the initial flag signal token0 and each sampled flag signal token are at the same level, while each inverted flag signal n_token is at a different level than the initial flag signal token0; furthermore, the initial flag signal token0 and each sampled flag signal token are at the first level, while each inverted flag signal n_token is at the second level.

[0041] It should be noted that in this embodiment, the first output terminal of each D flip-flop is the positive output terminal (Q) and the second output terminal of each D flip-flop is the negative output terminal ( / Q). In other embodiments, the terminals can be reversed or other terminals, and the solution can still be achieved. This embodiment does not limit this.

[0042] It should also be noted that the clock input of each D flip-flop can be connected to the same clock generation circuit, which is used to provide the clock signal clk for each D flip-flop.

[0043] In this embodiment of the disclosure, please continue to refer to Figure 4 or Figure 5 The level control circuit 120 can be a MOSFET; The control terminal of the MOSFET receives either the corresponding sampling flag signal token or the corresponding inverted flag signal n_token. The first terminal of the i-th MOSFET is connected to a first input signal that provides the first level state; The first terminal of the j-th MOSFET is connected to a second input signal that provides the second level state; The second end of the MOSFET is connected to the corresponding test bonding point 101.

[0044] It should be noted that MOSFETs include two types: PMOS and NMOS. The source of a PMOS transistor is connected to VDD (power supply), and the source of an NMOS transistor is connected to GND (ground). Under logic level control: inputting a high level "1" to the gate turns on the NMOS transistor, pulling its output down to ground (low level); inputting a low level "0" to the gate turns on the PMOS transistor, pulling its output up to the power supply (high level). In this embodiment, the control terminal of the MOSFET is the gate, the first terminal is the source, and the second terminal is the drain. In other embodiments, the first terminal of the MOSFET can also be the drain and the second terminal the source; this embodiment does not impose such a limitation.

[0045] It should also be noted that the first input signal refers to the control signal that can provide a first level state to the first terminal of the MOSFET, which can be provided by the first power supply circuit or other circuits; the second input signal refers to the control signal that can provide a second level state to the first terminal of the MOSFET, which can be provided by the second power supply circuit or other circuits.

[0046] In this embodiment of the disclosure, when the level control circuit 120 controls the level state of the test bonding point 101, it utilizes the switching characteristics of the MOSFET to actively pull the test bonding point 101 high to the power supply voltage (VDD) or low to ground (GND) by controlling its gate and source voltages.

[0047] In one example, when the input (D) of the D flip-flop is in a high-level state, and the clock input (CK) of the D flip-flop receives the clock signal clk, the high-level state flag signal is transmitted to the first output (Q) when the rising edge of the clock signal clk arrives. The first output (Q) then transmits the received high-level state flag signal to the input (D) of the next D flip-flop. The inverted low-level state flag signal n_token is transmitted to the second output ( / Q). The second output ( / Q) of the D flip-flop is connected to the control terminal of the PMOS transistor. The control terminal (i.e., the gate) of the PMOS transistor receives the inverted low-level state flag signal n_token, causing the PMOS transistor to turn on. The level of the test bonding point 101 connected to the second terminal of the PMOS transistor is pulled high.

[0048] In this embodiment, due to the strong pull-up / pull-down capability of the MOSFET, the MOSFET can be turned on based on the sampling flag signal token or the inverted flag signal n_token, transmitting the first input signal or the second input signal to the test bonding point 101 connected to the second terminal of the MOSFET, thereby quickly pulling the test bonding point 101 to a low-level state or a high-level state. This not only controls the level state of the test bonding point 101 but also overcomes the adverse factors such as parasitic capacitance and leakage current inherent in the test bonding point 101 itself, ensuring the stability of the level of the test bonding point 101.

[0049] Furthermore, since the control terminal of the MOSFET is directly connected to the output terminal of the D flip-flop, it receives the corresponding sampling flag signal token or the corresponding inverted flag signal n_token. This ensures that the gate control voltage of the MOSFET is stable and glitch-free, thereby keeping the level state of the test bonding point 101 constant during the test and improving the accuracy of bonding defect measurement.

[0050] In this embodiment, the type of MOS transistor and the high / low levels of the first and second voltage levels can be flexibly set, as illustrated below.

[0051] In some embodiments, the initial flag signal token0 and each sampling flag signal token are both in a first level state, and each inverted flag signal n_token is in a second level state; the first level state is a high level state, and the second level state is a low level state; based on this setting, there can be, but is not limited to, the following two implementation methods: like Figure 4 As shown in (a), the i-th MOS transistor is a PMOS transistor, and the control terminal of the PMOS transistor receives the corresponding inverted flag signal n_token; the j-th MOS transistor is an NMOS transistor, and the control terminal of the NMOS transistor receives the corresponding sampling flag signal token. Or, such as Figure 4 As shown in (b), the i-th MOS transistor is an NMOS transistor, and the control terminal of the NMOS transistor receives the corresponding sampling flag signal token; the j-th MOS transistor is a PMOS transistor, and the control terminal of the PMOS transistor receives the corresponding inverting flag signal n_token.

[0052] It should be noted that a PMOS transistor only conducts when the signal received at the control terminal is low, exhibiting a strong pull-up capability, while an NMOS transistor only conducts when the signal received at the control terminal is high, exhibiting a strong pull-down capability. Therefore, when the MOSFET is a PMOS transistor, its control terminal receives a low-level inverted flag signal n_token; when the MOSFET is an NMOS transistor, its control terminal receives a high-level sampling flag signal token.

[0053] It should also be noted that, since the presence of bonding defects needs to be determined based on whether the voltage levels of adjacent test bonding points 101 alternate, the control terminals of adjacent MOSFETs need to receive inverted signals. That is, when the i-th MOSFET is a PMOS transistor, the j-th MOSFET needs to be an NMOS transistor, and vice versa.

[0054] It should also be noted that since the D flip-flops receive the flag signal based on the clock signal clk, the flag signal is passed sequentially through the N D flip-flops according to the cycle of the clock signal clk. In each cycle, the MOS transistor is controlled to pull up or down the corresponding test bonding point 101. That is, in the first clock cycle, the level of the detection signal test is determined by the first test bonding point 101; in the second clock cycle, the level of the detection signal test is determined by the second test bonding point 101, and so on, until the Nth clock cycle, where the level of the detection signal test is determined by the Nth test bonding point 101.

[0055] Combination Figure 4 As shown in (a), the first level state is a high level state, and the second level state is a low level state. When the i-th MOS transistor is a PMOS transistor and the j-th MOS transistor is an NMOS transistor, the control terminal of the PMOS transistor receives the corresponding inverted flag signal n_token, and the control terminal of the NMOS transistor receives the corresponding sampling flag signal token. During the sequential level control process, the level states of the N test bonding points 101 connected to the N MOS transistors are 1, 0, 1, 0... in sequence, which is also the level states of the detection signal test are 1, 0, 1, 0... in sequence.

[0056] Combination Figure 4 As shown in (b), the first level state is a high level state, and the second level state is a low level state. When the i-th MOS transistor is an NMOS transistor and the j-th MOS transistor is a PMOS transistor, the control terminal of the NMOS transistor receives the corresponding sampling flag signal token, and the control terminal of the PMOS transistor receives the corresponding inverted flag signal n_token. During the sequential level control process, the level states of the N test bonding points 101 connected to the N MOS transistors are 0, 1, 0, 1... in sequence, which is also the level states of the detection signal test are 0, 1, 0, 1... in sequence.

[0057] In some embodiments, the initial flag signal token0 and each sampling flag signal token are both in a first level state, and each inverted flag signal n_token is in a second level state; the first level state is a low level state, and the second level state is a high level state; based on this setting, there can be, but is not limited to, the following two implementation methods: like Figure 5 As shown in (a), the i-th MOS transistor is a PMOS transistor, and the control terminal of the PMOS transistor receives the corresponding sampling flag signal token; the j-th MOS transistor is an NMOS transistor, and the control terminal of the NMOS transistor receives the corresponding inverting flag signal n_token; Or, such as Figure 5 As shown in (b), the i-th MOS transistor is an NMOS transistor, and the control terminal of the NMOS transistor receives the corresponding inverted flag signal n_token; the j-th MOS transistor is a PMOS transistor, and the control terminal of the PMOS transistor receives the corresponding sampling flag signal token.

[0058] Combination Figure 5 As shown in (a), the first level state is a low level state, the second level state is a high level state, the i-th MOS transistor is a PMOS transistor, and the j-th MOS transistor is an NMOS transistor. The control terminal of the PMOS transistor receives the corresponding sampling flag signal token, and the control terminal of the NMOS transistor receives the corresponding inverting flag signal n_token. During the sequential level control process, the level states of the N test bonding points 101 connected to the N MOS transistors are 1, 0, 1, 0... in sequence, which is also the level states of the detection signal test are 1, 0, 1, 0... in sequence.

[0059] Combination Figure 5 As shown in (b), the first level state is a low level state, the second level state is a high level state, the i-th MOS transistor is an NMOS transistor, and the j-th MOS transistor is a PMOS transistor. The control terminal of the NMOS transistor receives the corresponding inverted flag signal n_token, and the control terminal of the PMOS transistor receives the corresponding sampling flag signal token. During the sequential level control process, the level states of the N test bonding points 101 connected to the N MOS transistors are 0, 1, 0, 1... in sequence, that is, the level states of the detection signal test are 1, 0, 1, 0... in sequence.

[0060] In some embodiments, see Figure 6 It illustrates a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. Figure 5 , Figure 6 Only in Figure 4 The test control circuit 200 is explained using example (a) as a case study; the other examples are similar and will not be repeated here. Figure 6 As shown, the memory 10 also includes a test control circuit 200, which is connected in series with N register circuits 110 to form a loop, and the test control circuit 200 is also connected to the detection line 102. Test control circuit 200 is used to output initial flag signal token0; The test control circuit 200 is also used to receive the detection signal test and determine the detection result based on the detection signal test. The test control circuit 200 is also used to receive the Nth sampling flag signal tokenN and determine whether the detection result is valid based on the Nth sampling flag signal tokenN.

[0061] like Figure 7 As shown, the test control circuit 200 is connected in series with N test points to form a loop. Each test point includes one test circuit 100 and a corresponding test bonding point 101. The test control circuit 200 is connected in series with the register circuits 110 of the N test circuits 100 to form a loop, thereby generating a forward-propagating flag signal on the test chain (the first register circuit 110 receives the initial flag signal token0, and subsequent register circuits 110 are used to receive the sampled flag signal token output by the previous register circuit 110). In this way, the flag signal is transmitted in the loop in a specific manner, which can determine the current position of the flag signal and detect the connectivity of the loop containing the flag signal.

[0062] It should be noted that during testing, the memory 10 can be connected to an external device, which can be a test bench, such as an Automatic Test Equipment (ATE), or other controllers or control circuits, such as a System on Chip (SOC). The external device can send a test start signal to the memory 10. In response to the test start signal, the test control circuit 200 outputs an initial flag signal token0 to start the bonding test. After the test is completed, the test control circuit 200 can send the test results to the external device for evaluation.

[0063] It should also be noted that, in conjunction with the foregoing description, the test control circuit 200 can determine whether each test bonding point 101 has a defect based on whether the detection signal test presents "101010..." or "010101..." in a periodic manner. If the detection signal test presents the above-mentioned regular state, it is confirmed that the test result is that none of the test bonding points 101 have defects, and the test control circuit 200 can output a test indication signal indicating that the test has passed. If the detection signal test does not present the above-mentioned regular state, for example, "00001010", it indicates that a bonding defect exists, and the test control circuit 200 can output a test indication signal indicating that a bonding defect exists.

[0064] Specifically, since the test circuit 100 operates sequentially, the state of the detection signal 'test' can determine which test bonding point 101 has a problem. For example, under normal circumstances, the detection signal 'test' should show "010101", but if the detection signal 'test' is "010001", it can be seen that the signal in the 4th cycle should have been 1, but it is incorrectly 0, indicating that the 4th test bonding point 101 has a problem.

[0065] It should also be noted that since the flag signal is transmitted sequentially through the N D flip-flops, if all D flip-flops are working properly, the state of the Nth sampling flag signal tokenN is determined. For example, if the initial flag signal token0 is high, and each D flip-flop outputs the sampling flag signal token through its non-inverting output (Q), then the Nth sampling flag signal tokenN should also be high. If the Nth sampling flag signal tokenN is not high, it indicates a problem in the transmission of the flag signal, and the detection result is unreliable. The test control circuit 200 determines the reliability of the detection result based on whether the level of the Nth sampling flag signal tokenN meets the expected state, thus avoiding errors in the detection result caused by problems in the transmission of the flag signal, effectively increasing the reliability of the detection without increasing the complexity of the circuit.

[0066] In some embodiments, please continue to see Figure 6 The test control circuit 200 may include: Clock generator circuit 201 is used to generate and output clock signal clk; The discrimination circuit 203 is used to receive the detection signal test and determine the detection result based on the detection signal test. The logic circuit 204 is used to output the initial flag signal token0; it is also used to receive the Nth sampling flag signal tokenN. If the value of the Nth sampling flag signal tokenN is the expected value (e.g., the same as the initial flag signal token0), the detection result is determined to be valid.

[0067] It should be noted that the health status of the N test bonding points 101 is directly related to the alternation of the level state of the test signal "test" on the test line. As mentioned above, when the level state of the test signal "test" is out of phase, that is, when it alternates between "01" and "10", the test result is: the bonding is normal and there is no defect; when the level state of the test signal "test" is the same for two consecutive periods, that is, when it alternates between "00" and "11", the test result is: the bonding is abnormal and there is a defect.

[0068] Specifically, the discrimination circuit 203 is used to receive the clock signal clk and the detection signal test, sample the detection signal test based on the clock signal clk, and generate a first sampling signal; if the first sampling signal is in a first level state and the second level state alternates according to the clock cycle of the clock signal clk, it is determined that there is no defect; if the first sampling signal is in the same level state for two consecutive clock cycles, it is determined that there is a defect.

[0069] In other words, the first sampling signal is generated based on the clock signal clk and the sample detection signal test. The first sampling signal is an N-bit wide digital control code, such as 01010101… or 10101010…. When the first sampling signal alternates between high and low levels according to the clock cycle of the clock signal clk, i.e., it shows alternating “01” or “10”, the detection result is: the bonding is normal and there is no defect; when the first sampling signal has the same level state for two consecutive clock cycles, i.e., it shows “00” or “11”, the detection result is: the bonding is abnormal and there is a defect.

[0070] It should also be noted that logic circuit 204 is used to output the initial flag signal token0 and to determine whether the detection result is valid. In some examples, logic circuit 204 can output the initial flag signal token0 in response to a test start signal from an external device to initiate the bonding test, and after the test is completed, determine whether the test is valid based on the value of the Nth sampling flag signal tokenN. As mentioned earlier, when all N register circuits 110 are operating normally, the value of the Nth sampling flag signal tokenN is a predictable expected value; if its value is the expected value, it indicates that the detection result is valid.

[0071] exist Figures 4-6 In the example, the flag signal is passed through N register circuits 110 step by step without changing the level signal. Therefore, when the value of the Nth sampled flag signal tokenN is the same as the initial flag signal token0, the detection result can be determined to be valid.

[0072] In some embodiments, such as Figure 6 As shown, the test control circuit 200 may further include: a counting circuit 202; The counting circuit 202 is used to receive the clock signal clk and count based on the clock signal clk to generate a count value counter. The discrimination circuit 203 is also used to send an enabled defect signal to the logic circuit 204 when a defect is determined to exist; The logic circuit 204 is used to receive a defect signal and a counter value. When a defect signal in an enabled state is received, the test bonding point with a defect is determined based on the counter value at the corresponding time.

[0073] It should be noted that the counting circuit 202 can be a counter, such as a synchronous or asynchronous counter, which counts based on the toggling edge or level state of the clock signal clk, such as counting the rising edge, falling edge, high level state, or low level state. The count value counter is incremented by 1 every clock cycle.

[0074] It should also be noted that when the discrimination circuit 203 determines that the detection result is that there is a bonding defect, it sends a defect signal to the logic circuit 204. At the same time, the counting circuit 202 counts based on the clock signal clk, generates a count value counter, and outputs it to the logic circuit 204. The logic circuit 204 can determine the test bonding point 101 with the defect based on the defect signal in the enabled state and the count value counter at the corresponding time.

[0075] For example, suppose there are 6 test bonding points 101, and the normal trend of the corresponding detection signal test is "101010". If the 4th test bonding point 101 is defective, the corresponding count value counter will be 4. Based on this, the logic circuit 204 can determine that the 4th test bonding point 101 has failed.

[0076] It should be noted that the above counting method is only an example, and it can also start counting from 0 or other values. There is no specific limitation here.

[0077] This allows for rapid determination of the presence of defects at the test bonding point and immediate location of the defect. When using this memory to detect bonding defects in bonded chips, the testing method is simple and time-efficient.

[0078] Please see Figure 8 This illustration shows a signal timing diagram of a memory-based bonding defect detection process according to an embodiment of the present disclosure. The detection signal `test` is used to determine the detection result of the bonding defect. In this example, the initial flag signal `token0`, the sampling flag signal `token1`, and the sampling flag signal `token2` are all "1". Based on the first rising edge of the clock signal `clk`, a count value `counter` is generated with a value of 0, and the initial flag signal `token0` is set to 1; based on the second rising edge of the clock signal `clk`, a count value `counter` is generated with a value of 1, the sampling flag signal `token1` is set to 1, and the detection signal `test` is set to 1; based on the third rising edge of the clock signal `clk`, a count value `counter` is generated with a value of 2, the sampling flag signal `token2` is set to 1, and the detection signal `test` is set to 0, and so on. The detection result can be determined based on the detection signal `test`.

[0079] In some embodiments, such as Figure 9As shown, the memory 10 includes a first chip 130 and a second chip 140, and the test bonding point 101 is the bonding connection point of the first chip 130 and the second chip 140.

[0080] It illustrates a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. Figure 6 .like Figure 9 As shown, there are multiple test bonding points 101 at the bonding interface between the first chip 130 and the second chip 140, and the multiple test bonding points 101 are connected to the detection line 102.

[0081] Based on the aforementioned memory 10, in Figure 6 Based on this, an exemplary process for detecting bonding defects in memory 10 is as follows: After the test starts, the clock generation circuit 201 outputs a clock signal clk, which is sent to the clock terminals of the counting circuit 202, the discrimination circuit 203, and the D flip-flops. The counting circuit 202 counts based on the rising edge of the clock signal clk, generating a count value counter. The logic circuit 204 outputs an initial high-level flag signal token0 based on the first rising edge of the clock signal clk. The initial high-level flag signal token0 is input to the first D flip-flop. The non-inverting output (Q) of the first D flip-flop outputs the corresponding high-level sampling flag signal token1. The phase output terminal ( / Q) outputs the corresponding low-level inverted flag signal n_token1; the first level control circuit 120 is a PMOS transistor. The control terminal of the PMOS transistor receives the low-level inverted flag signal n_token1 output from the inverted output terminal ( / Q) of the first D flip-flop. The low-level inverted flag signal n_token1 turns on the PMOS transistor, and the output is pulled to a high level. At this time, the level of the first test bonding point 101 connected to the second terminal of the PMOS transistor is high, and the detection signal test on the detection line connected to the first test bonding point 101 is high. When the next rising edge of the clock signal clk arrives, the non-inverting output (Q) of the first D flip-flop outputs a high-level sampling flag signal token1 to the input (D) of the second D flip-flop. The non-inverting output (Q) of the second D flip-flop outputs a high-level sampling flag signal token2, and the inverting output ( / Q) of the second D flip-flop outputs a low-level inverted flag signal n_token2. The second level control circuit 120 is an NMOS transistor. The control terminal of the NMOS transistor receives the high-level sampling flag signal token2 output by the non-inverting output (Q) of the second D flip-flop. The high-level sampling flag signal token2 turns on the NMOS transistor, pulling the output to a low level. The detection signal test on the detection line connected to the second test bonding point 101 is low. According to the above method, the level state of the detection signal test on the detection line connected to the subsequent N-2 test bonding points 101 can be obtained. The discrimination circuit 203 generates a first sampling signal based on N detection signals 'test' obtained from sampling the clock signal 'clk'. If the first sampling signal is 10101010…, with high and low levels alternating according to the clock cycle of the clock signal 'clk', the detection result is: the bonding is normal, and there is no defect; otherwise, the detection result is: the bonding is abnormal, and there is a defect. At this time, the logic circuit 204 receives the sampling flag signal 'tokenN' output from the non-inverting output terminal (Q) of the Nth D flip-flop. If the level state of the sampling flag signal 'tokenN' is the same as the initial flag signal 'token0', the detection result is valid.Based on the valid detection results, the discrimination circuit 203 sends an enabled defect signal to the logic circuit 204. The logic circuit 204 determines the test bonding point 101 with a defect based on the corresponding count value counter when it receives the enabled defect signal, according to the received defect signal and the count value counter.

[0082] In summary, this embodiment of the present disclosure provides a memory 10, in which a register circuit 110 is placed in each test circuit 100 to store a flag signal. By connecting the test control circuit 200 and the register circuits 110 included in N test circuits 100 in series to form a loop, a flag signal that is passed backward is generated on the test chain (the first register circuit 110 receives the initial flag signal token0, and subsequent register circuits 110 are used to receive the sampled flag signal token output by the previous register circuit 110). The flag signal is transmitted in the loop in a specific manner, so the test circuit 100 can determine the current location of the flag signal and can detect the connectivity of the test circuit 100 where the flag signal is located. At the same time, each test circuit 100 corresponds to a test bonding point 101. The test circuit 100 controls the level state of the corresponding test bonding point 101. The test control circuit 200 can quickly determine whether there is a defect in the test bonding point 101 by the level state of the test bonding point 101 and locate the defect location in real time. Thus, when detecting bonding defects in the bonding chip through the memory 10, the testing method is simple and time-saving.

[0083] For details not described in this embodiment, please refer to the description of the above embodiments for understanding, and they will not be repeated here.

[0084] Based on the aforementioned memory 10, this application provides an electronic device that includes the memory 10 from any of the foregoing embodiments.

[0085] It should be noted that the electronic device can be user equipment (UE), mobile device, handheld device, computing device, vehicle-mounted device, wearable device, etc.

[0086] Examples include: personal computers (PCs), mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), enterprise digital assistants (EDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, server computers, data centers, workstations, mobile phones, smartphones, and tablets.

[0087] For details not disclosed in the embodiments of this disclosure, please refer to the description of the foregoing embodiments for understanding.

[0088] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0089] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0090] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0091] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0092] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0093] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0094] The above description is merely an embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this disclosure are included within the scope of protection of this disclosure.

Claims

1. A memory, characterized in that, include: There are N test circuits, where N is a positive integer, and each test circuit corresponds to one test bonding point of the memory. All N test bonding points are connected to a detection line, and the signal on the detection line is a detection signal. The i-th test circuit is used to control the level state of the i-th test bonding point to a first level state, so that the detection signal is in the first level state; i is an odd number that is greater than 0 and less than or equal to N; The j-th test circuit is used to control the level state of the j-th test bonding point to a second level state, so that the detection signal is in the second level state; j is an even number greater than 0 and less than or equal to N; Wherein, the first level state and the second level state are opposite to each other, and from the 1st to the Nth, the N test circuits sequentially control the level state of the corresponding test bonding point.

2. The memory according to claim 1, characterized in that, Each of the aforementioned test circuits includes a register circuit and a level control circuit; The first register circuit is used to receive the initial flag signal and perform sampling processing, and output the first sampling flag signal and the first inverted flag signal, wherein the sampling flag signal and the inverted flag signal are inverted relative to each other; the second to the Nth register circuits are used to receive the sampling flag signal output by the previous register circuit and perform sampling processing, and output the corresponding sampling flag signal and the inverted flag signal. The i-th level control circuit is used to control the level state of the i-th test bonding point to the first level state based on one of the i-th sampling flag signal and the i-th inverted flag signal; The j-th level control circuit is used to control the level state of the j-th test bonding point to the second level state based on the other of the j-th sampling flag signal and the j-th inverted flag signal.

3. The memory according to claim 2, characterized in that, The level control circuit is a MOSFET; The control terminal of the MOS transistor receives the corresponding sampling flag signal or the corresponding inverting flag signal; The first terminal of the i-th MOS transistor is connected to a first input signal that provides the first level state; The first terminal of the j-th MOS transistor is connected to a second input signal that provides the second level state; The second end of the MOS transistor is connected to the corresponding test bonding point.

4. The memory according to claim 3, characterized in that, The initial flag signal and each of the sampling flag signals are both in the first level state, and each of the inverted flag signals is in the second level state; the first level state is a high level state, and the second level state is a low level state; The i-th MOS transistor is a PMOS transistor, and the control terminal of the PMOS transistor receives the corresponding inverting flag signal; the j-th MOS transistor is an NMOS transistor, and the control terminal of the NMOS transistor receives the corresponding sampling flag signal. Alternatively, the i-th MOS transistor is an NMOS transistor, and the control terminal of the NMOS transistor receives the corresponding sampling flag signal; the j-th MOS transistor is a PMOS transistor, and the control terminal of the PMOS transistor receives the corresponding inversion flag signal.

5. The memory according to claim 3, characterized in that, The initial flag signal and each of the sampling flag signals are both in the first level state, and each of the inverted flag signals is in the second level state; the first level state is a low level state, and the second level state is a high level state; The i-th MOS transistor is a PMOS transistor, and the control terminal of the PMOS transistor receives the corresponding sampling flag signal; the j-th MOS transistor is an NMOS transistor, and the control terminal of the NMOS transistor receives the corresponding inversion flag signal. Alternatively, the i-th MOS transistor is an NMOS transistor, and the control terminal of the NMOS transistor receives the corresponding inverting flag signal; the j-th MOS transistor is a PMOS transistor, and the control terminal of the PMOS transistor receives the corresponding sampling flag signal.

6. The memory according to claim 2, characterized in that, The register circuit is a D flip-flop; The first input terminal of the D flip-flop is used to receive the initial flag signal; The inputs of the second to Nth D flip-flops are connected to the first output of the previous D flip-flop; The clock input of each of the D flip-flops is used to receive a clock signal; The first output terminal of each of the D flip-flops is used to output the corresponding sampling flag signal; The second output terminal of each of the D flip-flops is used to output the corresponding inverted flag signal.

7. The memory according to any one of claims 2-6, characterized in that, The memory also includes a test control circuit, which is connected in series with N of the register circuits to form a loop, and the test control circuit is also connected to the detection line; The test control circuit is used to output the initial flag signal; The test control circuit is also used to receive the detection signal and determine the detection result based on the detection signal; The test control circuit is also used to receive the Nth sampling flag signal and determine whether the detection result is valid based on the Nth sampling flag signal.

8. The memory according to claim 7, characterized in that, The test control circuit includes: Clock generator circuit, used to generate and output clock signals; A discrimination circuit is used to receive the detection signal and determine the detection result based on the detection signal; The logic circuit is used to output the initial flag signal; and also to receive the Nth sampling flag signal, and if the value of the Nth sampling flag signal is the expected value, determine that the detection result is valid.

9. The memory according to claim 8, characterized in that, The discrimination circuit is used to receive the clock signal and the detection signal, sample the detection signal based on the clock signal, and generate a first sampling signal; if the first sampling signal is a first level state and a second level state alternating according to the clock period of the clock signal, it is determined that there is no defect; If the first sampled signal is at the same level for two consecutive clock cycles, a defect is determined to exist.

10. The memory according to claim 8, characterized in that, The test control circuit also includes: a counting circuit; The counting circuit is used to receive the clock signal and count based on the clock signal to generate a count value; The discrimination circuit is also used to send an enabled defect signal to the logic circuit when a defect is determined to exist. The logic circuit is configured to receive the defect signal and the count value, and when the defect signal is in an enabled state, determine the test bonding point with a defect based on the count value at the corresponding time.

11. The memory according to any one of claims 1-6 and 8-10, characterized in that, The memory includes a first chip and a second chip, and the test bonding point is the bonding connection point between the first chip and the second chip.

12. An electronic device, characterized in that, Includes the memory as described in any one of claims 1-11.

Images