Test method and apparatus therefor

Abstract

The application discloses a test method and a device thereof, and the device comprises a test device, a computer readable storage medium and a computer program product. The test method is applied to a memory, and the test method comprises the following steps: while writing test data into the memory, applying multiple stresses to the memory based on preset stress loading data; obtaining quantization results of each storage unit of the memory under the multiple stresses; training a data retention capability prediction model based on the preset stress loading data and the quantization results; and testing the same type of memory based on the data retention capability prediction model to obtain corresponding test results. In this way, the test method can simulate the aging process of the memory under actual complex working conditions, thereby greatly reducing the test time and improving the test efficiency of the memory.

Description

Technical Field

[0001] This application relates to the field of memory testing technology, specifically to a testing method and its equipment. Background Technology

[0002] As a core component of electronic systems, the data retention capability of memory is a key factor determining the long-term reliability of devices. Data retention capability typically refers to the time-dependent characteristic of a memory to retain stored data without loss under power failure or extreme environmental conditions, which is particularly crucial for non-volatile memory. However, due to various factors such as manufacturing process variations, material defects, and external environmental stress, the data retention performance of different memory cells can vary significantly. Therefore, how to efficiently and accurately test the data retention capability of memory has become a critical problem that urgently needs to be solved in the field of memory technology. Summary of the Invention

[0003] This application proposes a testing method and apparatus to address the aforementioned problems.

[0004] To address the aforementioned technical problems, this application provides a testing method applied to a memory. The method includes: simultaneously writing test data to the memory and applying multiple stresses to the memory based on preset stress loading data; obtaining the quantization results of each memory cell under the multiple stresses; training a data retention capability prediction model based on the preset stress loading data and the quantization results; and testing similar memory types based on the data retention capability prediction model to obtain corresponding test results.

[0005] The step of applying multiple stresses to the memory based on preset stress loading data includes: setting multiple stress loading cycles based on the memory's test mode; obtaining the fine-tuning values ​​corresponding to the multiple stresses in each loading cycle; and dynamically adjusting the multiple stresses during the test based on the fine-tuning values.

[0006] The step of obtaining the fine-tuning values ​​of multiple stresses corresponding to each loading cycle includes: obtaining the electrical parameters during the memory testing process; and inputting the electrical parameters into the trained adaptive loading model to obtain the fine-tuning values ​​of multiple stresses corresponding to each loading cycle.

[0007] The quantification results include validity quantification values ​​and failure times. The steps for obtaining the quantification results of each memory cell under multiple stresses include: reading the stored data of each memory cell after each loading cycle; calculating the validity quantification value corresponding to each memory cell based on the stored data, test data, and electrical parameters during the test; and marking the memory cell as invalid and recording the failure time corresponding to the memory cell if the validity quantification value of a certain memory cell is lower than a preset threshold.

[0008] The electrical parameters include threshold voltage drift and leakage current. The steps for calculating the validity quantization value of each storage cell based on the stored data, test data, and electrical parameters during the test process include: calculating the bit error rate based on the stored data and test data; obtaining the quantization weights corresponding to the bit error rate, threshold voltage drift, and leakage current; and calculating the validity quantization value based on the bit error rate, threshold voltage drift, leakage current, and their corresponding quantization weights.

[0009] The steps of training a data retention capability prediction model based on preset stress loading data and quantization results include: constructing a data retention capability prediction model based on the guiding relationship between preset stress loading data and quantization results, and constructing a training set based on preset stress loading data and quantization results; training the data retention capability prediction model based on the training set; and, in response to the completion of training, associating and storing the model parameters of the data retention capability prediction model with the type of memory.

[0010] The test method further includes, before the step of applying multiple stresses to the memory based on preset stress loading data while writing test data to the memory, obtaining the memory model; initializing the test environment based on the model and configuring the test parameters corresponding to the model.

[0011] The steps for initializing the test environment based on the model and configuring the test parameters corresponding to the model include: configuring the hardware interface and communication protocol of the memory corresponding to the model; configuring the read / write timing parameters and electrical parameters of the memory corresponding to the model; and configuring the test mode and test data of the memory corresponding to the model.

[0012] The stresses include temperature, jitter voltage, write frequency, and loading time.

[0013] To address the aforementioned technical problems, another technical solution adopted in this application is: providing a testing device, which includes a stress loading module, a quantization result acquisition module, a model training module, and a testing module. The stress loading module is used to apply multiple stresses to the memory based on preset stress loading data while writing test data to the memory; the quantization result acquisition module is used to acquire the quantization result of each memory cell under multiple stresses; the model training module is used to train a data retention capability prediction model based on the preset stress loading data and quantization results; and the testing module is used to test similar types of memory based on the data retention capability prediction model to obtain corresponding test results.

[0014] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a computer-readable storage medium that stores program instructions internally, which are executed by a processor to implement the test method of any one of the above.

[0015] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a computer program product, which includes a computer program and is executed by a processor to implement the test method of any one of the above.

[0016] The beneficial effects of this application are as follows: Unlike existing technologies, the testing method of this application includes: simultaneously writing test data to the memory and applying multiple stresses to the memory based on preset stress loading data; obtaining the quantization results of each memory cell under multiple stresses; training a data retention capability prediction model based on the preset stress loading data and quantization results; and testing similar types of memory based on the data retention capability prediction model to obtain corresponding test results. Through the above methods, the testing method of this application can simulate the aging process of memory under actual complex working conditions, thereby significantly reducing testing time and improving memory testing efficiency. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.

[0018] Figure 1 This is a flowchart illustrating the first embodiment of the testing method provided in this application; Figure 2 yes Figure 1 A flowchart illustrating a specific embodiment of step S101; Figure 3 yes Figure 2 A flowchart illustrating a specific embodiment of step S202; Figure 4 yes Figure 1A flowchart illustrating a specific embodiment of step S102; Figure 5 yes Figure 4 A flowchart illustrating a specific embodiment of step S402; Figure 6 yes Figure 1 A flowchart illustrating a specific embodiment of step S103; Figure 7 This is a flowchart illustrating the second embodiment of the testing method provided in this application; Figure 8 yes Figure 7 A flowchart illustrating a specific embodiment of step S702; Figure 9 This is a schematic diagram of the structure of an embodiment of the testing device provided in this application; Figure 10 This is a schematic diagram of an embodiment of the computer-readable storage medium provided in this application. Detailed Implementation

[0019] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0021] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0022] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] As a core component of electronic systems, the data retention capability of memory is a key factor determining the long-term reliability of devices. Data retention capability typically refers to the time-dependent characteristic of a memory to retain stored data without loss under power failure or extreme environmental conditions, which is particularly crucial for non-volatile memory. However, due to various factors such as manufacturing process variations, material defects, and external environmental stress, the data retention performance of different memory cells can vary significantly. Therefore, how to efficiently and accurately test the data retention capability of memory has become a critical problem that urgently needs to be solved in the field of memory technology.

[0024] To address the aforementioned issues, this application first proposes a testing method, please refer to [link / reference needed]. Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the testing method provided in this application. In this embodiment, the testing method is applied to a memory to test the memory's data retention capability. Figure 1 As shown, the testing method in this embodiment includes steps S101 to S104: Step S101: While writing test data to the memory, apply multiple stresses to the memory based on preset stress loading data.

[0025] In this embodiment, during the data retention capability test of the memory, multiple stresses can be applied to the memory based on preset stress loading data while test data is being written to the memory. That is, this embodiment can perform dynamic coupling of multiple stresses while writing test data to the memory to simulate the complex operating conditions of the memory in actual use. The preset stress loading data in this embodiment includes multiple loading values ​​corresponding to multiple stresses, and the stresses in this embodiment include, but are not limited to, temperature, jitter voltage, write frequency, and loading time.

[0026] In this embodiment, during the application of multiple stresses to the memory based on preset stress loading data, the test data can be input cyclically, and the loading cycle of multiple stresses can be preset based on the test mode; moreover, in each loading cycle, multiple stresses in this embodiment need to be reloaded. Furthermore, the stresses applied during the test can be adaptively fine-tuned based on the electrical parameters of the memory to ensure that the memory is not damaged during the test. The specific adjustments are described below and will not be detailed further here.

[0027] Step S102: Obtain the quantization results of each memory cell under multiple stresses.

[0028] The memory includes multiple storage units. Therefore, before the end of each loading cycle in multiple stress loading processes, this embodiment can sequentially read the stored data of each storage unit, and obtain the quantitative result of the data retention capability of each storage unit based on the read stored data, preset test data, and the electrical parameters of the memory monitored during the test.

[0029] Step S103: Train a data retention capability prediction model based on preset stress loading data and quantization results.

[0030] As described above, this embodiment can acquire a set of quantization results in the memory corresponding to the preset stress loading data of that loading cycle in each stress loading cycle. Therefore, after acquiring multiple sets of quantization results, this embodiment can construct a data retention capability prediction model based on the guiding relationship between the preset stress loading data and the quantization results, and train the data retention capability prediction model based on the aforementioned acquired associated preset stress loading data and quantization results.

[0031] Step S104: Test similar types of memory based on the data retention capability prediction model to obtain the corresponding test results.

[0032] After training the data retention capability prediction model, the trained model can then be used to test similar types of memory to obtain the corresponding test results.

[0033] Unlike existing technologies, the testing method of this application includes: simultaneously writing test data to the memory and applying multiple stresses to the memory based on preset stress loading data; obtaining the quantization results of each memory cell under multiple stresses; training a data retention capability prediction model based on the preset stress loading data and quantization results; and testing similar memory types based on the data retention capability prediction model to obtain corresponding test results. Through this method, the testing method of this application can simulate the aging process of memory under complex actual working conditions, thereby significantly reducing testing time and improving memory testing efficiency.

[0034] Optionally, based on the above embodiments, please refer to Figure 2 , Figure 2 yes Figure 1 A flowchart illustrating a specific embodiment of step S101. This embodiment can be achieved through, as shown below... Figure 2 The steps shown implement step S101, specifically including steps S201 to S203: Step S201: Set multiple stress loading cycles in the memory-based test mode.

[0035] In this embodiment, before writing test data to the memory and applying multiple stresses collaboratively based on preset stress loading data, it is necessary to set multiple stress loading cycles based on the test mode during the memory testing process.

[0036] For example, if the memory's test mode is a full-chip write-erase cycle test mode, the loading cycles of multiple stresses in this embodiment can be set to a fixed duration. In this embodiment, the fixed duration can be set to one minute. In other embodiments, this fixed duration can be adjusted according to actual conditions and is not limited. If the memory's test mode is an accelerated test mode, the loading cycles of multiple stresses in this embodiment can be set in a gradual manner. For example, the initial cycle is set to one minute, then each cycle decreases by 10 seconds until the minimum cycle (e.g., 10 seconds) is reached; then each cycle increases by 10 seconds, returning to one minute, and this cycle is repeated.

[0037] Step S202: Obtain the fine-tuning values ​​of multiple stresses corresponding to each loading cycle.

[0038] In this embodiment, multiple stresses need to be applied to the memory in each loading cycle. However, to ensure that the memory is not damaged by the multiple applied stresses, it is also necessary to obtain the fine-tuning values ​​of the multiple stresses corresponding to each loading cycle based on the electrical parameters of the memory, and to fine-tune the loading values ​​of each stress. The specific method for obtaining the fine-tuning values ​​of the multiple stresses corresponding to each loading cycle is described below and will not be described in detail here.

[0039] Step S203: Dynamically adjust multiple stresses during the test based on the fine-tuning value.

[0040] Before applying multiple stresses to the memory in each loading cycle, this embodiment needs to obtain the fine-tuning values ​​corresponding to the multiple stresses in the loading cycle based on the current electrical parameters of the memory. After obtaining the fine-tuning values, the loading values ​​of the multiple stresses in the loading cycle can be adjusted accordingly to ensure that the memory is not damaged by the multiple stresses applied.

[0041] By introducing a mechanism based on test mode to set the loading cycle, this embodiment enables the testing process to accurately simulate the accelerated degradation behavior of memory cells at different aging stages, thereby effectively improving the accuracy of test results. Furthermore, this embodiment also achieves dynamic acquisition of the fine-tuning values ​​corresponding to each loading cycle under multiple stress conditions, allowing stress adjustment to respond in real-time to changes in the electrical parameters of the memory cells, thus helping to ensure the safety and reliability of the testing process.

[0042] Optionally, based on the above embodiments, please refer to Figure 3 , Figure 3 yes Figure 2A flowchart illustrating a specific embodiment of step S202. This embodiment can be achieved through, as shown below... Figure 3 The steps shown in step S202 are implemented, specifically including steps S301 to S302: Step S301: Obtain the electrical parameters during the memory testing process.

[0043] In this embodiment, when obtaining the fine-tuning values ​​of multiple stresses corresponding to each loading cycle, it is first necessary to obtain the electrical parameters of the memory during the testing process of each loading cycle. The electrical parameters in this embodiment include the threshold voltage, resistance value, tunnel magnetoresistance ratio, and leakage current of each memory cell.

[0044] Step S302: Input the electrical parameters into the trained adaptive loading model to obtain the fine-tuning values ​​of multiple stresses for each loading cycle.

[0045] After obtaining the electrical parameters during the memory test process of each loading cycle, this embodiment can input the electrical parameters into the trained adaptive loading model before each loading cycle to obtain the fine-tuning values ​​of multiple stresses corresponding to each loading cycle.

[0046] For example, the adaptive loading model in this embodiment can be represented as:

[0047] in, S t This is a fine-tuning value for the stress output by the adaptive loading model. P t Here are the input electrical parameters, and t is the time node. W Q 、W k 、W V These are the linear transformation matrices of query, key, and value in the self-attention mechanism, respectively. d For the dimensions of query, key, and value, W p The output weight matrix of the model. b P This is the output bias vector of the model. M constraint This is the coupling matrix of various stresses (describing the interactive effects of multiple stresses).

[0048] After constructing the adaptive loading model described above, this embodiment also needs to generate a corresponding training dataset for model training. The specific process of constructing the training set is as follows: First, the electrical parameters and fine-tuning values ​​are spatiotemporally aligned. The acquisition time of the electrical parameters is aligned with the setting time of the fine-tuning values, and the acquisition device (memory model) of the electrical parameters is aligned with the setting device (memory model) of the fine-tuning values. This yields a set of spatiotemporally synchronized electrical parameters and fine-tuning values. Second, the aligned data is mapped to a vector space and constructed as model input and output. An encoder maps the electrical parameters and fine-tuning values ​​into vector representations, and the electrical parameter vectors of each node are concatenated into a single vector on the spatiotemporal axis, serving as the model input. The corresponding fine-tuning value vectors are then concatenated to form the model output, thus creating input-output pairs. It is important to note that the decoder type used when subsequently restoring the fine-tuning values ​​from the model output should be consistent with that used in the encoding stage. Finally, all input-output pairs are integrated and stored as a training set for adaptive loading and model training.

[0049] In this embodiment, the trained adaptive loading model is used to automatically obtain fine-tuning parameters, making the process more efficient and reliable, thereby significantly shortening the testing cycle.

[0050] Optionally, based on the above embodiments, please refer to Figure 4 , Figure 4 yes Figure 1 A flowchart illustrating a specific embodiment of step S102. This embodiment can be achieved through, as shown below... Figure 4 The steps shown implement step S102, specifically including steps S401 to S403: Step S401: After each loading cycle ends, read the stored data of each memory cell.

[0051] In this embodiment, when obtaining the quantization results of the memory under multiple stresses, the memory can be divided into multiple memory cells, thereby obtaining the quantization results of multiple memory cells respectively.

[0052] In obtaining the quantization results, the first step is to read the stored data from each memory cell after each loading cycle. This stored data reflects the impact of various stresses on the memory.

[0053] Step S402: Based on the stored data, test data, and electrical parameters during the test, calculate the validity quantification value corresponding to each storage unit.

[0054] After acquiring the storage data of multiple storage cells after multiple stress loadings, the effectiveness quantification value corresponding to each storage cell can be calculated based on the storage data, the test data input during the test, and the electrical parameters during the test.

[0055] In this embodiment, the validity quantification value corresponding to the storage unit is mainly measured by three factors: bit error rate, threshold voltage drift, and leakage current. The bit error rate is obtained by comparing the stored data with the written test data, while the threshold voltage drift and leakage current are obtained through real-time monitoring during the testing process. The specific calculation method for the validity quantification value is described below and will not be described in detail here.

[0056] Step S403: In response to the validity quantification value of a certain storage cell being lower than a preset threshold, the storage cell is marked as invalid and the corresponding failure time of the storage cell is recorded.

[0057] In this embodiment, when the validity quantification value of a storage unit is lower than a preset threshold, the storage unit is marked as invalid, and the corresponding failure time is recorded. The failure time is equal to the sum of all loading cycles before the validity quantification value falls below the preset threshold.

[0058] In this embodiment, the preset threshold can be dynamically adjusted according to the memory type and model to ensure the accuracy of the test results.

[0059] In addition, for memory cells that have failed, this embodiment can also perform local heating repair (e.g., apply 50°C hot air for 10 seconds). If the validity quantification value of the memory cell is restored to above the preset threshold after repair, the memory cell will be included in the test range again; otherwise, the memory cell will be marked as permanently failed.

[0060] Through the above scheme, this embodiment decomposes the quantification result into two dimensions: validity quantification value and failure time. This allows for a more accurate description of the failure process of each memory unit, effectively improving test accuracy. Simultaneously, when the validity quantification value is lower than a preset threshold, the system automatically marks it as an invalid unit and accurately records the failure time. This enables rapid identification and precise location of failed units, facilitating high-reliability test determination.

[0061] Optionally, based on the above embodiments, please refer to Figure 5 , Figure 5 yes Figure 4 A flowchart illustrating a specific embodiment of step S402. In this embodiment, the electrical parameters include threshold voltage drift and leakage current. This embodiment can be achieved through, as shown in... Figure 5 The steps shown implement step S402, specifically including steps S501 to S503: Step S501: Calculate the bit error rate based on the stored data and test data.

[0062] As mentioned earlier, the validity quantification value of a memory cell is mainly measured by three factors: bit error rate (BER), threshold voltage drift, and leakage current. Therefore, when calculating the validity quantification value for each memory cell, it is first necessary to calculate the BER based on the stored data and test data. The BER is the ratio of the number of erroneous bits to the total number of bits in the test data.

[0063] Step S502: Obtain the quantization weights corresponding to the bit error rate, threshold voltage drift, and leakage current.

[0064] After obtaining the bit error rate corresponding to the memory cell, this embodiment also needs to obtain the quantization weights corresponding to the bit error rate, threshold voltage drift, and leakage current. The quantization weights corresponding to the bit error rate, threshold voltage drift, and leakage current can be dynamically adjusted based on the memory model, and are not specifically limited here.

[0065] Step S503: Calculate the validity quantization value based on the bit error rate, threshold voltage drift, leakage current, and their corresponding quantization weights.

[0066] Having obtained the bit error rate, threshold voltage drift, and leakage current, along with their corresponding quantization weights, this embodiment can calculate the validity quantization value based on the following formula, which is shown below:

[0067] in, R t Represented as a validity quantification value, V t This is expressed as the threshold voltage drift. M t Expressed as the number of error bits, N t This is expressed as the total number of bits in the test data. I t This is represented as leakage current. I initial This is represented as the initial leakage current value of the storage cell; V t This is expressed as the threshold voltage drift. Expressed as bit error rate, , and These are respectively represented as threshold voltage drift. V t Leakage current I t and bit error rate Quantization weights.

[0068] Optionally, based on the above embodiments, please refer to Figure 6 , Figure 6 yes Figure 1 A flowchart illustrating a specific embodiment of step S103. This embodiment can be achieved through, as shown in... Figure 6 The steps shown implement step S103, specifically including steps S601 to S603: Step S601: Construct a data retention capability prediction model based on the guiding relationship between preset stress loading data and quantization results, and construct a training set based on preset stress loading data and quantization results.

[0069] In this embodiment, after obtaining the associated preset stress loading data and quantization results, the first step is to construct a data retention capability prediction model based on the guiding relationship between the preset stress loading data and quantization results.

[0070] As mentioned above, the quantification result includes two items: the validity quantification value and the failure time. These two data points are used to jointly describe the data retention capability of the memory. Different preset stress loading data will cause certain changes in the quantification result. Therefore, the data retention capability prediction model needs to learn the hidden guiding relationship between the preset stress loading data and the quantification result in order to have the ability to predict the test result. Therefore, based on the above theory, a data retention capability prediction model can be constructed. In this embodiment, the data retention capability prediction model can be expressed by the following formula:

[0071] Among them, Y k This represents the quantized result of the data retention capability prediction model for the k-th memory cell. α、β These are the quantitative weights of validity quantification value and expiration time on the data retention capability, respectively. a 0 represents the offset of the k-th memory cell. a 1 ~a 4 represents the input temperature loading value. γ The loading value of the jitter voltage v and the load value of the write frequency f And the autoregressive coefficient of loading time T, T initial Let represent the initial failure time of the k-th memory cell, where ε, δ, τ, and η are failure acceleration factors for temperature, jitter voltage, write frequency, and load time, respectively.

[0072] After constructing the data retention capability prediction model, this embodiment also needs to build a training set based on preset stress loading data and quantization results. That is, to match the corresponding preset stress loading data and the quantization results obtained based on the preset stress loading data one by one, the input-output pairs of the data retention capability prediction model are obtained, and all input-output pairs are organized and stored as the training set.

[0073] Step S602: Train the prediction model for the ability to preserve training data based on the training set.

[0074] After obtaining the training set as described above, the data retention capability prediction model can be trained based on the training set. That is, as mentioned above, the data retention capability value can be obtained by weighted summing of the validity quantization value and the failure time in the quantization result. Then, preset stress loading data with different loading cycles are input into the data retention capability prediction model in a loop, and the absolute difference between the model's output value and the actual data retention capability value is calculated. The parameters in the data retention capability prediction model are iterated continuously with the goal of minimizing the difference. In this embodiment, a preset difference can be set as the target. When the output of the data retention capability prediction model for all preset stress loading data meets the expectations, the training can be stopped.

[0075] Step S603: In response to the completion of training, the model parameters of the data retention capability prediction model are associated with the memory model and stored.

[0076] Once the data retention capability prediction model is trained, its model parameters can be associated with the memory model and stored. When the data retention capability prediction model is subsequently tested for the data retention capability of the memory model, the model parameters can be retrieved based on the model number.

[0077] In other embodiments, when testing a memory using a data retention capability prediction model, if the data retention capability prediction model does not have model parameters corresponding to the memory model, it means that the memory model has not been trained. In this case, the test environment can still be used to obtain real-time test results. Then, the quantization results recorded during the test and the preset stress loading data at that time are used to train the data retention capability prediction model. When the output of the data retention capability prediction model meets expectations, the model parameters corresponding to the memory model and the corresponding model are associated and saved. When conducting subsequent tests on the memory model, the data retention capability prediction model can also be used to generate corresponding test results.

[0078] In addition, the data retention capability prediction model in this embodiment also needs to be incrementally trained with new test data periodically to ensure the accuracy of the model. Therefore, for memory models that have been tested in batches, it is also necessary to retest them periodically using the test environment to obtain new training sets.

[0079] Optionally, based on all the above embodiments, this application further proposes a testing method, please refer to [link to relevant documentation]. Figure 7 , Figure 7 This is a flowchart illustrating the second embodiment of the testing method provided in this application. Figure 7As shown, the testing method in this embodiment includes steps S701 to S706: Step S701: Obtain the model number of the memory.

[0080] Before obtaining the quantization result corresponding to the memory, this embodiment first needs to determine the model of the memory.

[0081] Step S702: Initialize the test environment based on the model and configure the test parameters corresponding to the model.

[0082] After obtaining the memory model, this embodiment needs to initialize the test environment based on the model and configure the test parameters corresponding to the model before testing the memory.

[0083] In addition, before initializing the test environment, this embodiment requires performing a three-stage temperature cycle calibration on the memory, with each stage lasting 30 minutes, to eliminate the influence of residual thermal stress on the test results. Then, the stability of the core voltage and programming voltage is verified through the built-in self-test circuit. If the voltage fluctuation exceeds ±2%, an alarm is triggered and the parameters are reconfigured.

[0084] Step S703: While writing test data to the memory, apply multiple stresses to the memory based on preset stress loading data.

[0085] Step S703 is the same as step S101, and will not be described again.

[0086] Step S704: Obtain the quantization results of each memory cell under multiple stresses.

[0087] Step S704 is the same as step S102, and will not be described again.

[0088] Step S705: Train a data retention prediction model based on preset stress loading data and quantization results.

[0089] Step S705 is the same as step S103, and will not be described again.

[0090] Step S706: Test similar types of memory based on the data retention capability prediction model to obtain the corresponding test results.

[0091] Step S706 is the same as step S104, and will not be described again.

[0092] Optionally, based on the above embodiments, please refer to Figure 8 , Figure 8 yes Figure 7 A flowchart illustrating a specific embodiment of step S702. This embodiment can be achieved through, as shown below... Figure 8 The steps shown implement step S702, specifically including steps S801 to S803: Step S801: Configure the hardware interface and communication protocol of the memory corresponding to the model.

[0093] During the initialization of the test environment and configuration of the memory's test parameters, different memories have different interface protocols and test methods, so the test environment and test parameters need to be configured as needed. In this embodiment, the hardware interface and communication protocol corresponding to the memory model need to be configured first.

[0094] That is, in this embodiment, the hardware interface of the test device can be switched according to the interface type supported by the memory. For example, non-volatile magnetic random access memory (MRAM) commonly uses the serial peripheral interface (SPI), which requires configuring the serial clock (SCLK) frequency (e.g., 50MHz) and transmission mode. Then, the communication protocol of the memory is configured, that is, the memory-specific command set is loaded. For example, the page program instruction (0x02) can be selected for flash memory, and the write pulse instruction (0x55) can be selected for resistive random access memory (RRAM).

[0095] In practical use, this embodiment also needs to periodically expand interface compatibility, add support for emerging interfaces (such as UFS 4.0 and HBM3), and dynamically switch interface modes through programmable logic devices to adapt to the signal timing requirements of different memories.

[0096] Step S802: Configure the read / write timing parameters and electrical parameters of the memory corresponding to the model.

[0097] After configuring the hardware interface and communication protocol, this embodiment also requires configuring the read / write timing parameters and electrical parameters of the memory corresponding to the model.

[0098] That is, setting critical timing parameters such as programming time, read time, and erase time for the memory, and setting the maximum operating frequency according to the memory specifications. For example, MRAM supports 200MHz, while electrically erasable programmable read-only memory (EEPROM) may only support 1MHz; configuring electrical parameters such as core voltage and programming voltage, such as the programming voltage of flash memory being 12V and the operating voltage of RRAM being 2.5V, and setting the maximum current during write / erase to prevent RRAM from being permanently damaged by overcurrent.

[0099] Step S803: Configure the test mode and test data for the memory corresponding to the model.

[0100] After configuring the read / write timing parameters and electrical parameters, this embodiment also requires configuring the test mode and test data corresponding to the memory model.

[0101] In this embodiment, as mentioned above, there are two test modes for the memory: full-chip write-erase cycle test mode and accelerated test mode. These two test modes can be switched at will during the test. In addition, this embodiment also needs to preset test data modes (such as all 0s, all 1s, checkerboard, or pseudo-random sequence) for the memory to ensure that all memory cell states are covered.

[0102] Optionally, this application further proposes a testing apparatus, please refer to [link to relevant documentation]. Figure 9 , Figure 9 This is a schematic diagram of an embodiment of the testing apparatus provided in this application. Figure 9 As shown, the testing device 100 in this embodiment includes a stress loading module 10, a quantization result acquisition module 20, a model training module 30, and a testing module 40.

[0103] The stress loading module 10 is used to apply multiple stresses to the memory based on preset stress loading data while writing test data to the memory; the quantization result acquisition module 20 is used to acquire the quantization result of each memory cell under multiple stresses; the model training module 30 is used to train a data retention capability prediction model based on preset stress loading data and quantization results; and the testing module 40 is used to test the same type of memory based on the data retention capability prediction model to obtain the corresponding test results.

[0104] Optionally, this application further proposes a computer-readable storage medium. See also... Figure 10 , Figure 10 This is a schematic diagram of an embodiment of the computer-readable storage medium provided in this application.

[0105] The computer-readable storage medium 200 of this application embodiment internally stores program instructions 210, which are executed to implement the test method described above.

[0106] Specifically, program instructions 210 can form a program file and be stored in the aforementioned storage medium as a software product, so that an electronic device (which may be a personal computer, server, or network device, etc.) or processor can execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks, or terminal devices such as computers, servers, mobile phones, and tablets.

[0107] In this embodiment, the computer-readable storage medium 200 may be, but is not limited to, a USB flash drive, SD card, PD optical drive, portable hard drive, large-capacity floppy drive, flash memory, multimedia memory card, server, etc.

[0108] In one embodiment, a computer program product or computer program is provided, the computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, causing the electronic device to perform the steps in the above-described method embodiments.

[0109] Furthermore, if the aforementioned functions are implemented as software functions and sold or used as independent products, they can be stored in a mobile terminal-readable storage medium. That is, this application also provides a storage device storing program data, which can be executed to implement the methods of the above embodiments. This storage device can be, for example, a USB flash drive, an optical disc, or a server. In other words, this application can be embodied in the form of a software product, which includes several instructions to cause a smart terminal to execute all or part of the steps of the methods of each embodiment.

[0110] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0111] Any process or method description in the flowchart or otherwise herein can be understood as representing an apparatus, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order according to the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0112] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequential list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (which may be a personal computer, server, network device, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable storage medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0113] The above are merely embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A testing method, characterized in that, Applied to memory, the test method includes: While writing test data to the memory, multiple stresses are applied to the memory based on preset stress loading data; Obtain the quantization result of each memory cell of the memory under the multiple stresses; A data retention prediction model is trained based on the preset stress loading data and the quantization results. The data retention capability prediction model is used to test the memory of the same type to obtain the corresponding test results.

2. The test method according to claim 1, characterized in that, The step of applying multiple stresses to the memory based on preset stress loading data includes: The loading cycle of the multiple stresses is set based on the test mode of the memory; Obtain the fine-tuning values ​​of the multiple stresses corresponding to each loading cycle; The multiple stresses are dynamically adjusted during the testing process based on the fine-tuning values.

3. The test method according to claim 2, characterized in that, The step of obtaining the fine-tuning values ​​of the plurality of stresses corresponding to each loading cycle includes: Obtain the electrical parameters during the memory testing process; The electrical parameters are input into the trained adaptive loading model to obtain the fine-tuning values ​​of the multiple stresses corresponding to each loading cycle.

4. The test method according to claim 2, characterized in that, The quantization result includes an effectiveness quantization value and a failure time. The step of obtaining the quantization result of each memory cell under the multiple stresses includes: After each loading cycle ends, the stored data of each storage cell in the memory is read; Based on the stored data, the test data, and the electrical parameters during the test, calculate the validity quantification value corresponding to each storage unit; If the validity quantification value of a certain storage unit is lower than a preset threshold, the storage unit is marked as invalid and the failure time corresponding to the storage unit is recorded.

5. The test method according to claim 4, characterized in that, The electrical parameters include threshold voltage drift and leakage current. The step of calculating the validity quantification value corresponding to each storage cell based on the stored data, the test data, and the electrical parameters during the test includes: The bit error rate is calculated based on the stored data and the test data. Obtain the quantization weights corresponding to the bit error rate, the threshold voltage drift, and the leakage current; The validity quantization value is calculated based on the bit error rate, the threshold voltage drift, and the leakage current and their corresponding quantization weights.

6. The test method according to claim 1, characterized in that, The step of training a data retention prediction model based on the preset stress loading data and the quantization results includes: The data retention capability prediction model is constructed based on the guiding relationship between the preset stress loading data and the quantization results, and a training set is constructed based on the preset stress loading data and the quantization results. The training data retention prediction model is trained based on the training set. Upon completion of training, the model parameters of the data retention capability prediction model are associated with the type of memory and stored.

7. The test method according to claim 1, characterized in that, Before the step of applying multiple stresses to the memory based on preset stress loading data while writing test data to the memory, the test method further includes: Obtain the model number of the memory; Initialize the test environment based on the model and configure the test parameters corresponding to the model.

8. The test method according to claim 7, characterized in that, The steps of initializing the test environment based on the model and configuring the test parameters corresponding to the model include: Configure the hardware interface and communication protocol of the memory corresponding to the model number; Configure the read / write timing parameters and electrical parameters of the memory corresponding to the specified model; Configure the test mode and test data corresponding to the memory model.

9. The test method according to claim 1, characterized in that, The stress includes temperature, jitter voltage, write frequency, and loading time.

10. A testing apparatus, characterized in that, include: The stress loading module is used to apply multiple stresses to the memory based on preset stress loading data while writing test data to the memory. A quantization result acquisition module is used to acquire the quantization result of each storage cell of the memory under the multiple stresses. The model training module is used to train a data retention capability prediction model based on the preset stress loading data and the quantization results. The testing module is used to test the memory of the same type based on the data retention capability prediction model in order to obtain the corresponding test results.

11. A computer-readable storage medium, characterized in that, It internally stores program instructions that are executed to implement the test method according to any one of claims 1-9.

12. A computer program product, characterized in that, Includes a computer program, which is executed by a processor to implement the test method according to any one of claims 1-9.

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