Parallel testing method and system for memory chips, electronic equipment and storage medium

Abstract

The application discloses a parallel test method and system of a storage chip, an electronic device and a storage medium. The method comprises: obtaining a plurality of target test items; wherein different target test items correspond to different performance test targets; determining a test channel platform type and a test support module corresponding to the target test items; distributing the target test items to corresponding test execution channels based on the test channel platform type and the test support module corresponding to the target test items; wherein the test execution channels are connected to the storage chip to be tested; controlling the test execution channels to start in parallel, and outputting a test result based on state information returned by the test execution channels. Therefore, by distributing different test items to different test execution channels, unified management of the test execution channels is realized to improve test efficiency, and the test execution channels start in parallel, which can realize parallelism of the target test items and further improve test efficiency.

Description

Technical Field

[0001] This application relates to the field of memory chip testing technology, and in particular to a parallel testing method, system, electronic device and storage medium for memory chips. Background Technology

[0002] With the continuous evolution of integrated circuit manufacturing processes, the complexity of chip functions is increasing exponentially, and the testing and verification stage has become a key bottleneck restricting the product launch cycle. In the mass production testing phase of memory chips, high-performance computing chips, and IoT system-on-a-chip, hundreds of different types of tests are typically required to verify the functional integrity, performance indicators, and long-term reliability of the devices.

[0003] In related testing technologies, single-channel or homogeneous multi-channel architectures are often used, with various test items executed sequentially, resulting in low testing efficiency. Furthermore, the lack of unified management of test channels leads to rigid resource allocation, preventing the full utilization of resources. Summary of the Invention

[0004] The main objective of this application is to propose a parallel testing method, system, electronic device, and storage medium for memory chips to address the problems of lack of unified management of test channels and low testing efficiency.

[0005] The first aspect of this application provides a parallel testing method for a memory chip, comprising: acquiring multiple target test items; wherein different target test items correspond to different performance test targets; determining the test channel platform type and test support module corresponding to the target test item; allocating the target test item to the corresponding test execution channel based on the test channel platform type and test support module corresponding to the target test item; wherein the test execution channel is connected to the memory chip under test; controlling each test execution channel to start in parallel, and outputting test results based on the status information returned by each test execution channel.

[0006] In some embodiments, the target test item is assigned to the corresponding test execution channel based on the test channel platform type and test support module corresponding to the target test item. This includes: determining the candidate test execution channel corresponding to the target test item based on the test channel platform type and working status information of each test execution channel; determining the test execution channel corresponding to the target test item based on the test support module configuration information of the candidate test execution channels and the availability status of each test support module, and assigning the target test item to the corresponding test execution channel.

[0007] In some embodiments, candidate test execution channels corresponding to the target test item are determined based on the test channel platform type corresponding to the target test item and the working status information of each test execution channel, including: obtaining real-time working status information of each test execution channel; wherein, the real-time working status information includes idle state, running state, waiting state and abnormal state; and selecting test execution channels whose test channel platform type is consistent with the test channel platform type corresponding to the target test item and are in the idle state as candidate test execution channels.

[0008] In some embodiments, the test support module configuration information includes information on whether the configuration is complete; based on the test support module configuration information of the candidate test execution channels and the availability status of each test support module, the test execution channel corresponding to the target test item is determined, including: if it is determined based on the test support module configuration information that the test support modules of all candidate test execution channels are not fully configured, then the configuration time required to configure the candidate test execution channels based on the available test support modules is determined; the candidate execution channel with the shortest configuration time is taken as the test execution channel corresponding to the target test item.

[0009] In some embodiments, after controlling the parallel startup of each test execution channel, the method further includes: obtaining the current working status information of each test execution channel, and determining, based on the current working status information, whether the test execution channel being started meets the preset abnormal conditions; marking the test execution channel that meets the preset abnormal conditions as an abnormal state, and controlling it to stop running, while keeping the remaining test execution channels running.

[0010] In some embodiments, before allocating target test items to corresponding test execution channels based on the test channel platform type and test support module corresponding to the target test items, the process includes: determining the test priority and expected test duration of multiple target test items; sorting the multiple target test items according to the test priority and expected test duration, so as to first allocate the top target number of target test items to the corresponding test execution channels; wherein, the total number of test execution channels is the target number.

[0011] A second aspect of this application provides a parallel testing system for memory chips, comprising: a host computer for generating a test verification plan; a central verification scheduling controller, communicatively connected to the host computer, for determining the test channel platform type and test support module corresponding to the target test item; and allocating the target test item to the corresponding test execution channel based on the test channel platform type and test support module corresponding to the target test item; multiple test execution channels connected to the central verification scheduling controller, each test execution channel having an independent SPI test link and a device under test interface; and a test support module, configured corresponding to at least some of the test execution channels, for providing a test environment for the corresponding target test item; wherein the central verification scheduling controller is also used to control the parallel startup of each test execution channel and determine the test result based on the status information returned by each test execution channel.

[0012] In some embodiments, the central verification scheduling controller includes: a binding module for establishing a binding relationship between target test items and test execution channels; a configuration module for configuring the corresponding test channel platform type and test support module according to the target test item; a scheduling module for controlling the operation of each test execution channel; a monitoring module for collecting the running status of each test execution channel in real time; and a processing module for receiving channel test results and outputting test results.

[0013] A third aspect of this application provides an electronic device, comprising: a processor and a memory; the memory for storing a computer program; and the processor for executing the computer program stored in the memory to cause the electronic device to perform a parallel testing method for a memory chip as described above.

[0014] A fourth aspect of this application provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, it implements a parallel testing method for a storage chip as described in any of the above claims.

[0015] The present application provides at least the following beneficial technical effects: Based on the parallel testing method, system, electronic device, and storage medium for memory chips provided in this application, the method includes: acquiring multiple target test items; wherein different target test items correspond to different performance test objectives; determining the test channel platform type and test support module corresponding to each target test item; allocating the target test items to corresponding test execution channels based on the test channel platform type and test support module; wherein the test execution channels are connected to the memory chip under test; controlling the parallel startup of each test execution channel, and outputting test results based on the status information returned by each test execution channel. Therefore, by allocating different test items to different test execution channels, unified management of test channels is achieved to improve testing efficiency, and the parallel startup of each test channel enables parallel testing of each target test item, further improving testing efficiency. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating an embodiment of the parallel testing method for memory chips provided in this application; Figure 2 This is a flowchart illustrating another embodiment of the parallel testing method for memory chips provided in this application; Figure 3 This is a flowchart illustrating yet another embodiment of the parallel testing method for memory chips provided in this application; Figure 4 This is a flowchart illustrating yet another embodiment of the parallel testing method for memory chips provided in this application; Figure 5 This is a flowchart illustrating yet another embodiment of the parallel testing method for memory chips provided in this application; Figure 6 This is a flowchart illustrating yet another embodiment of the parallel testing method for memory chips provided in this application; Figure 7 This is a structural block diagram of an embodiment of the parallel testing system for memory chips provided in this application; Figure 8 This is a structural block diagram of an embodiment of the central verification scheduling controller provided in this application; Figure 9 This is a schematic diagram of the structural framework of an embodiment of the electronic device provided in this application; Figure 10 This is a schematic diagram of the structural framework of an embodiment of the computer-readable storage medium provided in this application. Detailed Implementation

[0017] The solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments in this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0018] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0019] It should also be noted that when a component is referred to as "fixed to" or "set on" another component, it can be directly on the other component or an intervening component can be present simultaneously. When a component is referred to as "connected to" another component, it can be directly connected to the other component or an intervening component can be present simultaneously.

[0020] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0021] The first aspect of this application provides a parallel testing method for memory chips, which can be used to perform parallel testing on memory chips such as NAND flash memory with serial peripheral interfaces. Figure 1 This is a flowchart illustrating an embodiment of the parallel testing method for memory chips provided in this application. Figure 1 This method includes the following steps: S101: Obtain multiple target test items; wherein, different test items correspond to different performance test targets.

[0022] This involves receiving a list of test tasks to be executed from a host computer or test plan database, thereby identifying multiple target test items. Examples include read speed testing, write reliability testing, erase lifetime testing, data retention capability testing, and high / low temperature environment adaptability testing. Each target test item can include key attributes such as test type identifier, test parameter set, pass / fail criteria, and expected execution time. Different test items correspond to different performance testing objectives of the memory chip. For example, read speed testing aims to verify the continuous read rate and random read response time of the memory chip under different data block sizes; write reliability testing checks for bit flips or data errors by repeatedly writing specific data patterns.

[0023] S102: Determine the test channel platform type and test support module corresponding to the target test item.

[0024] The test channel platform type and test support module corresponding to the target test item can be determined based on a preset correspondence. The preset correspondence can be a pre-defined relationship between test items and test channel platform types and test support modules, implemented through configuration files, database tables, or a rule engine. The test channel platform type is essentially the type of test execution channel, which can include MCU test execution channels, FPGA test execution channels, and SoC test execution channels, among others. Different test channel platform types have different hardware architectures and processing capabilities. For example, MCU test execution channels are suitable for low-rate, low-complexity basic function tests, such as ID recognition and basic read / write operations. FPGA test execution channels, with their powerful parallel processing capabilities and reconfigurable characteristics, are suitable for high-speed data transmission tests and complex timing logic verification scenarios, such as NAND Flash page programming timing tests and burst data transmission rate tests. SoC test execution channels integrate multiple functional modules and can be used for system-level testing, such as the collaborative work test between memory chips and peripheral interfaces.

[0025] In some application scenarios, if the target test item is a long-cycle control-type test item, then the corresponding test channel platform type is determined to be the MCU test execution channel. Long-cycle control-type test items refer to test items with a relatively long execution duration, relatively low timing accuracy requirements, and the need for stable state control and timed polling. Although the MCU test execution channel has a lower computing speed than the FPGA test execution channel, it has complete peripherals such as timers, ADCs, and GPIOs, and its software development cycle is short, making it suitable for performing reliability tests that need to last for several hours or even days. Allocating long-cycle tests to the MCU test execution channel can free up high-performance FPGA resources for short-term, high-precision tests, achieving optimized resource allocation.

[0026] If the first target test item is a high timing accuracy test item, then the corresponding test channel platform type is determined to be an FPGA test execution channel. High timing accuracy test items refer to test items that have strict requirements on signal timing relationships, requiring fine delay control or high-speed parallel processing. The hardware parallelism of the FPGA test execution channel enables it to generate precise clock edges and achieve complex timing relationship determinations, a level of accuracy that is difficult to achieve with MCU test execution channels. Assigning timing-sensitive tests to the FPGA ensures the accuracy and reliability of the tests.

[0027] If the first target test item is a system compatibility test item, then the test channel platform type corresponding to the target test item is determined to be the System-on-a-Chip (SoC) test execution channel. System compatibility test items refer to test projects that require running a complete operating system, file system, or complex protocol stack, involving hardware and software co-verification. The SoC test execution channel possesses complete computing capabilities and a software ecosystem, capable of running operating systems such as Linux, and performing complex scenarios such as file system stress testing and driver compatibility verification. These types of tests require high-level software abstraction and are difficult for MCUs and FPGAs to complete independently.

[0028] In some application scenarios, long-cycle control-type test items include at least one of lifetime testing, data retention testing, and aging testing. Lifetime testing verifies the performance degradation of memory cells after multiple program / erase cycles. This type of test is lengthy and requires stable control of the cycle process, making it a typical long-cycle control-type test item. Data retention testing verifies the integrity of data after long-term storage in high-temperature environments, requiring precise temperature control and timing management. Aging testing accelerates device aging under high temperature and high pressure environments, screening for early failures. It requires continuous application of stress voltage and monitoring of leakage current, and is also a long-cycle control-type test item.

[0029] In some application scenarios, high timing accuracy test items include at least one of the following: Shmoo testing, high-frequency interface timing boundary testing, and fine timing scan testing. Shmoo testing explores the boundary conditions of device operation through two-dimensional scanning, requiring precise control of timing relationships with minute step sizes; it is a high timing accuracy test item. High-frequency interface timing boundary testing targets high-speed interfaces such as DDR and PCIe, testing the boundaries of setup and hold times, requiring picosecond-level adjustments at GHz-level clock speeds; it is also a high timing accuracy test item. Fine timing scan testing performs fine sampling of signal eye diagrams to analyze jitter and margins, requiring sub-nanosecond sampling resolution; it is also a high timing accuracy test item.

[0030] In some application scenarios, system compatibility testing includes at least one of the following: compatibility testing, file system stress testing, and system-level verification testing. Compatibility testing verifies the compatibility of the device under test (DUT) with different brands of controllers and different versions of drivers, requiring the execution of the complete software protocol stack; this falls under system compatibility testing. File system stress testing simulates scenarios such as heavy random read / write operations and power-off recovery on storage devices by the operating system, requiring the execution of file system management software; this also falls under system compatibility testing. System-level verification testing verifies the chip's functional performance in a complete system environment, requiring a complete hardware and software environment; this also falls under system compatibility testing.

[0031] Among them, the test support module is a hardware or software module that provides a specific test environment or auxiliary functions for the target test item. For example, the high and low temperature chamber module is used to provide an extreme temperature environment for the memory chip to test its performance stability under high and low temperature conditions; the power management module can precisely control the voltage and current parameters during the test process to simulate the impact of different power supply conditions on the test results of the memory chip; and the data acquisition and analysis module is responsible for real-time acquisition, storage and preliminary analysis of a large amount of raw data generated during the test process to provide data support for subsequent test result evaluation.

[0032] In some application scenarios, if the target test item involves a controlled high-temperature environment, the corresponding test support module is identified as a temperature control module. The temperature control module refers to the hardware device capable of providing and maintaining a specific temperature environment, including a heating plate, temperature control chamber, temperature sensor, and closed-loop control circuit. Many reliability tests must be conducted under specific temperature stress. By dynamically binding the temperature control module through mapping relationships, flexible sharing of environmental resources is achieved, rather than fixed binding, improving the utilization rate of expensive temperature control equipment.

[0033] In some application scenarios, if the target test item involves voltage and frequency scanning, the corresponding test support modules are identified as programmable power supply modules and variable clock modules. The programmable power supply module refers to a precision power supply with software-adjustable output voltage, while the variable clock module refers to a clock generator with programmable frequency and phase.

[0034] In some application scenarios, if the target test item involves file system verification, the corresponding test support module is identified as the software environment support module. The software environment support module refers to the software environment required to run the file system and protocol stack, including the operating system image, drivers, file system libraries, and stress testing tools.

[0035] S103: Based on the test channel platform type and test support module corresponding to the target test item, the target test item is assigned to the corresponding test execution channel; wherein, the test execution channel is connected to the memory chip under test.

[0036] In this step, based on the matching requirements determined in S102 and the real-time status of each test execution channel, the target test item is assigned to a specific physical channel, thereby achieving the binding between the target test item and the test execution channel. In some application scenarios, a set of channels matching the target platform type can be selected first, and then the supporting module configuration and availability status of these channels can be checked. Finally, a channel that is idle and has the required supporting modules can be selected as the target channel, thereby establishing the binding relationship between the test item and the channel.

[0037] It should be understood that one target test item corresponds to one test execution channel, and one test execution channel is connected to one memory chip under test. This one-to-one connection ensures that each test execution channel can independently execute its assigned target test item on the memory chip under test connected to it, avoiding mutual interference between different test items and guaranteeing the independence and accuracy of the testing process. For example, while one test execution channel is performing a write reliability test on its connected memory chip, another test execution channel can simultaneously perform an erase lifetime test on another connected memory chip. Both are physically and logically independent, operating according to their preset test procedures and parameters, thus laying the foundation for subsequent parallel startup and execution.

[0038] Furthermore, each test execution channel is equipped with an independent SPI test link for data communication with the device under test (DUT) based on the SPI bus protocol. An independent SPI test link refers to a serial peripheral interface bus configured independently for each test execution channel, rather than a shared bus across multiple channels, ensuring that communication between channels does not interfere with each other. The independent SPI test link includes independent clock signal lines, chip select signal lines, data input signal lines, and data output signal lines. It should be understood that the independent link design eliminates the arbitration delay and conflict risks associated with multiple devices sharing a bus, ensuring that each channel can communicate with the DUT at maximum speed, and that a communication error in one channel will not affect other channels.

[0039] Each test execution channel is equipped with local test execution logic, used to control the timing of the channel based on the test flow of the target test item, send test stimuli to the device under test, collect response data, and perform preliminary interpretation. For example, in the MCU test execution channel, the local logic is the embedded firmware program; in the FPGA test execution channel, it is the hardware state machine or soft-core processor; and in the SoC test execution channel, it is the Linux driver and test application. It should be understood that distributed execution logic pushes test timing control down to the channel locality, reducing communication latency between the central controller and the channel, supporting fast responses at the microsecond or even nanosecond level, while also reducing the computational burden on the central controller.

[0040] S104: Control each of the test execution channels to start in parallel, and output the test results based on the status information returned by each of the test execution channels.

[0041] Based on the above, after assigning the target test items to the corresponding test execution channels, the test execution channels are controlled to start in parallel, and verification results are output based on the status information returned by each test execution channel, thereby achieving parallel testing of multiple memory chips. It should be understood that when controlling the parallel start of the test execution channels, either all target test items are assigned to the corresponding test execution channels, or all test execution channels have completed the matching of the corresponding target test items (regardless of whether the matching was successful).

[0042] Specifically, during the parallel startup process, a startup command is sent to each test execution channel. Upon receiving the command, each channel independently executes the target test items for the memory chip under test according to the pre-configured test parameters and procedures. Each test execution channel is equipped with a result feedback interface for transmitting status information back to the central verification scheduling controller. During test execution, each test execution channel collects and transmits status information in real time. This status information includes, but is not limited to, the current test step, the execution time, real-time test data (such as read / write speed, error rate, etc.), and whether any anomalies have occurred. After receiving the transmitted status information, it is further analyzed. When all test execution channels have completed their test tasks, or the test ends according to the preset termination conditions, the test data and status information from each channel can be combined, and the final test result can be generated based on the preset pass / fail judgment criteria.

[0043] In summary, the parallel testing method for memory chips provided in the above embodiments achieves precise matching and allocation of test tasks by assigning different target test items to independent test execution channels with corresponding test channel platform types and test support modules. Each test execution channel starts in parallel under unified coordination, enabling simultaneous testing of multiple memory chips under test for different performance targets. This effectively avoids the time overlap inherent in traditional serial testing modes and significantly improves the overall test throughput.

[0044] Figure 2 This is a flowchart illustrating another embodiment of the parallel testing method for memory chips provided in this application. (Combined with...) Figure 2 Based on the test channel platform type and test support modules corresponding to the target test item, the target test item is assigned to the corresponding test execution channel, including: S201: Based on the test channel platform type corresponding to the target test item and the working status information of each test execution channel, determine the candidate test execution channel corresponding to the target test item.

[0045] It should be understood that the operational status information of each test execution channel reflects whether the channel is currently idle, executing a test task, experiencing a fault, or requiring maintenance. A candidate test execution channel refers to the set of test execution channels that meet the platform type requirements of the target test item and are currently in a state where they can receive tasks. For a single target test item, multiple candidate test execution channels may be identified based on the corresponding test channel platform type and the operational status information of each test execution channel.

[0046] S202: Based on the test support module configuration information of the candidate test execution channels and the availability status of each test support module, determine the test execution channel corresponding to the target test item, and assign the target test item to the corresponding test execution channel.

[0047] It should be understood that after identifying candidate test execution channels, these channels may or may not be configured with supporting modules. In this case, the test support module configuration information can include the types, quantities, and versions of the test support modules configured in the candidate test execution channel. The availability status of each test support module indicates whether the module is currently idle, occupied by other test tasks, faulty, or requires calibration. Therefore, determining the test execution channel corresponding to the target test item based on the test support module configuration information of the candidate test execution channels and the availability status of each test support module ensures that the assigned test execution channel not only matches the platform type but also provides all the valid supporting modules required by the test item, guaranteeing the smooth execution of the test.

[0048] Figure 3 This is a flowchart illustrating yet another embodiment of the parallel testing method for memory chips provided in this application. (Combined with...) Figure 3 Based on the platform type of the test channel corresponding to the target test item and the working status information of each test execution channel, candidate test execution channels corresponding to the target test item are determined, including: S301: Obtain real-time working status information for each test execution channel; the real-time working status information includes idle state, running state, waiting state, and abnormal state.

[0049] The real-time working status information of the test execution channels can be dynamically collected by a real-time monitoring system. Idle state indicates that the test execution channel is not currently carrying any test tasks, and its hardware resources are idle; it can immediately receive new test task assignments. Running state indicates that the channel is executing an assigned test task; at this time, the channel's CPU utilization, memory usage, and other resource indicators are at a high level, and it cannot process new tasks simultaneously. Waiting state usually indicates that the channel has completed some test steps and is waiting for external trigger conditions; in this state, although the channel is not completely idle, it cannot receive new tasks. Abnormal state indicates that the channel has encountered hardware failure, software error, or abnormal test data during operation, requiring manual intervention or automatic system recovery. Channels in abnormal state must be troubleshooted before they can be put back into use.

[0050] S302: Select test execution channels whose test channel platform type is consistent with the test channel platform type corresponding to the target test item and which are in an idle state as candidate test execution channels.

[0051] This step selects test execution channels whose platform type matches the target test item's platform type and which are currently idle as candidate test execution channels. This is because idle channels can immediately respond and execute new test tasks, avoiding task delays caused by busy channels. For example, if the target test item is a high timing precision test item, and its corresponding test channel platform type is an FPGA test execution channel, then the system will filter out currently idle channels from all FPGA test execution channels and include them in the candidate set.

[0052] Figure 4 This is a flowchart illustrating yet another embodiment of the parallel testing method for memory chips provided in this application. (Combined with...) Figure 4 The test support module configuration information includes whether the configuration is complete; based on the test support module configuration information of the candidate test execution channels and the availability status of each test support module, the test execution channel corresponding to the target test item is determined, including: S401: If it is determined based on the test support module configuration information that the test support modules for all candidate test execution channels have not been configured, then determine the configuration time required to configure the candidate test execution channels based on the available test support modules.

[0053] It should be understood that the test support module configuration information includes whether the configuration is complete. This means that some candidate test execution channels may not yet have all the test support modules required for the target test item fully configured. If, based on the test support module configuration information, it is determined that all candidate test execution channels have incomplete test support module configurations, it indicates that there are no candidate test execution channels with test support modules that meet the target test requirements. The configuration time required to configure candidate test execution channels based on available test support modules is then determined. Specifically, this can be done by estimating the time required to configure the missing test support modules for each candidate test execution channel based on the system's preset module configuration process and historical configuration data. At this point, the system needs to assess the time cost required to configure the missing modules for these candidate channels. For example, if a candidate FPGA test execution channel requires a specific model of high-speed signal conditioning module to meet the signal integrity requirements of the Shmoo test, and if the module is currently in sufficient stock and supports hot-swapping, the configuration time may only be 5 minutes.

[0054] S402: Select the candidate execution channel with the shortest configuration duration as the test execution channel corresponding to the target test item.

[0055] After determining the configuration duration, to minimize the overall startup latency of the test task, the system will prioritize the candidate execution channel with the shortest configuration duration as the final allocation channel for the target test item. For example, in two candidate FPGA test execution channels where neither has completed the configuration of the supporting modules, if channel A requires 5 minutes to configure the missing module and channel B requires 10 minutes, the system will allocate the target test item to channel A to expedite the test task startup process. It should be understood that this selection strategy based on configuration duration can improve the overall efficiency of the test system by optimizing configuration time when both candidate channels require configuration, ensuring that the test task can enter the execution phase as quickly as possible.

[0056] Figure 5 This is a flowchart illustrating yet another embodiment of the parallel testing method for memory chips provided in this application. (Combined with...) Figure 5 After controlling the parallel startup of each test execution channel, it also includes: S501: Obtain the current working status information of each test execution channel, and based on the current working status information, determine whether the test execution channel in the process of starting up meets the preset abnormal conditions.

[0057] It should be understood that the current operating status information of the test execution channel can reflect its operation in real time during the test startup phase, including but not limited to initialization progress, key signal levels, communication handshake status, and power stability parameters. Preset abnormal conditions are judgment criteria set based on common failure modes during the test startup phase, such as: initialization timeout, abnormal key signal line levels, communication handshake failure with the chip under test, and power module output voltage fluctuations exceeding the rated range.

[0058] S502: Mark the test execution channel that meets the preset abnormal conditions as an abnormal state and control it to stop running, while keeping the remaining test execution channels running.

[0059] It should be understood that this configuration allows the system to quickly isolate and stop some channels when they malfunction, preventing these abnormal channels from interfering with the overall parallel testing process. Simultaneously, it ensures that other normal channels remain unaffected and continue executing their test tasks, thereby minimizing the overall testing efficiency loss caused by localized anomalies. For example, if a test execution channel experiences an initialization timeout during startup, the system will immediately mark it as abnormal and cut off its power supply. Other channels that have successfully started will continue testing the memory chip under test according to the established procedure, ensuring the continuity and stability of the parallel testing.

[0060] Figure 6 This is a flowchart illustrating yet another embodiment of the parallel testing method for memory chips provided in this application. (Combined with...) Figure 6 Based on the test channel platform type and test support modules corresponding to the target test item, before assigning the target test item to the corresponding test execution channel, the following steps are taken: S601: Determine the test priority and expected test duration for multiple target test items.

[0061] Specifically, test priorities can be categorized based on the importance, urgency, or impact on the core functionality of the chip. For example, read / write verification tests involving data reliability can be set as high priority, performance optimization stress tests as medium priority, and compatibility verification extended function tests as low priority. The estimated test duration can be estimated based on historical test data, test case complexity, and the target chip's specifications. For instance, the estimated duration for a full-chip erase / write test on a large-capacity storage chip might be 2 hours, while the estimated duration for a read / write test of a specific function register might only be 5 minutes.

[0062] S602: Based on test priority and expected test duration, sort multiple target test items for testing, and first assign the top target number of target test items to the corresponding test execution channels; wherein, the total number of test execution channels is the target number.

[0063] Specifically, the test sorting strategy can be optimized by combining priority and duration. For example, a sorting rule of prioritizing high-priority tests and then prioritizing shorter-duration tests within the same priority range can be adopted. This means that all target test items are first sorted from highest to lowest priority, and for test items with the same priority, they are then sorted again according to their expected test duration from shortest to longest. This sorting method ensures that important and shorter-duration test tasks are started quickly, preventing high-priority tasks from being delayed by waiting for lower-priority, longer-duration tasks. After determining the test sorting, the top target number of test items (i.e., the total number of test execution channels) are selected sequentially according to the sorting results, and these test items are assigned to their corresponding test execution channels, thereby achieving orderly scheduling of test tasks and efficient utilization of resources.

[0064] For example, if the system has 5 test execution channels, and the sorted target test items are in the order of high priority short duration item A, high priority long duration item B, medium priority short duration item C, medium priority medium duration item D, and low priority short duration item E, then the system will prioritize allocating these 5 test items A, B, C, D, and E to the 5 test execution channels respectively, ensuring that all channel resources can be fully utilized during the parallel startup phase.

[0065] A second aspect of this application provides a parallel testing system 20 for memory chips. Figure 7 This is a structural block diagram of an embodiment of the parallel testing system 20 for memory chips provided in this application.

[0066] Combination Figure 7 The parallel testing system 20 for memory chips includes: a host computer 21, a central verification scheduling controller 22, multiple test execution channels 23, and a test support module 24.

[0067] Specifically, the host computer 21 is used to generate test verification plans. Specifically, it can generate test verification plans that include multiple test items such as life test, read interference test, data retention test, aging test, shmoo test, and compatibility test based on the verification requirements of the new part number memory chip.

[0068] Specifically, the central verification scheduling controller 22 is communicatively connected to the host computer 21. It determines the test channel platform type and test support module corresponding to the target test item, and accurately allocates the target test item to the corresponding test execution channel based on the working status information of each test execution channel and the configuration information of the test support module. Simultaneously, the central verification scheduling controller 22 is also responsible for controlling the parallel startup of test tasks on each test execution channel, and acquiring the status information and test data of each channel in real time during the test, performing comprehensive analysis and result determination. For details regarding the specific execution method and explanation of the above steps by the central verification scheduling controller 22, please refer to the relevant descriptions in the above embodiments, which will not be repeated here.

[0069] Specifically, each test execution channel 23 is connected to the central verification scheduling controller 22. Each test execution channel 23 has a specific test channel platform type, such as the FPGA test execution channel, ASIC test execution channel, or MCU test execution channel in the above embodiments. Test execution channels of different platform types have differentiated characteristics in terms of processing speed, interface type, and signal accuracy to adapt to the testing requirements of different types of memory chips. Each test execution channel 23 has an independent SPI test link and a device under test (DUT) interface. The SPI test link supports the standard SPI protocol and various extended protocols, and can flexibly configure clock frequency, data bit width, and transmission mode to meet the communication requirements of different memory chips. The DUT interface adopts a universal design and is equipped with a replaceable adapter, which can be compatible with memory chips in various package forms such as SOP, TSOP, and BGA, greatly improving the hardware compatibility of the test execution channels.

[0070] Specifically, the test support module 24 is configured corresponding to at least some of the test execution channels 23, providing auxiliary functions required for testing for the corresponding test execution channels 23, and providing a test environment for the corresponding target test items. It should be understood that the test support module 24 can be connected to different test execution channels 23 according to their actual needs. The test support module 24 includes, but is not limited to, a power supply module, a temperature control module, a signal conditioning module, and a load simulation module. The power supply module provides multi-level adjustable voltage output, supports fine voltage adjustment to meet the power supply requirements of memory chips at different process nodes, and has overcurrent and overvoltage protection functions. The temperature control module, through a combination of semiconductor cooling and heating, can simulate a wide range of temperature environments, ensuring that the performance of memory chips can be tested under extreme temperature conditions. The signal conditioning module includes a high-speed differential signal amplifier, a low-noise filter, and an impedance matching network, which can accurately amplify, filter, and impedance match the test signal, effectively improving the integrity of the high-frequency test signal. The load simulation module can simulate different load scenarios of memory chips in actual applications, such as the dynamic switching of resistive load, capacitive load and inductive load, providing conditions for testing that are closer to the real application environment.

[0071] Figure 8 This is a structural block diagram of an embodiment of the central verification scheduling controller 22 provided in this application.

[0072] Combination Figure 8 Regarding the specific configuration of the central verification scheduling controller 22, in some embodiments, the central verification scheduling controller includes: a binding module 221, used to establish a binding relationship between the target test item and the test execution channel; a configuration module 222, used to configure the corresponding test channel platform type and test support module according to the target test item; a scheduling module 223, used to control the operation of each test execution channel; a monitoring module 224, used to collect the running status of each test execution channel in real time; and a processing module 225, used to receive the channel test results and output the test results. For explanations of the execution of the above steps by the above modules, please refer to the relevant descriptions in the above embodiments, which will not be repeated here. For example, after receiving the test verification plan issued by the host computer 21, the binding module 81 will match the characteristics of the target test item (such as test type, accuracy requirements, etc.) with the platform capabilities of each test execution channel 23 to establish a preliminary binding relationship list.

[0073] In some application scenarios, the central verification scheduling controller 22 can adopt a collaborative architecture of a microcontroller unit (MCU) and a field-programmable gate array (FPGA). In this case, the MCU is responsible for high-level scheduling logic, such as test item parsing, priority sorting, anomaly decision-making, communication with the host computer, and running the embedded operating system. The FPGA is responsible for low-level high-speed parallel control, such as simultaneously sending start signals to multiple channels, precise synchronization, and high-speed data acquisition preprocessing. This collaborative architecture balances the flexibility of complex control logic with the real-time performance of parallel control, effectively improving the system's response speed and test data processing efficiency. For example, during the parallel test startup phase, after the MCU completes test item priority sorting and channel allocation, it sends control commands to the FPGA via its internal high-speed bus. The FPGA then utilizes its hardware parallel processing capabilities to synchronously trigger start signals for all test execution channels within microseconds, ensuring precise synchronous execution of test tasks on each channel. Simultaneously, the FPGA can perform real-time preprocessing on the high-speed test data streams returned from each channel, such as data format conversion and outlier filtering, before transmitting the processed data to the MCU for result analysis and judgment. This significantly reduces the data processing pressure on the MCU and ensures the stability and real-time performance of the system during multi-channel parallel testing.

[0074] This application also provides an electronic device, including: a processor; and a memory for storing a computer program, wherein the processor executes the computer program stored in the memory to cause the electronic device to perform a parallel testing method for a memory chip as described in any of the above embodiments.

[0075] Figure 9 This is a schematic diagram of the structural framework of an embodiment of the electronic device 600 provided in this application.

[0076] Combination Figure 9In some embodiments, the electronic device 600 includes a central processing unit (CPU) 601 and a read-only memory (ROM) 602. The CPU 601 is a processor, and the ROM 602 is a memory. The CPU 601 can perform various appropriate actions and processes, such as executing the methods described in the above embodiments, based on a program stored in the ROM 602 or a program loaded from storage portion 608 into random access memory (RAM) 603. The RAM 603 also stores various programs and data required for system operation. The CPU 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0077] The following components are connected to I / O interface 605: an input section 606 including a keyboard, mouse, etc.; an output section 607 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN (Local Area Network) card, modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to I / O interface 605 as needed. A removable medium 611, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 610 as needed so that computer programs read from it can be installed into storage section 608 as needed.

[0078] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program including a computer program for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 609, and / or installed from removable medium 611. When the computer program is executed by central processing unit (CPU) 601, it performs various functions defined in the system of this application.

[0079] This application also provides a computer-readable storage medium 40, Figure 10This is a schematic diagram of the structural framework of an embodiment of the computer-readable storage medium 40 provided in this application.

[0080] Combination Figure 10 The computer-readable storage medium 40 stores a computer program 41, which, when executed by a processor, implements the parallel testing method for the memory chip as described in any of the above embodiments.

[0081] It should be noted that the computer-readable medium 40 shown in the embodiments of this application can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying a computer-readable computer program. The transmitted data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to wireless, wired, etc., or any suitable combination thereof.

[0082] In summary, the parallel testing method, system, electronic device, and storage medium for memory chips provided in this application include: acquiring multiple target test items; wherein different target test items correspond to different performance test objectives; determining the test channel platform type and test support module corresponding to each target test item; allocating the target test items to corresponding test execution channels based on the test channel platform type and test support module; wherein the test execution channels are connected to the memory chip under test; controlling the parallel startup of each test execution channel, and outputting test results based on the status information returned by each test execution channel. Therefore, by allocating different test items to different test execution channels, unified management of test channels is achieved to improve testing efficiency, and the parallel startup of each test channel enables parallel testing of each target test item, further improving testing efficiency.

[0083] The above are only some or preferred embodiments of this application. Neither the text nor the drawings should limit the scope of protection of this application. All equivalent structural transformations made using the content of this application's specification and drawings under the overall concept of this application, or direct / indirect applications in other related technical fields, are included within the scope of protection of this application.

Claims

1. A parallel testing method for a memory chip, characterized in that, include: Obtain multiple target test items; wherein, different target test items correspond to different performance test objectives; Determine the test channel platform type and test support module corresponding to the target test item; Based on the test channel platform type and test support module corresponding to the target test item, the target test item is assigned to the corresponding test execution channel; wherein, the test execution channel is connected to the memory chip under test; The test execution channels are started in parallel, and the test results are output based on the status information returned by each test execution channel.

2. The method according to claim 1, characterized in that, The step of assigning the target test item to the corresponding test execution channel based on the test channel platform type and test support module corresponding to the target test item includes: Based on the platform type of the test channel corresponding to the target test item and the working status information of each test execution channel, the candidate test execution channel corresponding to the target test item is determined; Based on the test support module configuration information of the candidate test execution channels and the availability status of each test support module, the test execution channel corresponding to the target test item is determined, and the target test item is assigned to the corresponding test execution channel.

3. The method according to claim 2, characterized in that, The step of determining the candidate test execution channel corresponding to the target test item based on the test channel platform type and the working status information of each test execution channel includes: Obtain real-time working status information for each test execution channel; wherein, the real-time working status information includes idle state, running state, waiting state, and abnormal state; The test execution channel whose test channel platform type is consistent with the test channel platform type corresponding to the target test item and is in the idle state is selected as the candidate test execution channel.

4. The method according to claim 2, characterized in that, The test support module configuration information includes whether the configuration is complete; the determination of the test execution channel corresponding to the target test item based on the test support module configuration information of the candidate test execution channels and the availability status of each test support module includes: If, based on the test support module configuration information, it is determined that the test support modules for all candidate test execution channels have not been configured, then the configuration time required to configure the candidate test execution channels based on the available test support modules is determined. The candidate execution channel with the shortest configuration duration will be selected as the test execution channel corresponding to the target test item.

5. The method according to claim 1, characterized in that, After the parallel startup of each of the test execution channels is controlled, the method further includes: Obtain the current working status information of each test execution channel, and based on the current working status information, determine whether the test execution channel in the process of starting up meets the preset abnormal conditions; The test execution channel that meets the preset abnormal conditions is marked as abnormal and its operation is stopped, while the remaining test execution channels continue to run.

6. The method according to claim 1, characterized in that, Before allocating the target test item to the corresponding test execution channel based on the test channel platform type and test support module corresponding to the target test item, the following steps are included: Determine the test priority and expected test duration for the multiple target test items; Based on the test priority and the expected test duration, the multiple target test items are sorted for testing, so that the top target number of target test items are first assigned to the corresponding test execution channels; wherein, the total number of test execution channels is the target number.

7. A parallel testing system for a memory chip, characterized in that, include: The host computer is used to generate test verification plans; The central verification scheduling controller is connected to the host computer and is used to determine the test channel platform type and test support module corresponding to the target test item; Based on the test channel platform type and test support module corresponding to the target test item, the target test item is assigned to the corresponding test execution channel; Multiple test execution channels are connected to the central verification scheduling controller, and each test execution channel has an independent SPI test link and a device under test interface. A test support module is configured to correspond to at least some of the test execution channels and is used to provide a test environment for the corresponding target test items; The central verification scheduling controller is also used to control the parallel startup of each test execution channel and determine the test results based on the status information returned by each test execution channel.

8. The system according to claim 7, characterized in that, The central verification scheduling controller includes: The binding module is used to establish the binding relationship between target test items and test execution channels; The configuration module is used to configure the corresponding test channel platform type and test support module according to the target test item; The scheduling module is used to control the operation of each test execution channel; The monitoring module is used to collect the running status of each test execution channel in real time; The processing module is used to receive channel test results and output the test results.

9. An electronic device, characterized in that, include: Processor and memory; The memory is used to store computer programs; The processor is used to execute a computer program stored in the memory to cause the electronic device to perform a parallel testing method for the memory chip as described in any one of claims 1 to 6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the parallel testing method for the memory chip as described in any one of claims 1 to 6.

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