A test method based on motherboard memory and a test system thereof

Abstract

The application discloses a test method based on a mainboard memory and a test system thereof, and the test method comprises the following steps: a test end downloads a test program to a to-be-tested mainboard through a one-to-many test fixture; the to-be-tested mainboard runs the test program and performs scanning test on the memory on the to-be-tested mainboard; and the to-be-tested mainboard controls the one-to-many test fixture to perform corresponding lamp display prompting according to a test result. After the memory on each to-be-tested mainboard is tested separately at an SMT factory end and qualified, the to-be-tested mainboard enters an assembly process of a rear end. In this way, the repair loss caused by the memory itself can be greatly reduced, the cost of a mobile phone mainboard manufacturing factory is reduced, and the problem that the memory is tested after assembly and the defective product is inconvenient to repair is solved.

Description

Technical Field

[0001] This invention relates to the field of testing technology, and in particular to a testing method and system based on motherboard memory. Background Technology

[0002] In the mobile phone motherboard SMT (Surface Mount Technology) manufacturing industry, the memory ICs used in early mobile phone products were imported materials from major manufacturers. Based on the reliability of the imported materials, after they were assembled into mobile phone motherboards, there was basically no 100% performance testing specifically for the memory ICs on the motherboard, nor were there any relevant efficient and reliable testing solutions.

[0003] However, with the increase in memory IC manufacturers, although costs have decreased, the quality of some memory ICs remains unreliable. Instead of conducting batch testing at the SMT (Surface Mount Technology) factory to detect quality issues early, the memory ICs are still tested through aging tests after assembly into complete devices at the assembly plant, resulting in low testing efficiency. If defective products are found during testing, the phone needs to be disassembled, the motherboard removed, and the memory IC replaced for repair. Due to the various processes involved in disassembling the phone screen, frame, and adhesive application, it is extremely easy to damage valuable components like the screen during disassembly, leading to very high repair costs.

[0004] Therefore, it is particularly important to perform board-level memory IC performance testing at the SMT factory stage. However, memory is not currently tested at the SMT factory stage, so existing technology needs to be improved and enhanced. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a testing method and system based on motherboard memory, so as to solve the problems of troublesome repair of defective products when testing memory after assembly.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: A testing method based on motherboard memory, comprising: Step A: The test terminal downloads the test program to the motherboard under test through a one-to-many test fixture; Step B: Run the test program on the motherboard under test to scan and test the memory on the motherboard under test; Step C: The motherboard under test controls the multi-device test fixture to display corresponding LED prompts based on the test results.

[0007] In the aforementioned motherboard memory-based testing method, the step of running a test program on the motherboard under test to scan and test the memory on the motherboard under test includes: After the motherboard under test automatically powers on, it runs the test program, which then enters factory mode. Perform data stress tests on the memory.

[0008] In the aforementioned motherboard-based memory testing method, the step of performing data stress testing on the memory includes a data mode test. The processor on the motherboard writes corresponding data to each memory address according to a preset data mode. After writing, the processor compares the data read from each memory address with the written data. If they are the same, the test is considered normal. If the read and written data of at least one memory address are different, the test is considered abnormal.

[0009] In the aforementioned test method based on motherboard memory, the step of performing data stress test on the memory also includes a data width test. The processor writes a preset number of bits of data to each memory address. After writing, the number of bits of data read from each memory address is compared with the number of bits written. If they are the same, the test is considered normal. If the number of bits read from at least one memory address is different from the number of bits written, the test is considered abnormal.

[0010] In the aforementioned motherboard memory-based testing method, the step of performing data stress testing on the memory further includes access mode testing. The processor generates a segment of test data and writes it to the last 20MB address of the memory. Stress transfer is performed, using the NEON instruction set to write the test data to the corresponding memory address from high address to low address, with gaps of 20MB each. After writing is completed, the processor sequentially reads the written data and compares each read data segment with the test data stored in the last 20MB. If the data is different, it is considered an abnormal test; if all the data are the same, it is considered a normal test.

[0011] In the aforementioned test method based on motherboard memory, the step of performing data stress test on the memory also includes memory stress test, while simultaneously performing data generation, copying, and comparison for a preset number of processes; if the data compared by each process is the same, the test is considered normal; otherwise, the test is considered abnormal.

[0012] A test system for implementing the aforementioned motherboard memory-based testing method includes a multi-device test fixture and a test terminal. The motherboard under test (MDT) has a memory, and several MDTs are mounted in corresponding test positions on the multi-device test fixture. The test terminal connects to each MDT through the multi-device test fixture and downloads a test program to the MDT via the multi-device test fixture. The MDT runs the test program to scan and test the memory on its motherboard. Based on the test results, the MDT controls the multi-device test fixture to display corresponding LED prompts.

[0013] In the aforementioned testing system, several test positions are matched with several light boards, and the USB communication interface of each test position is connected to the USB communication interface of the test end through a USB communication cable with a crossover length.

[0014] In the aforementioned testing system, the first set of pins on the test position is connected to the USB communication test point of the motherboard under test, and the test program received by the test position is downloaded to the corresponding motherboard under test through this set of pins. The second set of pins on the test position is connected to the test points of two GPIOs on the motherboard under test, which is used for communication between the motherboard under test and the LED board, and to control the LED board to light up the corresponding color indicator light to display the test results. The third set of pins on the test position is connected to the VBAT and GND test points of the motherboard under test, and is used to supply power to the motherboard under test through the fixture.

[0015] Compared to existing technologies, the present invention provides a testing method and system based on motherboard memory. The testing method includes the following steps: the testing end downloads the test program to the motherboard under test via a multi-device test fixture; the motherboard under test runs the test program to scan and test the memory on the motherboard under test; the motherboard under test controls the multi-device test fixture to display corresponding LED prompts based on the test results. After each memory on the motherboard under test is individually tested and passes the test at the SMT factory, it enters the back-end assembly process. This significantly reduces rework losses caused by defective memory and lowers costs for mobile phone motherboard manufacturing plants. It solves the problems of post-assembly memory testing and troublesome repair of defective products. Attached Figure Description

[0016] Figure 1 This is a flowchart of the testing method based on motherboard memory provided by the present invention.

[0017] Figure 2 This is a schematic diagram of the test system based on motherboard memory provided by the present invention.

[0018] Figure 3 This is a schematic diagram of the light board on the multi-tasking test fixture provided by the present invention. Detailed Implementation

[0019] This invention provides a testing method and system based on motherboard memory. To make the objectives, technical solutions, and advantages of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the invention and are not intended to limit the invention.

[0020] Please also refer to Figure 1 and Figure 2 The flowchart of the testing method based on motherboard memory provided in the embodiments of the present invention is as follows: Figure 1 As shown, the memory testing method includes the following steps: S100, the test terminal downloads the test program to the motherboard under test through a one-to-many test fixture; S200: The test program runs on the motherboard under test to scan and test the memory on the motherboard under test. S300, the motherboard under test controls the multi-test fixture to display corresponding LED prompts based on the test results.

[0021] All steps in this embodiment are batch tests performed at the SMT factory's production testing end. The motherboard under test has memory (including volatile and non-volatile) soldered on it but not assembled with other components. The memory on each motherboard under test is individually tested using standard download stations at the SMT factory, undergoing 100% performance testing. Only after passing this test does the memory proceed to the back-end assembly process. This significantly reduces rework losses due to defective memory, lowers costs for mobile phone motherboard manufacturers, and provides an efficient manufacturing and testing solution for products with lower quality requirements for memory ICs.

[0022] This embodiment utilizes a multi-port test fixture 10 on an existing download station. The difference lies in the fact that the test program transmitted from the test end, the test points on the motherboard, and the testing requirements of the memory are all related. Specifically, the multi-port test fixture 10 has several test positions (test position 1 to test position n, where n is a positive integer) and several LED boards (LED board 1 to LED board n) matching the test positions. The USB communication interface of each test position is connected to the USB communication interface of the test end 20 (e.g., a computer) via a multi-port USB communication cable. When the motherboard under test is mounted on the corresponding test position, the first set of pins on the test position connects to the USB communication test point of the motherboard under test. The test program received by the test position is downloaded to the corresponding motherboard under test through this set of pins. The second set of pins on the test position connects to the test points of two GPIOs on the motherboard under test to enable communication between the motherboard under test and the LED board, thereby controlling the LED board to illuminate the corresponding color indicator light to display the test results. The third set of pins on the test position is connected to the VBAT and GND test points of the motherboard under test, enabling power to be supplied to the motherboard under test through the fixture.

[0023] Before step S100, after the tester mounts the motherboard under test (with the memory soldered on) to the test position, they can manually operate the test terminal 20 to open the memory test program and select to download the test program to the motherboard under test. The test terminal 20 then detects the completion of the download and controls the motherboard under test to automatically power on.

[0024] Step S200 specifically includes: Step 210: After the motherboard under test automatically powers on, the test program will run and enter factory mode.

[0025] The factory mode, also known as the test mode, uses the motherboard under test to control the lighting of the LED board to display test results. It can be entered within 10 seconds. Compared with the existing method of displaying test results on the screen (which requires entering the Android system user mode and waiting for more than 60 seconds after the first boot), this mode entry time is greatly shortened and the testing efficiency is improved.

[0026] Step 220: Perform a data stress test on the memory.

[0027] This step primarily involves stress testing the read and write functions of the memory by importing various data modes, different data widths, different access modes, and using multi-threaded algorithms. Compared to traditional DDR stress testing, this method can more efficiently identify defective DDR modules and distinguish those with stability issues.

[0028] The test involves importing multiple data modes, or data mode testing. The processor on the motherboard writes corresponding data to each memory address according to a preset data mode. Data modes include all numbers (e.g., writing 0 or 1 to each memory address), random data (different data written to each memory address, such as 08AD, 10B8), and incrementing or decrementing data (e.g., writing binary increments sequentially according to the memory address order, with 000 for the first address, 001 for the second, 010 for the third, and so on, the number of bits depending on the number of memory addresses). Only one or more of these data modes can be written, and the writing order is not limited. After writing a data mode, the memory sends a write-complete flag to the processor. Upon receiving the flag, the processor initiates a read operation, comparing the data read from each memory address with the written data. If they match, the memory data mode is considered normal; if at least one memory address has different read and write data, the test is considered abnormal.

[0029] The data width test involves the processor on the motherboard writing a preset number of bits of data to each memory address. These preset numbers include 8 bits, 16 bits, 32 bits, 64 bits, and 128 bits. After writing each bit of data, the memory sends a write-complete flag to the processor. Upon receiving the flag, the processor initiates a read operation, comparing the number of bits read from each memory address with the number of bits written. If they are the same (e.g., both are 8 bits), the memory data width is considered normal. If at least one memory address has a different number of bits read from and written, the test is considered abnormal.

[0030] The data content can be selected from one of the above data modes, such as binary. First, write 8 bits of binary 00000000 to all memory addresses. After completing the 8-bit read / write check, if it is normal, write 16 bits of binary 00000000000000000 to all memory addresses. After completing the 16-bit read / write check, if it is normal, continue writing and reading 32 bits, and so on. During the above check process, if any abnormality is found, the test will stop immediately and no further testing will be conducted, so that testers can quickly understand the test problem and resolve it in a timely manner.

[0031] Different access modes are tested using a reverse migration algorithm (equivalent to skip-writing data). The processor on the motherboard generates specific test data (such as a string of numbers) and writes it to the very end of memory, occupying the last 20MB. This test data serves as the standard answer for subsequent comparisons. Then, a pressure migration is performed, moving data from back to front using the NEON instruction set (a SIMD parallel computing technology that can move large amounts of data at once (e.g., 128 bits at a time), accelerating data movement). Every 20MB, the test data is written in a step-by-step manner, moving from high to low addresses, with a 20MB gap between each write operation. After the migration is complete, the processor sequentially reads the data written every 20MB, comparing it with the standard answer initially stored in the last 20MB. If the data is inconsistent, it indicates an abnormality in the corresponding memory address or an error in the data migration process, indicating a test anomaly. Only when all data is consistent is the test considered normal.

[0032] Multithreaded algorithms are used for memory stress testing, essentially subjecting multiple programs to simultaneous read and write operations on memory to observe potential errors. For example, six processes might simultaneously generate (write), copy (read), and compare (determine if the read and written data is identical). These six processes operate independently, each using its own data. If the compared data matches, the test is considered normal; otherwise, it is considered abnormal. The simultaneous execution of six processes increases the access frequency, thereby increasing the load on the DDR memory and helping to test stability and reliability under high load conditions.

[0033] The lamp panel provided in this embodiment is as follows: Figure 3 As shown, the front (top view) features a red alarm indicator R and a green normal indicator G (four LEDs form a group). The back (bottom view) has a power pad VBAT connected to the power supply terminal on the motherboard under test, a ground pad GND connected to the ground terminal on the motherboard under test, a red pad RED connected to the first test point on the motherboard under test, and a green pad GREEN connected to the second test point on the motherboard under test. It should be understood that below the two indicator lights is the component area, which contains circuitry consisting of switching transistors for controlling the indicator lights based on enable signals, current-limiting resistors, filtering capacitors, etc.; the circles on both sides of the LED board are screw holes for mounting; this is existing technology.

[0034] Step S300 specifically includes: when the processor on the motherboard determines that the test is normal, it outputs a valid normal enable signal LED-G (active low) to light up the normal indicator light on the light board; when it determines that the test is abnormal, it outputs a valid abnormal enable signal LED-R (active low) to light up the alarm indicator light on the light board. This greatly facilitates the tester's observation of the test results based on the color of the corresponding illuminated indicator light.

[0035] Based on the above-described motherboard-based memory testing method, this embodiment of the invention also provides a testing system for implementing the memory testing method. Please continue reading. Figure 2 The motherboard memory-based testing system includes a multi-device test fixture 10 and a test terminal 20. The motherboard under test is equipped with a memory IC (such as a flash memory chip mounted on the motherboard). Several motherboards under test are clamped in corresponding test positions on the multi-device test fixture 10. The test terminal 20 is connected to each motherboard under test through the multi-device test fixture 10. The test terminal 20 downloads the test program to the motherboard under test through the multi-device test fixture. The motherboard under test runs the test program to scan and test the memory on the motherboard under test. The motherboard under test controls the multi-device test fixture to display corresponding LED prompts based on the test results.

[0036] In summary, the motherboard memory-based testing method and system provided by this invention utilizes a conventional multi-device testing fixture in the SMT factory stage to perform 100% specialized testing on the Memory ICs on the motherboard. It directly illuminates indicator lights of corresponding colors to display normal or abnormal conditions, eliminating the need for connecting any screen to display test results or requiring the device to boot into the Android system. This makes memory testing more efficient and convenient. Assembly is then performed only after the test is passed, significantly reducing rework losses caused by defective memory and lowering costs for mobile phone motherboard manufacturing plants.

[0037] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A testing method based on motherboard memory, characterized in that, Including the following steps: The test terminal downloads the test program to the motherboard under test via a one-to-many test fixture; The test program runs on the motherboard under test to scan and test the memory on the motherboard under test; The motherboard under test controls the multi-test fixture to display corresponding LED prompts based on the test results.

2. The testing method based on motherboard memory according to claim 1, characterized in that, The steps for the motherboard under test to run the test program and perform a scan test on the memory on the motherboard under test include: After the motherboard under test automatically powers on, it runs the test program, which then enters factory mode. Perform data stress tests on the memory.

3. The testing method based on motherboard memory according to claim 2, characterized in that, The step of performing data stress testing on the memory includes a data pattern test, in which the processor on the motherboard writes corresponding data to each memory address according to a preset data pattern. After writing, the processor compares the data read from each memory address with the data written. If they are the same, the test is considered normal; if the data read from or written to at least one memory address is different, the test is considered abnormal.

4. The testing method based on motherboard memory according to claim 2, characterized in that, The step of performing data stress testing on the memory also includes a data width test. The processor writes a preset number of bits of data to each memory address. After writing, the number of bits of data read from each memory address is compared with the number of bits written. If they are the same, the test is considered normal. If the number of bits read from or written to at least one memory address is different, the test is considered abnormal.

5. The testing method based on motherboard memory according to claim 2, characterized in that, The step of performing data stress testing on the memory also includes access mode testing, whereby the processor generates a piece of test data and writes it to the last 20MB address of the memory; stress transfer is performed, using the NEON instruction set to write the test data to the corresponding memory address from high address to low address, with a gap of 20MB at each time. After the writing is complete, the processor reads the written data sequentially and compares each read data with the test data stored at the end of the last 20MB. If the data is different, it is considered an abnormal test; if all the data is the same, it is considered a normal test.

6. The testing method based on motherboard memory according to claim 2, characterized in that, The step of performing data stress testing on the memory also includes memory stress testing, while simultaneously performing data generation, copying, and comparison for a preset number of processes; if the data compared by each process is the same, the test is considered normal; otherwise, the test is considered abnormal.

7. A test system for implementing the motherboard memory-based test method of claim 1, characterized in that, The test includes a multi-test fixture and a test terminal. The motherboard under test is equipped with a memory. Several motherboards under test are clamped in corresponding test positions on the multi-test fixture. The test terminal is connected to each motherboard under test through the multi-test fixture. The test terminal downloads the test program to the motherboard under test through the multi-test fixture. The test program runs on the motherboard under test to scan and test the memory on the motherboard under test; The motherboard under test controls the multi-test fixture to display corresponding LED prompts based on the test results.

8. The testing system according to claim 7, characterized in that, Several test positions are matched with several light boards, and the USB communication interface of each test position is connected to the USB communication interface of the test end through a USB communication cable with a bit more than one point.

9. The testing system according to claim 8, characterized in that, The first set of pins on the test position is connected to the USB communication test point of the motherboard under test. The test program received by the test position is downloaded to the corresponding motherboard under test through this set of pins. The second set of pins on the test position is connected to the test points of two GPIOs on the motherboard under test, which is used for communication between the motherboard under test and the LED board, and to control the LED board to light up the corresponding color indicator light to display the test results. The third set of pins on the test position is connected to the VBAT and GND test points of the motherboard under test, and is used to supply power to the motherboard under test through the fixture.

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