MLCC product and method of manufacturing the same

Abstract

The application relates to an MLCC product and a manufacturing method thereof. The manufacturing method of the MLCC product comprises the following steps: obtaining a target length L, a target width W and a target thickness T of the MLCC product, L>W>T; taking the target width W direction as a stacking direction, taking the target thickness T as a design reference of a printing width d of an internal electrode layer, preparing a ceramic dielectric film with the printing width d, and making d<T; stacking the ceramic dielectric film and a blank dielectric layer in the target width W direction to form a bar block; after laminating the bar block, cutting according to the target length L and the target thickness T, so that the size of the obtained single chip in the direction perpendicular to the stacking direction is equal to the target length L and the target thickness T respectively, and the size in the direction parallel to the stacking direction is equal to the target width W; and sequentially performing a post-processing procedure to obtain the MLCC product. The method has the dual effects of cost reduction and efficiency improvement, and enhances the bending resistance and acoustic quality of the product.

Description

Technical Field

[0001] This application relates to the field of multilayer ceramic chip capacitor technology, and in particular to an MLCC product and its manufacturing method. Background Technology

[0002] Multilayer ceramic capacitors (MLCCs), also known as surface mount capacitors, are capacitors that use ceramic as the dielectric material and have a multilayer stacked structure. MLCCs have advantages such as small size, large capacitance, high temperature resistance, and good high-frequency characteristics. They are suitable for various circuits, such as oscillation circuits, timing or delay circuits, coupling circuits, and decoupling circuits, and are widely used in consumer electronics, automotive electronics, base stations, servers, and security industries.

[0003] The manufacturing process of MLCC products includes processes such as material preparation, casting, printing, stacking, lamination, cutting, glue removal, sintering, chamfering, end sealing, end firing, and electroplating. Among these, the stacking process involves layering the blank dielectric layer obtained from casting and the printed ceramic dielectric film to achieve the designed thickness, and then dividing them into blocks of a certain size. These blocks are then compacted through a lamination process and cut into multiple chips (also known as capacitor preforms). The number of chips obtained from a single block depends on the length and width of the chips, while the thickness of the block determines the thickness of the chips.

[0004] As MLCC products trend towards thinner designs, the thickness of the wafer blocks is gradually decreasing. However, the number of chips that can be cut from a single wafer block is still limited by the length and width of the chips, and cannot increase with the reduction in thickness. As a result, the costs of materials, labor, and equipment used in the processing of a single wafer block remain unchanged, and the manufacturing cost allocated to each MLCC product cannot be reduced, thus restricting its actual production capacity and cost optimization. Summary of the Invention

[0005] Therefore, it is necessary to provide an MLCC product and its manufacturing method to solve the problem that the manufacturing cost of MLCC products in traditional technology cannot be reduced as the thickness is reduced, and to optimize the internal electrode structure for products with different aspect ratios to improve product performance and reliability.

[0006] The above-mentioned objective of this application is achieved through the following technical solution: The first aspect of this application provides a method for manufacturing an MLCC product, comprising the following steps: Obtain the target length L, target width W, and target thickness T of the MLCC product, wherein the target length L is greater than the target width W, and the target width W is greater than the target thickness T; Using the target width W direction as the stacking direction and the target thickness T as the design reference for the printing width d of the inner electrode layer, a ceramic dielectric film with the printing width d is prepared, and the printing width d is made smaller than the target thickness T. The ceramic dielectric film and the blank dielectric layer are stacked along the target width W direction to form a block; After laminating the block, it is cut according to the target length L and the target thickness T, so that the size of the obtained single chip in the direction perpendicular to the stacking direction is equal to the target length L and the target thickness T, respectively, and the size in the direction parallel to the stacking direction is equal to the target width W; The MLCC products are obtained by performing post-processing steps in sequence.

[0007] In one embodiment, when the ratio of the target length L to the target thickness T, L / T, is ≥ 1.6, the coverage R of the inner electrode layer on the ceramic dielectric film satisfies: 41% ≤ R ≤ 75%, where the coverage R = (inner electrode layer area) / (ceramic dielectric film area).

[0008] In one embodiment, when the ratio of the target length L to the target thickness T, L / T, is ≥ 1.6, the ratio of the printing width d of the inner electrode layer to the target thickness T, d / T, satisfies: 0.76 ≤ d / T ≤ 0.92.

[0009] In one embodiment, the process further includes a tape-making process: placing the MLCC product flat in a carrier tape, such that the thickness direction of the MLCC product is perpendicular to the bottom surface of the carrier tape, wherein the thickness direction is perpendicular to the lamination direction.

[0010] In one embodiment, when stacking the ceramic dielectric films, the inner electrode layers are uniformly distributed in the stacking direction, and the spacing deviation between adjacent inner electrode layers is within ±10%.

[0011] In one embodiment, the ratio of the target width W to the target thickness T ranges from W / T = 1.25 to 2.95.

[0012] In one embodiment, the target width W ranges from 230 μm to 270 μm, and the target thickness T ranges from 180 μm to 220 μm.

[0013] In one embodiment, the number of chips obtained by cutting the block is 4.1 per cm. 2 ~ 4.93 pieces / cm 2 .

[0014] In one embodiment, the total number of layers of the inner electrode layer ranges from 340 to 395, and the target capacitance of the MLCC product ranges from 4.23 μF to 5.17 μF.

[0015] In the second aspect of the present application, an MLCC product is provided, which is manufactured by using the manufacturing method of the MLCC product as described above.

[0016] The present application has at least the following beneficial effects: Compared with the traditional structural design, for the thin MLCC product with the target width W greater than the target thickness T, the present application adopts the design idea of dimension interchange, and interchanges the target thickness T as the stacking direction in the traditional design with the target width W as the printing width direction of the inner electrode layer. Specifically: ① Stacking direction z: The target width W direction is used as the stacking direction z, so that the total size of the blank dielectric layer and the ceramic dielectric film after stacking along this direction is equal to the target width W; ② Printing of the inner electrode layer: The printing width d of the inner electrode layer is set to be the target thickness T minus the reserved margin, that is, d < T; ③ Cutting result: The bar block is cut according to the target length L and the target thickness T, so that the size of a single chip obtained in the direction perpendicular to the stacking direction z is equal to the target thickness T, and the size in the direction parallel to the stacking direction z is equal to the target width W. The MLCC product prepared thereby has the following advantages: (1) In the bar block cutting process, the arrangement density of the chips on the bar block depends on the size of the chips in the width direction of the bar block and perpendicular to the stacking direction. In the present application, this size is equal to the target thickness T - which is the minimum value among the three dimensions of the product, and is much smaller than the target width W which is the size in the chip width direction in the traditional design. Therefore, in the width direction of the bar block, the number of rows of chips that can be arranged increases from about "bar block width ÷ W" to "bar block width ÷ T". Since T is much smaller than W, the number of rows of chips increases significantly, resulting in a significant increase in the total number of chips that can be cut from the same bar block. This change directly leads to an increase in the single-batch production capacity, and at the same time, the material cost, equipment working hours, and labor cost分摊 by each product decrease as the number of chips increases, achieving the dual effects of cost reduction and efficiency improvement.

[0017] (2) The present application uses the target width W direction as the stacking direction. Since W is greater than the size T in the stacking direction in the traditional design, and the thickness of a single layer of dielectric remains basically unchanged, the required number of stacking layers N increases significantly. The increase in the number of stacking layers brings two effects: on the one hand, the inner electrode layer, as a metal material, is densely distributed in the ceramic matrix, forming more "toughening interlayers", which can effectively hinder the crack propagation, thereby improving the bending strength and reliability of the product; on the other hand, more inner electrode layers are simultaneously connected to the outer electrodes at both ends, increasing the connection area between the inner and outer electrodes, making the end adhesion stronger, and at the same time reducing the equivalent series resistance and dielectric loss of the product, and the high-frequency characteristics are better.

[0018] (3) The MLCC product of this application is laid flat during tape making, so that its thickness direction is perpendicular to the bottom surface of the carrier tape and the thickness direction is perpendicular to the stacking direction. When it is subsequently mounted on the PCB board, the inner electrode layer is 100% perpendicular to the PCB board surface. This not only enhances the product's resistance to PCB board bending and reduces cracking caused by board bending, but also ensures that the magnetic field generated by the product during power-on application is horizontal, effectively suppressing vertical vibration and howling caused by resonance with the PCB board, thus improving the acoustic quality of the product.

[0019] (4) Performance optimization for slender products: When the ratio of the target length L to the target thickness T of the product, L / T, is ≥ 10, the product exhibits slender geometric characteristics. This application optimizes the coverage R of the inner electrode layer (41% ≤ R ≤ 75%) and the printing width ratio d / T (0.76 ≤ d / T ≤ 0.92) to effectively improve the mechanical strength and bending resistance of slender products while ensuring capacitor performance, thus avoiding stress concentration or reliability degradation caused by improper inner electrode design. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application and to more completely understand this application and its beneficial effects, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of MLCC products in traditional technology; Figure 2 for Figure 1 The diagram shows the structure of the ceramic dielectric diaphragm in the MLCC product. Figure 3 for Figure 1 The diagram shows the state changes of MLCC products mounted on the PCB board. Figure 4 This is a schematic diagram of the structure of an MLCC product in one embodiment of this application; Figure 5 for Figure 4 The diagram shows the structure of the ceramic dielectric diaphragm in the MLCC product. Figure 6 for Figure 4 The diagram shows the state changes of MLCC products mounted on the PCB board. Figure 7 for Figure 6 The MLCC product shown is a cross-sectional view along line AA.

[0022] Figure label: 100, Traditional MLCC product; 110, Traditional ceramic dielectric film; 111, Traditional blank dielectric layer; 112, Traditional internal electrode layer; D, Traditional printing width of internal electrode layer.

[0023] 200, MLCC product of this application; 210, ceramic dielectric film of this application; 211, blank dielectric layer of this application; 212, internal electrode layer of this application; d, printing width of internal electrode layer of this application.

[0024] 300, PCB board. L, target length; W, target width; T, target thickness.

[0025] x, length direction of the block; y, width direction of the block; z, stacking direction. Detailed Implementation

[0026] To facilitate understanding of this application, the following detailed description is provided in conjunction with specific embodiments. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0028] In this application, "and / or" means any and all combinations of one or more of the related listed items. "At least one" means one or more, such as one, two, or more. "Multiple" or "several" means at least two, such as two, three, etc., and "multi-layered" means at least two layers, such as two, three, etc., unless otherwise expressly and specifically defined. In the description of this application, "several" means at least one, such as one, two, etc., unless otherwise expressly and specifically defined.

[0029] When a numerical range is disclosed in this application, the range is considered continuous and includes the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to an integer, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be merged. In other words, unless otherwise specified, all ranges disclosed in this application should be understood to include any and all subranges to which they are included.

[0030] Unless otherwise specified, all steps of this application can be carried out sequentially or randomly. For example, the method includes steps (a) and (b), indicating that the method can include steps (a) and (b) carried out sequentially, or can also include steps (b) and (a) carried out sequentially. For example, when it is mentioned that the method further includes step (c), it means that step (c) can be added to the method in any order. For example, the method can include steps (a), (b), and (c) in sequence, or can also include steps (a), (c), and (b), or can include steps (c), (a), and (b), etc.

[0031] In this application, "above" or "below" both include the corresponding number. For example, below 1 includes 1.

[0032] The temperature parameter in this application, unless otherwise specified, allows both constant temperature treatment and variation within a certain temperature range. It should be understood that the constant temperature treatment allows the temperature to fluctuate within the accuracy range controlled by the instrument. Fluctuations within ranges such as ±5°C, ±4°C, ±3°C, ±2°C, ±1°C are allowed.

[0033] In this application, room temperature refers to indoor temperature, normal temperature, or general temperature. Generally, the range of room temperature can be any one of the following temperature ranges: 23°C ± 2°C, 25°C ± 5°C, or 20°C ± 5°C.

[0034] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of the MLCC product 100 in the traditional technology. As Figure 1 shown, the MLCC product 100 is a thin product, and its target length L, target width W, and target thickness T satisfy L > W > T. In the traditional technology, taking the thickness direction of the product (i.e., the direction where the target thickness T is located) as the stacking direction z, multiple ceramic dielectric film sheets are stacked layer by layer along this direction to meet the requirement of the target thickness T.

[0035] Based on this selection of the stacking direction z, the design reference of the inner electrode layer is correspondingly determined: Since the stacking direction z is the thickness direction, the printing width D of the inner electrode layer needs to be designed based on the target width W. Specifically, when printing the inner electrode layer 112 on the blank dielectric layer 111, the printing width D of the inner electrode layer 112 is made slightly smaller than the target width W (i.e., D < W) to ensure margins on both sides, thereby forming the ceramic dielectric film sheet 110, and the result is shown in Figure 2 .

[0036] The manufacturing process of MLCC product 100 includes processes such as material preparation, casting, printing, stacking, lamination, cutting, glue removal, sintering, chamfering, end sealing, end firing, and electroplating. In the stacking process, multiple ceramic dielectric films 110 and blank dielectric layers are stacked layer by layer along the thickness direction until the total thickness reaches the target thickness T, resulting in a block of a certain size. Understandably, in... Figure 1 and Figure 2 In the diagram, x represents the length direction of the block, and y represents the width direction. Next, the block is compacted through a lamination process and then cut into multiple independent chips to obtain the MLCC semi-finished product.

[0037] The number of chips obtained from a single block depends on the length and width of the chips. Chip width typically ranges from several hundred micrometers to several millimeters. With a fixed length, a larger chip width results in fewer chips that can be cut from the same block. The block thickness only determines the chip thickness; variations in chip thickness do not affect the number of chips that can be cut from the same block.

[0038] During processing, the amount of auxiliary materials used for a single chip is independent of its thickness. Taking the lamination process as an example, regardless of the thickness of the chip, it must go through steps such as packaging in nylon or polyethylene bags, vacuum sealing, water pressure equalization, unpacking, and applying expanding foam, before cutting and removing the adhesive. Throughout the entire process from lamination to chip formation, the amount of packaging bags, expanding foam, and other auxiliary materials consumed by a single chip, as well as equipment and labor time, are basically the same.

[0039] As MLCC products trend towards thinner profiles, the thickness of the wafer blocks gradually decreases. However, the number of chips that can be cut from a single wafer block does not increase accordingly—this number remains limited by the length and width of the chips. Therefore, despite the reduction in product thickness, the costs of materials, labor, and equipment consumed in the processing of a single wafer block remain unchanged. This results in the inability to reduce the manufacturing cost per MLCC product, thus hindering the increase in production capacity and cost optimization for thinner products.

[0040] Furthermore, traditional techniques, which use the target thickness T as the stacking direction z, also present application-related problems. For example... Figure 3As shown, since the stacking direction z is the thickness direction, the large surface (i.e., the xy-plane) formed by the target length L and target width W of the product will become the supporting or bonding surface for subsequent processes such as tape taping and mounting. This means that the inner electrode layer 112 must be parallel to the carrier tape or PCB board 300 (Printed Circuit Board). This orientation has two adverse effects: First, the product has weak bending resistance after being mounted on the PCB board 300. When the PCB board bends, the product is prone to cracking, reducing reliability. Second, during power-on applications, the magnetic field generated by the product is perpendicular, which can easily cause vertical vibrations and friction with the PCB board, producing a whistling sound and affecting acoustic quality.

[0041] Based on this, the first aspect of this application provides a method for manufacturing MLCC products, which aims to overcome the problem that the manufacturing cost of MLCC products cannot be reduced as the thickness is reduced in the traditional technology, while improving the anti-bending performance and acoustic quality of MLCC products.

[0042] In some embodiments, a method for manufacturing an MLCC product includes the following steps: S1: Obtain the target length L, target width W, and target thickness T of the MLCC product. The target length L is greater than the target width W, and the target width W is greater than the target thickness T. S2: Using the target width W direction as the stacking direction z and the target thickness T as the design reference for the printing width d of the inner electrode layer, prepare a ceramic dielectric film with a printing width d, and make the printing width d smaller than the target thickness T. S3: Stack the ceramic dielectric film and the blank dielectric layer along the target width W direction to form a block; S4: After laminating the block, cut it according to the target length L and target thickness T so that the size of the obtained single chip is equal to the target thickness T in the direction perpendicular to the stacking direction and equal to the target width W in the direction parallel to the stacking direction. S5: Perform post-processing steps sequentially to obtain MLCC products.

[0043] The following combination Figure 4 , Figure 5 , Figure 6 , Figure 7 The above method is described in detail step by step.

[0044] S1: Obtain the target length L, target width W, and target thickness T of the MLCC product 200. For example... Figure 4 As shown, the MLCC product 200 is a thin product, which satisfies the requirement that the target length L is greater than the target width W, and the target width W is greater than the target thickness T, i.e., L>W>T.

[0045] In some embodiments, the ratio of the target length L to the target thickness T, L / T ≥ 1.6, and can be, for example, 1.6, 1.8, 2, 2.2, 2.5, 2.8, 3, 3.2, 3.5, 3.8, 4, 4.2, 4.5 or 4.8, preferably 1.6 to 3.8. Here, L / T represents the aspect ratio of the MLCC product 200.

[0046] In some embodiments, the ratio of the target width W to the target thickness T, W / T ≥ 1.25, and can be, for example, 1.25, 1.5, 1.75, 2, 2.25, 2.5, 2.75, 3, 3.25 or 3.5, preferably 1.25 to 2.95.

[0047] In some embodiments, the target length L is 290μm to 350μm, and can be, for example, 290μm, 300μm, 310μm, 320μm, 330μm, 340μm or 350μm.

[0048] In some embodiments, the target width W is 230μm to 270μm, and can be, for example, 230μm, 240μm, 250μm, 260μm or 270μm.

[0049] In some embodiments, the target thickness T is 180μm to 220μm, and can be, for example, 180μm, 190μm, 200μm, 210μm or 220μm.

[0050] S2: Take the target width W direction as the lamination direction z, and use the target thickness T as the design reference for the printing width d of the inner electrode layer 212. Prepare a ceramic dielectric film 210 with the printing width d, and make the printing width d less than the target thickness T to ensure a margin, that is, d < T.

[0051] For the thin-type MLCC product with W > T, this application creatively adopts the design idea of size interchange: converting the design in the traditional technology with the thickness direction as the lamination direction z and the width as the printing width reference to the design with the width direction as the lamination direction z and the thickness as the printing width reference. Specifically: ① Lamination direction z: Take the target width W direction as the lamination direction z, and make the total size of the blank dielectric layer and the ceramic dielectric film stacked along this direction equal to the target width W; ② Printing of the inner electrode layer: Set the printing width d of the inner electrode layer as the target thickness T minus the reserved margin, that is, d < T; ③ Cutting result: Cut the bar block according to the target length L and the target thickness T, so that the size of the single chip obtained in the direction perpendicular to the lamination direction z is equal to the target thickness T, and the size in the direction parallel to the lamination direction z is equal to the target width W.

[0052] In some embodiments, a printing screen plate is fabricated according to the printing width d designed in step S2, and then the ceramic dielectric film 210 is prepared through the following processes: (1) Batching: Ceramic powder, binder, solvent, and additives (including dispersant, plasticizer, defoamer, etc.) are ball-milled or sand-milled in a certain proportion to form a uniform and stable ceramic slurry. Among them, the ceramic powder determines the basic properties of the MLCC product; the binder is a polymer resin that maintains a certain distance between ceramic powders and provides strength; the solvent is a mixture of toluene and ethanol, etc., in a certain proportion; the dispersant is used to prevent the adhesion and agglomeration of ceramic powders and ensure that the ceramic slurry forms a stable and dispersed suspension.

[0053] (2) Casting: The ceramic slurry is coated on the winding silicone film through the pouring port of the casting machine to form a uniform thin layer of ceramic slurry; then it passes through the hot air zone, and most of the solvent in the ceramic slurry is volatilized by heating and drying to form a blank dielectric layer 211 with a certain thickness, density, and uniformity.

[0054] (3) Printing: The metal slurry is printed onto the blank dielectric layer 211 through the printing screen plate, and after drying, a clear and complete ceramic dielectric film 210 is obtained. The result is shown in Figure 5 .

[0055] As Figure 5 shown, the printing length of the inner electrode layer 212 remains unchanged, but the printing width d is less than the target thickness T (i.e., d < T), such that its printing width d is significantly less than Figure 2 the printing width D of the inner electrode layer 112 shown in Figure 4 and Figure 5 (i.e., d < D). Therefore, the number of inner electrode layers 212 printed on the same blank dielectric layer 211 increases significantly. Correspondingly, when cutting the bar later, the number of chips that can be obtained on the same bar will also increase significantly. Among them,

[0056] in

[0057] In some embodiments, the total number of layers N of the inner electrode layer 212 can be determined according to design requirements such as the target capacitance C, target width W, etc., and the value range is N = 340 - 395. For example, it can be 340, 345, 350, 355, 360, 365, 370, 375, 380, 385, 390, or 395.

[0058] At this point, the coverage R of the inner electrode layer 212 on the ceramic dielectric membrane 210 is controlled to satisfy: 41% ≤ R ≤ 75%, where the coverage R = (area of ​​inner electrode layer) / (area of ​​ceramic dielectric membrane), and its value can be 41%, 45%, 50%, 55%, 60%, 65%, 70%, or 75%. If R < 41%, the reinforcing effect of the inner electrode layer 212 on the ceramic substrate is insufficient, and the product's bending resistance decreases; if R > 75%, the exposed ceramic dielectric area is too small, which may affect the insulation performance and reliability.

[0059] Simultaneously, the ratio d / T of the printing width d of the inner electrode layer 212 to the target thickness T must satisfy: 0.76 ≤ d / T ≤ 0.92. The value of d / T can be 0.76, 0.78, 0.8, 0.82, 0.84, 0.86, 0.88, 0.9, or 0.92. If d / T < 0.76, the width of the inner electrode layer 212 is too small, resulting in insufficient effective capacitance area and difficulty in achieving the target capacitance C. If d / T > 0.92, the margin is too small, and the inner electrode layer 212 may be exposed on the side of the chip, leading to a short circuit risk or reduced adhesion at the chip tip.

[0060] S3: Stack the ceramic dielectric film 210 and the blank dielectric layer 211 prepared in step S2 along the target width W direction to form a block.

[0061] In the lamination process, the printed ceramic dielectric films 210 are stacked neatly layer by layer with a certain stagger to form a block of uniform thickness. During lamination, multiple blank dielectric layers 211 are added to the bottom and top, respectively, to serve as lower and upper protective covers, in order to increase mechanical strength and improve insulation performance.

[0062] According to the design in step S2, with the target width W as the stacking direction z, the total thickness of the blank dielectric layer 211 and the inner electrode layer 212 (or the ceramic dielectric film 210 printed with the inner electrode layer 212) stacked along this direction is equal to the target width W. This determines the total number of ceramic dielectric film 210 layers and the total number of blank dielectric layers 211 layers required in the stacking process, as well as their stacking order in the stacking direction z. Following this stacking order, the ceramic dielectric film 210 and the blank dielectric layer 211 are stacked sequentially to form a block.

[0063] In some embodiments, when stacking ceramic dielectric films 210, each inner electrode layer 212 is uniformly distributed in the stacking direction z, and the spacing deviation between adjacent inner electrode layers 212 is controlled within ±10%, so that the MLCC product 200 is subjected to bending stress with uniform stress distribution, avoiding local stress concentration and cracking caused by uneven arrangement of inner electrode layers 212.

[0064] S4: After laminating the block, cut it according to the target length L and target thickness T, so that the size of the obtained single chip in the direction perpendicular to the stacking direction z is equal to the target length L and target thickness T, respectively, and the size in the direction parallel to the stacking direction z is equal to the target width W.

[0065] In the lamination process of step S4, the layered films in the block are tightly bonded together by using static water pressure equalization at a uniform temperature, so as to improve the density of the sintered ceramic body and make it more tightly bonded together.

[0066] In the cutting process of step S4, the laminated block is cut longitudinally and laterally according to the design reference of step S2 using a blade according to the target length L and target thickness T, so that it becomes a completely separated chip, thus obtaining the MLCC semi-finished product.

[0067] In some embodiments, the number of chips obtained by cutting the block is 4.1 per cm. 2 ~ 4.93 pieces / cm 2 For example, it can be 4.1 per cm. 2 4.2 pieces / cm 2 4.3 pieces / cm 2 4.4 pieces / cm 2 4.5 pieces / cm 2 4.6 pieces / cm 2 4.7 per cm 2 4.8 pieces / cm 2 4.9 pieces / cm 2 Or 4.93 per cm 2 .

[0068] S5: Perform post-processing steps sequentially to obtain MLCC product 200.

[0069] In some embodiments, the MLCC product 200 includes an upper protective cover, a capacitor core, and a lower protective cover stacked sequentially along the stacking direction z. The capacitor core is formed by stacking multiple consecutive ceramic dielectric films 210 along the stacking direction z, and the inner electrode layers 212 of adjacent ceramic dielectric films 210 are intersected to form a capacitor unit. The upper and lower protective covers are each independently formed by stacking multiple blank dielectric layers 211 along the stacking direction z.

[0070] In some embodiments, the post-processing step S5 includes the following steps: (1) Removal of adhesive: The chip is laid flat on the nickel grid and transferred to the removal box. It is then heat-treated in a nitrogen atmosphere or an air atmosphere to promote the rapid decomposition and complete removal of organic components such as adhesives.

[0071] (2) Sintering: Using an atmosphere sintering furnace, high-temperature sintering is carried out between 1100℃ and 1350℃, so that the chip after debonding becomes a ceramic body with intact internal electrodes, high density, qualified size, high mechanical strength and excellent electrical properties.

[0072] (3) Chamfering: also known as grinding, the sintered ceramic chip body, along with chamfering balls, water, and grinding aids, is placed in a chamfering tank and moved by ball milling or planetary milling to remove burrs from the surface of the ceramic body, making its surface smooth, while fully exposing the inner electrode of the end face, facilitating the connection of the inner and outer electrodes.

[0073] (4) End sealing: Using an end sealing machine, the end electrode slurry is coated on both ends of the exposed inner electrode layer of the ceramic body after beveling, and the inner electrode layers on the same side are connected to form the outer electrode.

[0074] (5) Burning the end: Under high temperature conditions, the organic binder in the end electrode slurry is fully burned, the glass powder melts and wets the copper powder, so that the end is solidified and forms a good connection with the ceramic body and the inner electrode.

[0075] (6) Electroplating: In an electroplating solution containing nickel ions and / or tin ions, the end electrode is used as the cathode, and a nickel layer and a tin layer are deposited on the cathode by low-voltage direct current.

[0076] (7) Testing: All products are tested quickly for performance indicators such as capacity, loss, insulation, and withstand voltage. Defective products with short circuits, open circuits, or excessive capacity deviations are eliminated. At the same time, preliminary sorting is carried out according to different capacity ranges.

[0077] (8) External selection: Carefully observe the product surface under a magnifying glass or microscope using manual or automatic optical equipment, and remove products with appearance defects such as pits, cracks, missing corners, delamination, and poor end electrodes to ensure that the product appearance is intact.

[0078] (9) Final quality control: Conduct a comprehensive inspection of all products, accurately measure electrical parameters such as capacity, loss, insulation resistance, withstand voltage, equivalent series resistance, high frequency characteristics, and temperature characteristics, and strictly determine whether the products are qualified or not.

[0079] In the dicing process, the arrangement of chips on the dicing plane depends on the dicing direction. In the manufacturing method of this application, the length direction of the chip extends along the length direction x of the dicing block, while the size of the chip along the width direction y of the dicing block and perpendicular to the stacking direction z (i.e., the target thickness T direction) determines the chip arrangement density along the width direction y of the dicing block.

[0080] The target thickness T is the minimum of the three dimensions of the product, much smaller than the target width W, which is the chip width dimension in traditional designs. Therefore, more rows of chips can be arranged in the block width direction y. Specifically, in traditional designs, the chip width dimension is W, and the number of rows that can be arranged in the block width direction y is approximately the block width divided by W; while in this application, the chip dimension along the block width direction y is T, and the number of rows that can be arranged is approximately the block width divided by T. Since T is much smaller than W, the number of chip rows in the block width direction y is significantly increased in this application, thereby significantly increasing the total number of chips that can be cut from the same block.

[0081] The increase in the number of chips directly brings two benefits: first, the production capacity per batch increases, and the number of chips that can be produced per unit time increases significantly; second, the material cost, equipment hours and labor cost per unit decrease as the number of chips increases, achieving the dual effect of cost reduction and efficiency improvement.

[0082] On the other hand, the chip's dimension in the direction parallel to the stacking direction z is equal to the target width W, which significantly increases the number of ceramic dielectric film layers stacked along the stacking direction z (i.e., the total number of internal electrode layers). This increased number of layers not only strengthens the overall ceramic body of the product but also ensures a more complete connection between the internal electrode layers and the terminal electrodes, enhancing the adhesion of the terminals. Simultaneously, the increased number of stacked layers also leads to improved electrical performance, resulting in superior high-frequency characteristics and reduced equivalent series resistance and dielectric loss.

[0083] In some embodiments, after the FQC process, a tape-and-reel process is further included: the MLCC product 200 is laid flat in a carrier tape, with the thickness direction of the MLCC product 200 perpendicular to the bottom surface of the carrier tape. Since the thickness direction of this application is perpendicular to the stacking direction z, when the product is laid flat, its inner electrode layer 212 is necessarily perpendicular to the bottom surface of the carrier tape, thereby ensuring that when subsequently mounted on the PCB board 300, the inner electrode layer 212 is perpendicular to the surface of the PCB board 300.

[0084] The carrier tape has multiple grooves on its surface to accommodate MLCC products 200. The MLCC products 200 are placed flat in the grooves of the carrier tape and heat-sealed with a cover tape to form a continuous long braided tape. The long braided tape is wound onto a reel by a winding mechanism to form a reel that facilitates automatic gripping and placement by an SMT (Surface Mount Technology) pick-and-place machine.

[0085] In some embodiments, after the tape-making process, a packaging process is also included: the tape-made reels are placed in a moisture-proof bag, vacuum-sealed, and desiccant and humidity card are added. Labels containing specifications, batch number, and quantity are affixed, and finally, they are packed into cartons.

[0086] Please see Figure 6 and Figure 7 MLCC product 200 large surface area ( Figure 4 The xz plane shown is parallel to the stacking direction z, which naturally becomes the supporting or bonding surface for processes such as tape feeding and mounting. Because the ceramic dielectric diaphragm 210 of the product is perpendicular to this large surface, and the thickness direction of the product is perpendicular to the stacking direction z, it can be ensured that the ceramic dielectric diaphragm 210 and its inner electrode layer 212 are perpendicular to the PCB board 300. This not only enhances the product's resistance to PCB board 300 bending, reducing cracking caused by board bending and improving product reliability, but also, during power-on application, the magnetic field generated by the product is horizontal, effectively suppressing vertical vibrations and howling caused by resonance with the PCB board 300, thus improving the product's acoustic quality.

[0087] In some embodiments, the target capacitance of the MLCC product 200 ranges from 4.23 μF to 5.17 μF, for example, it can be 4.23 μF, 4.3 μF, 4.4 μF, 4.5 μF, 4.6 μF, 4.7 μF, 4.8 μF, 4.9 μF, 5 μF, 5.1 μF or 5.17 μF.

[0088] In some embodiments, the MLCC product 200 has a bending strength of 2mm to 10mm on the PCB board 300, for example, 2mm, 3mm, 4mm, 5mm, 6mm, 7mm, 8mm, 9mm, or 10mm. The bending strength can be characterized by bending the PCB board to a set value (e.g., 2mm to 10mm) at a speed of 1mm / sec, holding it for 60-65 seconds, and measuring the electrical properties of the MLCC product. If the deviation of its electrical properties from those before bending is within a specified deviation, the bending performance is deemed to be satisfied. A bending strength of 10mm indicates that the product meets the ≥10mm bending performance requirement.

[0089] In some embodiments, the noise caused by the resonance between the MLCC product 200 and the PCB board 300 is 20Hz to 20kHz, for example, it can be 20Hz, 50Hz, 100Hz, 200Hz, 500Hz, 800Hz, 1kHz, 2kHz, 5kHz, 8kHz, 10kHz, 12kHz, 15kHz or 20kHz.

[0090] In a second aspect, this application provides an MLCC product manufactured using the MLCC product manufacturing method described above.

[0091] Benefiting from the new structural design, the efficiency and production capacity of MLCC products have been significantly improved, and the material cost, equipment working hours, and labor cost have been greatly reduced. At the same time, the bending resistance of MLCC products on the PCB board has been enhanced, and the vibration and whistling phenomena generated during power-on applications have been effectively suppressed.

[0092] The following is a further description in combination with specific examples and comparative examples. The raw materials involved in the following specific examples and comparative examples, unless otherwise specified, can all be obtained commercially. The instruments used, unless otherwise specified, can all be obtained commercially. The processes involved, unless otherwise specified, are all conventional choices for those skilled in the art.

[0093] Example Please refer to Figure 4 、 Figure 5 、 Figure 6 and Figure 7 The manufacturing method of the MLCC product 200 in this embodiment is as follows: (1)Obtain the design parameters of the MLCC product 200: Target length L = 320μm; Target width W = 250μm; Target thickness T = 200μm; Target capacitance C = 4.7μF.

[0094] (2)Take the target width W direction as the stacking direction z. According to parameters such as the target width W and the target capacitance C, determine the total number of layers N of the inner electrode layer 212, and make the total thickness of the blank dielectric layer 211 and the inner electrode layer 212 stacked along the target width W direction equal to the target width W. At the same time, take the target thickness T as the design reference for the printing width d of the inner electrode layer 212, and obtain the printing width d of the inner electrode layer 212 according to the target thickness T, making d < T to ensure a margin.

[0095] Among them, the total number of layers N of the inner electrode layer 212 = 368, and the printing width d = 160μm.

[0096] (3)Prepare multiple blank dielectric layers 211 through batching and casting. Make a printing screen according to the printing width d designed in step (2), print the metal paste onto the blank dielectric layer 211 through the printing screen, and after drying, obtain a clear and complete ceramic dielectric film 210. The results are shown in Figure 5 .

[0097] (4) Stack the ceramic dielectric film 210 and the blank dielectric layer 211 prepared in step (3) along the target width W: First, stack multiple consecutive blank dielectric layers 211 to form the lower protective cover; then stack multiple consecutive ceramic dielectric films 210 layer by layer in a certain staggered and neat manner on top of the lower protective cover; finally, stack multiple consecutive blank dielectric layers 211 on top of the ceramic dielectric films 210 to form the upper protective cover, thereby obtaining a bar with a uniform thickness. The planar size of the bar is 310 mm × 310 mm.

[0098] (5) After laminating the bar, perform longitudinal cutting and transverse cutting according to the target length L and the target thickness T to obtain 7260 chips; the dimensions of the obtained chips in the direction perpendicular to the stacking direction z are respectively equal to the target length L and the target thickness T, and the dimension in the direction parallel to the stacking direction z is equal to the target width W.

[0099] (6) Perform processes such as degumming, sintering, chamfering, end sealing, end burning, electroplating, testing, external selection, and FQC in sequence to obtain qualified MLCC products 200; perform taping and packaging on the MLCC products 200.

[0100] Comparative Example Please refer to Figure 1 、 Figure 2 、 Figure 3 The manufacturing method of the MLCC product 100 in this comparative example is as follows: (1) Obtain the design parameters of the MLCC product 100: Target length L = 320 μm; Target width W = 250 μm; Target thickness T = 200 μm; Target capacitance C = 4.7 μF.

[0101] (2) Take the target thickness T direction as the stacking direction z, obtain the total number of layers N of the inner electrode layer 112 according to parameters such as the target thickness T and the target capacitance C, and make the total thickness after stacking the blank dielectric layer 111 and the inner electrode layer 112 along the target thickness T direction equal to the target thickness T. At the same time, take the target width W as the design reference for the printing width D of the inner electrode layer 112; obtain the printing width D of the inner electrode layer 112 according to the target thickness T, and make T < D < W to ensure a margin.

[0102] Among them, the total number of layers N of the inner electrode layer 112 is 240, and the printing width D is 200 μm.

[0103] (3) Multiple blank dielectric layers 111 are prepared by mixing and casting. A printing screen is made according to the printing width D designed in step (2). The metal paste is printed onto the blank dielectric layers 111 through the printing screen. After drying, a clear and complete ceramic dielectric film 110 is obtained. The results are shown in the figure. Figure 2 .

[0104] (4) Stack the ceramic dielectric film 110 and blank dielectric layer 111 prepared in step (3) along the target thickness T direction: First, stack multiple consecutive blank dielectric layers 111 to form a lower protective cover; then, stack multiple consecutive ceramic dielectric films 110 layer by layer on the lower protective cover with a certain stagger; finally, stack multiple consecutive blank dielectric layers 111 on the ceramic dielectric film 110 to form an upper protective cover, thereby obtaining a block with a uniform thickness. The planar dimensions of the block are 310 mm × 310 mm.

[0105] (5) The block is laminated and longitudinally and laterally cut according to the target length L and target width W to obtain 5808 chips; the size of the obtained chip in the width direction is equal to the target width W, and the size in the thickness direction is equal to the target thickness T.

[0106] (6) Perform the following processes in sequence: glue removal, sintering, chamfering, end sealing, end burning, electroplating, testing, external selection and FQC to obtain qualified MLCC product 100; then tape and package the MLCC product 100.

[0107] Test case The MLCC products prepared in the examples and comparative examples were tested as follows, and the results are shown in Table 1.

[0108] (1) Electrical performance: In accordance with the testing standards such as AEC-Q200-Rev E March 20, 2023 and GB / T 36651-2018, 100 samples were tested for electrical performance using a 4288A capacitor tester, an AN9642HS withstand voltage tester, and a 4339B high resistance tester to obtain electrical performance such as capacitance (Cap) and dielectric loss factor (DF). The equivalent series resistance (ESR) was measured using an E4990A impedance analyzer, and the average value was calculated as the final test result.

[0109] (2) Bending resistance: Bend at a speed of 1 mm / sec to the set value, hold for 60-65 seconds, and measure the electrical performance at bending times of 2 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm, 9 mm, and 10 mm respectively. If the electrical performance value is within the specified deviation, it is determined that the bending performance is met. Continue measuring up to 10 mm. If the electrical performance is not qualified when bending 5 mm, it is determined that the bending performance of 4 mm is met. If the electrical performance is qualified when bending 10 mm, the test is stopped and the bending performance of ≥10 mm is determined to be met.

[0110] (3) Acoustic quality: When the product is powered on on the PCB board, observe whether a whistling phenomenon occurs.

[0111] (4) Cost: Compared with the comparative example, in the stacking and lamination process of the embodiment, due to the increase in the number of chips obtained by cutting the block, the cost of materials and labor consumed by a single block can be allocated to more products, resulting in a 3% decrease in the total cost allocated to each product.

[0112] As shown in Table 1, compared with the comparative example, the MLCC product of the embodiment has the following advantages: The total number of inner electrode layers is significantly increased, that is, the number of stacked layers N in the stacking direction is significantly increased. This not only improves the bending strength and reliability of the product, but also increases the connection area between the inner and outer electrodes, making the end adhesion stronger, reducing the equivalent series resistance and dielectric loss of the product, and improving the high-frequency characteristics. The total number of chips that can be cut from a single block has been significantly increased, which can not only greatly increase the production capacity of a single batch, but also reduce the material cost, equipment time and labor cost per product, achieving the dual effect of cost reduction and efficiency improvement. The inner electrode layer is 100% perpendicular to the PCB board surface, which enhances the product's resistance to PCB board bending, reduces cracking caused by board bending, and effectively suppresses vertical vibration and howling caused by resonance with the PCB board, thus improving the product's acoustic quality.

[0113] Table 1. Performance Comparison of MLCC Products in Examples and Comparative Examples In summary, compared with the traditional structural design, for the thin MLCC product with the target width W greater than the target thickness T, this application adopts the design concept of dimension interchange, and interchanges the target thickness T in the traditional design as the stacking direction z and the target width W as the printing width direction of the inner electrode layer. Specifically: ① Stacking direction z: The target width W direction is used as the stacking direction z, so that the total size after stacking the blank dielectric layer and the ceramic dielectric film along this direction is equal to the target width W; ② Printing of the inner electrode layer: The printing width d of the inner electrode layer is set to the target thickness T minus the reserved margin, that is, d < T; ③ Cutting result: The bar block is cut according to the target length L and the target thickness T, so that the size of a single chip obtained in the direction perpendicular to the stacking direction z is equal to the target thickness T, and the size in the direction parallel to the stacking direction z is equal to the target width W. The MLCC product prepared in this way has the following advantages: (1) In the bar block cutting process, the arrangement density of the chips on the bar block depends on the size of the chips in the width direction y of the bar block and perpendicular to the stacking direction z. In this application, this size is equal to the target thickness T - which is the minimum value among the three dimensions of the product and is much smaller than the target width W which is the chip width direction size in the traditional design. Therefore, in the width direction y of the bar block, the number of rows of chips that can be arranged increases from about "bar block width ÷ W" to "bar block width ÷ T". Since T is much smaller than W, the number of chip rows increases significantly, resulting in a significant increase in the total number of chips that can be cut from the same bar block. This change directly leads to an increase in the production capacity per batch, and at the same time, the material cost, equipment working hours, and labor cost分摊 by a single product decrease as the number of chips increases, achieving the dual effects of cost reduction and efficiency improvement.

[0114] (2) This application uses the target width W direction as the stacking direction z. Since W is greater than the size T of the stacking direction z in the traditional design, with the single-layer dielectric thickness remaining basically unchanged, the required number of stacking layers N increases significantly. The increase in the number of stacking layers brings two effects: on the one hand, the inner electrode layer, as a metal material, is densely distributed in the ceramic matrix, forming more "toughening interlayers", which can effectively hinder the crack propagation, thus improving the bending strength and reliability of the product; on the other hand, more inner electrode layers are simultaneously connected to the outer electrodes at both ends, increasing the connection area between the inner and outer electrodes, making the end adhesion stronger, and at the same time reducing the equivalent series resistance and dielectric loss of the product, and the high-frequency characteristics are better.

[0115] (3) The MLCC product of this application is laid flat during tape making, so that its thickness direction is perpendicular to the bottom surface of the carrier tape and the thickness direction is perpendicular to the stacking direction z. When it is subsequently mounted on the PCB board, the inner electrode layer is 100% perpendicular to the PCB board surface. This not only enhances the product's resistance to PCB board bending and reduces cracking caused by board bending, but also ensures that the magnetic field generated by the product during power-on application is horizontal, effectively suppressing vertical vibration and howling caused by resonance with the PCB board, thus improving the acoustic quality of the product.

[0116] (4) Performance optimization for slender products: When the ratio of the target length L to the target thickness T of the product, L / T, is ≥1.6, the product exhibits slender geometric characteristics. This application optimizes the coverage R of the inner electrode layer (41% ≤ R ≤ 75%) and the printing width ratio d / T (0.76 ≤ d / T ≤ 0.92) to effectively improve the mechanical strength and bending resistance of slender products while ensuring capacitor performance, thus avoiding stress concentration or reliability degradation caused by improper inner electrode design.

[0117] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0118] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the appended claims.

Claims

1. A method for manufacturing an MLCC product, characterized in that, Includes the following steps: Obtain the target length L, target width W, and target thickness T of the MLCC product, wherein the target length L is greater than the target width W, and the target width W is greater than the target thickness T; Using the target width W direction as the stacking direction and the target thickness T as the design reference for the printing width d of the inner electrode layer, a ceramic dielectric film with the printing width d is prepared, and the printing width d is made smaller than the target thickness T. The ceramic dielectric film and the blank dielectric layer are stacked along the target width W direction to form a block; After laminating the block, it is cut according to the target length L and the target thickness T, so that the size of the obtained single chip in the direction perpendicular to the stacking direction is equal to the target length L and the target thickness T, respectively, and the size in the direction parallel to the stacking direction is equal to the target width W; The MLCC products are obtained by performing post-processing steps in sequence.

2. The method for manufacturing MLCC products as described in claim 1, characterized in that, When the ratio of the target length L to the target thickness T, L / T, is ≥ 1.6, the coverage R of the inner electrode layer on the ceramic dielectric film satisfies: 41% ≤ R ≤ 75%, where the coverage R = (inner electrode layer area) / (ceramic dielectric film area).

3. The method for manufacturing MLCC products as described in claim 1, characterized in that, When the ratio of the target length L to the target thickness T, L / T, is ≥ 1.6, then the ratio of the printing width d of the inner electrode layer to the target thickness T, d / T, satisfies: 0.76 ≤ d / T ≤ 0.

92.

4. The method for manufacturing the MLCC product as described in any one of claims 1 to 3, characterized in that, It also includes a tape-making process: placing the MLCC product flat in a carrier tape, such that the thickness direction of the MLCC product is perpendicular to the bottom surface of the carrier tape, wherein the thickness direction is perpendicular to the lamination direction.

5. The method for manufacturing the MLCC product as described in any one of claims 1 to 3, characterized in that, When stacking the ceramic dielectric films, each of the inner electrode layers is uniformly distributed in the stacking direction, and the spacing deviation between adjacent inner electrode layers is within ±10%.

6. The method for manufacturing the MLCC product according to any one of claims 1 to 3, characterized in that, The ratio of the target width W to the target thickness T ranges from W / T = 1.25 to 2.

95.

7. The method for manufacturing MLCC products as described in claim 6, characterized in that, The target width W ranges from 230μm to 270μm, and the target thickness T ranges from 180μm to 220μm.

8. The method for manufacturing the MLCC product as described in any one of claims 1 to 3, characterized in that, The number of chips obtained by cutting the block was 4.1 per cm. 2 ~ 4.93 pieces / cm 2 .

9. The method for manufacturing the MLCC product as described in any one of claims 1 to 3, characterized in that, The total number of inner electrode layers ranges from 340 to 395, and the target capacitance of the MLCC product ranges from 4.23 μF to 5.17 μF.

10. An MLCC product, characterized in that, It is manufactured using the manufacturing method of any one of claims 1 to 9 for MLCC products.

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