Semiconductor laser element and light emitting device

Abstract

The application relates to the technical field of semiconductor lasers, in particular to a semiconductor laser element and a light emitting device. The semiconductor laser element comprises a substrate and a semiconductor stack, and the semiconductor laser element is formed with a cavity surface at opposite ends in a first direction and has a first surface extending to both side cavity surfaces in the first direction and two side surfaces located on both sides of the first surface; at least part of the boundary between the first surface and at least one side surface is connected through a transition surface; the transition surface comprises a first transition surface extending in the first direction and connected with one end cavity surface, a second transition surface extending in the first direction and connected with the other end cavity surface, and a third transition surface located between the first transition surface and the second transition surface; a second direction is a thickness direction of the semiconductor laser element and is perpendicular to the first direction; the vertical heights of the first transition surface, the second transition surface and the third transition surface in the second direction are h1, h2 and h3 respectively; wherein h1 < h3, and / or h2 < h3.

Description

Technical Field

[0001] This invention relates to the field of semiconductor laser technology, and in particular to a semiconductor laser element and a light emitting device. Background Technology

[0002] Semiconductor lasers are light source devices widely used in communications, sensing, medical, and industrial processing. Their core working principle relies on the refractive index difference between the waveguide layer and the confinement layer in their internal structure to limit the lasing mode, thereby ensuring the stability of the laser's far-field spot characteristics and output power.

[0003] In traditional semiconductor laser design, the core structure includes a substrate and a semiconductor stack. Stress concentration occurs at the junction of the upper surface and the two side surfaces along the cavity length, which increases the probability of core chip cracking and skewing, and also significantly increases the proportion of edge and corner chipping, which seriously restricts the yield stability of mass production. Summary of the Invention

[0004] In view of at least one deficiency of the prior art, the purpose of this application is to provide a semiconductor laser element and a light emitting device that can improve the reliability of the semiconductor laser element.

[0005] In a first aspect, embodiments of this application provide a semiconductor laser element, the semiconductor laser element comprising at least a substrate and a semiconductor stack located on the substrate; The semiconductor laser element forms cavity surfaces at opposite ends along a first direction. The semiconductor laser element has a first surface extending along the first direction to both cavity surfaces, and two opposing side surfaces located on both sides of the first surface and extending along the first direction. The first surface is the other side of the semiconductor laser element surface opposite to the surface of the substrate facing away from the semiconductor stack. The side surfaces are located between the first surface and the surface of the substrate facing away from the semiconductor stack. At least a portion of the boundary between the first surface and at least one of the side surfaces is transitionally connected by a transition surface. The transition surface includes a first transition surface extending along the first direction and connecting one of the cavity surfaces, a second transition surface extending along the first direction and connecting the other cavity surface, and a third transition surface extending along the first direction and located between the first and second transition surfaces. The second direction is defined as a thickness direction perpendicular to the first direction. The vertical heights of the first, second, and third transition surfaces along the second direction are h1, h2, and h3, respectively. The vertical height is the distance between the edge of each transition surface that contacts the first surface and the edge that contacts the side surface along the second direction. Wherein, h1 < h3, and / or, h2 < h3.

[0006] Secondly, this application also provides a light emitting device, which employs a semiconductor laser element as described in the above embodiments.

[0007] Based on the above, compared with the prior art, the semiconductor laser element provided in this application can effectively improve the stability and reliability of the laser element by designing different transition surface heights.

[0008] Other features and beneficial effects of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing this application. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a perspective view of the semiconductor laser element provided in the embodiments of this application; Figure 2 This is a top view of the semiconductor laser element provided in the embodiments of this application; Figure 3 yes Figure 2 A sectional view of the central section line AA; Figure 4 yes Figure 2 A sectional view of the center section line BB; Figure 5 , Figure 6 Is with Figure 3 Cross-sectional views of different variations; Figure 7 It is a top view of multiple semiconductor laser elements having a cutting path along a first direction.

[0011] Figure label: 10-Substrate; 20-Semiconductor stack; 21-First semiconductor layer; 22-Active layer; 23-Second semiconductor layer; 30-Transition surface; 31-First transition surface; 32-Second transition surface; 33-Third transition surface; 40-Ridge; 51-First coating layer; 52-Second coating layer; 61-First electrode; 62-Second electrode; 70-Insulating layer; S1-Cavity surface; S2-First surface; S3-Side surface. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings; the technical features designed in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0013] It should also be noted that the dimensions and thicknesses in the accompanying drawings are merely examples and not intended to limit the specific technical solution of the present invention. The parameters such as length, width, height, thickness, and relative dimensional proportions between components presented in the drawings are only intended to more clearly and intuitively illustrate the structural composition, connection relationships, and working principle of the present invention, facilitating understanding of the inventive concept by those skilled in the art, and are not intended to limit the scope of protection of the present invention to the dimensions shown in the examples. In actual implementation of this application, the dimensions and thicknesses shown in the drawings can be reasonably adjusted, optimized, or replaced according to the needs of specific application scenarios. As long as such adjustments do not deviate from the technical principles and core inventive points disclosed in this application, they should all fall within the scope of protection of this application.

[0014] This application provides a semiconductor laser element, which includes at least a substrate 10 and a semiconductor stack 20 located on the substrate 10; the semiconductor laser element forms cavity surfaces S1 at opposite ends along a first direction, and has a first surface S2 extending along the first direction to both cavity surfaces S1, and two opposing side surfaces S3 located on both sides of the first surface S2 and extending along the first direction; the first surface S2 is a semiconductor laser element surface opposite to the surface of the substrate 10 facing away from the semiconductor stack 20; the side surfaces S3 are located between the first surface S2 and the surface of the substrate 10 facing away from the semiconductor stack 20; at least a partial boundary exists between the first surface S2 and at least one of the side surfaces S3. The transition surfaces are connected by a transition surface 30. The transition surface 30 includes a first transition surface 31 extending along a first direction and connecting one end cavity surface S1, a second transition surface 32 extending along the first direction and connecting the other end cavity surface S1, and a third transition surface 33 extending along the first direction and located between the first transition surface 31 and the second transition surface 32. The second direction is defined as the thickness direction of the semiconductor laser element and is perpendicular to the first direction. The vertical heights of the first transition surface 31, the second transition surface 32, and the third transition surface 33 along the second direction are h1, h2, and h3, respectively. The vertical height is the distance between the edge of each transition surface 30 that is in contact with the first surface S2 and the edge that is in contact with the side surface S3 along the second direction. Wherein, h1 < h3, and / or, h2 < h3.

[0015] Furthermore, the total thickness of the semiconductor laser element is defined as H, where h3 ≥ 2 / 5H.

[0016] Furthermore, h3 ≥ 30 μm.

[0017] Furthermore, h1≤5μm and / or h2≤5μm.

[0018] Furthermore, 0 < h1 / h3 ≤ 1 / 6, and / or 0 < h2 / h3 ≤ 1 / 6.

[0019] Further, the third direction is defined as a width direction perpendicular to the first direction and the second direction; the first transition surface 31 has a horizontal width w1 along the third direction, the second transition surface 32 has a horizontal width w2 along the third direction, and the third transition surface 33 has a horizontal width w3 along the third direction; wherein, w1 < w3, and / or, w2 < w3.

[0020] Furthermore, the first transition surface 31 and the second transition surface 32 have equal or unequal extension lengths along the first direction; the semiconductor laser element has a total length D along the first direction, the first transition surface 31 has a length d1 along the first direction, and the second transition surface 32 has a length d2 along the first direction; wherein, d1 > 0 and d1 ≤ 0.1D, d2 > 0 and d2 ≤ 0.1D.

[0021] Furthermore, the semiconductor stack 20 has a total length D along the first direction, and the third transition surface 33 has a length d3 along the first direction; wherein, d3 ≥ 0.8D and d3 < D.

[0022] Further, the semiconductor stack 20 includes a first semiconductor layer 21, an active layer 22, and a second semiconductor layer 23 sequentially stacked on the substrate 10 along a second direction; the first transition surface 31 extends from the first surface S2 along the second direction toward the substrate 10 side but does not extend to the active layer 22; and / or, the second transition surface 32 extends from the first surface S2 along the second direction toward the substrate 10 side but does not extend to the active layer 22.

[0023] Furthermore, the third transition surface 33 extends from the first surface S2 across the active layer 22 and connects to the side surface S3 located below the active layer 22 on the side facing the substrate 10.

[0024] Furthermore, the transition surface 30 is an inclined surface, a curved surface, or a combination thereof that continuously connects the first surface S2 and the side surface S3.

[0025] Further, the third direction is defined as the width direction perpendicular to the first direction and the second direction; on the first surface S2, the first transition surfaces 31 located on opposite sides of the side surfaces S3 have a maximum horizontal distance L1 along the third direction, the second transition surfaces 32 located on opposite sides of the side surfaces S3 have a maximum horizontal distance L2 along the third direction, and the third transition surfaces 33 located on opposite sides of the side surfaces S3 have a maximum horizontal distance L3 along the third direction; wherein, L1 > L3, and / or, L2 > L3.

[0026] Furthermore, the semiconductor laser element further includes a first film layer and a second film layer; the first film layer is disposed at the cavity surface S1 on the side near the first transition surface 31, and the second film layer is disposed at the other cavity surface S1 on the side near the second transition surface 32; the first film layer includes at least a high reflectivity layer; and the second film layer includes at least an antireflection layer.

[0027] Further, the first surface S2 extends to the upper surfaces of the first film layer and the second film layer; the side surface S3 extends to the sidewalls of the first film layer and the second film layer; the first transition surface 31 extends from the boundary between the first surface S2 and the side surface S3 of the semiconductor stack 20 along a first direction to the boundary between the upper surface of the first film layer and the sidewall; the second transition surface 32 extends from the boundary between the first surface S2 and the side surface S3 of the semiconductor stack 20 along a first direction to the boundary between the upper surface of the second film layer and the sidewall.

[0028] Furthermore, the boundary between the upper surface of the first membrane layer and its sidewall has only a first transition surface 31, and the boundary between the upper surface of the second membrane layer and its sidewall has only a second transition surface 32.

[0029] Furthermore, the semiconductor laser element further includes: a ridge 40 located on a first surface S2 and extending out of the first surface S2 along a first direction; an insulating layer 70 covering a portion of the ridge 40 and extending to at least a portion of the first surface S2; a first electrode 61 covering the insulating layer 70 and electrically connected to the ridge 40; and a second electrode 62 located on the surface of the substrate 10 opposite to the semiconductor stack 20.

[0030] Furthermore, the total length D of the semiconductor laser element along the first direction and the total width W along the third direction satisfy: D / W≥1.5.

[0031] This application also provides a light emitting device that employs a semiconductor laser element as described in any of the above embodiments to effectively improve the photoelectric performance of the light emitting device.

[0032] The technical solution of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application and through various specific implementation methods.

[0033] Example 1 Please see Figure 1 , Figure 1 This is a perspective view of a semiconductor laser element provided in an embodiment of this application. To achieve at least one or more of the aforementioned advantages, the semiconductor laser element provided in Embodiment 1 of this application includes at least a substrate 10 and a semiconductor stack 20 located on the substrate 10.

[0034] The substrate 10 includes, but is not limited to, gallium nitride substrates, gallium arsenide substrates, sapphire substrates, silicon carbide substrates, etc. In this embodiment, the substrate 10 can be a growth substrate or a support substrate. The thickness of the substrate 10 is, for example, at least 40 μm and / or at most 400 μm, preferably 50 μm, 60 μm, 80 μm, 100 μm, 120 μm, and 150 μm.

[0035] Furthermore, the upper and lower positions mentioned above in this specification are defined by the position of the substrate 10. It is assumed that the direction closer to the substrate 10 is lower, and the direction extending away from the substrate 10 and towards the semiconductor stack 20 is upper. The upper and lower position settings in this specification are only for illustrating the positional relationship of the components in the illustrated embodiments and do not represent an indication or imply that they must have a specific orientation.

[0036] The semiconductor stack 20 is located on the substrate 10. In this embodiment, the semiconductor stack 20 can be formed on the substrate 10 by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD), or ion plating. In this embodiment, the semiconductor stack 20 is preferably made of GaN-based semiconductor material.

[0037] The semiconductor stack 20 includes at least a first semiconductor layer 21, an active layer 22, and a second semiconductor layer 23 sequentially stacked on the substrate 10. The first semiconductor layer 21 is disposed between the active layer 22 and the substrate 10, and the second semiconductor layer 23 is disposed on the side of the active layer 22 facing away from the substrate 10. In this embodiment, the first semiconductor layer 21 may include, but is not limited to, a first confinement layer, a first waveguide layer, and a buffer layer (not shown in the figure), and the second semiconductor layer 23 may include, but is not limited to, a second waveguide, a second confinement layer, an electron blocking layer (not shown in the figure), and a contact layer (not shown in the figure). Specific functional layers should be reasonably configured according to actual needs; this embodiment does not impose any limitations on this.

[0038] The first confinement layer is an N-type doped material, used to confine the light field in the direction towards the substrate 10; the second confinement layer is a P-type doped material, used to confine the light field in the direction away from the substrate 10. The first waveguide layer is an N-type doped material and the second waveguide layer is a P-type doped material, used to increase the confinement of charge carriers, increase the distribution of charge carriers in the active layer 22, improve the light confinement factor, reduce the threshold current, and improve the luminous efficiency. Preferably, the first waveguide layer, the second waveguide layer, the first confinement layer, and the second confinement layer are any one or any combination of GaN, InGaN, InN, AlInN, AlGaN, AlInGaN, AlN, GaAs, GaP, InP, AlGaAs, AlInGaAs, AlGaInP, InGaAs, InGaAsN, AlInAs, AlInP, AlGaP, InGaP, GaSb, InSb, InAs, InAsSb, AlGaSb, AlSb, InGaSb, AlGaAsSb, InGaAsSb, SiC, Ga2O3, and BN.

[0039] The active layer 22 can be a single quantum well layer composed of indium gallium nitride / gallium nitride, or a multiple quantum well layer composed of indium gallium nitride / gallium nitride grown in multiple alternating periods, to provide optical gain.

[0040] Furthermore, the semiconductor laser element forms cavity surfaces S1 at opposite ends along a first direction. The first direction is the length direction of the resonant cavity of the semiconductor laser element (i.e., the direction of the laser lasing propagation axis, such as...). Figure 1 , Figure 2 (As indicated by the arrow), cavity surface S1 is the core functional surface for laser reflection, oscillation, and final output, located at both ends of the element along the first direction. Meanwhile, the second direction is defined as the thickness direction of the semiconductor laser element, and is perpendicular to the first direction (e.g., ...). Figure 1 , Figure 3 (As indicated by the arrow), the third direction is the width direction perpendicular to the first and second directions (i.e., the horizontal width direction of the semiconductor laser element perpendicular to the first direction, such as...). Figure 1 As shown in the figure, the three form an orthogonal three-dimensional coordinate system.

[0041] In this embodiment, the semiconductor laser element has a first surface S2 extending along a first direction to both cavity surfaces S1, and two opposing side surfaces S3 located on both sides of the first surface S2 and extending along the first direction; the first surface S2 is the other side of the semiconductor laser element surface opposite to the surface of the substrate 10 facing away from the semiconductor stack 20; it should be noted that the first surface S2, as the other side of the semiconductor laser element opposite to the surface of the substrate 10 facing away from the semiconductor stack 20, can be specifically set according to the actual product structure of the semiconductor laser element, and includes, but is not limited to, the following: Figure 3 As shown, the first surface S2 is the surface of the semiconductor stack 20 on the side of the semiconductor stack 20 facing away from the substrate 10, such as... Figure 5 In the diagram, the first surface S2 is the upper surface of the insulating layer 70 covering the semiconductor stack 20, or as shown... Figure 6 The first surface S2 shown is the surface of the region on the substrate 10 that is not covered by the epitaxial structure. As long as it is the surface of the element opposite to the side of the substrate 10 that is away from the semiconductor stack 20, it falls within the protection scope of the first surface S2 as defined in this application.

[0042] The side surface S3 is located between the first surface S2 and the surface of the substrate 10 facing away from the semiconductor stack 20; the side surface S3 is a cut side surface formed by cutting and separating adjacent semiconductor laser elements along the cutting path, i.e. Figure 7 When the cutting path is divided along the first direction as shown, the longitudinal side surfaces formed on both sides of the long side of a single semiconductor laser element are connected to the cavity surface S1 along the first direction and penetrate the entire thickness of the element along the second direction, forming the long side dimension boundary of the element.

[0043] The semiconductor laser element also includes a ridge 40 located on the first surface S2 and extending beyond the first surface S2 along a first direction. That is, the ridge 40 is a raised structure on the first surface S2, its extension direction is consistent with the first direction (the direction of the resonant cavity length), and its height is higher than the first surface S2. Its core function is to confine lateral charge carriers and the optical field, thereby improving the luminous efficiency and beam quality of the device. The extension range of the ridge 40 does not exceed the boundary of the first surface S2 along the first direction (i.e., it does not cross the two end cavity surfaces S1), and its width along the third direction is less than the lateral width of the first surface S2. In this embodiment, the ridge 40 is formed using an ICP etching process.

[0044] The semiconductor laser element further includes an insulating layer 70, which covers a portion of the ridge 40 and extends to at least a portion of the first surface S2; the insulating layer 70 has an opening formed on the upper surface of the ridge 40. The insulating layer 70 is preferably made of SiO2, Si3N4, or Al2O3, and the opening precisely exposes the electrical contact area of ​​the ridge 40, ensuring effective electrical connection between the electrode and the ridge 40.

[0045] The semiconductor laser element also includes a first electrode 61 located on the side of the semiconductor stack 20 away from the substrate 10 and a second electrode 62 located on the side of the substrate 10 away from the semiconductor stack 20. The first electrode 61 is electrically connected to the second semiconductor layer 23, and the second electrode 62 is electrically connected to the first semiconductor layer 21. Simultaneously, the first electrode 61 and the second electrode 62 are typically made of metal and electrically connected to the outside environment to control the conduction of the semiconductor laser.

[0046] In traditional semiconductor laser device design, a "back-grinding and front-splitting" dicing process is commonly used to divide the core. This involves first laser-grinding the back of the substrate and then mechanically splitting the semiconductor stack from the front. The transition boundary between the first surface and the side surface of the device in this process is a single sharp junction. This design has several inherent drawbacks: First, the stress concentration effect is significant. GaN material itself is brittle, and the stress generated during the dicing and splitting process tends to accumulate at sharp edges and corners, causing cracks to propagate along the side surface, resulting in chipping and corner breakage. In particular, chipping and corner breakage near the cavity surface can directly destroy the integrity of the cavity surface, leading to lasing aging failure. Second, the miniaturization adaptability of the core is poor. As the aspect ratio of the core increases and the channel size decreases, the existing structure cannot release the stress in the narrow space, and the probability of core dicing deviation increases significantly.

[0047] To effectively resolve the above issues, please refer to [link / reference]. Figures 1-3 In this embodiment, at least a portion of the boundary between the first surface S2 and at least one of the side surfaces S3 is transitionally connected by a transition surface 30; the transition surface 30 includes a first transition surface 31 extending along a first direction and connecting one of the end cavity surfaces S1, a second transition surface 32 extending along a first direction and connecting the other end cavity surface S1, and a third transition surface 33 extending along a first direction and located between the first transition surface 31 and the second transition surface 32.

[0048] Specifically, the transition surface 30 can replace the sharp boundary structure between the first surface and the side surface in a traditional semiconductor laser element. By dispersing stress concentration through a continuously connected transition shape, it avoids crack initiation and propagation. Here, "at least a partial boundary between the first surface S2 and at least one of the side surfaces S3" means that the transition surface 30 can be set only at a partial or complete boundary between the first surface S2 and a single side surface S3, or simultaneously at a partial or complete boundary between the first surface S2 and two opposite side surfaces S3, depending on the actual stress distribution requirements.

[0049] The first transition surface 31 and the second transition surface 32 extend along the first direction, with their ends directly adjacent to the two end cavity surfaces S1 of the semiconductor laser element, forming a smooth transition connection from the cavity surface S1 to the side surface S3 and the first surface S2. Here, "connection" does not mean that the transition surface 30 covers or embeds into the cavity surface S1, but rather that the end of the transition surface 30 is flush with or adjacent to the edge of the cavity surface S1, ensuring that the integrity of the cavity surface S1 and the laser oscillation function are not affected. The third transition surface 33 also extends along the first direction, and its extension range along the first direction is between the first transition surface 31 and the second transition surface 32. The three are arranged sequentially in the first direction, covering the boundary area between the first surface S2 and the side surface S3, forming a segmented transition structure. Preferably, the transition surface 30 is a slope, curved surface, or a combination thereof that continuously connects the first surface S2 and the side surface S3, avoiding stress concentration caused by traditional sharp corners or discontinuous boundaries.

[0050] Similarly, the location of the boundary region between the first surface S2 and the side surface S3 is set according to the structural requirements of the actual product, for example, in the following cases: the first case can be formed in such a way as Figure 3 The location shown is specifically the surface of the semiconductor stack 20 facing away from the substrate 10. This surface is the native upper surface of the semiconductor stack 20, and the insulating layer 70 does not cover this boundary region. That is, the edge of the insulating layer 70 maintains a certain distance from the boundary region and does not extend to the intersection of the first surface S2 and the side surface S3. This surface intersects with the side surface S3 of the semiconductor stack 20 along the first direction. In this case, the boundary region is formed only by the connection between the upper surface of the semiconductor stack 20 and the side surface S3, without the participation of the insulating layer 70. The second scenario can be formed in, as shown in... Figure 5 The location shown is specifically the upper surface of the insulating layer 70, which covers the boundary region, that is, the insulating layer 70 extends to the side edge of the semiconductor laser element. This upper surface intersects with the side surface S3 of the semiconductor laser element, which is parallel to the first direction. In this case, the boundary region is formed by the connection between the upper surface of the insulating layer 70 and the side surface S3 of the element, and the insulating layer 70 becomes part of the boundary region. The third scenario can be formed in... Figure 6 The location shown is specifically the surface of the substrate 10 near the semiconductor stack 20. This surface is a partial exposed surface of the substrate 10. Part of the semiconductor stack 20 in the edge region of the substrate 10 has been removed, so that this part of the surface of the substrate 10 is exposed from below the semiconductor stack 20. This surface intersects with the side surface S3 of the substrate 10 along the first direction. At this time, the boundary region is formed by the connection between the exposed surface of the substrate 10 and the side surface S3 of the substrate 10. The semiconductor stack 20 does not cover the boundary region.

[0051] Among them, such as Figure 1 , Figure 3As shown, the vertical heights of the first transition surface 31, the second transition surface 32, and the third transition surface 33 along the second direction are h1, h2, and h3, respectively. The vertical height is the distance between the edge of each transition surface 30 that is in contact with the first surface S2 and the edge that is in contact with the side surface S3 along the second direction. In this embodiment, h1 < h3, and / or h2 < h3.

[0052] In specific implementation, the first transition surface 31 and the second transition surface 32 are close to the two end cavity surfaces S1 of the semiconductor laser element. Their relatively small vertical heights h1 and h2 can form a gentle stress buffer region near the cavity surface S1. This region can effectively absorb the local stress generated during laser cleaving and subsequent processes, avoiding stress concentration at the edge of the cavity surface S1, thereby reducing the risk of edge chipping and corner breakage of the cavity surface S1 due to stress impact. At the same time, it prevents the cleaving energy from being conducted to the cavity surface S1, causing film damage or optical catastrophic damage (COD). The third transition surface 33 is located in the middle region of the element. Its larger vertical height h3 can provide sufficient cleavage guiding force to guide the cleaving cracks to propagate along a preset path, counteracting the inherent 60° natural cleavage surface characteristics of the substrate 10, avoiding cleavage distortion or back breakage of the core particles, and ensuring the structural integrity of the element after segmentation.

[0053] Meanwhile, the above arrangement ensures that the third transition surface 33, which has a deeper vertical height h3, does not extend to the cavity surface S1. Instead, the first transition surface 31 and the second transition surface 32, which have shallower vertical heights h1 and h2, extend to the cavity surface S1. This design can effectively avoid directly damaging the structural integrity of the cavity surface S1 region and causing edge defects in the cavity surface S1. It can also prevent the shearing stress from being directly transmitted to the cavity surface S1, reducing the risk of damage to the cavity surface S1, thereby reducing the probability of device lasing aging failure and optical catastrophic damage (COD).

[0054] In one embodiment, the total thickness of the semiconductor laser element is defined as H, then the vertical height h3 of the third transition surface 33 satisfies: h3 ≥ 2 / 5H. Wherein, as... Figure 4 As shown, the total thickness H of the semiconductor laser element is the height distance along the second direction (thickness direction) from the farthest point below the semiconductor laser element to the farthest point above the semiconductor laser element. Since the substrate 10 has an inherent 60° natural cleavage plane, if the vertical height h3 of the third transition surface 33 is less than 2 / 5 of the total thickness, the cleavage guiding force it provides will be less than the force of the natural cleavage plane, easily leading to backscraping or skewing during the core chip cleaving process due to insufficient guidance. However, if h3 ≥ 2 / 5H, a stable cleavage guiding path can be formed, forcing the crack to propagate along a preset direction, thus suppressing structural damage caused by disordered cracks at the source. For example, h3 ≥ 30μm, such as h3 being 30μm, 40μm, 50μm, 60μm, 70μm, etc.

[0055] Preferably, 0 < h1 / h3 ≤ 1 / 6, and / or 0 < h2 / h3 ≤ 1 / 6. For example, h1 / h3 and h2 / h3 are 1 / 6, 1 / 8, 1 / 9, 1 / 10, 1 / 12, 1 / 15, 1 / 16, 1 / 18, 1 / 20, etc. This ratio limitation is a further optimization of h1 < h3 and h2 < h3. By adjusting the vertical height ratio of each transition surface 30, h1 and h2 are always kept within a sufficiently small range relative to h3, avoiding the problem of weakened buffering effect or insufficient guiding function due to excessive differences in the values ​​of h1, h2, and h3. At the same time, the limitation that the ratio is greater than 0 ensures that the first and second transition surfaces 32 will not lose their buffering function due to a height of 0, avoiding the structural defects of reverting to a traditional single sharp boundary. As an example, h1 ≤ 5μm and / or h2 ≤ 5μm. For example, h1 and h2 can be 1μm, 2μm, 3μm, 4μm, 5μm, etc., and their specific values ​​can be flexibly adjusted according to the total thickness H of the component, the position of the active layer 22, and the laser scribing energy parameters. Of course, h1 and h2 can satisfy h1=h2 or h1≠h2, which is not limited in this embodiment. If h1 and h2 are greater than 5μm, the scribing stress is easily transmitted to the cavity surface S1, and when laser scribing is used, the surface scribing laser energy will damage the cavity surface S1, causing changes in the cavity surface S1 film layer, which may ultimately lead to the risk of optical catastrophic damage (COD).

[0056] Through the above-mentioned segmented transition surface 30 design, the junction area between the first surface S2 and the side surface S3 can be transformed from a single sharp corner into a multi-segment smooth transition structure, effectively dispersing the stress generated during dicing, packaging and use, suppressing edge and corner chipping from the root, and avoiding damage to the cavity surface S1 caused by stress transmission, reducing the risk of COD, and ensuring the structural stability and lasing reliability of the device.

[0057] Optionally, the first transition surface 31 has a horizontal width w1 along a third direction, the second transition surface 32 has a horizontal width w2 along a third direction, and the third transition surface 33 has a horizontal width w3 along a third direction; wherein w1 < w3, and / or w2 < w3.

[0058] In specific implementation, the first transition surface 31 and the second transition surface 32 are close to the cavity surface S1. The core is to form a local stress buffer at the edge of the cavity surface S1. If the horizontal width is too wide, the shallow cleaving area will occupy too much space near the cavity surface S1, which may cause the cleaving energy to be conducted to the cavity surface S1 or interfere with the optical field distribution near the cavity surface S1. Smaller w1 and w2 can ensure the buffering effect while precisely controlling the shallow cleaving range, avoiding adverse effects on the performance of the cavity surface S1. The third transition surface 33 is located in the middle of the device and is the core structure of cleavage guidance. The wider w3 can make the contact width range of the transition surface 30 larger, providing a more stable cleavage guidance force, while expanding the stress dispersion area, effectively counteracting the natural cleavage characteristics of the substrate 10 and avoiding core chip cracking and skewing.

[0059] As an example, w3≤15, w1≤5, w2≤5. Among these, w1 and w2≤5μm can strictly control the lateral influence range of the shallow cut, avoiding interference with structures such as the ridge 40 and insulating layer 70, while also preventing damage to the cavity surface S1 film layer caused by concentrated energy from the shallow cut. w3≤15μm is particularly suitable for the lateral space constraints of small-sized chips (especially narrow-width chips with an aspect ratio >2), preventing the transition surface 30 from becoming too wide, which would increase the overall width of the device and affect integration density. The values ​​of w1 and w2 can be the same or different, without affecting the stress buffering effect.

[0060] In one embodiment, the first transition surface 31 and the second transition surface 32 have equal or unequal extension lengths along the first direction; the semiconductor laser element has a total length D along the first direction, the first transition surface 31 has a length d1 along the first direction, and the second transition surface 32 has a length d2 along the first direction; wherein, d1 > 0 and d1 ≤ 0.1D, d2 > 0 and d2 ≤ 0.1D.

[0061] In specific implementation, the first direction is the length direction of the resonant cavity of the semiconductor laser element, such as... Figure 2 As shown, the total length D is the complete dimension of the component along this direction from one end cavity surface S1 to the other end cavity surface S1. d1 and d2 are the extension ranges of the first transition surface 31 and the second transition surface 32 along this direction, respectively. By limiting d1 ≤ 0.1D and d2 ≤ 0.1D, the first transition surface 31 and the second transition surface 32 are prevented from extending excessively towards the middle of the component, thus reserving a continuous and sufficient cleavage guidance range for the third transition surface 33. In practical applications, d1 and d2 can be chosen to be equal or unequal according to the device design requirements.

[0062] In another embodiment, the third transition surface 33 has a length d3 along the first direction; that is, d3 is the extension range of the third transition surface 33 along the first direction. Wherein, d3 ≥ 0.8D and d3 < D. If d3 < 0.8D, the coverage of the third transition surface 33 is insufficient, the middle region lacks effective guidance, and is easily interfered with by the 1060° natural cleavage plane of the substrate, leading to crack propagation deviation and causing core particle scratching, skewing, or back-breakage; while when d3 ≥ 0.8D, it can guide the main body region of the component, forcing the crack to extend along the preset direction of the transition surface 30, ensuring the regularity of the segmented core particle structure.

[0063] Optionally, the first transition surface 31 extends from the first surface S2 along the second direction toward the substrate 10 but does not extend to the active layer 22; and / or, the second transition surface 32 extends from the first surface S2 along the second direction toward the substrate 10 but does not extend to the active layer 22. That is, when the first transition surface 31 and the second transition surface 32 extend from the first surface S2 along the second direction toward the substrate 10, their termination positions are both on the side of the active layer 22 away from the substrate 10 (e.g., Figure 3 As shown, it terminates above the active layer 22 and does not remain on the sidewall of the active layer 22 or extend downward beyond the active layer 22.

[0064] In practice, if the first transition surface 31 or the second transition surface 32 extends excessively to the active layer 22, it will directly disrupt the electrical isolation between the active layer 22 and the lower first semiconductor layer 21 and the upper second semiconductor layer 23, and may form an additional conductive path in the transition surface 30 region, causing the risk of infrared (IR) conduction.

[0065] Optionally, such as Figure 3 As shown, the third transition surface 33 extends from the first surface S2 beyond the active layer 22 and connects with the side surface S3 located below the active layer 22 on the side facing the substrate 10. That is, the third transition surface 33 extends from the first surface S2 toward the substrate 10, extending beyond the active layer 22, and finally connects with the side surface S3; the side surface S3 is located in the region below the active layer 22 near the substrate 10, thereby forming a continuous scribing guide structure.

[0066] In practical implementation, if the third transition surface 33 does not extend beyond the active layer 22, its extension depth is limited, and the cleavage guiding force it provides is insufficient to counteract the inherent 60° natural cleavage plane force of the substrate 10. When the core particle is scratched, it is easy to deviate (skew) along the natural cleavage plane or cause backscrambling on the substrate 10 side. Therefore, in this embodiment, it is preferable that the third transition surface 33 extends from the first surface S2 beyond the active layer 22.

[0067] Preferably, such as Figure 2As shown, on the first surface S2, the first transition surfaces 31 located on opposite sides of the side surfaces S3 have a maximum horizontal distance L1 along a third direction, the second transition surfaces 32 located on opposite sides of the side surfaces S3 have a maximum horizontal distance L2 along a third direction, and the third transition surfaces 33 located on opposite sides of the side surfaces S3 have a maximum horizontal distance L3 along a third direction; wherein, L1 > L3, and / or, L2 > L3.

[0068] In specific implementation, L1, L2, and L3 are all lateral spacing parameters on the first surface S2. "The two side surfaces S3" refer to the two longitudinal side surfaces distributed along a third direction on both sides of the first surface S2. Figure 1 , Figure 2 As shown, both side surfaces S3 have a first transition surface 31, a second transition surface 32, and a third transition surface 33. The maximum horizontal distance L1 refers to the maximum distance between the first transition surface 31 on the opposite side surfaces S3 and the edge connecting to the first surface S2 in the third direction; the maximum horizontal distance L2 refers to the maximum distance between the second transition surface 32 on the opposite side surfaces S3 and the edge connecting to the first surface S2 in the third direction; and the maximum horizontal distance L3 refers to the maximum distance between the third transition surface 33 on the opposite side surfaces S3 and the edge connecting to the first surface S2 in the third direction. By limiting L1 > L3 and / or L2 > L3, the essence is to further optimize stress dispersion and cleavage guidance effects through the differentiated design of the lateral spacing on the first surface S2, in conjunction with the vertical height and horizontal width of the transition surface 30.

[0069] Traditional semiconductor laser chip dicing processes generally employ a single dicing mode of "back-dicing and front-splitting," where laser dicing is first performed on the back side of the substrate 10, followed by mechanical splitting on the front side of the semiconductor stack 20. This process cannot create a differentiated transition surface 30 for the corresponding components, and the stress concentration problem remains unresolved. Furthermore, this single dicing method is highly prone to edge chipping and corner breakage. Especially when edge chipping and corner breakage occur on the cavity surface S1, it can easily damage the cavity surface S1, leading to failure during lasing aging. Particularly in scenarios where the chip size is constantly decreasing, the size of the dicing channels between adjacent laser components is also shrinking. If the aforementioned traditional design is still used, the chips within the narrow channels are susceptible to mechanical interference from adjacent chips, resulting in edge damage and severely restricting mass production yield.

[0070] Therefore, in order to effectively achieve the design of the differentiated transition surface 30 to suppress crack propagation and curb edge and corner chipping, this embodiment innovatively utilizes laser scribing or etching processes to obtain the above structure, addressing the limitations of existing processes. For example, the first transition surface 31 and the second transition surface 32 are formed by laser scribing or ICP etching, and the third transition surface 33 is formed by laser scribing. The scribing depth of the third transition surface 33 is greater than the scribing depth or etching depth of the second transition surface 32 and the first transition surface 31, thus obtaining the differentiated transition surface 30.

[0071] Specifically, laser scribing refers to the process of scanning the long side of a semiconductor laser element along a first direction with a laser beam to form a first transition surface 31, a second transition surface 32, or a third transition surface 33. The specific scribing depth can be obtained by adjusting the energy and spot size to form a suitable laser beam. Similarly, the ICP etching process can precisely control the etching depth and lateral dimensions of the first transition surface 31 and the second transition surface 32 by adjusting parameters such as etching power and etching time, ensuring a clear depth difference with the third transition surface 33 formed by laser scribing, while avoiding damage to the core functional areas of the device. The above processes utilize SEM to detect the height and shape of the transition surface 30, ensuring the structural requirements of h1 < h3 and h2 < h3.

[0072] Through the above process design, not only can the vertical height relationship of the three transition surfaces 30 be precisely controlled, but the synergistic effect of laser scribing / ICP etching can also counteract the natural cleavage characteristics of the substrate 10, preventing chip skewing, tilting, and back breakage. Simultaneously, the first transition surface 31 and the second transition surface 32 employ a low-energy design with shallow scribing or low-power ICP etching, effectively protecting the cavity surface S1 and the active layer 22, preventing film damage and light field leakage caused by excessive energy. The third transition surface 33 employs a deep scribing design with precise control of the cut-off position, reducing energy dispersion near the cavity surface S1, further alleviating stress concentration, and effectively curbing edge and corner breakage. Especially for small-sized chips with an aspect ratio greater than or equal to 1.5, this process enables precise control of the transition surface 30 structure, avoiding the defects of traditional single scribing processes, and providing process assurance for improved device aging performance.

[0073] Therefore, based on the above, such as Figure 2As shown, in this embodiment, the total length D of the semiconductor laser element along the first direction and the total width W along the third direction preferably satisfy: D / W ≥ 1.5, for example, D / W is 1.5, 1.6, 1.8, 2.0, 2.2, 2.4, 2.5, 2.6, 2.8, 3.0, etc. This aspect ratio limitation can meet the current development requirements of semiconductor laser elements for "small size and high integration". In particular, when D / W ≥ 1.5, the core extends longer along the first direction and is narrower along the third direction (i.e., the width direction of the semiconductor laser element). The defects of the traditional single transition surface 30 design and "back-splitting and front-splitting" process are significantly amplified. However, the differential design of the transition surface 30 in this embodiment can fundamentally solve the core technical pain points of using traditional structures and scribing processes for large aspect ratio cores.

[0074] Example 2 Based on Example 1, such as Figure 4 As shown, the semiconductor laser element also includes a first coating layer 51 and a second coating layer 52 located on both sides of the cavity surface S1. The first coating layer 51 includes at least a high-reflectivity coating (HR), and the second coating layer 52 includes at least an antireflection coating (AR). The high-reflectivity coating is mainly used to reflect light within the laser element to form effective optical feedback, maintain laser oscillation, effectively increase the light intensity within the cavity, and improve output power. The antireflection coating is mainly used to reduce surface reflection at the laser output end face, effectively reduce mode competition and power loss within the laser, improve the laser output power, and also protect the end face from contamination and physical damage. As an example, the material of the high-reflectivity coating includes, but is not limited to, Ag, Au, Al, or other semiconductor materials such as GaAs, AlAs, etc., and can be a multilayer structure or a single-layer structure. The material of the antireflection coating includes, but is not limited to, silicon dioxide, titanium dioxide, silicon nitride, magnesium fluoride, etc. In this embodiment, the high-reflectivity coating is preferably a multi-period structure containing aluminum oxide and tantalum oxide, and the antireflection coating is a single-period structure containing aluminum nitride and aluminum oxide. Of course, the first coating layer 51 and the second coating layer 52 may also include functional layer structures such as a confinement layer, a contact layer, a protective layer, a wavelength selective layer, and an anti-corrosion layer (not shown in the figure). The specific design is based on actual needs, and this embodiment is not limited thereto.

[0075] In this embodiment, the first surface S2 extends to the upper surfaces of the first film layer and the second film layer; the side surface S3 extends to the sidewalls of the first film layer and the second film layer; the first transition surface 31 extends from the boundary between the first surface S2 and the side surface S3 of the semiconductor stack 20 along a first direction to the boundary between the upper surface of the first film layer and the sidewall; the second transition surface 32 extends from the boundary between the first surface S2 and the side surface S3 of the semiconductor stack 20 along a first direction to the boundary between the upper surface of the second film layer and the sidewall.

[0076] In specific implementation, the first surface S2 is a continuous interface, which includes the surface above the semiconductor stack 20 (this surface is the upper surface of the semiconductor stack 20 or the upper surface of the insulating layer 70 covering the semiconductor stack 20) ​​and the upper surface of the first film layer and the upper surface of the second film layer; the second surface is a continuous interface, which includes the sidewall of the semiconductor stack 20 and the sidewall of the first film layer and the sidewall of the second film layer. In this embodiment, the first transition surface 31 is preferably located in the partial boundary region between the surface above the semiconductor stack 20 and the sidewall of the semiconductor stack 20, and in the partial or complete boundary region between the upper surface of the first film layer and the sidewall of the first film layer; the second transition surface 32 is located in the partial boundary region between the surface above the semiconductor stack 20 and the sidewall of the semiconductor stack 20, and in the partial or complete boundary region between the upper surface of the second film layer and the sidewall of the second film layer.

[0077] Through the above settings, the first transition surface 31 and the second transition surface 32 can form a smooth transition with the junction area of ​​the semiconductor stack 20, the first film layer and the second film layer, eliminating the sharp corners at the junction of the semiconductor stack 20 and the corresponding film layer, fundamentally avoiding the stress concentration problem at the interface of different layers, and preventing film cracking and delamination caused by stress.

[0078] Preferably, the boundary between the upper surface of the first film layer and its sidewall has only a first transition surface 31, and the boundary between the upper surface of the second film layer and its sidewall has only a second transition surface 32. That is, a third transition surface 33 is not formed at the boundary between the upper surface of the first film layer and its sidewall, and a third transition surface 33 is not formed at the boundary between the upper surface of the second film layer and its sidewall.

[0079] This design ensures that the third transition surface 33 does not extend to the first and second membrane layers, effectively preventing the corner areas of the first and second membrane layers from experiencing excessive stress due to the greater vertical height of the third transition surface 33, which could lead to cracking, defects, or delamination. This safeguards the structural integrity of the membrane layers themselves and prevents stress from being transmitted to the cavity surface S1 on the outer side of the first and second membrane layers.

[0080] Example 3 This application also provides a light emitting device, which includes at least one semiconductor laser element as described in any of the above embodiments, which can effectively improve the light emission performance and can be applied to light emitting devices using semiconductor laser elements in various industries.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor laser element, characterized in that: The semiconductor laser element includes a substrate and a semiconductor stack on the substrate; The semiconductor laser element forms cavity surfaces at opposite ends along a first direction. The semiconductor laser element has a first surface extending along the first direction to both cavity surfaces, and two opposite side surfaces located on both sides of the first surface and extending along the first direction. The first surface is the other side of the semiconductor laser element surface opposite to the surface of the substrate away from the semiconductor stack. The side surface is located between the first surface and the surface of the substrate on the side away from the semiconductor stack; At least a portion of the boundary between the first surface and at least one of the side surfaces is transitionally connected by a transition surface; the transition surface includes a first transition surface extending along a first direction and connecting one of the end cavity surfaces, a second transition surface extending along the first direction and connecting the other end cavity surface, and a third transition surface extending along the first direction and located between the first transition surface and the second transition surface. The second direction is defined as the thickness direction of the semiconductor laser element and is perpendicular to the first direction; the vertical heights of the first transition surface, the second transition surface, and the third transition surface along the second direction are h1, h2, and h3, respectively, and the vertical height is the distance between the edge of each transition surface that is in contact with the first surface and the edge that is in contact with the side surface along the second direction; wherein, h1 < h3, and / or, h2 < h3.

2. The semiconductor laser element according to claim 1, characterized in that: The total thickness of the semiconductor laser element is defined as H, and h3 ≥ 2 / 5H.

3. The semiconductor laser element according to claim 1, characterized in that: h3≥30μm.

4. The semiconductor laser element according to claim 1, characterized in that: h1≤5μm and / or h2≤5μm.

5. The semiconductor laser element according to claim 1, characterized in that: 0 < h1 / h3 ≤ 1 / 6, and / or 0 < h2 / h3 ≤ 1 / 6.

6. The semiconductor laser element according to claim 1, characterized in that: The third direction is defined as a width direction perpendicular to the first direction and the second direction; the first transition surface has a horizontal width w1 along the third direction, the second transition surface has a horizontal width w2 along the third direction, and the third transition surface has a horizontal width w3 along the third direction; wherein, w1 < w3, and / or, w2 < w3.

7. The semiconductor laser element according to claim 1, characterized in that: The first transition surface and the second transition surface have equal or unequal extension lengths along the first direction; the semiconductor laser element has a total length D along the first direction, the first transition surface has a length d1 along the first direction, and the second transition surface has a length d2 along the first direction; wherein, d1 > 0 and d1 ≤ 0.1D, d2 > 0 and d2 ≤ 0.1D.

8. The semiconductor laser element according to claim 1, characterized in that: The semiconductor stack has a total length D along the first direction, and the third transition surface has a length d3 along the first direction; wherein, d3 ≥ 0.8D and d3 < D.

9. The semiconductor laser element according to claim 1, characterized in that: The semiconductor stack includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially stacked on the substrate along a second direction; the first transition surface extends from the first surface toward the substrate side along the second direction but does not extend to the active layer; And / or, the second transition surface extends from the first surface toward the substrate side along the second direction but does not extend to the active layer.

10. The semiconductor laser element according to claim 9, characterized in that: The third transition surface extends from the first surface across the active layer and connects to the side surface located below the active layer on the side facing the substrate.

11. The semiconductor laser element according to claim 1, characterized in that: The transition surface is an inclined surface, a curved surface, or a combination thereof that continuously connects the first surface and the side surface.

12. The semiconductor laser element according to claim 1, characterized in that: The third direction is defined as the width direction perpendicular to the first direction and the second direction; on the first surface, the first transition surfaces located on opposite sides have a maximum horizontal distance L1 along the third direction, the second transition surfaces located on opposite sides have a maximum horizontal distance L2 along the third direction, and the third transition surfaces located on opposite sides have a maximum horizontal distance L3 along the third direction; wherein, L1 > L3, and / or, L2 > L3.

13. The semiconductor laser element according to any one of claims 1 to 12, characterized in that: The semiconductor laser element further includes a first film layer and a second film layer; the first film layer is disposed on the cavity surface near the first transition surface, and the second film layer is disposed on the other cavity surface near the second transition surface; the first film layer includes at least a high-reflection layer; and the second film layer includes at least an anti-reflection layer.

14. The semiconductor laser element according to claim 13, characterized in that: The first surface extends to the upper surfaces of the first film layer and the second film layer; The side surface extends to the sidewalls of the first film layer and the second film layer; the first transition surface extends from the boundary between the first surface and the side surface of the semiconductor stack along the first direction to the boundary between the upper surface and the sidewall of the first film layer; The boundary between the first surface and the side surface of the second transition surface semiconductor stack extends along the first direction to the boundary between the upper surface and the sidewall of the second film layer.

15. The semiconductor laser element according to claim 13, characterized in that: The boundary between the upper surface of the first membrane layer and its sidewall has only a first transition surface, and the boundary between the upper surface of the second membrane layer and its sidewall has only a second transition surface.

16. The semiconductor laser element according to claim 1, characterized in that, The semiconductor laser element further includes: The ridge is located on the first surface and extends out of the first surface along a first direction; An insulating layer that covers a portion of the ridge and extends to at least a portion of the first surface; The first electrode covers the insulating layer and is electrically connected to the ridge. The second electrode is located on the surface of the substrate opposite to the semiconductor stack.

17. The semiconductor laser element according to claim 1, characterized in that: The total length D of the semiconductor laser element along the first direction and the total width W along the third direction satisfy: D / W≥1.

5.

18. A light emitting device, characterized in that: The semiconductor laser element described in any one of claims 1 to 17 is used.

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