A load state triggered output protection system with no delay safe restart

Abstract

The application discloses a load state triggering output protection system with no time-delay safe restart, belongs to the technical field of electronic circuits, and aims to solve the technical problem that when a load fault is not eliminated, an impact circuit formed by circuit hiccup causes component damage and the like, and the technical solution is characterized in that: a fault detection module is used for detecting whether a circuit exists a fault; when the fault detection module detects that a fault occurs, a signal is sent to an MCU control module; a load state detection module is used for detecting whether a load is released; the MCU control module controls the turn-off of an output according to the inspection result of the fault detection module; when the fault occurs, the MCU control module pulls down MCU_GATE to cut off the output; meanwhile, the load state detection module is used for detecting whether the load is released, if the load is not released, the MCU control module controls the output port to be closed, and if the load has been released, the MCU control module restores the output.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, specifically relating to an output short-circuit protection circuit, and more particularly to an intelligent protection circuit that automatically and instantaneously restores output based on load status without requiring a fixed delay after a fault is cleared. It can be widely applied in power adapters, battery management systems, industrial automation equipment, automotive electronics, communication infrastructure, and emergency safety systems. Background Technology

[0002] When electronic systems, such as switching power supplies and drive circuits, are in operation, if an overcurrent or short circuit occurs, the circuit needs to be cut off to achieve overcurrent protection or short circuit protection. Current protection methods include repetitive hiccup protection and fixed delay recovery protection.

[0003] The traditional repetitive hiccup-type protection scheme works as follows: When the protection detection module detects an abnormal state such as overcurrent, short circuit, or overload at the output terminal, the protection circuit immediately activates, quickly shutting off the power switch or cutting off the output path, causing the output voltage and current to rapidly drop to a safe range. After shutting off the output and after a fixed short delay, the protection circuit automatically resets and attempts to restart the output to restore power to the load. If the fault condition on the load side is still not eliminated at this time, the output current or voltage will exceed the threshold again, and the protection circuit will be triggered again to shut off the output. This forms a cycle of periodic shutdown, short delay, retry output, and shutdown again, which is the "hiccup" working mode.

[0004] The main drawback of this protection method is: Throughout the duration of the load fault, the output terminal will repeatedly experience periodic, high-amplitude current spikes and voltage surges. These periodic, strong impacts not only continuously affect the downstream load components, causing stress fatigue and performance degradation in critical components such as semiconductor devices, capacitors, and inductors, but also conduct in reverse to the front-end input power supply and bus circuit, creating repeated electromagnetic and power surges on the front-end power module, significantly increasing the safety risks of front-end circuit damage, failure, and even fire. Furthermore, because this protection mode relies solely on a simple delay-retry mechanism and lacks fault identification and intelligent judgment capabilities, once the load enters a permanent fault state, the system will remain in a state of continuous spikes and surges, unable to completely lock out or enter a safe shutdown, failing to achieve reliable and stable automatic recovery, resulting in low overall safety and reliability.

[0005] The traditional fixed-delay recovery protection scheme is an improved protection strategy proposed to improve the problem of repeated hiccup impact. Its workflow is as follows: When the detection circuit detects abnormal events such as output overcurrent or short circuit, the protection logic immediately performs a shutdown operation, stopping power output and simultaneously starting a preset, long-duration fixed delay timer (usually on the order of several seconds). During the timing period, the output remains off and no retry is performed; when the timing period expires, regardless of whether the fault on the load side has been eliminated or the system has truly returned to safe conditions, the protection circuit forcibly performs a reset operation, restarts the output, and attempts to restore power supply.

[0006] This solution has obvious inherent flaws: On the one hand, if the load fault is not resolved, the first recovery output after the delay will still generate a sudden large current and voltage surge, causing stress damage to the power devices and the load, and does not fundamentally eliminate the impact hazard; On the other hand, if the load fault is eliminated before the delay ends, the system must still passively wait for the full delay period to end before resuming normal operation, resulting in a significant amount of unnecessary downtime and directly reducing the system's continuous operation capability, availability, and response speed. In applications with high requirements for power supply continuity, such as industrial control, vehicle power supply, and medical equipment, excessively long and unnecessary downtime can severely impact equipment operating efficiency, production continuity, and user experience. Furthermore, because the delay parameters are fixed, they cannot be adaptively adjusted according to load type, fault severity, and system status, resulting in poor flexibility in protection strategies and making it difficult to balance safety, response speed, and service life.

[0007] Based on this, the present invention provides a load state-triggered output protection system with no delay and safe restart. Summary of the Invention

[0008] The purpose of this invention is to provide: A load-state-triggered output protection system with no delay and safe restart is provided to completely avoid repeated restarts of the output circuit when the load fault has not been eliminated, thus achieving a deeper level of component protection. After the load fault is eliminated, normal output is immediately and automatically restored without any waiting delay.

[0009] Terminology Explanation: Unless otherwise defined, all technical terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which this subject matter pertains. Unless otherwise stated, all patents, patent inventions, and disclosures cited throughout this document are incorporated herein by reference in their entirety. Where multiple definitions exist for terms herein, the definitions provided in this chapter shall prevail.

[0010] It should be understood that the above brief description and the following detailed description are exemplary and for illustrative purposes only, and do not limit the subject matter of the invention in any way. In this invention, the singular is used in conjunction with the plural unless otherwise specifically stated. It should also be noted that, unless otherwise stated, the use of “or” or “or” means “and / or”. Furthermore, the use of the term “comprising” and other forms such as “including,” “containing,” and “contains” are not limiting.

[0011] Unless specifically defined herein, the use of various commercially available products herein employs standard techniques. For example, they may be implemented using the manufacturer's instructions for use, or in accordance with methods known in the art or the description of this invention. The techniques and methods described herein can generally be implemented according to conventional methods well known in the art, based on the descriptions in the various general and more specific documents cited and discussed in this specification.

[0012] The terms “optional / arbitrary” or “optionally / arbitrarily” mean that the event or situation described below may or may not occur, including both the occurrence and non-occurrence of the event or situation.

[0013] The term “load has been released” as used in this article means that the load has been removed or disconnected.

[0014] The term "hiccup" used in this article refers to an intermittent restart protection mechanism. For example, when a circuit experiences faults such as overcurrent, short circuit, or overtemperature, the power supply / controller will repeatedly "shut down → restart → shut down again → restart again," just like a person hiccuping, periodically starting and stopping.

[0015] The term "high level" as used in this article refers to the voltage range in digital circuits that represents logic "1", that is, the voltage close to the positive terminal of the power supply.

[0016] The term "low level" as used in this article refers to the voltage range in digital circuits that represents logic "0", that is, the voltage close to ground.

[0017] A load-state-triggered output protection system with no delay and safe restart, comprising: The fault detection module is used to detect whether there is a fault in the circuit; when the fault detection module detects a fault, it sends a signal to the MCU control module. The load status detection module is used to detect whether the load has been released; The MCU control module controls the shutdown of the output based on the inspection results of the fault detection module; The fault detection module includes a sampling circuit and a comparator. The comparator is also connected to a reference voltage sampling circuit, which is used to collect the supply voltage as a reference voltage. The other end of the sampling circuit is connected to the MCU control module through the MCU_GATE node to collect the actual output voltage. The MCU control module is connected to the load status detection module through the MCU_IO node. The load status detection module includes a transistor Q2 and a chip Q1. The base of the transistor Q2 is connected to the MCU_IO; the base of the transistor Q2 is also grounded through a pull-down resistor R5; the collector of the transistor Q2 is connected to the gate of the chip Q1; and the emitter of the transistor Q2 is connected to the load P+. The chip Q1 is also connected to a voltage divider network. The voltage divider network includes voltage divider resistors R3 and R6 connected in series; the upper end of resistor R3 is connected to the load P+, and the lower end of R3 is connected in series with resistor R6 and then grounded. The connection point of resistors R3 and R6 is led out to the MCU control module. The MCU control module is configured as follows: When a fault occurs, the MCU control module pulls MCU_GATE low to cut off the output; at the same time, the load status detection module detects whether the load has been released. If the load has not been released, the MCU control module controls the output port to close; if the load has been released, the MCU control module resumes the output.

[0018] Based on further solutions to the technical problems of the present invention, or simultaneous solutions to multiple technical problems, the preferred solution in the technical solution provided in the first aspect of the present invention includes: First preferred option: The reference voltage sampling circuit includes resistors R7 and R8. One end of resistor R7 is connected to the comparator, and the other end is connected to the supply voltage VCC. One end of resistor R8 is connected to the comparator, and the other end is grounded.

[0019] Second preferred option: The sampling circuit includes a MOSFET Q3. The source of the MOSFET Q3 is connected to the positive output terminal BAT+, the drain of the MOSFET Q3 is connected to the load terminal P+, and the gate of the MOSFET Q3 is connected to the MCU control module through the MCU_GATE node.

[0020] Third preferred option: The MOSFET Q3 is also connected in parallel with a diode.

[0021] Fourth preferred option: The source of chip Q1 is connected to the positive terminal BAT+ of the battery, the drain of chip Q1 is connected to the load P+, and the gate of chip Q1 is connected to the positive terminal BAT+ of the battery via pull-up resistor R1.

[0022] Fifth preferred option: The base of transistor Q2 is also connected to Zener diode D2. This protects Q2 from damage due to overvoltage.

[0023] Sixth preferred option: The base of transistor Q2 is connected to MCU_IO via diode D1. This prevents the base current of Q2 from flowing back into MCU_IO.

[0024] Seventh preferred option: Diode D1 is a 1N4148 high-speed switching diode.

[0025] Eighth preferred option: Filter capacitors C1 and C2 are connected in parallel at the connection point of resistors R3 and R6. These are used to filter out high-frequency noise and improve sampling accuracy.

[0026] Ninth preferred option: Chip Q1 is a P-channel enhancement-mode chip.

[0027] The present invention has at least the following beneficial effects: The output protection recovery trigger mechanism of this invention changes from the traditional time-driven to an event-driven state, completely avoiding the repeated restart impact of the output circuit when the load fault has not been eliminated, and achieving a deeper level of component protection.

[0028] By employing a load sensing network, when a fault occurs, the output will not repeat, generating very large spikes in current and voltage, if the load is not removed. Output recovery requires no waiting time; once the load is released, normal output resumes immediately and automatically without any delay. Attached Figure Description

[0029] Figure 1 This is the circuit schematic of the fault detection module; Figure 2 This is the circuit schematic of the MCU control module; Figure 3 This is the circuit schematic of the load status detection module; Figure 4 This is a schematic diagram of the working principle of the present invention. Detailed Implementation

[0030] The following non-limiting embodiments are intended to enable those skilled in the art to gain a more comprehensive understanding of the present invention, but do not limit the invention in any way. The following content is merely an exemplary description of the scope of protection claimed by the present invention, and those skilled in the art can make various changes and modifications to the present invention based on the disclosed content, and such changes should also fall within the scope of protection claimed by the present invention.

[0031] The present invention will be further described below by way of specific embodiments. Unless otherwise specified, all instruments, devices, equipment and other items used in the embodiments of the present invention are obtained through conventional commercial means.

[0032] Example 1 This embodiment provides a load-state-triggered output protection system with no-delay safe restart, such as... Figure 1 and Figure 2 As shown, it includes: A. Fault Detection Module The fault detection module includes a sampling circuit and a comparator. The voltage drop across the sampling circuit reflects the magnitude of the output current. This voltage is sent to one end of the comparator and compared with the overcurrent reference voltage at the other end.

[0033] Specifically, such as Figure 1 As shown, the fault detection module includes a comparator chip, which is a dual-channel comparator chip. Pin 1IN+ of the comparator chip is connected to a voltage divider circuit, which includes resistors R7 and R8. Resistors R7 and R8 divide VCC to provide a reference voltage for the comparator.

[0034] Pin 1IN- of the comparator chip is connected to the sampling circuit, and the other end of the sampling circuit is connected to the node between MCU_GATE and P+ of the MCU control module to sample the actual output voltage.

[0035] Specifically, the sampling circuit includes a connection to the output port of the comparator chip, the output port is connected to MOSFET Q3, MOSFET Q3 is connected to the MCU_GATE node of the MCU control module, and is also connected to the positive input BAT+ of the battery.

[0036] The judgment logic of the fault detection module is as follows: When the actual output voltage and the reference voltage are basically equal, the comparator outputs a high level and ERR_FLAG is a low level, indicating that there is no fault. When the actual output voltage deviates from the reference voltage, the comparator flips and outputs a low level, then ERR_FLAG becomes high, indicating a fault has occurred.

[0037] B. Load Status Detection Module The load status detection module is used to detect the load status, specifically whether a load is currently connected to the load output terminal. If a load is connected to the load output terminal, it is determined that the load has not been released; if no load is connected to the load output terminal, it is determined that the load has been released.

[0038] Specifically, the load status detection module and the MCU control module are connected; the load status detection module includes chip Q1, which is a P-channel enhancement-mode chip. Its source is connected to the positive input of the battery BAT+, and its drain is connected to the subsequent load P+. In addition, a pull-up resistor R1 is set to pull the gate of chip Q1 to the positive input voltage of the battery BAT+, so that chip Q1 is in the off state by default.

[0039] The MCU_IO port is connected in series with resistor R4, diode D1, and transistor Q2. The base of transistor Q2 is connected to diode D1. Diode D1 is used to prevent reverse current, thus protecting the MCU_IO port. The emitter of transistor Q2 is connected to the load P+, and its base is connected to the load P+ through pull-down resistor R5. The collector of transistor Q2 is connected to the gate of chip Q1 through resistor R2.

[0040] In addition, a diode D2 is connected in parallel between the base and emitter of transistor Q2 to clamp the base voltage of transistor Q2 and prevent damage from overvoltage.

[0041] Chip Q1 is also connected to a voltage divider network, including resistor R3 and resistor R6 connected in series with resistor R3. Resistors R3 and R6 form a voltage divider circuit to divide the voltage at the drain of chip Q1. The voltage after voltage division is sent to the MCU_ADC pin for the MCU to read and convert into battery voltage. Two capacitors C1 and C2 are connected in parallel with resistor R6. Capacitors C1 and C2 are connected in parallel to form an RC low-pass filter network to filter out high-frequency noise and improve sampling accuracy.

[0042] C. MCU control module The MCU control module automatically outputs high and low levels based on the detection results of the fault detection module. When ERR_FLAG is high, it indicates that a fault has occurred. At this time, the MCU control module triggers the protection logic and immediately shuts off the output.

[0043] The workflow of this embodiment is as follows: 1. Initialization: When the MCU control module pulls MCU_GATE low, the field-effect transistor Q3 is turned off, and there is no output; when MCU_IO is set to low, the load detection circuit is in standby mode.

[0044] 2. Load detection: When the MCU control module pulls MCU_IO high, the load detection circuit is activated. If the MCU_ADC samples a valid voltage, it indicates that the load has been connected and is ready to output. If the voltage sampled by the MCU_ADC is too low, it indicates that the load has not been connected and output is prohibited.

[0045] 3. Normal working condition (no fault occurred) After the MCU control module confirms the load connection, it pulls MCU_GATE high, the gate of MOSFET Q3 is given a high level, MOSFET Q3 is turned on, and the BAT+ terminal supplies power to the load; at the same time, the fault detection module monitors the output voltage in real time, and ERR_FLAG remains at a low level.

[0046] 4. Troubleshooting: If a fault occurs, ERR_FLAG will be high, the MCU control module will immediately pull MCU_GATE low, turn off the field-effect transistor Q3, and the BAT+ terminal will stop outputting.

[0047] 5. Fault Recovery: When the fault detection circuit detects overcurrent or short circuit, the MCU control module receives a fault signal. The MCU_IO output of the MCU control module goes high through resistor R4, diode D1, and transistor Q2. When the load has been released, transistor Q2 will not conduct because the voltage at the P+ terminal is equal to the base voltage of transistor Q2, and no circuit is formed. At this time, resistors R1 and R2 do not form a circuit, and chip Q1 does not conduct. Consequently, the MCU_ADC does not detect a voltage value, which is transmitted to the MCU control module, which then determines that the load has been released. At this point, the output can be restored, and the gate voltage of the field-effect transistor Q3 is given a high level, allowing the output port to drive the load normally.

[0048] When a short circuit or overcurrent occurs, and the load is not released, the MCU_IO outputs a high level through resistor R4, diode D1, and a load connected to the output port. The P+ terminal connects to GND, at which point transistor Q2 conducts. Resistors R1 and R2 form a circuit through transistor Q2, turning on chip Q1. The BAT+ voltage flows through resistors R3 and R6, forming a voltage divider. The MCU_ADC receives a voltage value, which is transmitted to the MCU control module. The MCU control module determines that there is a short circuit or overcurrent and the load has not been released, and therefore cannot open the output port. The MOSFET Q3 is turned off. The MOSFET is only turned on after the load has been detected as released, thus preventing repeated oscillations and achieving protection.

[0049] In summary, this invention does not generate hiccup-like inrush current, nor does it have a fixed delay. Instead, it uses the presence or absence of voltage sampling to determine whether the chip is conducting to the load, thus achieving shock-free and adaptive recovery.

[0050] Finally, it should be noted that the above content is only used to illustrate the technical solution of the present invention, and is not intended to limit the scope of protection of the present invention. Simple modifications or equivalent substitutions made by those skilled in the art to the technical solution of the present invention do not depart from the essence and scope of the technical solution of the present invention.

Claims

1. A load-state-triggered output protection system with no-delay safe restart, characterized in that, include: The fault detection module is used to detect whether there is a fault in the circuit; When the fault detection module detects a fault, it sends a signal to the MCU control module. The load status detection module is used to detect whether the load has been released; The MCU control module controls the shutdown of the output based on the inspection results of the fault detection module; The fault detection module includes a sampling circuit and a comparator. The comparator is also connected to a reference voltage sampling circuit, which is used to collect the supply voltage as a reference voltage. The other end of the sampling circuit is connected to the MCU control module through the MCU_GATE node to collect the actual output voltage. The MCU control module is connected to the load status detection module through the MCU_IO node. The load status detection module includes a transistor Q2 and a chip Q1. The base of the transistor Q2 is connected to the MCU_IO; the base of the transistor Q2 is also grounded through a pull-down resistor R5; the collector of the transistor Q2 is connected to the gate of the chip Q1; and the emitter of the transistor Q2 is connected to the load P+. The chip Q1 is also connected to a voltage divider network. The voltage divider network includes voltage divider resistors R3 and R6 connected in series; the upper end of resistor R3 is connected to the load P+, and the lower end of R3 is connected in series with resistor R6 and then grounded. The connection point of resistors R3 and R6 is led out to the MCU control module. The MCU control module is configured as follows: When a fault occurs, the MCU control module pulls MCU_GATE low to cut off the output; at the same time, the load status detection module detects whether the load has been released. If the load has not been released, the MCU control module controls the output port to close; if the load has been released, the MCU control module resumes the output.

2. The load state-triggered output protection system with no-delay safe restart as described in claim 1, characterized in that, The reference voltage sampling circuit includes resistors R7 and R8. One end of resistor R7 is connected to the comparator, and the other end is connected to the supply voltage VCC. One end of resistor R8 is connected to the comparator, and the other end is grounded.

3. The load state-triggered output protection system with no-delay safe restart as described in claim 1, characterized in that, The sampling circuit includes a MOSFET Q3. The source of the MOSFET Q3 is connected to the positive output terminal BAT+, the drain of the MOSFET Q3 is connected to the load terminal P+, and the gate of the MOSFET Q3 is connected to the MCU control module through the MCU_GATE node.

4. The load state-triggered output protection system with no-delay safe restart as described in claim 3, characterized in that, The MOSFET Q3 is also connected in parallel with a diode.

5. The load state-triggered output protection system with no-delay safe restart as described in claim 1, characterized in that, The source of chip Q1 is connected to the positive terminal BAT+ of the battery, the drain of chip Q1 is connected to the load P+, and the gate of chip Q1 is connected to the positive terminal BAT+ of the battery via pull-up resistor R1.

6. The load state-triggered output protection system with no-delay safe restart as described in claim 1, characterized in that, The base of transistor Q2 is also connected to Zener diode D2.

7. The load state-triggered output protection system with no-delay safe restart as described in claim 1, characterized in that, The base of transistor Q2 is connected to the MCU_IO node via diode D1.

8. The load state-triggered output protection system with no-delay safe restart as described in claim 1, characterized in that, Diode D1 is a 1N4148 high-speed switching diode.

9. The load state-triggered output protection system with no-delay safe restart as described in claim 1, characterized in that, The connection point of resistors R3 and R6 is also connected in parallel with filter capacitors C1 and C2.

10. The load state-triggered output protection system with no-delay safe restart as described in claim 1, characterized in that, Chip Q1 is a P-channel enhancement-mode chip.

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