A low power consumption power management system and method based on dual blade self-restoring switch

Abstract

The application provides a low-power consumption power management system and method based on a double-knife self-restoration switch, relates to the technical field of power management, and realizes the cooperative mechanism of multi-source triggering and power supply self-locking through adopting the double-knife self-restoration switch cooperating with the discrete OR gate logic control circuit composed of an isolation diode array and a driving triode, so that when a user short-presses the switch, the logic control circuit can instantly turn on the bidirectional MOS switch to start the system, and outputs a maintenance signal to take over the control right after the power management unit is powered on, thereby overcoming the characteristic that the self-restoration switch is disconnected when the hand is released, ensuring continuous and stable power supply of the system, and in the shutdown state, the bidirectional MOS switch completely cuts off the connection between the battery and the system main power rail, and controls the leakage current at a very low level, meanwhile, the architecture is also compatible with external power supply access and long-press shutdown logic, so that the hardware circuit design is simplified, the cost is reduced, and the reliability and energy efficiency ratio of power management are significantly improved.

Description

Technical Field

[0001] This application relates to the field of power management technology, and in particular to a low-power power management system and method based on a double-pole self-resetting switch. Background Technology

[0002] In the design of battery-powered devices, the reliability, low power consumption, and ease of user operation of the power management system are core considerations. However, traditional power path designs often suffer from leakage current after power-off, which causes the battery to slowly lose power and fails to meet the stringent requirements of the device for extremely low standby power consumption. At the same time, existing technologies often struggle to deeply integrate power-on / off control, status locking, and automatic charging functions, resulting in complex systems or poor user experience. Summary of the Invention

[0003] This application provides a low-power power management system and method based on a double-pole self-resetting switch to solve one or more technical problems existing in the prior art, and at least provides a beneficial option or creates conditions that enable the system to self-lock power supply after button triggering through the coordinated cooperation of the double-pole self-resetting switch, diode OR gate logic circuit and power management unit, and completely cut off the battery circuit when the device is powered off by using a bidirectional MOS switch, which significantly extends the battery storage life and standby time of the device.

[0004] On the one hand, this application provides a low-power power management system based on a dual-pole self-resetting switch, comprising: The double-pole self-resetting switch has a first contact channel and a second contact channel that are triggered by the same button. One end of the first contact channel is connected to the positive terminal of the battery, and the other end is connected to the first input terminal of the logic control circuit. One end of the second contact channel is grounded, and the other end is connected to the power-on trigger terminal of the host system. A bidirectional MOS switch is connected in series between the positive terminal of the battery and the main power rail of the system. The logic control circuit is implemented by a discrete OR gate logic consisting of an isolation diode array and a driving transistor. Its first input terminal is connected to the first contact channel of the double-pole self-resetting switch, its second input terminal is connected to the sustain signal output terminal of the power management unit, its third input terminal is connected to the external power supply access detection terminal, and its output terminal is connected to the control terminal of the bidirectional MOS switch. The logic control circuit is configured to: output a drive signal to turn on the bidirectional MOS switch when the first contact channel is detected to be on, or when the power management unit outputs a sustain signal, or when an external power supply is connected; when the first contact channel is detected to be on, the bidirectional MOS switch is turned on first, and after the power management unit outputs a sustain signal, the bidirectional MOS switch is kept on based on the sustain signal to achieve system power supply self-locking.

[0005] Furthermore, the bidirectional MOS switch is composed of two P-channel MOS transistors connected in series back to back, including a first P-channel MOS transistor and a second P-channel MOS transistor. The source of the first P-channel MOSFET is connected to the source of the second P-channel MOSFET. The drain of the first P-channel MOSFET is connected to the battery terminal, and the drain of the second P-channel MOSFET is connected to the main power rail of the system. The gates of both the first P-channel MOSFET and the second P-channel MOSFET are connected to the output terminal of the logic control circuit.

[0006] Furthermore, the isolation diode array includes three input branches, which are respectively connected to the first contact channel of the double-pole self-resetting switch, the sustain signal output terminal of the power management unit, and the external power supply access detection terminal. Each input branch is unidirectionally isolated by diodes. The common output terminal of the isolation diode array is connected to the base of the driving transistor, and the collector of the driving transistor is connected to the gate of the bidirectional MOS switch. The gate of the bidirectional MOS switch is also connected to a first pull-up resistor, and the other end of the first pull-up resistor is connected to the power supply terminal. The driving transistor is used to conduct to ground when any branch of the isolation diode array is turned on, thereby pulling down the gate potential of the bidirectional MOS switch.

[0007] Furthermore, the power-on trigger terminal of the host system is connected to a second pull-up resistor, which is connected to a preset voltage domain; The second contact channel of the double-pole self-resetting switch is turned on when the button is pressed, shorting the power-on trigger terminal of the host system to ground, causing the power-on trigger terminal to generate a high-to-low level transition pulse, which is used to trigger the motherboard power management controller to enter the power-on sequence.

[0008] Furthermore, the power management unit is also used to detect long-press events of the double-pole self-recovery switch, wherein the threshold for determining the long-press event is 3 to 8 seconds; When a long press event is detected and the power-off conditions are met, the power management unit withdraws the sustain signal, and the logic control circuit then shuts off the drive signal, causing the bidirectional MOS switch to turn off and disconnecting the battery from the system's main power rail.

[0009] Furthermore, the system also includes a charging management circuit, the input of which is connected to an external power supply interface; When an external power source is plugged in, the charging management circuit outputs a high-level signal to the third input terminal of the logic control circuit. The logic control circuit preferentially turns on the bidirectional MOS switch to establish a charging and power supply path, regardless of whether the double-pole self-resetting switch is in the pressed state.

[0010] Furthermore, the logic control circuit is configured to turn on the bidirectional MOS switch at the instant the first contact channel of the double-pole self-resetting switch is turned on; The power management unit is configured to: after detecting that the system is powered on, output the sustain signal to the second input terminal of the logic control circuit, and take over the conduction control of the bidirectional MOS switch; The sustaining signal is configured to remain on when the double-pole self-resetting switch is disconnected due to its self-resetting characteristic, so as to overcome the power interruption caused by the self-resetting characteristic of the double-pole self-resetting switch and ensure stable system operation.

[0011] Furthermore, the external power interface is connected to the system's main power rail via an anti-reverse-feedback diode; When an external power source is connected, the system is powered by the external power source first, while the battery is charged through the bidirectional MOS switch, forming a dual-source power supply architecture with external power priority and battery backup.

[0012] Furthermore, the logic control circuit also includes a fourth input branch, which is connected to the control output terminal of the host CPU and is used to support software-triggered power on / off control.

[0013] On the other hand, this application provides a low-power power management method based on a dual-pole self-resetting switch, applied to the power management system as described above, including the following steps: A short press of the double-pole self-resetting switch closes the first contact channel, inputting a high level to the logic control circuit, and closes the second contact channel, pulling down the power-on trigger terminal of the host system. The logic control circuit then turns on the bidirectional MOS switch, and the system powers on and starts up. After the system is powered on, the power management unit outputs a sustain signal to the logic control circuit. The logic control circuit locks the conduction state of the bidirectional MOS switch based on the sustain signal. At this time, the double-pole self-resetting switch is released, and the system maintains normal power supply. When the dual-pole self-recovery switch is pressed and held for a preset duration threshold, the power management unit recognizes the long press signal and executes the shutdown procedure. Then, the sustain signal is withdrawn, the logic control circuit turns off the bidirectional MOS switch, the system is completely powered off, and enters a low-power standby state. When an external power source is connected, the logic control circuit automatically turns on the bidirectional MOS switch to establish a charging circuit to charge the battery. If the system is in a shutdown state, it will not trigger the power-on process. If the system is in a running state, it will switch to the external power priority mode.

[0014] The beneficial effects of this application are as follows: This application provides a low-power power management system and method based on a dual-pole self-resetting switch. This technical solution uses a dual-pole self-resetting switch in conjunction with a discrete OR gate logic control circuit composed of an isolation diode array and a driving transistor to achieve a collaborative mechanism of multi-source triggering and power supply self-locking. When the user presses the switch briefly, the logic control circuit can immediately turn on the bidirectional MOS switch to start the system, and output a maintenance signal to take over control after the power management unit is powered on, thereby overcoming the characteristic of the self-resetting switch turning off immediately when released, ensuring continuous and stable power supply to the system. In the power-off state, the bidirectional MOS switch completely cuts off the connection between the battery and the system's main power rail, keeping the leakage current at an extremely low level. At the same time, this architecture is also compatible with external power input and long-press power-off logic, which not only simplifies the hardware circuit design and reduces costs, but also achieves deep integration of battery power supply, external charging and system state locking, significantly improving the reliability and energy efficiency of power management.

[0015] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0016] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the technical solutions of the present invention, and do not constitute a limitation on the technical solutions of the present invention.

[0017] Figure 1 This is the circuit schematic diagram of the double-pole self-resetting switch provided in this application; Figure 2 This is a schematic diagram of the low-power power management system based on a double-pole self-resetting switch provided in this application; Figure 3 This is a flowchart of the low-power power management method based on a double-pole self-resetting switch provided in this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0019] The present application will be further described below with reference to the accompanying drawings and specific embodiments. The described embodiments should not be considered as limitations on the present application, and all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present application.

[0020] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0022] In the field of portable electronic devices and IoT terminals, the design of power management systems has always been a key technological aspect affecting product competitiveness. Current technologies commonly rely on single-pole single-throw switches paired with dedicated power management chips, or on mechanically latched switches to maintain the device's power supply. These traditional solutions face inherent contradictions and shortcomings in practical applications.

[0023] On the one hand, solutions that rely solely on physical switches often struggle to achieve complex logic control. For example, they may not be able to automatically respond to the connection of an external charger when the device is off, or they may not be able to maintain a stable power supply path when the system software restarts. On the other hand, solutions that rely excessively on software control or complex logic circuits, while feature-rich, usually result in excessive static power consumption. When the device is off or in standby mode, because the power path is not completely cut off physically, the battery will generate continuous leakage current through the external circuit. This not only severely shortens the standby time of the device but also affects the user experience of the product.

[0024] Furthermore, existing power path management technologies often lack flexibility, making it difficult to gracefully integrate multiple event sources within the same system, such as manual button power-on, software command power-off, and external power hot-swapping. When multiple event sources exist simultaneously, logic conflicts or race conditions can easily arise, leading to unstable power supply or even malfunctions. Additionally, to achieve low-power standby, existing solutions typically require additional high-cost dedicated low-power chips or complex timing control circuits, which undoubtedly increases the complexity of hardware design and overall material costs.

[0025] To address the aforementioned issues, this application provides a low-power power management system and method based on a dual-pole self-resetting switch. It employs a low-power power management architecture based on the collaborative operation of a dual-pole self-resetting switch and discrete component logic circuits. The first contact channel of the dual-pole self-resetting switch triggers the logic control circuit, while the second contact channel triggers the host system power-on signal. An OR gate logic circuit composed of an isolation diode array and a driving transistor integrates the switch button signal, the power management unit sustain signal, and the external power detection signal to control the on / off state of the bidirectional MOS switch connected in series between the battery and the system's main power rail. This allows the power management unit to take over control after a single-button power-on trigger, overcoming the defect of the switch self-resetting and achieving system power supply self-locking. Simultaneously, under power-off or long-press commands, the bidirectional MOS switch is completely cut off, achieving microampere-level extremely low standby leakage current. Furthermore, it supports a dual-source power supply mode that prioritizes external power supply and automatically establishes a charging circuit.

[0026] First, this application provides a low-power power management system based on a dual-pole self-resetting switch, including a dual-pole self-resetting switch, a bidirectional MOS switch, and a logic control circuit.

[0027] The dual-pole self-resetting switch has a first contact channel and a second contact channel that are triggered by the same button. One end of the first contact channel is connected to the positive terminal of the battery, and the other end is connected to the first input terminal of the logic control circuit. One end of the second contact channel is grounded, and the other end is connected to the power-on trigger terminal of the host system.

[0028] Specifically, the dual-pole self-resetting switch serves as the system's physical input, simultaneously controlling two independent electrical paths with a single button. The first contact channel directly connects to the battery's positive terminal and the logic control circuit, detecting the user's power-on intention and providing initial energy. The second contact channel connects to the host system's power-on trigger terminal and ground, sending a standard level trigger signal to the motherboard. This dual-channel design decouples the traditional "power on / off" and "system wake-up" functions, allowing the mechanical switch's action to not only establish a power supply path but also independently trigger the motherboard's startup sequence. This resolves the contradiction of traditional single-pole switches simultaneously meeting power switching and logic signal triggering requirements, laying the hardware foundation for subsequent power self-locking and low-power management.

[0029] A bidirectional MOS switch is connected in series between the battery's positive terminal and the system's main power rail, serving as the core actuator in the power path and acting as an electronic valve between the battery and the system. In the on state, the switch allows current to flow bidirectionally, supporting both battery discharge and reverse charging current into the battery. In the off state, it exhibits extremely low leakage current, physically disconnecting the battery from the system load. This design completely blocks the static power consumption generated by the battery through external circuitry in the power-off state, a key element in achieving microampere-level standby power consumption and effectively solving the technical problem of slow battery charge loss after power-off in traditional power supply architectures.

[0030] The logic control circuit is implemented using discrete OR gate logic consisting of an isolation diode array and a driving transistor. Its first input is connected to the first contact channel of a double-pole self-resetting switch, its second input is connected to the sustain signal output of the power management unit, and its third input is connected to the external power supply detection terminal. Its output is connected to the control terminal of a bidirectional MOS switch. The function of this circuit is to unify dispersed trigger sources (such as button presses, charger insertion, and system software commands) into a single gate drive signal. This not only reduces system cost but also ensures the real-time performance and reliability of power control through hardware-level logic operations, avoiding the risk of power failure due to software crashes.

[0031] Furthermore, the logic control circuit is configured to output a drive signal to turn on the bidirectional MOS switch when the first contact channel is detected to be on, or when the power management unit outputs a sustain signal, or when an external power supply is connected. When the first contact channel is detected to be on, the bidirectional MOS switch is turned on first, and after the power management unit outputs a sustain signal, the bidirectional MOS switch is kept on based on the sustain signal to achieve system power supply self-locking.

[0032] Therefore, the power path can be activated independently regardless of whether the user manually presses a button, an external adapter is plugged in, or a software wake-up command is issued within the system. This design achieves seamless integration of external power priority and automatic charging functions. When an external power source is connected, the logic circuit can automatically turn on the MOS switch to establish a charging circuit, regardless of the system's state, greatly improving the device's adaptability and user experience in mixed power supply environments.

[0033] When the logic control circuit detects that the first contact channel is conducting, it prioritizes turning on the bidirectional MOS switch. Subsequently, after the power management unit powers on and outputs a sustain signal, this sustain signal maintains the bidirectional MOS switch in the on state. This process achieves the self-locking function of the system power supply, resolving the contradiction between the physical characteristics of the self-resetting switch and the continuous power supply requirements of the system. In other words, the user only needs to lightly press the button to trigger the power-on, and the system can take over the switch state through the feedback signal from the power management unit. Even if the user releases the button and the switch is turned off, the system can still maintain a stable power supply. This hardware and software combined self-locking mechanism not only simulates the user experience of a mechanical latching switch but also avoids system power outages caused by button bounce or accidental touches, ensuring the stability of the device operation.

[0034] It should be noted that in actual circuit design, the use of single-pole switches is indeed very common, but single-pole switches face a classic problem: to control the power supply, the switch must be connected in series in the main battery circuit (high voltage side), but to generate the power-on logic signal (give a pulse to the PMU), the circuit must first be powered.

[0035] Therefore, the core necessity of adopting a double-pole self-resetting switch lies in resolving the physical isolation and power supply contradiction between high-voltage side power switching and low-voltage side logic wake-up in traditional single-pole switches. In an architecture using only single-pole switches, if discrete component logic circuits are to control the gate of a bidirectional MOS switch, energy (base bias current) must be provided to the logic circuit at the moment the button is pressed. This forces the single-pole switch to directly carry the battery main circuit current or to rely on a bias circuit that is always connected to the battery, thus making it impossible to achieve true zero-power shutdown. This application decouples the physical path through a double-pole structure: the first contact channel is directly connected across the battery positive terminal and logic ground, independently constructing a power trigger circuit to provide energy for the logic control circuit; the second contact channel independently constructs a low-level wake-up signal circuit. This design allows the logic control circuit to be activated without relying on the system main power rail (VSYS) to be pre-powered, fundamentally overcoming the physical limitation of single-pole switches that "cannot generate control signals in the absence of power," and realizing the electronic self-locking startup logic triggered only by mechanical action in the state of complete system power failure (VSYS floating).

[0036] If traditional solutions such as single-pole switches combined with RC delay circuits are used, a small static current must be maintained at the battery terminal to maintain the capacitor voltage or bias resistor operation, which contradicts the "microamp-level ultra-low standby power consumption" goal pursued in this application. The dual-pole structure of this application allows the first contact channel to be completely disconnected after completing the triggering task, and together with the bidirectional MOS switch, it achieves a complete physical disconnection between the battery positive terminal and the system main power rail, eliminating any maintenance current path. At the same time, the power-on trigger pulse (PWRON_L) independently generated by the second contact channel avoids the interference of power switching noise in single-pole switches on sensitive logic signals. This decoupled design of "power triggering and signal wake-up" not only eliminates the leakage current caused by the pull-down / pull-up bias resistors that must exist in the single-pole solution, but also ensures the purity and reliability of the power-on signal in complex electromagnetic environments through hardware-level signal isolation. It is a key structural feature for achieving highly reliable wake-up in passive standby mode.

[0037] In some embodiments of this application, the bidirectional MOS switch is composed of two P-channel MOS transistors connected back-to-back, including a first P-channel MOS transistor and a second P-channel MOS transistor. This topology, which uses two P-channel MOS transistors cascaded back-to-back, constructs a power switching device that can withstand bidirectional voltage blocking.

[0038] Compared to a single MOSFET or a conventional series connection, this structure utilizes the inherent parasitic diode orientation characteristics within the P-channel MOSFET. By connecting the two parasitic diodes back-to-back in reverse series, it physically blocks the bidirectional flow of current when the switch is turned off. This design is crucial for battery-powered systems. It not only prevents battery energy leakage through the load when the system is off, but also prevents current from flowing back to the battery when an external charging power source is connected. This achieves complete isolation of the power path and is a key technical means to achieve ultra-low quiescent power consumption at the microampere level and prevent the safety hazards of reverse charging.

[0039] Furthermore, the source of the first P-channel MOSFET is connected to the source of the second P-channel MOSFET, the drain of the first P-channel MOSFET is connected to the battery terminal, and the drain of the second P-channel MOSFET is connected to the main power rail of the system. This specific physical layout, with the source connected to the same terminal and the drain connected to the power supply and the load respectively, defines a clear power transmission path and optimizes electrical performance.

[0040] By directly connecting the sources of two MOSFETs as an internal node, current can flow smoothly from the battery to the system's main power rail through the channels of the two MOSFETs when the circuit is on. When off, the floating characteristic of the intermediate source node enhances the blocking effect. This connection method ensures that the circuit can precisely adjust the on-resistance by controlling the gate potential in bidirectional current scenarios, including battery discharge and external reverse charging. This effectively reduces conduction losses, improves power conversion efficiency, simplifies PCB layout and routing complexity, and enhances the stability and anti-interference capability of the power circuit.

[0041] Furthermore, the gates of both the first and second P-channel MOSFETs are connected to the output of the logic control circuit. This electrical connection enables synchronous driving and consistent state control of the two transistors. Since the drive signal output by the logic control circuit acts simultaneously on the gates of both P-channel MOSFETs, the two switching devices can be turned on or off synchronously in the same timing sequence, avoiding the risk of accidental conduction of the body diode or current runaway caused by single-transistor driving.

[0042] This parallel-gate control strategy ensures that the two MOSFETs can work together as a single unit during complex switching transitions, maintaining the integrity of the power path. Whether during the transient process of system startup or the shutdown process, synchronous drive prevents unnecessary voltage spikes or current backflow, thus ensuring the reliability of the power management system and preventing device damage or system malfunctions caused by asynchronous drive.

[0043] In some embodiments of this application, the isolation diode array includes three input branches, which are respectively connected to the first contact channel of the double-pole self-resetting switch, the sustain signal output terminal of the power management unit, and the external power supply access detection terminal. Each input branch is unidirectionally isolated by diodes to construct a pure hardware-level OR gate logic circuit for integrating trigger signals from different sources.

[0044] By utilizing the unidirectional conductivity of diodes, this array can physically isolate and logically integrate the power-on pulse generated by the button, the sustain signal issued by the system software, and the detection signal of external power supply insertion. This ensures that any signal input can independently trigger subsequent circuits without causing current backflow or signal interference between different voltage domains. This design not only achieves seamless integration of multi-source triggering mechanisms but also greatly simplifies the control logic, enabling the system to flexibly respond to manual operations and changes in the external environment without relying on complex software intervention, thus providing a fundamental guarantee for the reliability of power management.

[0045] Furthermore, the common output of the isolation diode array is connected to the base of the driver transistor, and the collector of the driver transistor is connected to the gate of the bidirectional MOS switch, establishing a signal amplification drive stage that converts weak logic level signals into driving capabilities capable of controlling high-power MOS transistors. The driver transistor acts as an electronic switch here; its base receives the aggregated signal from the diode array, while its collector directly controls the gate potential of the bidirectional MOS switch.

[0046] This connection method allows the logic control circuit to precisely control the switching of high-current power circuits with a small input current, achieving electrical isolation and impedance matching between the control and power terminals. This design not only improves the load-carrying capacity of the drive signal but also ensures that the bidirectional MOS switch can respond quickly and accurately to control commands through the switching characteristics of the transistor, avoiding overheating or instability of the MOS transistor due to insufficient drive capability.

[0047] Furthermore, the gate of the bidirectional MOS switch is also connected to a first pull-up resistor, the other end of which is connected to the power supply terminal, providing a defined static bias potential to the gate of the bidirectional MOS switch, ensuring that the power switch is in a reliable off state when it is not triggered.

[0048] Because the driving transistor uses an open-collector output structure, it cannot actively output a high level in the off state. The first pull-up resistor's function is to pull the gate potential high to the power supply voltage, thereby ensuring that the P-channel bidirectional MOS switch remains off when the system is in standby or powered off, preventing false turn-on due to induced voltage caused by a floating gate. This design eliminates circuit uncertainties, ensures system safety in low-power mode, and prevents battery power loss due to accidental conduction, making it a key guarantee for achieving microampere-level ultra-low standby power consumption.

[0049] Furthermore, the driving transistor is used to conduct to ground when any branch of the isolation diode array is turned on, thereby pulling down the gate potential of the bidirectional MOS switch. This step describes the specific execution logic for activating the power supply path of the system, that is, turning on the main power circuit through the potential reversal mechanism.

[0050] When any input branch (such as a button press or external power supply connection) is turned on, current flows into the base of the driving transistor, causing it to saturate and conduct, thereby pulling the gate potential of the bidirectional MOS switch down to near ground. Since the bidirectional MOS switch is composed of a P-channel MOS transistor, a low gate level means that the gate-source voltage difference meets the conduction condition, thus turning on the MOS transistor and allowing the battery or external power supply to power the system. This process realizes the conversion from logic signal to power action, ensuring that the system can quickly establish a power supply path as long as any trigger condition is met, achieving flexibility and immediate response in power management.

[0051] In some embodiments of this application, the power-on trigger terminal of the host system is connected to a second pull-up resistor, which is connected to a preset voltage domain to establish a stable static high-level reference for the power-on signal line, preventing the system from malfunctioning due to a floating signal.

[0052] In digital circuit logic, floating input pins are highly susceptible to electromagnetic interference, resulting in unpredictable level transitions and potentially causing system logic malfunctions. By introducing a second pull-up resistor, the power-on trigger pin is forced to a high level within a preset voltage range when inactive. This not only ensures signal determinism and anti-interference capabilities but also provides the necessary potential difference for subsequent button triggering. This design is essential for ensuring the motherboard power management controller can accurately recognize the power-on command, guaranteeing the system's logic stability in standby mode and preventing the risk of accidental power-on or system crashes caused by floating pins.

[0053] Furthermore, the second contact channel of the double-pole self-resetting switch is turned on when the button is pressed, shorting the power-on trigger terminal of the host system to ground, causing the power-on trigger terminal to generate a high-to-low level transition pulse, which is used to trigger the motherboard power management controller to enter the power-on sequence, and generate a standard hardware interrupt signal through physical short circuit to wake up the motherboard logic in hibernation.

[0054] When the user presses a button, the second contact channel closes. Utilizing the potential difference between the second pull-up resistor and ground, a clear falling edge signal is instantaneously generated at the power-on trigger. This high-to-low transition pulse is crucial for the motherboard power management controller to recognize the user's power-on intention. It directly triggers the internal state machine to enter the power-on initialization process, activating the voltage regulation module and clock circuit. This hardware-level triggering mechanism offers fast response and high reliability, ensuring the system can accurately and promptly transition from the power-off state to the operating state, achieving seamless integration between user operation and system response.

[0055] In some embodiments of this application, the power management unit is also used to detect long press events of the double-pole self-resetting switch. The threshold for judging long press events is 3 to 8 seconds. The duration of the button press is precisely quantified and logically judged by software algorithms, thereby multiplexing the two completely different functions of power on and power off on a single physical button, effectively preventing the risk of accidental power off caused by user accidental touch or button vibration.

[0056] Because the dual-pole self-resetting switch is a momentary switch in physical characteristics, the power management unit continuously monitors the duration of the button input signal level through an internal timer. Only when the pressing duration exceeds a preset threshold of 3 to 8 seconds is the system recognized as a valid shutdown command. This time-based determination mechanism not only realizes the intelligence of human-computer interaction logic but also ensures the stability of the system during operation. Short presses only serve as trigger signals, while long presses serve as control signals for system state switching, greatly improving the fault tolerance and user experience.

[0057] Furthermore, when a long press event is detected and the power-off conditions are met, the power management unit withdraws the sustain signal, and the logic control circuit shuts off the drive signal, causing the bidirectional MOS switch to turn off, cutting off the connection between the battery and the system's main power rail. The standby current of the entire device drops below 1uA, thus constructing a hardware and software collaborative deep sleep and zero-power protection mechanism, which completely solves the problem of battery dark current loss that still exists in traditional electronic devices after power-off.

[0058] Once the power management unit confirms the shutdown intention, it actively withdraws the hold signal output to the logic control circuit. This causes the OR gate logic circuit, composed of an isolation diode and a driving transistor, to lose its high-level input, thereby turning off the driving transistor. The gate potential of the bidirectional MOS switch is then pulled up by the pull-up resistor, turning it off. This chain reaction completely disconnects the electrical connection between the battery and the main load of the system at the physical level, eliminating all static leakage paths. This ensures that the power consumption of the entire device in the shutdown state depends only on the physical characteristics of the battery itself, achieving true microampere or even nanoampere standby, significantly extending the device's storage life and battery life.

[0059] In some embodiments of this application, the system architecture integrates a key functional module called a charging management circuit. The input of this circuit is electrically connected to an external power interface, creating an independent and efficient energy access and conversion channel. By directly connecting the charging management circuit to the external power interface, the system gains the ability to identify, regulate, and distribute external electrical energy. It not only converts unstable external input voltages into stable voltages suitable for system operation and battery charging, but also undertakes safety responsibilities such as overvoltage protection, overcurrent protection, and temperature monitoring.

[0060] The establishment of this hardware connection means that the entire power management system no longer relies solely on battery power, but forms a dual-energy supply system that combines internal and external power. This provides a physical basis for subsequent automatic wake-up, power path switching, and battery charging and discharging management, greatly enhancing the device's adaptability and battery life in different usage scenarios.

[0061] When an external power source is successfully plugged in, the charging management circuit immediately detects this physical event and outputs a high-level signal to the third input of the logic control circuit. This signal interaction translates the external power supply connection status into digital logic, serving as a trigger command for system state switching. The third input is specifically designed to receive this particular external power supply status signal, enabling the logic control circuit to distinguish between a manual button press and a system wake-up caused by external power supply connection.

[0062] This signal transmission not only signifies that energy supply is ready, but also represents a transfer of control, informing the logic control circuit that the system is now ready to prioritize the use of external power. Through this explicit signal definition and transmission mechanism, the system establishes the ability to perceive changes in the external environment, providing a basis for decision-making in realizing intelligent power management strategies and ensuring that the system can adjust its internal operating mode in a timely manner according to energy availability.

[0063] Upon receiving a high-level signal from the third input terminal, the logic control circuit executes the instruction to prioritize the conduction of the bidirectional MOS switch, thereby establishing a charging and power supply path. This achieves intelligent power path allocation and rapid establishment of physical pathways. As the core component of power control, the conduction state of the bidirectional MOS switch directly determines the energy flow. By controlling its gate voltage, the logic control circuit keeps it in a low-impedance conduction state, thus constructing a low-loss energy transmission channel between the external power supply, the battery, and the system load.

[0064] This path serves a dual purpose: firstly, it allows external power to directly supply power to the various functional modules within the system, ensuring normal equipment operation; secondly, it provides a charging circuit for the battery, enabling it to be recharged while the system is running. This simultaneous establishment of dual paths optimizes energy utilization efficiency, avoids unnecessary losses during energy conversion, and ensures stable power supply and efficient charging.

[0065] Regardless of whether the double-pole self-resetting switch is pressed, the logic control circuit will execute the aforementioned priority conduction operation, breaking the absolute dependence of traditional power control on mechanical buttons and realizing unconditional automatic wake-up and power supply when an external power source is connected. In traditional systems, devices typically require the user to manually press the power button to start the power supply. However, in this application, the connection of an external power source itself has the same or even higher wake-up authority as a button. This means that even if the device is completely powered off and the user has not performed any button operation, as long as the charger is plugged in, the system can automatically recognize and start the power supply process.

[0066] This feature greatly enhances the user experience, especially after the device shuts down due to depleted battery. Users no longer need to repeatedly press buttons to wait for it to power on; they can simply connect to a power source to immediately resume use or charge. Simultaneously, this reflects the system's priority design principle for logic control: external power access takes precedence over local human operation, ensuring that the device can immediately enter working or charging mode when power supply is restored, achieving true "plug and play" and intelligent power management.

[0067] In some embodiments of this application, the logic control circuit is configured to immediately turn on the bidirectional MOS switch the instant the first contact channel of the double-pole self-resetting switch is turned on, thereby achieving zero-delay response during system startup and establishing an efficient energy path. The double-pole self-resetting switch, acting as a physical button for user interaction, signifies that the user has issued a power-on or wake-up command upon the closure of its first contact channel. The instantaneous capture and processing of this signal by the logic control circuit demonstrates the system's high sensitivity to human operation. By turning on the bidirectional MOS switch at this instant, the system rapidly utilizes the extremely low on-resistance of the MOS transistor, replacing the traditional method of directly carrying large currents with mechanical switches, thus avoiding the arcing problem that may occur when mechanical contacts are connected to large currents.

[0068] More importantly, this action quickly establishes the main circuit for supplying power to the system load from the battery or external power source, enabling voltage to be rapidly built up and supplied to the back-end circuits. This ensures that the processor and various sensors can obtain operating voltage immediately. This design cleverly transforms the trigger signal of the mechanical button into the control signal of the electronic switch, retaining the tactile feel of the physical button while leveraging the high efficiency and stability of semiconductor switches in power transmission, thus laying a solid foundation for the system's rapid startup.

[0069] Furthermore, the power management unit is configured to output a sustain signal to the second input of the logic control circuit after detecting system power-on, thereby taking over the conduction control of the bidirectional MOS switch and achieving a smooth transfer of control from "triggered startup" to "continuous operation," thus constructing an intelligent power management closed loop. When the system completes its initial power-on, the power management unit, acting as the system's brain, begins monitoring the stability of the voltage rails and the status of the software operation. Once it confirms that the system has started normally, it sends a sustain signal to the logic control circuit through the second input, which is essentially an electronic implementation of a "self-locking" mechanism.

[0070] This change transforms the on / off state of the bidirectional MOS switch from being mechanically held by an external button to being held by an internal logic level. This takeover of control means the system no longer requires the user to hold down the button to maintain power, but instead enters an autonomous operating state. It not only improves the system's automation level but also allows the power management unit to dynamically adjust power strategies based on internal parameters such as battery level and load demand. This provides a flexible control interface for subsequent standby, hibernation, or shutdown logic, making it a key element in achieving low-power management in modern electronic devices.

[0071] Furthermore, the sustaining signal is configured to remain on when the double-pole resettable switch disconnects due to its resettable characteristic. This overcomes the power interruption caused by the resettable characteristic of the double-pole resettable switch, ensuring stable system operation. Electronic logic compensates for the physical limitations of mechanical components, resolving the contradiction between transient button presses and continuous power supply requirements. Double-pole resettable switches are typically designed as momentary switches or have an automatic reset function, meaning that when the user presses and releases the switch, the contacts automatically spring open and disconnect. If such a switch is used directly to control the main power supply, the circuit will be de-energized the moment the button is released, causing the system to repeatedly restart or malfunction.

[0072] The introduction of a sustain signal addresses this physical limitation. At the instant the mechanical contacts open, a feedback loop within the logic circuit continues to provide drive voltage to the gate of the bidirectional MOS switch. This is analogous to an invisible hand continuing to hold the switch after the user releases their button, allowing current to flow continuously through the MOS transistor unaffected by the mechanical switch opening. This design not only ensures stable and continuous system operation after the user releases the button, preventing data loss or hardware damage due to power supply fluctuations, but also significantly enhances the user experience, making the device's operating logic align with users' expectations of "one-button power-on and continuous operation" for electronic products.

[0073] In some embodiments of this application, the external power interface is connected to the system's main power rail via a reverse-current protection diode. This utilizes the unidirectional conductivity of semiconductor devices to ensure absolute safety in energy flow. The reverse-current protection diode is connected in series between the external power input and the system's main power rail. Its forward conduction and reverse cutoff characteristics ensure that current can only flow from the external interface to the system interior, and reverse flow is strictly prohibited. This design effectively prevents the reverse leakage of electrical energy stored in the battery within the system through the external interface when the external power supply is not connected or its voltage is lower than the battery voltage. This avoids unnecessary energy loss from the battery and potential interface damage or safety hazards caused by external discharge.

[0074] At the same time, the diode also plays a preliminary role in voltage isolation, separating the unstable external power supply environment from the internal precision power rail, providing the first line of defense for subsequent voltage regulation and distribution, and ensuring that the main power rail of the system can maintain relative independence and stability when faced with external plug-in transients or voltage fluctuations.

[0075] Furthermore, when an external power source is connected, the system prioritizes power from the external source, establishing a priority principle in the power management strategy: fully utilizing continuous external energy to ensure equipment operation and conserve valuable battery reserves. Since external power sources typically have unlimited energy supply capacity and higher voltage levels, the system automatically switches the load's power supply path to the external power source after detecting its presence through voltage comparison or logic control circuitry.

[0076] This priority power supply mechanism not only meets the system's power demands during high-load operation, preventing battery overheating and lifespan degradation under high-current discharge, but also allows the battery to "rest" and no longer bear the burden of power supply. This design greatly optimizes energy efficiency, ensuring that the device can operate at its best performance when connected to a power source, while reserving maximum battery power for unforeseen needs, embodying the energy-saving and protection concept of "external power priority" in intelligent power management.

[0077] Simultaneously, the battery is charged via a bidirectional MOS switch. Leveraging the low on-resistance and high controllability of MOS transistors, a highly efficient and controllable energy replenishment channel is established while an external power supply is provided. Unlike traditional diode charging circuits, the bidirectional MOS switch is controlled by logic circuits to conduct in charging mode. Its extremely low internal resistance significantly reduces voltage drop and power loss in the charging circuit, reducing heat generation and thus improving charging efficiency.

[0078] At this point, part of the energy from the external power supply is used to power the system load, while the other part flows through the MOS switch to the battery, achieving constant current or constant voltage replenishment of the battery. The introduction of the bidirectional MOS switch makes the charging process more intelligent. It can not only adjust the conduction level according to the battery's voltage state, but also quickly cut off the circuit after it is fully charged to prevent overcharging. This design enables parallel processing of power supply and charging, ensuring that the device can work normally and quickly restore battery power when plugged in.

[0079] This architecture not only extends the battery life of devices in mobile scenarios, but more importantly, it provides power outage protection, preventing data loss or system crashes caused by sudden power outages. This greatly improves the stability of electronic devices and the user experience, making it an ideal paradigm for power supply design in modern portable electronic products.

[0080] In some embodiments of this application, the logic control circuit further includes a fourth input branch, which is connected to the control output terminal of the host CPU to support software-triggered power on / off control. This elevates the power management control from a purely hardware logic level to an intelligent software system level, giving the device's "brain" the ability to directly manage its own energy.

[0081] By establishing a direct communication link between the host CPU and the underlying logic control circuitry, the system no longer relies solely on passive events such as physical buttons or external power supply insertion to trigger power on / off. Instead, the operating system or applications running on the processor are allowed to proactively initiate power control commands based on complex business logic, user settings, or system status. This design achieves deep integration of hardware and software, making power management no longer an isolated circuit behavior but a programmable and schedulable functional module within the entire system ecosystem. This lays the physical foundation for highly intelligent power strategies in devices.

[0082] Furthermore, the CPU can output specific level signals or pulse sequences through its general-purpose input / output ports or dedicated control pins. These signals are transmitted to the logic control circuit via the fourth input branch, thereby changing the state of the power switch. When the software determines that the system needs to be shut down—for example, when the user clicks the power button on the screen, or when the system detects prolonged inactivity and needs to enter hibernation—the CPU sends a control signal through this branch, forcing the logic control circuit to cut off the conduction path of the bidirectional MOS switch, thus cutting off the system's main power supply. Conversely, in standby mode, the CPU can also send a wake-up signal through this branch, or trigger power-on at a predetermined time in conjunction with the real-time clock module. This mechanism makes power on / off extremely flexible, no longer constrained by the physical location of the mechanical switch or manual operation by the user, enabling remote control and automated management.

[0083] Furthermore, software-triggered power on / off control greatly enriches the device's functionality and user experience. First, it enables "soft shutdown," allowing the CPU sufficient time to perform cleanup tasks such as data saving, file system unloading, and peripheral reset before cutting off mains power, thus avoiding the risk of data corruption from forced power outages. Second, this mechanism is key to advanced power management features, such as timed automatic power on / off, automatic low-battery shutdown, and remote wake-up via network commands. In case of device malfunction or crash, the software can also attempt to reset the power management logic through this branch for self-repair. In addition, combined with operating system-level power management strategies, the system can dynamically adjust its power supply based on the current workload, such as automatically entering deep sleep mode after background tasks are completed, thereby significantly reducing standby power consumption and extending battery life.

[0084] In some embodiments of this application, reference is made to Figure 1 and Figure 2 When the user presses the double-pole self-reset button, pins 3 and 4 of the JP300 (these two pins are connected to one channel of the double-pole self-reset switch) are shorted, and the network PWRON_L is pulled low. Figure 2 The discrete components operate, causing the EN_VSYS output to reach an enable level. When the system power is on, the PMU outputs the enable signal PMIC_EXT_EN_OUT to the base of Q305 to lock the power-on circuit.

[0085] Additionally, pins 5 and 6 of JP300 (these two pins are connected to another channel of the double-pole self-resetting switch) will also be shorted. Network BIGBAT_8V4 is the battery voltage, which will be shorted with network BATTY_L. BATTY_L will enable Q407, causing the bidirectional MOSFET to conduct and the battery to be connected to the system for power supply. Figure 3 The five diodes D1802, D405, D406, D407, and D410 form an OR gate, which can control the bidirectional MOSFET to turn on through the PMU output, 12V power supply input, double-pole self-reset button press, and CPU output.

[0086] The system can be shut down via buttons and operating system software. When a button is pressed for more than 6 seconds, or a button is pressed once and then the system is selected to shut down, the PMU will detect this and then turn off the IO output. Q407 and Q305 will be cut off, thereby disconnecting the battery from the system. The system power enable signal will also be turned off.

[0087] Secondly, refer to Figure 3 This application provides a low-power power management method based on a dual-pole self-resetting switch, applied to the power management system described above, including the following steps.

[0088] In step S100, a short press of the double-pole self-resetting switch closes the first contact channel, inputting a high level to the logic control circuit. The second contact channel closes, pulling down the power-on trigger terminal of the host system. The logic control circuit then turns on the bidirectional MOS switch, and the system powers on and starts up.

[0089] In step S100, the system utilizes the dual-path parallel triggering mechanism of the double-pole self-resetting switch to input a high-level wake-up command to the logic control circuit through the first contact channel, while simultaneously using the second contact channel to pull down the host power-on trigger terminal, simulating the processor power-on signal, thus achieving synchronous response between the hardware and the main control chip. This dual confirmation mechanism not only effectively prevents accidental touches caused by single-path signal interference, but also drives the logic circuit to quickly turn on the bidirectional MOS switch, utilizing its low impedance characteristics to establish the main power supply path, instantly delivering battery energy to the load, completing the physical switch from power failure to operation, and providing a stable energy foundation for system software initialization.

[0090] In step S200, after the system is powered on, the power management unit outputs a sustaining signal to the logic control circuit. The logic control circuit locks the conduction state of the bidirectional MOS switch based on the sustaining signal. At this time, the double-pole self-resetting switch is released, and the system maintains normal power supply.

[0091] In step S200, the system takes over control through the sustain signal output by the power management unit, and uses a logic control circuit to construct a feedback loop to replace the physical holding of the mechanical switch, thus achieving a smooth transfer of power supply self-locking and control. This mechanism forms an electronic self-locking after the system voltage is established. Even if the double-pole self-resetting switch is reset and opened, it can still force the bidirectional MOS switch to remain in the conducting state, thereby overcoming the limitation of mechanical switches being disconnected as soon as they are released. This ensures power supply continuity and prevents the system from repeatedly restarting, marking the official entry of the equipment into a stable operation phase dominated by software, and laying the foundation for the execution of complex power management strategies.

[0092] In step S300, the double-pole self-recovery switch is pressed and held for a preset duration threshold. The power management unit recognizes the long-press signal and executes the shutdown procedure. Then, the sustain signal is withdrawn, the logic control circuit turns off the bidirectional MOS switch, and the system is completely powered off and enters a low-power standby state.

[0093] In step S300, the system establishes a safe and orderly forced shutdown process through long-press detection and software collaboration mechanism, effectively distinguishing between shutdown commands and accidental touch interference using a preset duration threshold. Once the shutdown request is confirmed, the system prioritizes data saving and peripheral reset procedures to ensure data integrity and hardware security. Subsequently, the power management unit withdraws the sustain signal, drives the logic control circuit to turn off the bidirectional MOS switch, and completely cuts off the main power supply circuit, allowing the device to smoothly transition to a microampere-level low-power standby state, achieving a reliable exit from operation to hibernation.

[0094] In step S400, when an external power source is connected, the logic control circuit automatically turns on the bidirectional MOS switch to establish a charging circuit to charge the battery. If the system is in a power-off state, the power-on process is not triggered. If the system is in a running state, the system switches to the external power priority mode.

[0095] In step S400, the system detects the external power supply status through a logic control circuit, automatically activates the bidirectional MOS switch to establish a charging circuit independently of button operation, and executes differentiated power management strategies based on the device's operating status. In the off state, the system only provides background power without waking the host, avoiding accidental triggering and interference; in the running state, it switches to an external power priority mode, using external power to replace battery power to reduce battery wear. This intelligent energy scheduling mechanism achieves seamless coordination between power supply and charging, significantly improving the device's battery life and user experience.

[0096] In summary, the embodiments of this application provide a low-power power management system and method based on a dual-pole self-resetting switch, which has the following technical effects.

[0097] This technical solution achieves hardware-level isolation between the power-on trigger and logic control signals. Combined with a soft OR gate logic circuit constructed from a diode array and NMOS transistors, it effectively solves the signal coupling and interference problems of traditional single-contact switches. The first contact channel sends a clean start command to the logic control circuit, while the second contact channel independently pulls low the host system's power-on trigger terminal. Their collaborative operation ensures the reliability and anti-interference capability of the system startup. Furthermore, the sustain signal output by the power management unit takes over power supply control, overcoming the power-off problem caused by mechanical switch reset using an electronic self-locking mechanism. This not only eliminates the reliance on continuous button pressing but also, thanks to the low impedance and bidirectional blocking characteristics of the back-to-back cascaded dual PMOS transistor structure, significantly reduces static power consumption while preventing current backflow, thus constructing a stable, efficient, and intuitive one-button start continuous power supply operation mode.

[0098] This technical solution further establishes a safe and orderly forced shutdown process through long-press recognition and software collaboration, ensuring data integrity while achieving a smooth transition to a low-power standby state. The preset duration threshold effectively prevents accidental touch interference, while the program execution phase before shutdown allows the host CPU time for data saving and peripheral reset, avoiding hardware damage or data loss caused by forced power outages. Furthermore, the system possesses intelligent external power identification and path management capabilities, automatically switching power supply strategies based on device status. During shutdown, it only provides background power without waking the system, while during operation, it prioritizes external power to protect battery life. This dual-source architecture, prioritizing external power and providing battery backup, significantly improves energy efficiency and device battery life, achieving a high degree of integration and intelligence in power management.

[0099] It should be noted that in all specific embodiments of this application, all data processing activities related to user identity or personal characteristics, such as user information, user behavior data, historical data, and location information, will be conducted in accordance with the principles of legality, legitimacy, and necessity. All data collection, use, storage, and processing will be subject to compliance with applicable national and regional laws, regulations, and industry standards, and informed consent from users will be obtained in a clear and explicit manner before processing. For the processing of sensitive personal information, separate consent from users will be obtained through prominent means such as pop-up prompts and independent confirmation pages. If any processing conflicts with laws and regulations, the laws and regulations will prevail, and necessary data processing will only be carried out within the scope permitted by laws and regulations, ensuring that all data-based applications, analyses, and technical implementations are conducted within the scope permitted by laws and regulations.

[0100] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this application are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and sub-operations described as part of a larger operation are executed independently.

[0101] Furthermore, although this application is described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding this application. Rather, given the properties, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of the module will be understood within the scope of ordinary skill of an engineer. Therefore, those skilled in the art can implement the application set forth in the claims using ordinary skill. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of this application, which is determined by the full scope of the appended claims and their equivalents.

[0102] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several programs to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0103] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequential list of executable programs for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, a program execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can retrieve and execute a program from or in conjunction with such a program execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can mean any means that can contain, store, communicate, propagate, or transmit a program for use by or in conjunction with a program execution system, apparatus, or device.

[0104] More specific examples (a non-exhaustive list) of computer-readable media include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Additionally, computer-readable media can even be paper or other suitable media on which programs can be printed, for example, by optically scanning the paper or other media, then editing, interpreting, or, if necessary, processing it in a suitable manner to obtain the program electronically, and then storing it in computer memory.

[0105] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable program execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0106] In the foregoing description of this specification, the reference to terms such as "one embodiment / implementation," "another embodiment / implementation," or "certain embodiments / implementations," etc., indicates that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in an embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0107] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0108] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.

Claims

1. A low-power power management system based on a double-pole self-resetting switch, characterized in that, include: The double-pole self-resetting switch has a first contact channel and a second contact channel that are triggered by the same button. One end of the first contact channel is connected to the positive terminal of the battery, and the other end is connected to the first input terminal of the logic control circuit. One end of the second contact channel is grounded, and the other end is connected to the power-on trigger terminal of the host system. A bidirectional MOS switch is connected in series between the positive terminal of the battery and the main power rail of the system. The logic control circuit is implemented by a discrete OR gate logic consisting of an isolation diode array and a driving transistor. Its first input terminal is connected to the first contact channel of the double-pole self-resetting switch, its second input terminal is connected to the sustain signal output terminal of the power management unit, its third input terminal is connected to the external power supply access detection terminal, and its output terminal is connected to the control terminal of the bidirectional MOS switch. The logic control circuit is configured to: output a drive signal to turn on the bidirectional MOS switch when the first contact channel is detected to be on, or when the power management unit outputs a sustain signal, or when an external power supply is connected; when the first contact channel is detected to be on, the bidirectional MOS switch is turned on first, and after the power management unit outputs a sustain signal, the bidirectional MOS switch is kept on based on the sustain signal to achieve system power supply self-locking.

2. The low-power power management system based on a double-pole self-resetting switch according to claim 1, characterized in that, The bidirectional MOS switch is composed of two P-channel MOS transistors connected in series back to back, including a first P-channel MOS transistor and a second P-channel MOS transistor. The source of the first P-channel MOSFET is connected to the source of the second P-channel MOSFET. The drain of the first P-channel MOSFET is connected to the battery terminal, and the drain of the second P-channel MOSFET is connected to the main power rail of the system. The gates of both the first P-channel MOSFET and the second P-channel MOSFET are connected to the output terminal of the logic control circuit.

3. A low-power power management system based on a double-pole self-resetting switch according to claim 1, characterized in that, The isolation diode array includes three input branches, which are respectively connected to the first contact channel of the double-pole self-resetting switch, the sustain signal output terminal of the power management unit, and the external power supply access detection terminal. Each input branch is unidirectionally isolated by diodes. The common output terminal of the isolation diode array is connected to the base of the driving transistor, and the collector of the driving transistor is connected to the gate of the bidirectional MOS switch. The gate of the bidirectional MOS switch is also connected to a first pull-up resistor, and the other end of the first pull-up resistor is connected to the power supply terminal. The driving transistor is used to conduct to ground when any branch of the isolation diode array is turned on, thereby pulling down the gate potential of the bidirectional MOS switch.

4. A low-power power management system based on a double-pole self-resetting switch according to claim 1, characterized in that, The power-on trigger terminal of the host system is connected to a second pull-up resistor, which is connected to a preset voltage domain. The second contact channel of the double-pole self-resetting switch is turned on when the button is pressed, shorting the power-on trigger terminal of the host system to ground, causing the power-on trigger terminal to generate a high-to-low level transition pulse, which is used to trigger the motherboard power management controller to enter the power-on sequence.

5. A low-power power management system based on a double-pole self-resetting switch according to claim 1, characterized in that, The power management unit is also used to detect long-press events of the double-pole self-recovery switch, wherein the threshold for determining the long-press event is 3 to 8 seconds; When a long press event is detected and the power-off conditions are met, the power management unit withdraws the sustain signal, and the logic control circuit then shuts off the drive signal, causing the bidirectional MOS switch to turn off and disconnecting the battery from the system's main power rail.

6. A low-power power management system based on a double-pole self-resetting switch according to claim 1, characterized in that, The system also includes a charging management circuit, the input of which is connected to an external power supply interface; When an external power source is plugged in, the charging management circuit outputs a high-level signal to the third input terminal of the logic control circuit. The logic control circuit preferentially turns on the bidirectional MOS switch to establish a charging and power supply path, regardless of whether the double-pole self-resetting switch is in the pressed state.

7. A low-power power management system based on a double-pole self-resetting switch according to claim 1, characterized in that, The logic control circuit is configured to turn on the bidirectional MOS switch at the instant the first contact channel of the double-pole self-resetting switch is turned on; The power management unit is configured to: after detecting that the system is powered on, output the sustain signal to the second input terminal of the logic control circuit, and take over the conduction control of the bidirectional MOS switch; The sustaining signal is configured to remain on when the double-pole self-resetting switch is disconnected due to its self-resetting characteristic, so as to overcome the power interruption caused by the self-resetting characteristic of the double-pole self-resetting switch and ensure stable system operation.

8. A low-power power management system based on a double-pole self-resetting switch according to claim 6, characterized in that, The external power interface is connected to the system's main power rail via an anti-reverse-feedback diode; When an external power source is connected, the system is powered by the external power source first, while the battery is charged through the bidirectional MOS switch, forming a dual-source power supply architecture with external power priority and battery backup.

9. A low-power power management system based on a double-pole self-resetting switch according to claim 1, characterized in that, The logic control circuit also includes a fourth input branch, which is connected to the control output terminal of the host CPU and is used to support software-triggered power on / off control.

10. A low-power power management method based on a double-pole self-resetting switch, applied to a power management system as described in any one of claims 1 to 9, characterized in that, Includes the following steps: A short press of the double-pole self-resetting switch closes the first contact channel, inputting a high level to the logic control circuit, and closes the second contact channel, pulling down the power-on trigger terminal of the host system. The logic control circuit then turns on the bidirectional MOS switch, and the system powers on and starts up. After the system is powered on, the power management unit outputs a sustain signal to the logic control circuit. The logic control circuit locks the conduction state of the bidirectional MOS switch based on the sustain signal. At this time, the double-pole self-resetting switch is released, and the system maintains normal power supply. When the dual-pole self-recovery switch is pressed and held for a preset duration threshold, the power management unit recognizes the long press signal and executes the shutdown procedure. Then, the sustain signal is withdrawn, the logic control circuit turns off the bidirectional MOS switch, the system is completely powered off, and enters a low-power standby state. When an external power source is connected, the logic control circuit automatically turns on the bidirectional MOS switch to establish a charging circuit to charge the battery. If the system is in a shutdown state, it will not trigger the power-on process. If the system is in a running state, it will switch to the external power priority mode.

Images