A wide input dc voltage automatic switching power supply circuit

Abstract

The application relates to the field of power supply control and discloses a wide-input direct-current voltage automatic switching power supply circuit; the circuit comprises an input end, an output end, a PMOS bypass branch, a DC-DC Buck voltage reduction branch, a voltage comparison unit, a delay conduction unit and a delay unlocking unit. The voltage comparison unit samples the input end voltage and outputs a switching control signal according to the comparison result of the input end voltage and a first switching threshold value and a second switching threshold value; when the input end voltage is higher than the first switching threshold value, the PMOS bypass branch is cut off, and the output end is powered by the DC-DC Buck voltage reduction branch; when the input end voltage is lower than the second switching threshold value, the switching control signal acts on the PMOS bypass branch through a control channel formed by the delay conduction unit and the delay unlocking unit, so that the output end is powered by the PMOS bypass branch. The first switching threshold value is greater than the second switching threshold value, so as to form a back difference control. The application further sets a power-off automatic reset delay unit for releasing residual charges of a delay capacitor, so that the delay is re-timed when power is supplied again.

Description

Technical Field

[0001] This invention relates to the field of power supply control, and more specifically to a wide input DC voltage automatic switching power supply circuit. Background Technology

[0002] In industrial control, embedded computers, and servo control equipment, DC power supplies are often required to power the motherboard, processor, and peripheral loads. Since common input voltages in different application scenarios include 12V, 19V, and 24V, the power supply input typically needs to have a wide DC input adaptability to meet the usage requirements of different power supply environments.

[0003] In existing wide-range DC input power supply solutions, buck-boost or buck power supply chips are typically used to achieve constant voltage output. Buck-boost solutions can cover a wide input range, but they have a large number of power stage devices, resulting in higher circuit area and cost. When the input voltage is close to the output voltage, power may still be supplied through the power conversion path, leading to increased conduction and conversion losses.

[0004] As processor and motherboard power consumption increases, the startup current requirement under low-voltage input conditions also increases. If the low-voltage input still passes through a power conversion path with significant losses, the voltage drop between the input and output terminals will weaken the startup power supply available to the load, easily leading to startup power failures or repeated restarts. Therefore, how to balance low-loss power supply under low-voltage input and stable step-down power supply under higher input conditions over a wide range of DC input conditions is a technical problem that needs to be solved. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a wide-input DC voltage automatic switching power supply circuit to solve the technical problems existing in the prior art.

[0006] The above-mentioned technical objective of the present invention is achieved through the following technical solution:

[0007] A wide input DC voltage automatic switching power supply circuit includes:

[0008] Input terminal, output terminal, PMOS bypass branch, DC-DCBuck buck branch, voltage comparator unit, delayed turn-on unit and delayed unlock unit;

[0009] The input terminal is used to connect a wide range of DC input voltages. The PMOS bypass branch is connected between the input terminal and the output terminal. The input side of the DC-DCBuck buck branch is connected to the input terminal, and the output side of the DC-DCBuck buck branch is connected to the output terminal.

[0010] The PMOS bypass branch includes a PMOS transistor and a gate control node connected to the gate of the PMOS transistor.

[0011] The voltage comparison unit has a sampling input terminal and a switching control signal output terminal. The sampling input terminal is connected to the input terminal, and the switching control signal output terminal is connected to the delayed unlocking unit and the PMOS bypass branch respectively.

[0012] The delayed turn-on unit has a turn-on signal output terminal, which is connected to the delayed unlock unit.

[0013] The delayed unlocking unit is connected between the switching control signal output terminal of the voltage comparison unit and the gate control node;

[0014] When the wide-range DC input voltage is higher than the first switching threshold, the switching control signal output terminal of the voltage comparator unit outputs the first level. The first level acts on the gate control node, causing the PMOS bypass branch to be cut off and the output terminal to be powered by the DC-DCBuck step-down branch.

[0015] When the wide-range DC input voltage is lower than the second switching threshold, the switching control signal output terminal of the voltage comparison unit outputs the second level. The second level acts on the gate control node through the control path formed by the delayed turn-on unit and the delayed unlock unit, so that the PMOS bypass branch is turned on and the output terminal is powered by the PMOS bypass branch.

[0016] The first switching threshold is greater than the second switching threshold.

[0017] Preferably, the PMOS bypass branch further includes a first pull-up resistor and a first gate capacitor;

[0018] The source of the PMOS transistor is connected to the input terminal, and the drain of the PMOS transistor is connected to the output terminal.

[0019] The first pull-up resistor is connected between the input terminal and the gate control node;

[0020] The first gate capacitor is connected between the input terminal and the gate control node.

[0021] Preferably, the circuit further includes an anti-backflow circuit;

[0022] The backflow prevention circuit is connected in series between the output side and the output terminal of the DC-DCBuck step-down branch;

[0023] The drain of the PMOS transistor and the output side of the anti-backflow circuit are both connected to the output terminal.

[0024] Preferably, the voltage comparison unit includes a reference source, an input voltage divider branch, a first comparator, a second comparator, and a feedback resistor;

[0025] The input voltage divider branch is connected between the input terminal and the ground terminal, and the voltage divider node of the input voltage divider branch is connected to the non-inverting input terminal of the first comparator.

[0026] The output terminal of the reference source is connected to the inverting input terminal of the first comparator and the inverting input terminal of the second comparator, respectively.

[0027] The output terminal of the first comparator forms the switching control signal output terminal, and the output terminal of the first comparator is connected to the non-inverting input terminal of the second comparator;

[0028] The output of the second comparator is connected to the non-inverting input of the first comparator through a feedback resistor.

[0029] Preferably, both the first comparator and the second comparator are open-drain output comparators;

[0030] The output of the first comparator is connected to the logic power supply terminal via a first output pull-up resistor;

[0031] The output of the second comparator is connected to the voltage divider node of the input voltage divider branch via a feedback resistor;

[0032] When the output of the second comparator is low, the feedback resistor is connected to the voltage divider node of the input voltage divider branch;

[0033] When the output of the second comparator is in a high-impedance state, the pull-down channel between the feedback resistor and the ground terminal is disconnected.

[0034] Preferably, the reference source includes a TL431 reference device;

[0035] The reference source outputs a 2.5V reference voltage;

[0036] The wide-range DC input voltage is 9V to 36V;

[0037] The output terminal is a 12V output terminal;

[0038] The first switching threshold is 13V, and the second switching threshold is 12.5V.

[0039] Preferably, the delayed conduction unit includes a first logic gate device, a first input resistor, a second input resistor, and a first delay capacitor;

[0040] The first logic gate device has a first input terminal, a second input terminal, and an output terminal;

[0041] The first input terminal of the first logic gate device is connected to the logic power supply terminal via a first input resistor;

[0042] The second input terminal of the first logic gate device is connected to the logic power supply terminal via a second input resistor;

[0043] The first delay capacitor is connected between the first input terminal of the first logic gate device and the ground terminal;

[0044] The output terminal of the first logic gate device forms a conduction signal output terminal.

[0045] Preferably, the delayed unlocking unit includes a second logic gate device, a third input resistor, a fourth input resistor, a second delay capacitor, and an unlocking switch network;

[0046] The second logic gate device has a first input terminal, a second input terminal, and an output terminal;

[0047] The first input terminal of the second logic gate device is connected to the turn-on signal output terminal of the delayed turn-on unit via a third input resistor;

[0048] The second input terminal of the second logic gate device is connected to the turn-on signal output terminal of the delayed turn-on unit via the fourth input resistor;

[0049] The second delay capacitor is connected between the first input terminal of the second logic gate device and the ground terminal;

[0050] The output of the second logic gate device is connected to the control terminal of the unlock switch network;

[0051] The unlocking switch network is connected between the switching control signal output terminal of the voltage comparator unit and the gate control node.

[0052] Preferably, the unlocking switch network includes an on-permission branch and an off-permission control branch;

[0053] The conduction permission branch is connected between the switching control signal output terminal of the voltage comparator unit and the gate control node;

[0054] The first control terminal of the conduction permission branch is connected to the conduction signal output terminal of the delayed conduction unit, and the second control terminal of the conduction permission branch is connected to the output terminal of the second logic gate device.

[0055] The cutoff control branch is connected between the input terminal and the gate control node;

[0056] The control terminal of the cutoff control branch is connected to the switching control signal output terminal of the voltage comparison unit.

[0057] Preferably, the circuit further includes an automatic reset delay unit in case of power failure;

[0058] The automatic reset delay unit after power failure includes a reset voltage divider branch, a first discharge transistor, a second discharge transistor, a first discharge diode, and a second discharge diode.

[0059] The reset voltage divider branch is connected between the input terminal and the ground terminal, and the voltage divider node of the reset voltage divider branch is connected to the base of the first discharge transistor.

[0060] The first discharge transistor and the second discharge transistor are connected to form a discharge control branch;

[0061] The first discharge diode is connected between the first delay capacitor and the discharge control branch;

[0062] The second discharge diode is connected between the second delay capacitor and the discharge control branch;

[0063] When the voltage at the input terminal is lower than the reset voltage, the discharge control branch forms a discharge path with the first delay capacitor and the second delay capacitor respectively.

[0064] The reset voltage is 7.2V to 8.4V.

[0065] In summary, the present invention has the following main beneficial effects:

[0066] This application connects a PMOS bypass branch and a DC-DCBuck buck branch between the input and output terminals, respectively. A voltage comparator unit controls the switching of the two power supply paths based on comparisons between the input voltage and a first and a second switching threshold. This achieves the effect of supplying power to the output terminal with lower conduction losses via the PMOS bypass branch under low-voltage input conditions, and providing a load-appropriate supply voltage to the output terminal via the DC-DCBuck buck branch under higher input conditions. Compared to solutions using simple buck-boost converters, this application eliminates the need for a step-down-boost or continuous power conversion path when the input voltage is close to the rated 12V load power requirement. This reduces voltage loss and device heating under low-voltage input conditions and improves the load-carrying capacity for downstream load startup current under low-voltage input conditions.

[0067] By incorporating a first comparator, a second comparator, and a feedback resistor in the voltage comparison unit, and ensuring that the first switching threshold is greater than the second switching threshold, hysteresis control is achieved during the rise and fall of the input voltage. Specifically, when the input voltage rises from low to high, it switches to the DC-DCBuck buck branch for power supply after exceeding the first switching threshold; when the input voltage falls from high to low, it switches to the PMOS bypass branch for power supply after falling below the second switching threshold. This avoids repeated switching between the PMOS bypass branch and the DC-DCBuck buck branch due to small voltage fluctuations when the input voltage is near the switching point, resulting in a more stable output power supply and reducing the impact of switching jitter on the startup and continuous operation of downstream loads.

[0068] By configuring a delayed turn-on unit, a delayed unlock unit, and a power-off automatic reset delay unit, the PMOS turn-on operation under low voltage conditions requires simultaneous fulfillment of three conditions: the input voltage is below the second switching threshold, delayed turn-on is complete, and delayed unlock is complete. Furthermore, the residual charge in the delay capacitor is released after a short power-off, effectively suppressing false PMOS turn-on upon power-up and preventing the delayed state from failing to reset during repeated power-ups. Simultaneously, when the input voltage is above the first switching threshold, the first level output by the voltage comparator unit ensures timely cut-off of the PMOS bypass branch, guaranteeing that the low-voltage turn-on path is time-constrained during power supply path switching, while the high-voltage cut-off path maintains timely response. This improves the hardware control reliability in wide-range DC input power supply scenarios. Attached Figure Description

[0069] Figure 1 This is an overall structural block diagram of the present invention.

[0070] Figure 2 This is a circuit diagram of the voltage comparison unit of the present invention.

[0071] Figure 3 This is a circuit schematic diagram of the delayed conduction unit of the present invention.

[0072] Figure 4 This is a circuit diagram of the delayed unlocking unit of the present invention.

[0073] Figure 5 This is a circuit diagram of the automatic reset delay unit for power failure of the present invention. Detailed Implementation

[0074] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0075] Example 1

[0076] refer to Figure 1-5 A wide input DC voltage automatic switching power supply circuit, comprising:

[0077] Input terminal, output terminal, PMOS bypass branch, DC-DCBuck buck branch, voltage comparator unit, delayed turn-on unit and delayed unlock unit;

[0078] The input terminal is used to connect a wide range of DC input voltages. The PMOS bypass branch is connected between the input terminal and the output terminal. The input side of the DC-DCBuck buck branch is connected to the input terminal, and the output side of the DC-DCBuck buck branch is connected to the output terminal.

[0079] The PMOS bypass branch includes a PMOS transistor and a gate control node connected to the gate of the PMOS transistor.

[0080] The voltage comparison unit has a sampling input terminal and a switching control signal output terminal. The sampling input terminal is connected to the input terminal, and the switching control signal output terminal is connected to the delayed unlocking unit and the PMOS bypass branch respectively.

[0081] The delayed turn-on unit has a turn-on signal output terminal, which is connected to the delayed unlock unit.

[0082] The delayed unlocking unit is connected between the switching control signal output terminal of the voltage comparison unit and the gate control node;

[0083] When the wide-range DC input voltage is higher than the first switching threshold, the switching control signal output terminal of the voltage comparator unit outputs the first level. The first level acts on the gate control node, causing the PMOS bypass branch to be cut off and the output terminal to be powered by the DC-DCBuck step-down branch.

[0084] When the wide-range DC input voltage is lower than the second switching threshold, the switching control signal output terminal of the voltage comparison unit outputs the second level. The second level acts on the gate control node through the control path formed by the delayed turn-on unit and the delayed unlock unit, so that the PMOS bypass branch is turned on and the output terminal is powered by the PMOS bypass branch.

[0085] The first switching threshold is greater than the second switching threshold.

[0086] The input terminal is used to connect a wide range of DC input voltages. In this embodiment, the wide range of DC input voltages is 9V to 36V. For ease of description, the wide range of DC input voltages connected to the input terminal will be referred to as the input terminal voltage, and the input terminal voltage and the wide range of DC input voltage refer to the same voltage signal.

[0087] The output terminal is a power supply output terminal for connecting a load with a rated operating voltage of 12V. It should be noted that the output terminal is for connecting a load with a rated operating voltage of 12V, and does not mean that the output terminal is limited to outputting a fixed 12V voltage from the same power supply branch across the entire input voltage range. When the input terminal voltage is lower than the second switching threshold and the PMOS bypass branch is on, the output terminal voltage is the input terminal voltage minus the PMOS transistor's on-state voltage drop; when the input terminal voltage is higher than the first switching threshold and the PMOS bypass branch is off, the output terminal is supplied with a power supply voltage adapted to the rated 12V load via a DC-DCBuck step-down branch and an anti-reverse-current circuit.

[0088] It should be further explained that when the input voltage is lower than the second switching threshold, the PMOS bypass branch of this application is used to reduce the conduction loss between the input and output terminals and does not perform a boost conversion on the input voltage; at this time, the output voltage changes with the input voltage and is close to the input voltage. The phrase "for connecting a load with a rated operating voltage of 12V" means that the output terminal is suitable for a 12V bus power supply scenario, and the power supply capability in the low-voltage bypass state depends on the allowable input voltage range of the downstream load, the on-resistance of the PMOS transistor, and the load current.

[0089] The PMOS bypass branch connects between the input and output terminals to form a direct power supply path under low input voltage conditions. The input side of the DC-DCBuck buck branch is connected directly to the input terminal, and the output side is connected to the output terminal via a reverse-current protection circuit to supply power to the output terminal under higher input voltage conditions. The reverse-current protection circuit is located between the output side and the output terminal of the DC-DCBuck buck branch to prevent voltage from the output side from flowing back into the DC-DCBuck buck branch.

[0090] The sampling input terminal of the voltage comparator unit is connected to the input terminal to sample the input voltage and output a switching control signal based on the sampling result. The delayed turn-on unit outputs a PMOS turn-on signal after a delay following circuit power-on. The delayed unlock unit sets the unlocking condition for allowing a low-level switching control signal to act on the PMOS bypass branch after the delayed turn-on unit outputs the PMOS turn-on signal.

[0091] In this embodiment, the voltage comparison unit, the delayed turn-on unit, and the delayed unlock unit jointly control the turn-on and turn-off of the PMOS bypass branch. When the input voltage is higher than the first switching threshold, the PMOS bypass branch is turned off, and the output is powered by the DC-DCBuck buck branch; when the input voltage is lower than the second switching threshold, the PMOS bypass branch does not turn on immediately, but needs to turn on after both the delayed turn-on unit and the delayed unlock unit meet the corresponding timing conditions.

[0092] The PMOS bypass branch includes a PMOS transistor, a first pull-up resistor, and a first gate capacitor. The source of the PMOS transistor is connected to the input terminal, the drain of the PMOS transistor is connected to the output terminal, and the gate of the PMOS transistor is connected to the gate control node. The first pull-up resistor is connected between the input terminal and the gate control node, and the first gate capacitor is connected between the input terminal and the gate control node.

[0093] When the gate control node is pulled up to a potential close to the input terminal by the first pull-up resistor, the gate-source voltage of the PMOS transistor does not meet the turn-on condition, and the PMOS bypass branch is in the off state. When the gate control node is pulled down to a low potential through the turn-on permission branch, the gate-source voltage of the PMOS transistor meets the turn-on condition, and the input terminal supplies power to the output terminal through the PMOS transistor.

[0094] The first gate capacitor works in conjunction with the gate control node of the PMOS transistor to control gate voltage changes and reduce the possibility of the PMOS transistor being falsely turned on due to interference or short-term uncertain levels at the gate control node during power-up. The first pull-up resistor is used to maintain the gate control node in a state that keeps the PMOS transistor off when no valid turn-on permission is established.

[0095] The input side of the DC-DCBuck step-down branch is connected to the input terminal, the output side of the DC-DCBuck step-down branch is connected to the input side of the backflow prevention circuit, and the output side of the backflow prevention circuit is connected to the output terminal. The drain of the PMOS transistor and the output side of the backflow prevention circuit are both connected to the output terminal.

[0096] In this embodiment, the DC-DCBuck step-down branch is in an operational state after the circuit is powered on. When the input voltage is higher than the first switching threshold, the voltage comparator outputs a first level to cut off the PMOS bypass branch, the PMOS bypass branch is disconnected, and the output is powered by the DC-DCBuck step-down branch through the anti-backflow circuit.

[0097] When the input voltage is lower than the second switching threshold, and both the delayed turn-on unit and the delayed unlock unit meet the turn-on conditions, the PMOS bypass branch is turned on, and the output is powered by the PMOS bypass branch. At this time, the anti-reverse current circuit prevents the output voltage from flowing back into the DC-DCBuck buck branch, thus avoiding the formation of an unexpected reverse current path between the PMOS bypass branch and the DC-DCBuck buck branch.

[0098] The voltage comparison unit includes a reference source, an input voltage divider branch, a first comparator, a second comparator, and a feedback resistor. The input voltage divider branch is connected between the input terminal and the ground terminal, and its dividing node is connected to the non-inverting input of the first comparator. The output of the reference source is connected to both the inverting inputs of the first and second comparators. The output of the first comparator forms a switching control signal output, and is also connected to the non-inverting input of the second comparator. The output of the second comparator is connected to the non-inverting input of the first comparator via the feedback resistor.

[0099] In this embodiment, a TL431 reference device is used as the reference source, and the reference source outputs a 2.5V reference voltage. Both the first and second comparators are open-drain output comparators. The output of the first comparator is connected to the logic power supply terminal via a first output pull-up resistor. The output of the second comparator is connected to the voltage divider node of the input voltage divider branch via a feedback resistor.

[0100] The input voltage divider branch is used to convert the input voltage into a sampled voltage that can be compared by the first comparator. The first comparator compares the sampled voltage with a 2.5V reference voltage and outputs a first level or a second level. In this embodiment, the first level is a high level and the second level is a low level.

[0101] When the input voltage is lower than the second switching threshold, the first comparator outputs a second level. This second level output from the first comparator is input to the non-inverting input of the second comparator, causing the second comparator to output a second level. This second level is then connected to the non-inverting input of the first comparator via a feedback resistor. After the feedback resistor is connected, the equivalent voltage division at the non-inverting input of the first comparator changes, meaning the first comparator only switches from the second level to the first level when the input voltage rises to the first switching threshold.

[0102] When the input voltage is higher than the first switching threshold, the first comparator outputs a first level. This first level output is then fed to the non-inverting input of the second comparator. Since the second comparator has an open-drain output structure, its output is in a high-impedance state, and the pull-down path between the feedback resistor and ground is broken. At this time, the feedback resistor does not provide a pull-down voltage divider effect at the non-inverting input of the first comparator.

[0103] In this embodiment, the first switching threshold is 13V, and the second switching threshold is 12.5V. The first switching threshold is greater than the second switching threshold, resulting in a 0.5V hysteresis between them. The first and second switching thresholds are jointly determined by the input voltage divider branch, the reference source, and the feedback resistor. The input voltage divider branch ensures that the input voltage reaches the second switching threshold, corresponding to the reference comparison condition of the first comparator. The feedback resistor is connected to the voltage divider node of the input voltage divider branch when the second comparator outputs the second level, ensuring that the first comparator only flips to the first level after reaching the first switching threshold during the input voltage increase process.

[0104] During the input voltage rise from low to high, once the voltage comparator unit has its operating voltage, the TL431 reference device provides a 2.5V reference voltage to the first and second comparators. Since the input voltage has not yet reached the first switching threshold, the first comparator outputs a second level. The second comparator, receiving the second level output from the first comparator, also outputs a second level. A feedback resistor is connected to the non-inverting input of the first comparator, ensuring that the first comparator only switches to the first level when the input voltage reaches 13V.

[0105] As the input voltage decreases from high to low, the output of the second comparator is in a high-impedance state, the pull-down channel between the feedback resistor and the ground terminal is broken, and the feedback resistor does not participate in the voltage division at the non-inverting input of the first comparator. When the input voltage drops below 12.5V, the first comparator outputs a second level, and the second comparator subsequently outputs a second level, and the feedback resistor is reconnected to the non-inverting input of the first comparator.

[0106] Therefore, the circuit uses 13V as the threshold for switching from the PMOS bypass branch to the DC-DCBuck buck branch during the input voltage rise, and 12.5V as the threshold for switching from the DC-DCBuck buck branch to the PMOS bypass branch during the input voltage fall. This hysteresis control prevents repeated switching between the PMOS bypass branch and the DC-DCBuck buck branch when the input voltage fluctuates around a single switching point.

[0107] The delayed turn-on unit includes a first logic gate device, a first input resistor, a second input resistor, and a first delay capacitor. The first logic gate device has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first logic gate device is connected to the logic power supply terminal via the first input resistor, the second input terminal of the first logic gate device is connected to the logic power supply terminal via the second input resistor, the first delay capacitor is connected between the first input terminal of the first logic gate device and the ground terminal, and the output terminal of the first logic gate device forms a turn-on signal output terminal.

[0108] When the circuit is powered on, the logic power supply terminal charges the first delay capacitor through the first input resistor. Before the voltage across the first delay capacitor reaches the input toggle threshold of the first logic gate device, the output of the first logic gate device does not output a valid PMOS turn-on signal. Once the voltage across the first delay capacitor reaches the input toggle threshold of the first logic gate device, the output of the first logic gate device outputs a PMOS turn-on signal.

[0109] The first input resistor and the first delay capacitor are used to set the delay time of the delayed turn-on unit. The resistance value of the first input resistor, the capacitance value of the first delay capacitor, and the input toggle threshold of the first logic gate device together determine the time when the output of the first logic gate device generates a valid PMOS turn-on signal. In specific implementation, the input toggle threshold of the first logic gate device is based on the datasheet of the selected logic gate device, and the first input resistor and the first delay capacitor are selected according to the required power-on delay.

[0110] The delayed unlocking unit includes a second logic gate device, a third input resistor, a fourth input resistor, a second delay capacitor, and an unlocking switch network. The second logic gate device has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second logic gate device is connected to the turn-on signal output terminal of the delayed turn-on unit via the third input resistor. The second input terminal of the second logic gate device is connected to the turn-on signal output terminal of the delayed turn-on unit via the fourth input resistor. The second delay capacitor is connected between the first input terminal of the second logic gate device and the ground terminal. The output terminal of the second logic gate device is connected to the control terminal of the unlocking switch network.

[0111] When the delayed turn-on unit outputs a PMOS turn-on signal, this PMOS turn-on signal charges the second delay capacitor through the third input resistor. Before the terminal voltage of the second delay capacitor reaches the input toggling threshold of the second logic gate device, the second logic gate device does not output a valid PMOS unlock signal, and the unlock switch network does not allow the second level output by the voltage comparator unit to directly act on the gate control node.

[0112] When the voltage across the second delay capacitor reaches the input toggling threshold of the second logic gate, the second logic gate outputs a PMOS unlock signal, and the unlock switch network enters a state that allows the transmission of low-level switching control signals. At this time, if the voltage comparator unit outputs a second level, the second level can be applied to the gate control node through the unlock switch network, turning on the PMOS transistor.

[0113] The third input resistor and the second delay capacitor are used to set the delay time of the delayed unlock unit. The resistance value of the third input resistor, the capacitance value of the second delay capacitor, and the input toggling threshold of the second logic gate device together determine the time when the second logic gate device outputs the PMOS unlock signal. In specific implementation, the input toggling threshold of the second logic gate device is based on the datasheet of the selected logic gate device, and the third input resistor and the second delay capacitor are selected according to the required unlock delay.

[0114] The unlock switch network is connected between the switching control signal output of the voltage comparator unit and the gate control node. The unlock switch network includes a turn-on permission branch and a turn-off control branch.

[0115] The enable branch is connected between the switching control signal output of the voltage comparator unit and the gate control node. The first control terminal of the enable branch is connected to the turn-on signal output of the delayed turn-on unit, and the second control terminal is connected to the output of the second logic gate device. The enable branch is used to pull the gate control node to a low potential when the PMOS turn-on signal, the PMOS unlock signal, and the second level output of the voltage comparator unit simultaneously meet the corresponding turn-on conditions.

[0116] The cutoff control branch is connected between the input terminal and the gate control node, and its control terminal is connected to the switching control signal output terminal of the voltage comparator unit. The cutoff control branch is used to maintain the gate control node at a potential that turns off the PMOS transistor when the voltage comparator unit outputs the first level.

[0117] The enable branch includes a first enable switch controlled by a delayed enable unit, a second enable switch controlled by a delayed unlock unit, and a gate pull-down switch connected between the switching control signal output and the gate control node. The control terminal of the first enable switch receives the PMOS enable signal output by the delayed enable unit, the control terminal of the second enable switch receives the PMOS unlock signal output by the delayed unlock unit, and the control terminal of the gate pull-down switch receives the second voltage level output by the voltage comparison unit. Only when the PMOS enable signal, the PMOS unlock signal, and the second voltage level are all in their corresponding enable states will the enable branch pull the gate control node to a low potential, thus enabling the PMOS transistor to conduct.

[0118] The control terminal of the cutoff control branch receives the first level output from the voltage comparison unit. When the switching control signal output terminal outputs the first level, the cutoff control branch keeps the gate control node at the potential that turns off the PMOS transistor. Since the first level corresponds to an input voltage higher than the first switching threshold, the first level can put the PMOS bypass branch into the cutoff state without waiting for the delayed unlocking unit to form a conduction permission.

[0119] Through the aforementioned unlocking switch network, the PMOS bypass branch forms two distinct control paths. The low-voltage turn-on path is constrained by both the delayed turn-on unit and the delayed unlocking unit, while the high-voltage cut-off path is triggered by the first level output from the voltage comparator unit. This control relationship ensures that the PMOS bypass branch will not prematurely turn on due to the low-level switching control signal at power-on, and that it can be promptly cut off when the input voltage rises above the first switching threshold.

[0120] When the circuit is powered on, the input voltage gradually rises from 0V. At this time, the first delay capacitor in the delayed turn-on unit has not yet finished charging, and the delayed turn-on unit does not output a valid PMOS turn-on signal; the second delay capacitor in the delayed unlock unit has also not finished charging, and the delayed unlock unit does not output a valid PMOS unlock signal. Therefore, even if the voltage comparator unit outputs a second level during the low-voltage phase, the second level cannot directly act on the gate control node, and the PMOS transistor remains in the off state.

[0121] Once the input voltage rises to the operating voltage range of the voltage comparator unit, the reference source outputs a 2.5V reference voltage. The first comparator then begins comparing the voltage at the voltage divider node of the input voltage divider branch with the 2.5V reference voltage. Before the input voltage reaches the first switching threshold, the first comparator outputs a second level. The second comparator receives the second level output from the first comparator and outputs its own second level. A feedback resistor is connected to the non-inverting input of the first comparator, ensuring that the first comparator only switches to the first level when the input voltage reaches 13V.

[0122] When the input voltage is in a low-voltage supply state, for example, the input voltage is 12V, and after the delay turn-on unit and the delay unlock unit have completed their delays in sequence, the second level output by the voltage comparator unit acts on the gate control node through the turn-on permission branch, turning on the PMOS transistor. The input terminal supplies power to the output terminal through the PMOS bypass branch. In this state, the output voltage is the input voltage minus the turn-on voltage drop of the PMOS transistor.

[0123] When the input voltage rises from a low voltage state and exceeds the first switching threshold (in this embodiment, when the input voltage is higher than 13V), the output of the first comparator flips from the second level to the first level. The first level acts on the gate control node through the cutoff control branch, causing the PMOS transistor to be cut off and the PMOS bypass branch to be disconnected.

[0124] Since the DC-DCBuck buck branch is operational after the circuit is powered on, and the PMOS bypass branch is turned off, the DC-DCBuck buck branch supplies power to the output terminal through the anti-backflow circuit. This switching process is jointly completed by the output level of the voltage comparator unit, the cutoff control branch, and the gate control node, without requiring processor software to determine the input voltage range.

[0125] During this process, the first voltage level corresponds to the cutoff control of the PMOS bypass branch, and the first voltage level is not restricted by the conduction permission of the delayed unlocking unit. Therefore, when the input voltage is higher than the first switching threshold, the PMOS bypass branch can promptly exit the power supply path.

[0126] When the input voltage decreases from a high-voltage state, the output of the second comparator is in a high-impedance state, the pull-down channel between the feedback resistor and the ground terminal is broken, and the feedback resistor does not participate in the voltage division at the non-inverting input of the first comparator. Therefore, the first comparator will not immediately switch to the second level when the input voltage just drops below 13V.

[0127] When the input voltage drops below the second switching threshold (in this embodiment, when the input voltage is below 12.5V), the first comparator outputs a second level, and the second comparator subsequently outputs a second level. The feedback resistor is reconnected to the non-inverting input of the first comparator. If the delayed turn-on unit and the delayed unlock unit are already in the completed delay state, the second level acts on the gate control node through the turn-on permission branch, turning on the PMOS transistor, and the output is powered by the PMOS bypass branch.

[0128] Through this process, the circuit does not switch directly to the PMOS bypass branch at 13V when the input voltage drops, but only switches after it falls below 12.5V. This creates a 0.5V hysteresis with the 13V switching point when the input voltage rises.

[0129] The automatic reset delay unit after power failure includes a reset voltage divider branch, a first discharge transistor, a second discharge transistor, a first discharge diode, and a second discharge diode. The reset voltage divider branch is connected between the input terminal and the ground terminal, and the voltage divider node of the reset voltage divider branch is connected to the base of the first discharge transistor. The first and second discharge transistors are connected to form a discharge control branch. The first discharge diode is connected between the first delay capacitor and the discharge control branch, and the second discharge diode is connected between the second delay capacitor and the discharge control branch.

[0130] When the input voltage is lower than the reset voltage, the discharge control branch is activated. The first delay capacitor releases its residual charge through the first discharge diode and the discharge control branch, and the second delay capacitor releases its residual charge through the second discharge diode and the discharge control branch. In this embodiment, the reset voltage is 7.2V to 8.4V.

[0131] The reset voltage is used to determine that the input voltage has fallen below the power supply range required for the delayed turn-on unit and delayed unlock unit to maintain an effective delay state. The reset voltage is not used as the power supply switching threshold between the PMOS bypass branch and the DC-DCBuck buck branch. The power supply switching between the PMOS bypass branch and the DC-DCBuck buck branch is determined by a first switching threshold and a second switching threshold.

[0132] The reset voltage can be determined by the reset voltage divider branch and the base-emitter forward voltage drop of the first and second discharge transistors. The base-emitter forward voltage drop of the transistors can be selected from 0.6V to 0.7V according to the device datasheet. The reset voltage does not need to be set as a precision voltage comparison threshold; it only needs to release the residual charge of the first and second delay capacitors when the input voltage drops to a level insufficient to maintain the normal power-on delay state.

[0133] By automatically resetting the delay unit upon power failure, both the first and second delay capacitors restart charging from their discharged state upon power restoration after a short power outage, and the delayed turn-on and delayed unlock units reset their timings. Therefore, the PMOS bypass branch will not prematurely turn on during the initial power-on phase due to residual charge in the first or second delay capacitors.

[0134] In this embodiment, the logic power supply can be provided by the auxiliary power output in the DC-DCBuck step-down branch. For example, the 4.9V power output of the DC-DCBuck power chip itself can be used as the logic power supply for the voltage comparison unit, the delayed turn-on unit, and the delayed unlock unit.

[0135] In another embodiment, the logic power supply can also be provided by an independent LDO power chip or a small DC-DC power chip. When an independent logic power supply is used, the voltage comparison unit, the delayed turn-on unit, and the delayed unlock unit do not depend on the output state of the PMOS bypass branch or the main DC-DC Buck buck branch, making it easy to adapt the automatic switching power supply circuit of this application to different models of Buck buck power chips.

[0136] Whether the auxiliary power output of the DC-DCBuck power chip itself is used, or an independent LDO power chip or a small DC-DC power chip is used as the logic power supply terminal, the basic circuit relationship of the present application, which realizes automatic switching of power supply branches through voltage comparison unit, delayed conduction unit, delayed unlocking unit, hysteresis control and power failure automatic reset delay unit, remains unchanged.

[0137] In this embodiment, the wide-range DC input voltage is 9V to 36V. This input range is used to cover 12V, 19V, and 24V DC power supply scenarios, and also takes into account the application requirements of power supply by DC-DCBuck buck branch at higher input voltages.

[0138] In this embodiment, the first switching threshold is 13V, and the second switching threshold is 12.5V, forming a 0.5V hysteresis. The first switching threshold is used to switch the power supply path from the PMOS bypass branch to the DC-DCBuck buck branch when the input voltage rises from low to high; the second switching threshold is used to switch the power supply path from the DC-DCBuck buck branch to the PMOS bypass branch when the input voltage falls from high to low. The 0.5V hysteresis is obtained from the difference between the first and second switching thresholds.

[0139] In this embodiment, the reference source outputs a 2.5V reference voltage. The input voltage divider branch forms a voltage divider node voltage that is compared with this 2.5V reference voltage based on the input voltage. When the second comparator outputs a second level, the feedback resistor is connected to the non-inverting input of the first comparator, ensuring that the input voltage rises from low to high until it reaches 13V before the first comparator outputs a first level. When the second comparator outputs a high-impedance state, the feedback resistor does not form a pull-down voltage divider path, ensuring that when the input voltage falls from high to low, the first comparator outputs a second level only after it drops below 12.5V.

[0140] In this embodiment, the capacitance values ​​of the first and second delay capacitors, and the resistance values ​​of the first and third input resistors, are used to set the delay turn-on time and delay unlock time, respectively. The RC parameters are determined based on the input toggle threshold of the selected logic gate device, the DC-DCBuck buck branch startup time, load startup characteristics, and PMOS transistor gate drive requirements. This embodiment does not limit the RC parameter values ​​to a single value.

[0141] The delay times of the delayed turn-on unit and the delayed unlock unit can be set using the following relationship:

[0142] ;

[0143] In the formula, This indicates the delay time of the corresponding delay unit. This indicates the input resistance value in the corresponding delayed charging branch. This indicates the capacitance value of the corresponding delay capacitor. Represents the natural logarithm function. This represents the input toggling threshold of the corresponding logic gate device. This represents the voltage at the logic gate terminals. This relationship is used to illustrate the correspondence between the time required for the resistor-capacitor charge to reach the logic gate input toggling threshold and the input resistance, delay capacitor, and logic gate input toggling threshold. It does not limit the delay-on unit and delay-off unit to using only one resistor-capacitor parameter.

[0144] The PMOS transistor's withstand voltage should not be lower than the highest input voltage, its continuous drain current should not be lower than the maximum operating current of the load, and its on-resistance should meet the output voltage drop requirements under low input conditions. The input voltage range of the DC-DCBuck buck circuit should cover 9V to 36V, and its output capability should meet the operating current requirements of a load with a rated operating voltage of 12V under high input conditions. The withstand voltage and current carrying capacity of the reverse current protection circuit should match the output capability of the DC-DCBuck buck circuit.

[0145] The wide-range DC voltage automatic switching power supply circuit of this embodiment has a defined hardware state under low voltage input, high voltage input, input voltage rise, input voltage drop, and short-term repeated power-on conditions.

[0146] When the input voltage is low and the delay turn-on and delay unlock units have completed their delays, the voltage comparator outputs a second level. The turn-on permission branch transmits this second level to the gate control node, turning on the PMOS transistor. The output is then powered by the PMOS bypass branch. In this low-voltage bypass state, the PMOS bypass branch reduces the conduction loss between the input and output terminals and does not perform boost conversion.

[0147] Under high voltage input conditions, the voltage comparator outputs the first level, the cutoff control branch keeps the gate control node at the potential that turns off the PMOS transistor, the PMOS bypass branch is cut off, and the output is powered by the DC-DCBuck step-down branch through the anti-backflow circuit.

[0148] When the input voltage rises from low to high, the power supply path switches from the PMOS bypass branch to the DC-DCBuck buck branch once the input voltage exceeds 13V. When the input voltage falls from high to low, the power supply path switches from the DC-DCBuck buck branch to the PMOS bypass branch once the input voltage falls below 12.5V. The 0.5V hysteresis between these two switching paths limits repeated switching near the switching point.

[0149] When power is restored after a brief power outage, the automatic reset delay unit releases the residual charge in the first and second delay capacitors, causing both the delayed turn-on and delayed unlock units to reset their timings. Therefore, the PMOS bypass branch will not prematurely turn on due to residual charge in the delay capacitors.

[0150] In summary, this embodiment does not simply set up the PMOS bypass branch and the DC-DCBuck buck branch in parallel, nor does it directly select the power supply branch based solely on the input voltage range. Instead, based on the switching control signal output by the voltage comparator unit, it limits the conduction and cutoff conditions of the PMOS bypass branch through a delayed turn-on unit, a delayed unlock unit, hysteresis control, and a power-off automatic reset delay unit. The PMOS bypass branch only turns on when the input voltage is below the second switching threshold, after the delayed turn-on and delayed unlock are completed, and turns off when the input voltage is above the first switching threshold, thus forming a complete, clear, and implementable circuit control chain.

[0151] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A wide-input DC voltage automatic switching power supply circuit, characterized in that, include: Input terminal, output terminal, PMOS bypass branch, DC-DCBuck buck branch, voltage comparator unit, delayed turn-on unit and delayed unlock unit; The input terminal is used to connect a wide range of DC input voltages. The PMOS bypass branch is connected between the input terminal and the output terminal. The input side of the DC-DCBuck buck branch is connected to the input terminal, and the output side of the DC-DCBuck buck branch is connected to the output terminal. The PMOS bypass branch includes a PMOS transistor and a gate control node connected to the gate of the PMOS transistor. The voltage comparison unit has a sampling input terminal and a switching control signal output terminal. The sampling input terminal is connected to the input terminal, and the switching control signal output terminal is connected to the delayed unlocking unit and the PMOS bypass branch respectively. The delayed turn-on unit has a turn-on signal output terminal, which is connected to the delayed unlock unit. The delayed unlocking unit is connected between the switching control signal output terminal of the voltage comparison unit and the gate control node; When the wide-range DC input voltage is higher than the first switching threshold, the switching control signal output terminal of the voltage comparator unit outputs the first level. The first level acts on the gate control node, causing the PMOS bypass branch to be cut off and the output terminal to be powered by the DC-DCBuck step-down branch. When the wide-range DC input voltage is lower than the second switching threshold, the switching control signal output terminal of the voltage comparison unit outputs the second level. The second level acts on the gate control node through the control path formed by the delayed turn-on unit and the delayed unlock unit, so that the PMOS bypass branch is turned on and the output terminal is powered by the PMOS bypass branch. The first switching threshold is greater than the second switching threshold; The PMOS bypass branch also includes a first pull-up resistor and a first gate capacitor; The source of the PMOS transistor is connected to the input terminal, and the drain of the PMOS transistor is connected to the output terminal. The first pull-up resistor is connected between the input terminal and the gate control node; The first gate capacitor is connected between the input terminal and the gate control node; The circuit also includes a backflow prevention circuit; The backflow prevention circuit is connected in series between the output side and the output terminal of the DC-DCBuck step-down branch; The drain of the PMOS transistor and the output side of the anti-backflow circuit are both connected to the output terminal.

2. The wide input DC voltage automatic switching power supply circuit according to claim 3, characterized in that, The voltage comparison unit includes a reference source, an input voltage divider branch, a first comparator, a second comparator, and a feedback resistor; The input voltage divider branch is connected between the input terminal and the ground terminal, and the voltage divider node of the input voltage divider branch is connected to the non-inverting input terminal of the first comparator. The output terminal of the reference source is connected to the inverting input terminal of the first comparator and the inverting input terminal of the second comparator, respectively. The output terminal of the first comparator forms the switching control signal output terminal, and the output terminal of the first comparator is connected to the non-inverting input terminal of the second comparator; The output of the second comparator is connected to the non-inverting input of the first comparator through a feedback resistor.

3. The wide input DC voltage automatic switching power supply circuit according to claim 2, characterized in that, Both the first comparator and the second comparator are open-drain output comparators. The output of the first comparator is connected to the logic power supply terminal via a first output pull-up resistor; The output of the second comparator is connected to the voltage divider node of the input voltage divider branch via a feedback resistor; When the output of the second comparator is low, the feedback resistor is connected to the voltage divider node of the input voltage divider branch; When the output of the second comparator is in a high-impedance state, the pull-down channel between the feedback resistor and the ground terminal is disconnected.

4. The wide input DC voltage automatic switching power supply circuit according to claim 3, characterized in that, The reference source includes a TL431 reference device; The reference source outputs a 2.5V reference voltage; The wide-range DC input voltage is 9V to 36V; The output terminal is a 12V output terminal; The first switching threshold is 13V, and the second switching threshold is 12.5V.

5. The wide input DC voltage automatic switching power supply circuit according to claim 4, characterized in that, The delayed conduction unit includes a first logic gate device, a first input resistor, a second input resistor, and a first delay capacitor; The first logic gate device has a first input terminal, a second input terminal, and an output terminal; The first input terminal of the first logic gate device is connected to the logic power supply terminal via a first input resistor; The second input terminal of the first logic gate device is connected to the logic power supply terminal via a second input resistor; The first delay capacitor is connected between the first input terminal of the first logic gate device and the ground terminal; The output terminal of the first logic gate device forms a conduction signal output terminal.

6. The wide input DC voltage automatic switching power supply circuit according to claim 5, characterized in that, The delayed unlocking unit includes a second logic gate device, a third input resistor, a fourth input resistor, a second delay capacitor, and an unlocking switch network; The second logic gate device has a first input terminal, a second input terminal, and an output terminal; The first input terminal of the second logic gate device is connected to the turn-on signal output terminal of the delayed turn-on unit via a third input resistor; The second input terminal of the second logic gate device is connected to the turn-on signal output terminal of the delayed turn-on unit via the fourth input resistor; The second delay capacitor is connected between the first input terminal of the second logic gate device and the ground terminal; The output of the second logic gate device is connected to the control terminal of the unlock switch network; The unlocking switch network is connected between the switching control signal output terminal of the voltage comparator unit and the gate control node.

7. The wide input DC voltage automatic switching power supply circuit according to claim 6, characterized in that, The unlocking switch network includes an on / off permission branch and an off / off control branch; The conduction permission branch is connected between the switching control signal output terminal of the voltage comparator unit and the gate control node; The first control terminal of the conduction permission branch is connected to the conduction signal output terminal of the delayed conduction unit, and the second control terminal of the conduction permission branch is connected to the output terminal of the second logic gate device. The cutoff control branch is connected between the input terminal and the gate control node; The control terminal of the cutoff control branch is connected to the switching control signal output terminal of the voltage comparison unit.

8. The wide input DC voltage automatic switching power supply circuit according to claim 7, characterized in that, The circuit also includes an automatic reset delay unit in case of power failure; The automatic reset delay unit after power failure includes a reset voltage divider branch, a first discharge transistor, a second discharge transistor, a first discharge diode, and a second discharge diode. The reset voltage divider branch is connected between the input terminal and the ground terminal, and the voltage divider node of the reset voltage divider branch is connected to the base of the first discharge transistor. The first discharge transistor and the second discharge transistor are connected to form a discharge control branch; The first discharge diode is connected between the first delay capacitor and the discharge control branch; The second discharge diode is connected between the second delay capacitor and the discharge control branch; When the voltage at the input terminal is lower than the reset voltage, the discharge control branch forms a discharge path with the first delay capacitor and the second delay capacitor respectively. The reset voltage is 7.2V to 8.4V.

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