Network state intelligent monitoring control system based on multi-core heterogeneous hardware architecture

Abstract

The application discloses a power distribution network state intelligent monitoring control system based on a multi-core heterogeneous hardware architecture and concretely relates to the technical field of power distribution network state monitoring, and comprises a multi-core heterogeneous hardware platform, an adaptive monitoring module, a dynamic computing power resource pooling topology layer and a hot migration module.The adaptive monitoring module identifies and hard-latches fault conditions in real time through time domain integration and a hardware comparator, and triggers a non-masked interrupt.The topology layer uniformly addresses and homogenizes abstracts the heterogeneous cores, performs computing power pooling reorganization based on bus arbitration and atomic operation protection execution, and the hot migration module solidifies hardware context snapshots by using compilation alignment and direct memory access technology, and realizes microsecond-level lossless takeover and pipeline chasing of cross instruction set algorithms through a bottom layer hardware mailbox mechanism.The application eliminates the time delay and data consistency risk caused by traditional software scheduling, and significantly improves the real-time performance and reliability of control.

Description

Technical Field

[0001] This invention relates to the field of power distribution network condition monitoring technology, and more specifically, to a power distribution network condition intelligent monitoring and control system based on a multi-core heterogeneous hardware architecture. Background Technology

[0002] With the deepening of the construction of new power systems, distributed power sources such as distributed photovoltaics, energy storage systems, and electric vehicle charging piles, along with a large number of high-energy-consuming loads, are being connected to the distribution network. This has led to new characteristics in the distribution network, including strong randomness, fluctuations at multiple temporal and spatial scales, and high-frequency broadband oscillations. To achieve accurate control of the distribution network status, edge-side intelligent monitoring terminals not only need to maintain microsecond-level transient fault traveling wave capture and millisecond-level relay protection control, but also need to handle complex multi-dimensional tasks such as minute-level or hour-level distributed energy load forecasting, panoramic status estimation, and communication networking.

[0003] Existing power distribution network terminals are generally beginning to adopt multi-core heterogeneous hardware architectures consisting of general-purpose processors, digital signal processors, and artificial intelligence inference cores. However, existing multi-core heterogeneous systems typically employ fixed "dedicated cores for specific purposes" and "static binding" task scheduling modes.

[0004] In actual operation, the physical state and computational demands of various nodes in the power distribution network exhibit severe spatiotemporal imbalances. For example, during peak solar power generation in the daytime, the core responsible for harmonic analysis and broadband oscillation calculations is prone to overload, while the core responsible for nighttime lighting management and reactive power compensation control is completely idle. In the instant of a sudden short-circuit fault, if the system cannot allocate computing power across cores, fragmented hardware resources will cause high-priority protection criteria to experience delays of microseconds to milliseconds due to insufficient computing power. Traditional architectures cannot achieve seamless algorithm migration across heterogeneous instruction sets through task switching at the operating system level, resulting not only in severe uneven distribution and waste of hardware resources but also failing to meet the performance requirements of new power systems for extreme real-time analysis and control of transient faults under extreme conditions. Summary of the Invention

[0005] In order to overcome the above-mentioned defects of the prior art, embodiments of the present invention provide a power distribution network status intelligent monitoring and control system based on a multi-core heterogeneous hardware architecture to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a distribution network status intelligent monitoring and control system based on a multi-core heterogeneous hardware architecture, comprising a multi-core heterogeneous hardware platform, an adaptive monitoring module, a dynamic computing power resource pooling topology layer, and a hot migration module.

[0007] The multi-core heterogeneous hardware platform includes at least one general-purpose computing core, at least one digital signal processing core, and at least one artificial intelligence inference core.

[0008] The adaptive monitoring module is used to collect time-series physical state data of the distribution network in real time, and dynamically identify the current operating condition of the distribution network based on the characteristics of the state data, and output the corresponding operating condition command.

[0009] The dynamic computing resource pooling topology layer is deployed on the underlying hardware abstraction layer. It is used to uniformly address the register address space and static random access memory of the general computing core, digital signal processing core and artificial intelligence inference core, abstract each heterogeneous core into homogeneous virtual computing power element, and construct a dynamic computing resource status table.

[0010] The hot migration module is used to establish multiple sets of binary image code spaces for power core algorithms compiled for different heterogeneous kernel instruction sets, but with the same data interface structure; and according to the operating status instructions, it sends inter-core interrupts through a hardware communication mailbox mechanism to perform microsecond-level lossless migration of the hardware context snapshot of the currently running power core algorithm between the homogeneous virtual computing units.

[0011] Preferably, as a preferred embodiment of the intelligent monitoring and control system for distribution network status based on a multi-core heterogeneous hardware architecture described in this invention, it includes the adaptive monitoring module, which acquires the bus voltage timing signal and branch current timing signal of the distribution network node in real time through an off-chip analog-to-digital converter, constructs a sliding monitoring window, and extracts physical feature quantities including fundamental effective value features, abrupt change features, harmonic features and distributed power source features in real time through internal computing components.

[0012] The adaptive monitoring module is equipped with a condition state mutual exclusion arbitrator. The condition state mutual exclusion arbitrator is configured with priority fixed logic of "fault state > load prediction state > normal monitoring state". By comparing the physical feature quantity with the preset boundary threshold in real time, it dynamically identifies the normal monitoring state, load prediction state and fault state and latches them, and sends the corresponding hardware instructions to the underlying bus.

[0013] The adaptive monitoring module also includes a fundamental frequency change rate time-domain integrator. When extracting the abrupt change feature, the abrupt change difference of a consecutive preset number of sampling points is integrated and accumulated in the time domain. When the accumulated value of the time domain integration exceeds the integration trigger threshold continuously within a preset time window, it is determined to be a real working condition transition, so as to eliminate the high-frequency flickering switching of the working condition caused by glitch noise at the hardware level.

[0014] The adaptive monitoring module includes a hardware comparator and configuration timing interlock logic.

[0015] When a fault condition is determined, the hardware comparator sends the highest priority non-maskable interrupt directly to the hot-migrating module through a dedicated hardware pin, and hardware latches the fault condition instruction until the protection action is completed and all fault characteristic quantities for a consecutive preset number of cycles are restored to the normal range, and the fault reset timer inside the system times out, at which point the latch is automatically cleared.

[0016] The boundary threshold is statically stored in on-chip non-volatile memory and can only be remotely configured by the management core in a non-fault state. When the system latches a fault state instruction, the write enable control line of the non-volatile memory is forcibly shut down by hardware, rejecting remote rewrite requests.

[0017] Preferably, as a preferred embodiment of the intelligent monitoring and control system for distribution network status based on multi-core heterogeneous hardware architecture described in this invention, it includes the dynamic computing power resource pooling topology layer. During the system startup phase, the underlying firmware executes a globally unified memory mapping to asymmetrically divide the physical address space of the entire chipset, allocating a globally unique physical address to the register group and memory of each heterogeneous core.

[0018] The bus memory protection unit is configured to intercept unauthorized core bus out-of-bounds transactions. Each core is mapped to a physically contiguous shared static random access memory. The shared static random access memory is configured with a hardware-level memory access arbitrator and supports four access modes: exclusive write, shared read, read-write lock, and uncached direct write.

[0019] Preferably, as a preferred embodiment of the intelligent monitoring and control system for distribution network status based on a multi-core heterogeneous hardware architecture as described in this invention, it includes the homogeneous virtual computing power units, each corresponding to a set of standardized descriptor structures in the underlying hardware abstraction layer; the hardware abstraction layer defines a normalized standard computing power equivalent based on the number of hardware multipliers, floating-point and fixed-point arithmetic capabilities, and current operating frequency of each heterogeneous core, so as to realize the equivalent quantization mapping of the computing power of heterogeneous cores;

[0020] The dynamic computing resource pooling topology layer constructs a dynamic computing resource status table in a specific reserved area within the chip, and maintains in real time multi-dimensional indicators including core utilization rate, thermal safety and power consumption indicators, and computing kernel status markers;

[0021] The dynamic computing resource pooling topology layer scans the dynamic computing resource status table in real time and performs computing resource scheduling:

[0022] In normal monitoring mode, the power management unit powers down and marks the dedicated acceleration core with zero load as dormant. In load prediction mode, the AI ​​inference core in dormant mode is powered on and marked as ready, and the bus interconnect topology is reconstructed. In fault mode, the general computing core that is executing low-priority business is quickly identified, and the bus arbiter deprives the general computing core that is executing low-priority business of its bus usage rights.

[0023] The bus arbiter is equipped with computing power slicing stripping logic and atomic operation protection state machine;

[0024] When the bus arbiter executes the deprivation of bus access, it disconnects the bus routing matrix corresponding to the peripheral management slice within a single clock cycle through the computing power slice stripping logic, while maintaining the clock continuity of the core control slice. It executes the computing power slice stripping logic based on dynamic priority topology: disconnects the bus routing matrix corresponding to the peripheral management slice within a single clock cycle through the hardware mask register, while maintaining the clock continuity of the core control slice.

[0025] The bus arbiter follows the atomic operation protection principle: when the truncated task is within the critical section, the bus transaction is latched and the atomic operation is waited for to complete; when it is outside the critical section, it is immediately suspended and its context is saved to the privileged priority rescue area in the shared static random access memory, and the computing resources released are reorganized into the fault-protected computing pool; after the fault state is cleared, the execution of the suspended task is resumed from the privileged priority rescue area.

[0026] Preferably, as a preferred embodiment of the intelligent monitoring and control system for distribution network status based on a multi-core heterogeneous hardware architecture according to the present invention, it includes the hot migration module, which constructs multiple binary code image spaces corresponding to each heterogeneous instruction set during system initialization, pre-statically stores pre-compiled binary code images of each computing core in non-volatile memory, and specifies, through compilation constraint keywords, that the byte alignment, field order, and physical space occupied by the data input and output interface structures inside the two sets of images are completely consistent in memory;

[0027] The hot-migrating module, through the on-chip direct memory access controller, directly writes a hardware context snapshot containing the program counter value, general-purpose register set value, stack pointer value, and original sampled data buffer pointer into the designated reserved address segment of the shared static random access memory at the interrupt response boundary of the hardware clock cycle.

[0028] The control flow of the hot migration module is implemented based on the underlying hardware mailbox mechanism, including a hardware snapshot security verification component and a sampling data pipeline freeze and restore unit; the hardware snapshot security verification component includes a cyclic redundancy check engine, and the sampling data pipeline freeze and restore unit includes a hardware first-in-first-out queue.

[0029] The hardware mailbox contains a set of shadow registers built on the system bus and equipped with hardware mutexes. When the source core writes the snapshot base address and migration command word into the shadow register, it sends a hardware inter-core interrupt signal directly to the non-maskable interrupt pin of the target core through the underlying combinational logic circuit. After the target core responds to the interrupt, it performs base address redirection through the address translation unit and jumps to the corresponding binary code image execution entry point for algorithm hot connection.

[0030] The hardware snapshot security verification component adds a gate-level check code through a hardware cyclic redundancy check engine when writing the snapshot. When the target core reads the snapshot, it performs a hardware comparison. When the comparison is inconsistent, the fault-tolerant self-healing protection is triggered. The hot migration module writes a cold start command word to the reset control register of the target core through hardware combinational logic circuits, controls the target core to jump to the cold start initialization entry address pre-stored in the non-volatile memory, and recaptures the full waveform data of the current period at the maximum sampling rate for replacement calculation.

[0031] When the source core captures a snapshot, the sampling data pipeline freeze and restore unit sends a freeze signal to the analog-to-digital converter interrupt controller to temporarily store the newly arrived sampling points in the hardware first-in-first-out queue. After the target core completes the jump, it sends a catch-up instruction to control the target core to process the backlog of data in the queue in batches at a speed higher than the normal sampling rate until the queue is cleared and the normal sampling rhythm is restored.

[0032] On the other hand, the present invention provides a computer device, including a memory and a processor, wherein the memory stores a computer program, wherein when the computer program is executed by the processor, it implements the functional modules of the intelligent monitoring and control system for distribution network status based on a multi-core heterogeneous hardware architecture as described above.

[0033] On the other hand, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, it implements the intelligent monitoring and control system for distribution network status based on a multi-core heterogeneous hardware architecture as described above in the present invention.

[0034] The technical effects and advantages provided by the present invention in the above technical solution are as follows:

[0035] By using globally unified physical addressing and shared memory mapping of heterogeneous cores, homogeneous quantization alignment and pooling allocation of heterogeneous computing power are achieved. Based on the operating condition mutual exclusion arbiter and hardware-level time-domain integral debouncing logic, this invention can adaptively identify and hard-lock sudden fault states. Through the underlying hardware mailbox and non-maskable interrupt mechanism, it directly bypasses the software operating system scheduling, performs microsecond-level lossless hot migration of power algorithm hardware context snapshots, and introduces atomic operation protection and privileged rescue mechanisms in bus preemption. Combined with data pipeline freezing and first-in-first-out queue catch-up units, it ensures the temporal integrity and data consistency of data, completely solves the computing power idleness and resource limitations caused by traditional dedicated cores in terminals, and significantly improves the extreme real-time performance and high reliability of intelligent monitoring and control of distribution network status. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0037] Figure 1 This is a schematic diagram of the architecture of the intelligent monitoring and control system for distribution network status based on a multi-core heterogeneous hardware architecture provided in an embodiment of the present invention.

[0038] Figure 2 The timing diagram for bus preemption and slice isolation control of the bus arbiter under fault conditions is provided in the embodiments of the present invention. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0040] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0041] In the description of this application, the term "for example" is used to mean "used as an example, illustration, or description." Any embodiment described as "for example" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use the invention. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that the invention can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of the invention with unnecessary detail. Therefore, the invention is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0042] Example 1

[0043] This embodiment provides, for example Figure 1 The distribution network status intelligent monitoring and control system shown is based on a multi-core heterogeneous hardware architecture, specifically including a multi-core heterogeneous hardware platform, an adaptive monitoring module, a dynamic computing power resource pooling topology layer, and a hot migration module.

[0044] The multi-core heterogeneous hardware platform includes at least one general-purpose computing core, at least one digital signal processing core, and at least one artificial intelligence inference core.

[0045] The adaptive monitoring module is used to collect time-series physical state data of the distribution network in real time, and dynamically identify the current operating condition of the distribution network based on the characteristics of the state data, and output the corresponding operating condition command.

[0046] The dynamic computing resource pooling topology layer is deployed on the underlying hardware abstraction layer. It is used to uniformly address the register address space and static random access memory of the general computing core, digital signal processing core and artificial intelligence inference core, abstract each heterogeneous core into homogeneous virtual computing power element, and construct a dynamic computing resource status table.

[0047] The hot migration module is used to establish multiple sets of binary image code spaces for power core algorithms compiled for different heterogeneous kernel instruction sets, but with the same data interface structure; and according to the operating status instructions, it sends inter-core interrupts through a hardware communication mailbox mechanism to perform microsecond-level lossless migration of the hardware context snapshot of the currently running power core algorithm between the homogeneous virtual computing units.

[0048] In this embodiment, the adaptive monitoring module is specifically described. This module is used to collect real-time time-series physical state data of the distribution network, dynamically identify the current operating condition of the distribution network based on the characteristics of the state data, and output corresponding operating condition commands. Specifically, it includes the following:

[0049] A high-precision off-chip analog-to-digital converter acquires the bus voltage and branch current time-series signals of the distribution network nodes in real time at a fixed high-frequency sampling rate. A sliding monitoring window with a time span of one standard power frequency cycle is constructed. At each sampling point, physical characteristic quantities are extracted in real time through differential calculation components, RMS value calculation components, and fast Fourier transform accelerated preprocessing units. These include fundamental RMS characteristics, abrupt change characteristics, harmonic characteristics, and distributed generation characteristics. The fundamental RMS characteristics include the fundamental RMS values ​​of the bus voltage and branch current. The abrupt change characteristics are obtained by subtracting the fundamental RMS value of the corresponding moment in the previous power frequency cycle from the fundamental RMS value of the current cycle and taking the absolute value. The harmonic characteristics include the total voltage harmonic distortion rate and total current harmonic distortion rate extracted by performing fast low-order harmonic analysis on the data within the sliding monitoring window through hardware. The distributed generation characteristics include the rate of change of the backfeed power from the distributed generation side over time.

[0050] The adaptive monitoring module also includes an internal operating condition mutual exclusion arbiter, configured with priority-based logic: fault state > load prediction state > normal monitoring state. By comparing the extracted physical feature quantities with preset power grid safe operation boundary thresholds in real time, the module dynamically identifies the following three typical operating conditions and sends corresponding hardware commands to the underlying bus:

[0051] State 1, Normal Monitoring State: When the system simultaneously meets the following four conditions, and the current system real-time clock is not within the preset peak load prediction trigger period:

[0052] The bus voltage fluctuation is less than the preset steady-state voltage fluctuation threshold.

[0053] The branch current mutation is less than the preset primary threshold for current mutation.

[0054] The total current harmonic distortion rate is less than the preset harmonic distortion threshold.

[0055] The rate of change of the backfeed power on the distributed power source side over time is less than the preset basic threshold for power fluctuation.

[0056] The adaptive monitoring module outputs a normal monitoring state command to the underlying hardware abstraction layer;

[0057] State 2, Load Prediction State: When the system detects that the sudden change in the branch current is less than the preset short-circuit setting current threshold, and meets any of the following conditions:

[0058] The system's real-time clock has entered the preset period for distributed photovoltaic power generation.

[0059] The rate of change of the backfeed power on the distributed power source side over time is greater than or equal to a preset basic threshold for power fluctuation.

[0060] The total current harmonic distortion rate is greater than or equal to the preset harmonic distortion threshold.

[0061] The adaptive monitoring module outputs load prediction state instructions to the underlying hardware abstraction layer;

[0062] State 3, Fault State: When a phase-to-phase short-circuit fault occurs in the distribution network, the physical characteristic quantity within the sliding monitoring window instantaneously satisfies any of the following conditions:

[0063] The sudden change in the branch current is greater than or equal to the preset short-circuit setting current threshold.

[0064] The bus voltage surge is greater than or equal to a preset surge severity threshold.

[0065] Within microseconds of any of the above-mentioned judgment conditions being met, the hardware comparator in the adaptive monitoring module directly bypasses the software scheduling chain of the upper-layer embedded operating system and sends a high-priority non-maskable interrupt to the hot migration module through a dedicated hardware pin, and latches the fault state instruction; wherein, after the protection action is completed, the latched state must be automatically cleared only after it is continuously detected that all fault characteristic quantities within the sliding monitoring window of at least three power frequency cycles have recovered to the normal monitoring state threshold range and the fault reset timer has expired;

[0066] The adaptive monitoring module also includes a fundamental frequency change rate time-domain integrator. When extracting the bus voltage change and branch current change, the hardware comparator performs time-domain integration and accumulation of the change difference of a consecutive preset number of sampling points through the fundamental frequency change rate time-domain integrator. When the accumulated time-domain integration value continuously exceeds the integration trigger threshold within a preset time window, it is determined to be a real operating condition transition. Through the dual constraints of the time-domain integration accumulation and the time window, the hardware eliminates the instantaneous pseudo-changes caused by the inrush current of the power grid due to switch closing and high-frequency random glitches, and avoids high-frequency flickering switching of the operating condition mutual exclusion arbitrator.

[0067] In this embodiment, all the power grid safety operation boundary thresholds mentioned above, including steady-state voltage fluctuation threshold, primary current mutation threshold, short-circuit setting current large current threshold, and surge severity threshold, are statically stored in the on-chip non-volatile memory within the multi-core heterogeneous hardware platform and can be remotely configured through the management core in a non-faulty state.

[0068] In this embodiment, the dynamic computing resource pooling topology layer needs to be specifically described. Deployed at the underlying hardware abstraction layer, this layer is used to uniformly address the register address spaces and static random access memory of the general-purpose computing core, digital signal processing core, and artificial intelligence inference core. It abstracts each heterogeneous core into homogeneous virtual computing power elements and constructs a dynamic computing resource status table, specifically including the following:

[0069] During the system startup phase, a globally unified memory mapping is performed through the underlying firmware, including address space partitioning, hardware barriers, and shared access. The address space partitioning involves asymmetrically dividing the physical address space of the entire chipset, allocating globally unique physical addresses to the control register group, configuration register group, internal high-speed static random access memory, and off-chip global dynamic memory of each heterogeneous core. The hardware barriers and shared access are achieved by configuring a bus memory protection unit, where each core, while having its own independent private memory space, shares a physically contiguous shared static random access memory. The shared static random access memory is equipped with a hardware-level memory access arbitrator, supporting four access modes: exclusive write, shared read, read-write lock, and unbuffered direct write.

[0070] Based on the globally unified addressing, the dynamic computing resource pooling topology layer eliminates the differences in physical hardware architecture and instruction set type among heterogeneous cores, and abstracts them into logically homogeneous virtual computing power elements. Each virtual computing power element corresponds to a set of standardized descriptor structures. The descriptor structures are used to shield the underlying hardware microarchitecture details, enabling the upper-layer scheduling logic to align and allocate computing power resources. The hardware abstraction layer defines a normalized standard computing power equivalent based on the number of hardware multipliers, floating-point and fixed-point arithmetic capabilities, and current clock frequency of each heterogeneous core, in order to realize the quantification and equivalent mapping of the computing power of heterogeneous cores.

[0071] The dynamic computing resource pooling topology layer constructs and maintains a dynamic computing resource status table in real time within a specific reserved area of ​​the static random access memory inside the chip. It is driven in real time by the on-chip underlying hardware statistical counter to dynamically reflect the current computing load overload status of the entire multi-core heterogeneous system. The core indicators maintained include: core utilization rate, thermal safety and power consumption, and computing kernel status markers.

[0072] The core utilization rate metric is achieved by using an on-chip hardware timer to cyclically count the number of effective instruction execution clock cycles for each virtual computing unit within a unit time window, and to update and register the current real-time load utilization rate percentage of each core in real time.

[0073] Thermal safety and power consumption indicators are measured by using an on-chip integrated digital temperature sensor and current and voltage monitoring circuit to periodically read the current operating temperature and real-time power consumption of each core area, which serve as thermal safety limits during dynamic pooling scheduling of computing power.

[0074] The computing kernel status flag is a flag that explicitly marks the current hardware enable status of each virtual computing element and the priority flag of the power service it is currently executing in the status table;

[0075] The system scans the dynamic computing resource status table in real time and performs dynamic reorganization and pooling scheduling of computing resources based on different operating condition commands issued by the adaptive monitoring module. The specific response process includes:

[0076] Normal monitoring state response: When a normal monitoring state command is received, the topology layer searches the state table and, through the power management unit, cuts off the power to the dedicated digital signal processing core and the artificial intelligence inference core, which are under zero load, and marks them as "sleep state" in the state table to achieve the ultimate low power consumption operation of the entire system;

[0077] Load forecasting response: When a load forecasting command is received, the topology layer retrieves the status table and, in response to the surge in computing demand caused by power fluctuations on the distributed power supply side, immediately powers on and wakes up the dormant AI inference core, changes its status to "ready" and includes it in the currently available computing power pool, and dynamically reconstructs the bus interconnection topology and routing path.

[0078] Fault response: When the highest priority fault command is received, the topology layer searches the status table within microseconds to quickly identify the general computing core that is currently executing low-priority non-control services, and revokes the bus usage right of the low-priority service through the bus arbiter;

[0079] The bus arbiter is equipped with computing power slicing stripping logic and atomic operation protection state machine;

[0080] When the bus arbiter executes the deprivation of bus access, it performs a computing power slice stripping logic based on dynamic priority topology: the dynamic computing power resource status table divides virtual computing power elements into core control slices, basic monitoring slices, and peripheral management slices according to service tags; when the highest priority fault state instruction is received, the bus arbiter forcibly disconnects the bus routing matrix corresponding to the peripheral management slice within a single clock cycle through the hardware mask register, while maintaining the clock continuity of the core control slice; when the truncated task is within the atomic operation critical section, the bus arbiter latches the current bus transaction until the moment the hardware state machine issues the atomic operation completion signal, and immediately activates the bus deprivation circuit, achieving extreme speed reorganization of heterogeneous computing power resources while ensuring the consistency of underlying hardware data;

[0081] The arbitrator follows the atomic operation protection principle: if the truncated task is outside the critical section, it is immediately suspended; if it is inside the critical section, it waits for the atomic operation to complete. The task context is saved to the privileged priority rescue area in shared static random access memory, and its computing resources are reorganized into the fault-protected computing pool. After the fault is cleared, the execution of the suspended task is resumed from the rescue area.

[0082] This invention also provides a bus arbitration and isolation mechanism; such as Figure 2 The diagram illustrates the hardware timing logic for the bus arbiter to preempt the bus and perform slice isolation in a fault state; Before a certain time, the system is in normal monitoring / load prediction state, the external management bus routing remains at a high level and is executing low-priority non-real-time protection services; when When a fault determination is established, the hardware comparator triggers instantaneously, and the highest priority interrupt abruptly goes high; the bus arbiter responds to this interrupt, forcibly disconnecting the peripheral management bus route within a single clock cycle, achieving instantaneous physical isolation of the peripheral slice; the system master clock pulse and core control bus route maintain continuous and uninterrupted levels to ensure the deterministic timing of the power core protection services; Immediately after the event, the low-priority core bus rights are forcibly revoked and suspended, and its hardware context is written to the privileged rescue area in shared static random access memory. The fault-protected compute pool is instantly reorganized and activated, controlling the target core to read the snapshot and initiate high-frequency catch-up clearing of backlogged data in a first-in-first-out queue, entering the fault-protected takeover running state. The entire preemption, isolation, and hot migration process is completed losslessly within microseconds.

[0083] In this embodiment, the hot migration module is specifically described. This module is used to establish multiple sets of binary image code spaces for the power core algorithm, compiled for different heterogeneous kernel instruction sets but with the same data interface structure. Based on the operating status instructions, it sends inter-core interrupts via a hardware communication mailbox mechanism to perform microsecond-level lossless migration of the hardware context snapshot of the currently running power core algorithm between the homogeneous virtual computing units. Specifically, this includes the following:

[0084] A dual code mirror space is constructed during system initialization, specifically as follows:

[0085] Heterogeneous instruction set pre-compilation: In a specific sector of non-volatile memory, a first binary code image compiled for a general-purpose computing core instruction set and a second binary code image compiled for a digital signal processing core instruction set are pre-statically stored.

[0086] Data interface structure alignment: The first binary code image and the second binary code image have completely equivalent logical functions at the source code level, and during the compilation stage, the byte alignment, field order and physical space of their internal data input / output interface structures in memory are completely consistent through compilation constraint keywords.

[0087] The capture and extraction of hardware context snapshots are performed through on-chip hardware components, specifically including:

[0088] Snapshot content definition: The hardware context snapshot includes the current program counter value of the general-purpose computing core, the numerical snapshot of the current general-purpose register group, the current stack pointer value, and the starting address pointer and data length counter value of the raw sampled data buffer currently being processed;

[0089] Snapshot hardware hardening: In response to the migration signal, the hot migration module writes the hardware context snapshot directly into the designated reserved address segment of the aforementioned physically contiguous shared static random access memory through the on-chip direct memory access controller at the interrupt response boundary of the hardware clock cycle, thus completing the physical hardening of the snapshot. The entire extraction and hardening process does not go through any upper-layer operating system software protocol stack.

[0090] The control flow for algorithm migration based on the hardware mailbox mechanism includes:

[0091] Hardware mailbox topology construction: On the system bus of a multi-core heterogeneous chip, a set of shadow registers with hardware mutexes are constructed as a hardware mailbox data buffer;

[0092] Microsecond-level transmission control: When the adaptive monitoring module generates normal monitoring state instructions, load prediction state instructions, and fault state instructions, it directly writes the corresponding instruction code words into the designated register of the hardware mailbox;

[0093] Hardware mailbox control chain response: After the general computing core completes the hardening of the hardware context snapshot, it writes a specific migration command word to the source control register of the system hardware mailbox through the on-chip bus, and at the same time writes the base address pointer of the context snapshot stored in the shared static random access memory.

[0094] Hardware inter-core interrupt triggering: After the hardware mailbox detects that a command word has been written to the target register, it sends a hardware inter-core interrupt signal directly to the non-maskable interrupt pin of the target digital signal processing core through the underlying hardware combinational logic circuit; the target digital signal processing core directly responds to and processes the non-maskable interrupt at the hardware circuit layer, with the time controlled within the microsecond range, bypassing the process context switching wait of the software operating system.

[0095] After responding to the hardware inter-core interrupt, the target digital signal processing core reads the migration command word and the snapshot base address pointer through the hardware mailbox, and executes the following seamless takeover and execution process:

[0096] Address space remapping and jump: The target digital signal processing core directly addresses across the bus and reads the hardware context snapshot stored in the shared static random access memory by reading the snapshot base address pointer; the address translation unit in the module converts the program counter value and waveform pointer in the snapshot into the corresponding logical physical address on the target digital signal processing core side, and directly redirects the inline program counter of the target digital signal processing core to the corresponding execution entry point of the second binary code image;

[0097] The hot migration module also includes a hardware snapshot security verification component. When the general-purpose computing core writes the hardware context snapshot to the physically contiguous shared static random access memory, the on-chip hardware cyclic redundancy check engine simultaneously performs parallel calculations on the program counter value, the general-purpose register group value, and the stack pointer value, and appends a gate-level checksum to the end of the snapshot. When the target digital signal processing core responds to an unmasked interrupt and reads the snapshot, its internal verification circuit performs hardware comparison of the checksum. If the comparison matches, the address space remapping and jump are executed. If the comparison does not match, the snapshot data is determined to be corrupted, the system triggers fault-tolerant self-healing protection, directly abandons breakpoint recovery, controls the target digital signal processing core to jump to the cold start initialization entry of the second binary code image, and recaptures the full waveform data of the current power frequency cycle at the maximum sampling rate for replacement calculation.

[0098] Algorithm microsecond-level hot-connection: After the digital signal processing core completes the jump, it directly reads the current sampling waveform pointer and intermediate register status in the shared static random access memory, skips the algorithm initialization, memory allocation and pre-filtering stages, and directly continues to execute large-point fast Fourier transform calculations at the breakpoint position of the takeover.

[0099] 15ms limit control closed loop: Through the above-mentioned cross-instruction set hardware context snapshot hot migration, the data recopy and state reconstruction delay during heterogeneous instruction set algorithm switching is eliminated, so that the entire path closed loop control time of the multi-core heterogeneous system from the adaptive monitoring module capturing the phase-to-phase short circuit fault to the completion of hot migration, and then to the output of the final trip control command by the dedicated digital signal processing core is strictly controlled within 15 milliseconds.

[0100] The hot migration module also includes a sampling data pipeline freeze and restore unit, the execution flow of which is as follows:

[0101] While the source core begins capturing a hardware context snapshot, a freeze signal is sent to the analog-to-digital converter data-ready interrupt controller to suspend the writing of new sampled data to shared static random access memory and temporarily store newly arrived sampled points in the hardware first-in-first-out queue. After the target core completes address remapping and begins executing the algorithm, this unit sends a catch-up instruction to the target core. After the target core completes the calculation of the current breakpoint, it processes the backlogged data in the first-in-first-out queue at a rate higher than the normal sampling rate until the queue is cleared and the normal sampling processing rhythm is resumed. The entire freeze-catch-up process is completely transparent to the upper-layer power algorithm, ensuring the temporal integrity and non-overlap of the sampled data before and after migration.

[0102] To prevent millisecond-level latency caused by the software protocol stack when transmitting operating status commands between heterogeneous cores, in this embodiment, the command transmission between the adaptive monitoring module and the hot migration module is entirely completed by the underlying hardware mailbox:

[0103] Hardware mailbox topology: On the system bus of a multi-core heterogeneous chip, a set of shadow registers with hardware mutexes are set up as a hardware mailbox data buffer.

[0104] Microsecond-level transmission control: Once the adaptive monitoring module generates normal monitoring state instructions, load prediction state instructions, and fault state instructions, it directly writes the corresponding instruction code words into the designated register of the hardware mailbox;

[0105] Hardware interrupt triggering: After the write operation is completed, the hardware mailbox automatically triggers an inter-core interrupt of the target computing core at the hardware circuit layer; the target computing core responds to the interrupt within microseconds and reads the instruction code word in the register, and immediately starts the computing power pooling reconstruction and cross-instruction set hot migration of the algorithm, thereby eliminating the computing power response lag caused by traditional software communication methods.

[0106] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0107] This embodiment also provides a storage medium storing a computer program. When executed by a processor, the program implements the functional modules of the intelligent monitoring and control system for distribution network status based on a multi-core heterogeneous hardware architecture as proposed in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0108] Example 2

[0109] The following is another embodiment of the present invention, which provides an intelligent monitoring and control system for distribution network status based on a multi-core heterogeneous hardware architecture. In order to verify the beneficial effects of the present invention, a simulation experiment is conducted for scientific demonstration.

[0110] This experiment aims to verify the effectiveness of a distribution network status intelligent monitoring and control system based on a multi-core heterogeneous hardware architecture. Through power status data acquisition, dynamic operating condition identification, heterogeneous computing power pooling and reorganization, hardware context snapshot extraction, and cross-instruction set algorithm hot migration, the system enhances its early warning and ultra-low latency dynamic response capabilities under extreme sudden fault conditions in the distribution network. The experiment uses simulated high-frequency operating data of distribution network nodes and analyzes the full-path closed-loop control time and task reorganization success rate under different operating condition switching scenarios to verify the system's accuracy, real-time performance, and robustness in identifying distribution network operating conditions and dynamically allocating heterogeneous computing power.

[0111] The simulation experiment steps are implemented according to the content of the intelligent monitoring and control system for distribution network status based on multi-core heterogeneous hardware architecture provided in Example 1, and the specific steps include:

[0112] By using a high-precision analog-to-digital converter to acquire the bus voltage and branch current time-series signals of the distribution network nodes in real time at a fixed high-frequency sampling rate, a sliding monitoring window with a standard power frequency cycle is constructed to extract physical characteristic quantities including the fundamental effective value, abrupt changes, harmonics, and the rate of change of distributed power sources in real time.

[0113] Under the priority-fixed logic of the mutual exclusion arbitrator of the working condition, the extracted physical feature quantities are compared with the preset boundary thresholds in real time to dynamically identify whether the system is currently in "normal monitoring state", "load prediction state" or "fault state", and send the corresponding hardware instructions to the underlying bus.

[0114] The dynamic computing resource pooling topology layer scans the dynamic computing resource status table in static random access memory in real time. Based on the issued working status instructions, it dynamically executes power switching, bus preemption, and computing resource pooling reorganization of heterogeneous cores through the bus arbiter, power management unit, and hardware mask register.

[0115] When the system transitions to a critical fault state, the hardware comparator bypasses the software scheduling chain and directly triggers an unmasked interrupt; the hot migration module captures a snapshot of the hardware context of the general computing core and saves it to shared static random access memory, and triggers an inter-core interrupt of the target digital signal processing core based on the underlying hardware mailbox mechanism. The target core performs address remapping and jumps to the corresponding pre-compiled binary code image execution entry point, realizing microsecond-level lossless hot connection and takeover of the algorithm.

[0116] The specific data from the above simulation experiment are shown in Table 1.

[0117] Table 1 Data Recording Table of Simulation Experiment of the Invention

[0118] 0–5.0 No. 1 transformer bus Voltage: 1.0 pu; Current: 0.8 pu; Harmonic distortion: 1.2% Normal monitoring status General-purpose core: Running; DSP core: Sleeping; AI core: Sleeping Normal / Not Triggered - 0.5 milliseconds (fixed period) Dedicated accelerated core power-off enables the system to operate at extremely low power consumption. 5.0–10.0 No. 1 transformer bus Voltage: 1.01 pu; Current: 1.1 pu; Harmonic distortion: 1.5% Normal monitoring status General-purpose core: Running; DSP core: Sleeping; AI core: Sleeping Normal / Not Triggered - 0.5 milliseconds (fixed period) The time-domain integrator filters out minor fluctuations and maintains normal monitoring. 10.0–15.0 Distributed photovoltaic point No. 2 Voltage: 1.03 pu; Current: 1.2 pu; Power change rate: 15% / s Load forecast state General-purpose core: Running; DSP core: Sleeping; AI core: Ready. Normal / Not Triggered - 1.2 milliseconds Awaken the core of artificial intelligence inference and reconstruct the bus interconnection topology and routing. 15.0–15.1 Branch Line 3 Voltage: 0.3 pu; Current: 8.5 pu; Sudden change: Exceeded limits Fault state (phase-to-phase short circuit) General-purpose core: Suspend DSP core: Take over AI core: Ready Verification passed / Gate-level checksum attached 4.2 microseconds 11.5 milliseconds (burst response) Send the highest priority non-maskable interrupt, latch the fault state, forcibly strip the general-purpose core bus, and the DSP core takes over the algorithm at the microsecond level and outputs a trip command. 15.1–20.0 Branch Line 3 Voltage: 0.0 pu; Current: 0.0 pu; Sudden change: Returned to normal range Fault state (state latching in progress) General Core: Suspend DSP Core: Run AI Core: Ready Normal / Keep - 0.8 milliseconds Protection action completed, freeze-catch-up unit cleared backlogged data, fault reset timer is counting down. After 20.0 No. 1 transformer bus Voltage: 1.0 pu; Current: 0.75 pu; Harmonic distortion: 1.1% Normal monitoring status General Core: Restore DSP Core: Hibernate AI Core: Hibernate Normal / Clear latch - 0.5 milliseconds If the timer times out and three consecutive cycles show normal characteristics, the latch is automatically cleared, and the suspended general-purpose core task is resumed from the privileged rescue zone.

[0119] Experimental Analysis:

[0120] By comparing the dynamic response indicators of a multi-core heterogeneous system under different operating conditions, the real-time performance and reliability of the system in rapidly identifying distribution network status, dynamically reorganizing computing power, and migrating across instruction sets are verified. Experimental results show that under sudden fault conditions such as phase-to-phase short circuits, this invention utilizes the underlying hardware mailbox, non-maskable interrupts, and hardware snapshot verification mechanisms to directly bypass the embedded operating system software scheduling chain, keeping the hot migration time of cross-instruction set algorithms within 4.2 microseconds. The bus arbitrator, in conjunction with the privileged priority rescue area and the first-in-first-out queue catch-up unit, achieves extreme-speed reorganization of heterogeneous computing resources while ensuring the consistency and timing integrity of underlying hardware data. This ensures that the closed-loop control time of the entire path from fault capture, algorithm reconstruction migration to outputting the final trip control command is strictly controlled within 15 milliseconds, effectively avoiding the delays caused by traditional software communication and process switching, and significantly improving the relay protection robustness and overall system energy efficiency of the multi-core heterogeneous distribution network terminal under extreme operating conditions.

[0121] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A distribution network status intelligent monitoring and control system based on a multi-core heterogeneous hardware architecture, characterized in that: It includes a multi-core heterogeneous hardware platform, an adaptive monitoring module, a dynamic computing resource pooling topology layer, and a hot migration module; The multi-core heterogeneous hardware platform includes at least one general-purpose computing core, at least one digital signal processing core, and at least one artificial intelligence inference core. The adaptive monitoring module is used to collect time-series physical state data of the distribution network in real time, and dynamically identify the current operating condition of the distribution network based on the characteristics of the state data, and output the corresponding operating condition command. The adaptive monitoring module acquires the bus voltage timing signal and branch current timing signal of the distribution network node in real time through an off-chip analog-to-digital converter, constructs a sliding monitoring window, and extracts physical feature quantities including fundamental effective value characteristics, abrupt change characteristics, harmonic characteristics and distributed power source characteristics in real time through internal computing components. The adaptive monitoring module is equipped with a condition state mutual exclusion arbitrator. The condition state mutual exclusion arbitrator is configured with priority fixed logic of "fault state > load prediction state > normal monitoring state". By comparing the physical feature quantity with the preset boundary threshold in real time, it dynamically identifies the normal monitoring state, load prediction state and fault state and latches them, and sends the corresponding hardware instructions to the underlying bus. The adaptive monitoring module includes a hardware comparator and configuration timing interlock logic. When a fault condition is determined, the hardware comparator sends the highest priority non-maskable interrupt directly to the hot-migrating module through a dedicated hardware pin and hardware latches the fault condition instruction until the protection action is completed, all fault characteristic quantities for a consecutive preset number of cycles are restored to the normal range, and the fault reset timer inside the system times out, at which point the latch is automatically cleared. The boundary threshold is statically stored in on-chip non-volatile memory and can only be remotely configured by the management core in a non-fault state. When the system latches a fault state instruction, the write enable control line of the non-volatile memory is forcibly closed by hardware, rejecting remote rewrite requests. The dynamic computing resource pooling topology layer is deployed on the underlying hardware abstraction layer. It is used to uniformly address the register address space and static random access memory of the general computing core, digital signal processing core and artificial intelligence inference core, abstract each heterogeneous core into homogeneous virtual computing power element, and construct a dynamic computing resource status table. The hot migration module is used to establish multiple sets of binary image code spaces for power core algorithms that are compiled for different heterogeneous kernel instruction sets and have the same data interface structure. Based on the operating status instructions, the hardware context snapshots of the currently running power core algorithm are transferred between the homogeneous virtual computing units in microseconds through the hardware communication mailbox mechanism to send inter-core interrupts.

2. The intelligent monitoring and control system for distribution network status based on a multi-core heterogeneous hardware architecture according to claim 1, characterized in that: The adaptive monitoring module also includes a fundamental frequency change rate time-domain integrator. When extracting abrupt change features, it performs time-domain integration and accumulation of the abrupt change difference of a consecutive preset number of sampling points. When the time-domain integrated cumulative value continuously exceeds the integration trigger threshold within a preset time window, it is determined to be a real working condition transition, thereby eliminating the high-frequency flickering switching of the working condition caused by glitch noise at the hardware level.

3. The intelligent monitoring and control system for distribution network status based on a multi-core heterogeneous hardware architecture according to claim 1, characterized in that: The dynamic computing power resource pooling topology layer, during the system startup phase, performs a globally unified memory mapping through the underlying firmware to asymmetrically divide the physical address space of the entire chipset and allocate globally unique physical addresses to the register group and memory of each heterogeneous core. The bus memory protection unit is configured to intercept unauthorized core bus out-of-bounds transactions. Each core is mapped to a physically contiguous shared static random access memory. The shared static random access memory is configured with a hardware-level memory access arbitrator and supports four access modes: exclusive write, shared read, read-write lock, and uncached direct write.

4. The intelligent monitoring and control system for distribution network status based on a multi-core heterogeneous hardware architecture according to claim 1, characterized in that: Each homogeneous virtual computing power unit corresponds to a set of standardized descriptor structures in the underlying hardware abstraction layer. The hardware abstraction layer defines a normalized standard computing power equivalent based on the number of hardware multipliers, floating-point and fixed-point arithmetic capabilities, and current operating frequency of each heterogeneous core, so as to realize the equivalent quantization mapping of the computing power of heterogeneous cores. The dynamic computing resource pooling topology layer constructs a dynamic computing resource status table in a specific reserved area within the chip, and maintains in real time multi-dimensional indicators including core utilization rate, thermal safety and power consumption indicators, and computing kernel status markers; The dynamic computing resource pooling topology layer scans the dynamic computing resource status table in real time and performs computing resource scheduling: In normal monitoring mode, the power management unit powers down and marks the dedicated acceleration core with zero load as dormant. In load prediction mode, the AI ​​inference core in dormant mode is powered on and marked as ready, and the bus interconnect topology is reconstructed. In fault mode, the general computing core that is executing low-priority business is quickly identified, and the bus arbiter deprives the general computing core that is executing low-priority business of its bus usage rights.

5. The intelligent monitoring and control system for distribution network status based on a multi-core heterogeneous hardware architecture according to claim 4, characterized in that: The bus arbiter is equipped with computing power slicing stripping logic and atomic operation protection state machine; When the bus arbiter executes the deprivation of bus access, it disconnects the bus routing matrix corresponding to the peripheral management slice within a single clock cycle through the computing power slice stripping logic, while maintaining the clock continuity of the core control slice. The bus arbiter follows the atomic operation protection principle: when the truncated task is within the critical section, the bus transaction is latched and the atomic operation is waited for to complete; when it is outside the critical section, it is immediately suspended and its context is saved to the privileged priority rescue area in the shared static random access memory, and the computing resources released are reorganized into the fault-protected computing pool. After the fault is cleared, the execution of the suspended task is resumed from the privileged priority rescue area.

6. The intelligent monitoring and control system for distribution network status based on a multi-core heterogeneous hardware architecture according to claim 1, characterized in that: The hot migration module constructs multiple binary code image spaces corresponding to each heterogeneous instruction set during system initialization. It pre-statically stores pre-compiled binary code images of each computing power kernel in non-volatile memory and specifies, through compilation constraint keywords, that the byte alignment, field order, and physical space occupied by the data input and output interface structures inside each image are completely consistent in memory. The hot-migrating module, through the on-chip direct memory access controller, directly writes a hardware context snapshot containing the program counter value, general-purpose register set value, stack pointer value, and original sampled data buffer pointer into a designated reserved address segment of shared static random access memory at the interrupt response boundary of the hardware clock cycle.

7. The intelligent monitoring and control system for distribution network status based on a multi-core heterogeneous hardware architecture according to claim 6, characterized in that: The control flow of the hot migration module is implemented based on the underlying hardware mailbox mechanism, including a hardware snapshot security verification component and a sampling data pipeline freeze and restore unit; the hardware snapshot security verification component includes a cyclic redundancy check engine, and the sampling data pipeline freeze and restore unit includes a hardware first-in-first-out queue. The hardware mailbox contains a set of shadow registers built on the system bus and equipped with hardware mutexes. When the source core writes the snapshot base address and migration command word into the shadow register, it sends a hardware inter-core interrupt signal directly to the non-maskable interrupt pin of the target core through the underlying combinational logic circuit. After the target core responds to the interruption, the base address is redirected through the address translation unit, and the execution entry point of the corresponding binary code image is jumped to perform algorithm hot connection. The hardware snapshot security verification component adds a gate-level check code through a hardware cyclic redundancy check engine when writing the snapshot. When the target core reads the snapshot, it performs a hardware comparison. When the comparison is inconsistent, the fault-tolerant self-healing protection is triggered. The hot migration module writes a cold start command word to the reset control register of the target core through hardware combinational logic circuits, controls the target core to jump to the cold start initialization entry address pre-stored in the non-volatile memory, and recaptures the full waveform data of the current period at the maximum sampling rate for replacement calculation. When the source core captures a snapshot, the sampling data pipeline freeze and restore unit sends a freeze signal to the analog-to-digital converter interrupt controller and temporarily stores the newly arrived sampling points in the hardware first-in-first-out queue. After the target core completes the jump, a catch-up instruction is sent to control the target core to process the backlog of data in the queue at a rate higher than the normal sampling rate, until the queue is cleared and the normal sampling rhythm is restored.

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