Metro vehicle depot low-voltage power distribution three-level load cabinet interlinkage control method and system

Abstract

The present application relates to the technical field of low-voltage power distribution of rail transit, and discloses a metro vehicle depot low-voltage power distribution three-level load inter-cabinet linkage control method and system, which collects the instantaneous voltage of the bus of the incoming line power distribution cabinet and charges the energy storage module; according to the voltage drop trend and the dynamic characteristic impedance obtained by injecting high-frequency current, double-factor composite recognition is carried out, and the fault state quantity is generated after the recognition; the fault state quantity is modulated into a trip instruction with a check feature and sent to the second incoming line cabinet for collaborative verification; when the fault state quantity or the cross-cabinet instruction verification is valid, the power supply circuit is disconnected and the energy storage module is used for power supply, and the corresponding power supply circuit is sequentially disconnected according to the three-level load classification and the step delay time sequence. The present application overcomes the fault misjudgment caused by the residual voltage interference of inductive load, eliminates the false triggering of the communication bus background noise, and ensures that the power distribution cabinet independently and smoothly executes the load gradient linkage removal under the condition of bus physical power loss.

Description

Technical Field

[0001] This invention relates to the field of low-voltage power distribution technology for rail transit, specifically to a method and system for the linkage control of three-level load cabinets in low-voltage power distribution in subway depots. Background Technology

[0002] The low-voltage power distribution system in subway depots is responsible for supplying power to facilities such as train maintenance, environmental control and ventilation, and station lighting. It is usually equipped with dual-incoming power distribution cabinets to ensure power redundancy. In the event of a transient power outage fault in the main power grid, the power distribution system usually needs to disconnect tertiary loads to mitigate the sudden load impact that may occur when power is restored to the incoming lines or the bus tie is closed.

[0003] The third-level loads in the depot often contain a large number of high-capacity inductive devices. When a power outage occurs in the power distribution network, the rotor of the induction motor continues to slide due to mechanical inertia, which can easily generate residual voltage on the busbar due to stator back EMF. Conventional low-voltage distribution protection logic often relies on fixed voltage amplitude thresholds as the trigger criterion for undervoltage. Under the condition of residual voltage, the busbar voltage amplitude decays relatively slowly, which can easily interfere with the judgment of the actual physical power outage state. This makes it difficult for the incoming distribution cabinet to quickly identify the undervoltage fault in the early stage of power failure, increasing the risk of protection failure or delayed action. The incoming distribution cabinets need to exchange information on the tripping status to coordinate the execution of linkage isolation. The electrical environment at the subway site is relatively complex, often accompanied by transient common-mode interference and background noise, while some inter-cabinet linkage communication mainly transmits basic level or conventional pulse signals. Electromagnetic interference on the physical bus can sometimes affect the judgment of the receiving distribution cabinet, posing a risk of misinterpreting interference spikes as linkage commands, which may lead to unexpected disconnection of the power supply branch load. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a method and system for the linkage control of three-level load cabinets in low-voltage power distribution in subway depots. This method solves the problems of inaccurate judgment and disordered action sequence caused by residual voltage interference from inductive equipment, communication noise between cabinets, and lack of control power supply under pressure loss conditions.

[0005] To achieve the above objectives, the present invention provides the following technical solution: The first aspect of this invention provides a method for inter-level linkage control of three-level load cabinets in low-voltage power distribution in a subway depot, applied to the first incoming power distribution cabinet, comprising: The instantaneous voltage signal of the first incoming power distribution cabinet bus is collected, and the energy storage module is charged using the first incoming power distribution cabinet bus. The voltage drop state is obtained based on the instantaneous voltage signal, and when the voltage drop state meets the drop trend condition, a probe current is injected into the busbar of the first incoming distribution cabinet to obtain the dynamic characteristic impedance. When the voltage drop condition meets the direct drop condition, or when the drop trend condition is met and the dynamic characteristic impedance shows open circuit characteristics, the two-factor composite identification of the undervoltage fault is determined to be valid, and a fault state quantity characterizing the undervoltage fault is generated. When a fault status quantity is generated, the fault status quantity is modulated into a trip command with verification characteristics and sent to the second incoming distribution cabinet. When the first incoming power distribution cabinet generates a fault status quantity, or receives a trip command from the second incoming power distribution cabinet and the collaborative verification is valid, the power supply circuit between the first incoming power distribution cabinet and the first incoming power distribution cabinet bus is cut off, the energy storage module provides working power, and according to the three-level load classification set and the preset tiered delay sequence, the corresponding three-level load power supply circuits are disconnected in sequence to perform load gradient shedding.

[0006] Furthermore, to ensure the reliability of the operating energy during the power outage dead zone, the specific implementation logic for charging the energy storage module using the first incoming distribution cabinet bus is as follows: The system monitors the instantaneous voltage across the energy storage module in real time and calculates the module's stored energy. The mathematical model for calculating the stored energy is set as half the product of the energy storage module's capacitance and the energy voltage factor. Specifically, the energy voltage factor is set as the difference between the square of the instantaneous voltage across the energy storage module and the square of a preset minimum blocking voltage threshold. The formula for calculating the stored energy is as follows: ; In the above formula: E represents the effective stored energy of the energy storage module at the current moment, in joules. This parameter is calculated in real time by the system processor; C represents the inherent capacitance value of the energy storage module, in farads. This parameter is obtained based on the rated nameplate parameters of the energy storage module and entered into the memory. This represents the instantaneous voltage across the energy storage module, measured in volts. This parameter is obtained by real-time acquisition of the potential difference across the energy storage module's plates via an internal analog-to-digital conversion channel. This parameter represents the preset minimum blocking voltage threshold, measured in volts. It represents the minimum supply voltage required to maintain normal logic operation of the control system and trigger the output relay. It is calibrated based on power consumption test data of the equipment hardware under extreme environments.

[0007] Under normal power supply conditions, the system controls the charging circuit to maintain this stored energy. It is always greater than the rated dissipation energy required for a single complete tripping process.

[0008] Furthermore, in order to accurately eliminate the interference from the back-feeding electromotive force of the induction motor group, the composite logic steps for determining whether the drop trend condition, the direct drop condition, and the open circuit characteristic are valid include: The system calculates the effective value and instantaneous rate of change of the instantaneous voltage signal in real time. When the effective value is less than the preset absolute undervoltage action threshold, the direct voltage drop condition is determined to be met, indicating that the power grid has experienced a momentary complete physical power outage.

[0009] When the instantaneous rate of change is less than the preset drop slope threshold and the effective value is greater than or equal to the absolute undervoltage action threshold, the drop trend condition is determined to be met. This indicates a residual voltage condition where the grid incoming line is disconnected but there is residual voltage due to the inductive load's inertial sliding and back-feeding stator back EMF. The absolute undervoltage action threshold is defined based on the minimum operating voltage required for the equipment to maintain normal computing power, and the drop slope threshold is calculated based on the electromagnetic energy attenuation constant during the rotor sliding phase of the inductive equipment.

[0010] Under this operating condition, a detection current is injected into the busbar of the first incoming distribution cabinet. The frequency of the detection current is set to strictly avoid the power frequency and power frequency harmonics band, and a high-frequency detection current is injected into the busbar of the first incoming distribution cabinet. The high-frequency response voltage fed back from the busbar of the first incoming distribution cabinet is collected simultaneously; then the impedance detection logic is executed, and the formula for calculating the dynamic characteristic impedance is as follows: ; in: The dynamic characteristic impedance of the bus circuit under the injected high-frequency band is expressed in ohms and is calculated by the system in real time. The amplitude of the high-frequency response voltage is represented by volts. This parameter is obtained by performing a frequency domain transformation on the synchronously acquired voltage signal sequence to extract the target frequency point. This represents the amplitude of the probe current, measured in amperes. This parameter is obtained by reading the control reference value fed back from the signal injection circuit.

[0011] When the obtained dynamic characteristic impedance is greater than the preset open-circuit impedance judgment threshold, the dynamic characteristic impedance is judged to have open-circuit characteristics. The open-circuit impedance judgment threshold is determined based on the leakage reactance parameters of the power supply transformer and the equivalent test data of the bus-to-ground distributed capacitance.

[0012] Furthermore, to ensure the physical layer anti-interference and anti-interception capabilities of inter-cabinet communication commands, the steps for modulating and sending trip commands include: introducing a dynamic time-varying verification mask at the transmitting end of the first incoming distribution cabinet; mapping the fault status quantity into a high-frequency pulse sequence, and performing a mixing operation between the high-frequency pulse sequence and the verification mask to generate a high-frequency pseudo-differential pulse sequence as a trip command; and coupling the high-frequency pseudo-differential pulse sequence to the inter-cabinet physical bus via an isolation transformer.

[0013] Further, the confirmation step for the collaborative verification to be valid includes: receiving the received signal corresponding to the trip command sent by the second incoming distribution cabinet; performing demodulation on the received signal, and performing time integration on the demodulated signal within a preset signal sliding verification window width; when the integration result of the time integration operation is greater than a preset minimum integration energy threshold, and the result of feature matching verification of the received signal using a local verification mask is successful, the received trip command is determined to be valid after collaborative verification. The minimum integration energy threshold is calibrated based on the background common-mode noise energy peak test data picked up under the no-load state of the physical bus.

[0014] Furthermore, in order to prevent arcing and bus voltage oscillation caused by large-scale synchronous load shedding, the load gradient shedding step is carried out based on the constructed three-level load classification set: the system obtains the pre-configured electrical attribute tags of each three-level load power supply circuit; the power supply circuits characterized by electrical attribute tags as power equipment and inductive equipment are classified into the first type of load set; the power supply circuits characterized by electrical attribute tags as lighting equipment and resistive equipment are classified into the second type of load set.

[0015] The timing control actions for performing gradient shedding include: starting from the triggering time, after the first stage action dead time interval reaches the first time, triggering the first output solid-state relay to disconnect the power supply circuit corresponding to the first type of load set; starting from the first time, after the second stage action dead time interval reaches the second time, triggering the second output solid-state relay to disconnect the power supply circuit corresponding to the second type of load set, thus completing the shedding of all three levels of loads.

[0016] Furthermore, the timing constraints and power grid recovery actions include: the system sets the sum of the first-stage action dead time interval and the second-stage action dead time interval to constitute the overall action execution cycle, and executes the following timing constraint logic: ; in: This represents the overall execution cycle of the action, in seconds. The dead zone time interval for the first stage of action is represented in seconds. This parameter is calibrated based on the time it takes for the induced electromotive force inside the power equipment to decay to a safe threshold. This represents the dead time interval of the second stage of action, in seconds. This parameter is calibrated based on the inherent dead time data required for the relay to complete a single start-stop cycle. This represents the maximum fault clearance time window, measured in seconds. This parameter is obtained by reading the setting configuration file issued by the relay protection device of the superior substation.

[0017] After all the level 3 loads have been disconnected, when the voltage of the first incoming distribution cabinet busbar recovers and remains above the set normal operating voltage threshold, the fault status is reset, and the power supply circuit connection between the first incoming distribution cabinet and the energy storage module and the first incoming distribution cabinet busbar is restored.

[0018] A second aspect of the present invention provides a three-level load inter-cabinet linkage control system for low-voltage power distribution in a subway depot, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the steps of the three-level load inter-cabinet linkage control method for low-voltage power distribution in a subway depot as described in any specific implementation of the first aspect above.

[0019] This invention provides a method and system for the coordinated control of three-level load cabinets in low-voltage power distribution in subway depots. It has the following beneficial effects: 1. This invention combines voltage drop trends with dynamic characteristic impedance for composite identification, and modulates the generated fault state quantity into an instruction with verification characteristics and sends it to the second incoming distribution cabinet for collaborative verification, establishing a distribution cabinet linkage cut-off mechanism to eliminate false triggering caused by residual voltage of inductive equipment and bus noise.

[0020] 2. This invention utilizes the busbar to charge the energy storage module. After generating a fault status quantity or receiving and verifying the cross-cabinet command, the power supply circuit is cut off and the energy storage module supplies power. According to the load classification set and the stepped delay sequence, the corresponding circuits are disconnected in sequence to ensure that the distribution cabinet can independently perform load gradient shedding linkage action under the condition of physical power failure of the busbar. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the overall hardware architecture of the system of the present invention; Figure 2 This is the main flowchart of the linkage control method of the present invention; Figure 3 This is a flowchart of the logic judgment for the two-factor composite identification of undervoltage faults in this invention; Figure 4 This is a flowchart of the inter-cabinet command communication and collaborative verification process of the present invention; Figure 5 This is the timing control diagram for the three-level load gradient shedding of the present invention; Figure 6 This is a schematic diagram of the logic module of the linkage control device of the present invention. Detailed Implementation

[0022] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] Please see the appendix Figure 1 To be continued Figure 6 This invention provides a method and system for inter-level linkage control of low-voltage power distribution cabinets in a subway depot. This linkage control system is specifically applied to the first incoming power distribution cabinet, which, together with the second incoming power distribution cabinet, constitutes a dual-power supply network for the subway depot, serving as backup for each other. A physical communication bus for transmitting high-frequency modulated signals is arranged between the first and second incoming power distribution cabinets. This physical communication bus preferably adopts an RS485 differential bus architecture and is used in conjunction with an isolation transformer to transmit high-frequency pseudo-differential pulse signals.

[0024] The first incoming power distribution cabinet houses a processor and a memory connected to the processor. The processor is a high-performance microcontroller chip with a digital signal processing core, such as the STM32F429IGT6. The processor is electrically connected to a voltage acquisition circuit, a signal injection circuit, a communication transmitter circuit, a communication receiver circuit, and a relay control circuit. The sampling terminal of the voltage acquisition circuit is directly connected to the busbar of the first incoming power distribution cabinet, reading the instantaneous analog electrical signal on the busbar in real time and converting it into a digital signal for transmission to the processor. One end of the signal injection circuit is connected to the processor, and the other end is coupled to the busbar of the first incoming power distribution cabinet, responsible for applying an alternating electrical signal of a specific frequency to the busbar circuit according to the processor's trigger commands.

[0025] An energy storage module is installed inside the first incoming power distribution cabinet. The input terminal of the energy storage module is connected to the busbar of the first incoming power distribution cabinet through a power supply circuit, and the output terminal of the energy storage module is connected to the power supply terminal of the processor and the drive terminal of the relay control circuit. The relay control circuit includes several output solid-state relays. The operating contacts of each output solid-state relay are connected in series in the corresponding three-level load power supply circuit. The physical isolation of the three-level load power supply circuit is controlled by the on / off level signal of the processor.

[0026] The inter-cabinet linkage control method for the low-voltage power distribution three-level load cabinets in the subway depot may include the following steps: Step S1: Collect the instantaneous voltage signal of the first incoming power distribution cabinet bus and use the first incoming power distribution cabinet bus to charge the energy storage module. Step S2: Obtain the voltage drop state based on the instantaneous voltage signal, and when the voltage drop state meets the drop trend condition, inject a probe current into the busbar of the first incoming distribution cabinet to obtain the dynamic characteristic impedance. Step S3: When the voltage drop state meets the direct drop condition, or when the drop trend condition is met and the dynamic characteristic impedance exhibits open circuit characteristics, it is determined that the undervoltage fault dual-factor composite identification is established, and a fault state quantity characterizing the occurrence of the undervoltage fault is generated. Step S4: When the fault status quantity is generated, the fault status quantity is modulated into a trip command with verification features and sent to the second incoming distribution cabinet. Step S5: When the first incoming power distribution cabinet generates the fault status quantity, or receives a trip command sent by the second incoming power distribution cabinet and the collaborative verification is valid, the power supply circuit between the first incoming power distribution cabinet and the first incoming power distribution cabinet bus is cut off, the energy storage module provides working power, and according to the three-level load classification set and the preset stepped delay sequence, the corresponding three-level load power supply circuits are disconnected in sequence to perform load gradient shedding.

[0027] Regarding the specific implementation process of step S1, the system monitors the voltage fluctuation of the first incoming power distribution cabinet busbar in real time through a voltage acquisition circuit. Utilizing the normal power supply status of the busbar, the power extraction circuit is closed to maintain the energy reserve of the energy storage module. The energy storage module is a supercapacitor module with a rated voltage of 48V and a capacity of 500F. The power extraction circuit consists of a step-down regulator module, a reverse-charging diode, and a constant-current charging chip. The input terminal of the step-down regulator module is connected to the busbar, and the output terminal is connected to the constant-current charging chip via the reverse-charging diode. The output terminal of the constant-current charging chip is connected to both ends of the supercapacitor module. The processor monitors the instantaneous voltage across the energy storage module in real time and calculates the stored energy. The mathematical model for calculating the stored energy is set as half the product of the energy storage module's capacitance value and the energy voltage factor. The energy voltage factor is specifically set as the difference between the square of the instantaneous voltage across the energy storage module and the square of a preset minimum blocking voltage threshold. The processor performs real-time calculation of the stored energy according to the following formula: ; Where: E represents the effective stored energy of the energy storage module at the current moment, in joules, which is calculated in real time by the processor; C represents the inherent capacitance of the energy storage module, in farads, which is obtained based on the rated nameplate parameters of the energy storage module and entered into the memory. This represents the instantaneous voltage across the energy storage module, measured in volts. This parameter is obtained in real time by acquiring the potential difference across the plates of the energy storage module through the analog-to-digital conversion channel inside the processor. This represents the preset minimum latching voltage threshold in volts. This parameter represents the minimum supply voltage required to maintain normal logic operation of the processor and trigger the output solid-state relay. It is calibrated based on power consumption test data of the control device hardware under extreme environments and historical experience data (e.g., set to 42 volts).

[0028] Based on the above-described energy reserve calculation logic, the system continuously monitors the effective energy reserve when the first incoming distribution cabinet busbar is under normal power supply. The processor has a baseline dissipation energy parameter, which represents the rated dissipation energy required for a single complete tripping process. The rated dissipation energy required for a single complete tripping process is derived from the sum of the operating current consumption of all output solid-state relays corresponding to each level 3 load power supply circuit within the stepped delay sequence, plus historical statistical data on the computing power consumption of the processor executing the composite identification algorithm.

[0029] The processor continuously compares the effective reserve energy with the rated dissipation energy required for a single complete tripping process. When the effective reserve energy is detected to be close to or equal to the rated dissipation energy required for a single complete tripping process, the system controls the power supply circuit to draw current from the first incoming distribution cabinet bus in constant current mode to input current into the energy storage module, maintaining the effective reserve energy at a level greater than or equal to the rated dissipation energy required for a single complete tripping process (for example, setting the effective reserve energy to be maintained at a level greater than or equal to 20 joules). This mechanism ensures that during the dead time period of the first incoming distribution cabinet bus losing voltage and disconnecting the power supply circuit, the system has completely independent and sufficient internal energy to support the complete communication and load shedding operations.

[0030] In this embodiment, the processor executes the relevant logic steps to determine the validity of the dual-factor composite identification of undervoltage fault based on the digital signal continuously fed in by the voltage acquisition circuit. The processor distinguishes between the actual power outage and network disconnection state and the inertial reverse power supply state of the inductive load through multi-dimensional analysis of the bus electrical signal characteristics.

[0031] The processor receives the aforementioned digital signals in real time and calculates the effective value and instantaneous rate of change of the instantaneous voltage signal. The processor performs root mean square (RMS) calculation on discrete voltage sampling points within a preset time window to obtain the effective value; simultaneously, the processor calculates the instantaneous rate of change based on the difference between effective values ​​within adjacent time steps. The mathematical expression for the processor's instantaneous rate of change calculation is as follows: ; in: Represents the instantaneous rate of change, measured in volts per second. This parameter is calculated in real time by the processor through the internal arithmetic logic unit. This represents the effective voltage value calculated at the current moment, in volts. This represents the effective voltage value calculated at the previous time step, in volts. This represents the time step interval between two consecutive effective value calculations, in seconds. This parameter is set based on the hardware sampling frequency of the voltage acquisition circuit and the processing cycle length of the processor.

[0032] The processor continuously compares the real-time calculated effective value with the pre-stored absolute undervoltage action threshold in memory. When the comparison result shows that the effective value is less than the absolute undervoltage action threshold, the processor determines that the direct voltage drop condition has been met. The direct voltage drop condition corresponds to a scenario of instantaneous and complete power outage of the power grid. After determining that the condition has been met, the processor directly generates a fault state quantity representing the occurrence of a voltage drop fault. This absolute undervoltage action threshold is defined based on the minimum operating voltage required for the equipment hardware to maintain normal computing power and historical instantaneous power outage waveform test data from similar substations.

[0033] In an operating scenario where the incoming power line is disconnected but an inductive motor group load is internally connected, the rotor's sliding action sends a stator back EMF to the bus, causing the bus voltage to gradually decrease. At this point, the calculated effective value is greater than or equal to the absolute undervoltage action threshold. The processor then switches to numerical logic to evaluate the instantaneous rate of change, determining whether it is less than a preset drop slope threshold. If both the instantaneous rate of change and the effective value being greater than or equal to the absolute undervoltage action threshold are satisfied, the processor determines that the drop trend condition is met. This drop slope threshold is calculated based on the electromagnetic energy attenuation constant during the rotor sliding phase of the inductive equipment.

[0034] In this invention, after the processor determines that the drop trend condition is met, the system initiates the high-frequency impedance detection logic. The frequency parameter of the output detection current of the signal injection circuit is set so that this frequency parameter avoids the power frequency (50Hz) and harmonic frequency bands that are integer multiples of the power frequency (100Hz, 150Hz, 200Hz…), specifically selecting a high-frequency band of 2kHz to 5kHz. The processor controls the signal injection circuit to inject a high-frequency detection current into the busbar of the first incoming distribution cabinet according to this frequency parameter.

[0035] Within the time window of the injected probe current, the processor instructs the voltage acquisition circuit to synchronously acquire the high-frequency response voltage fed back from the busbar of the first incoming distribution cabinet. The processor extracts the amplitude of this high-frequency response voltage and the amplitude of the probe current, and then performs a division operation to obtain the dynamic characteristic impedance. The mathematical expression for the processor to calculate the dynamic characteristic impedance is as follows: ; in: This represents the dynamic characteristic impedance of the bus circuit under injected high-frequency bands, in ohms. This parameter is calculated in real time by the processor. The amplitude of the high-frequency response voltage is represented by volts. This parameter is obtained by the processor performing a fast Fourier transform on the synchronously acquired voltage signal sequence and extracting the amplitude data corresponding to the target frequency point. This represents the amplitude of the probe current, measured in amperes. This parameter is obtained by reading the constant current control reference value fed back from the signal injection circuit.

[0036] In a specific numerical embodiment, the signal injection circuit injects a constant current into the bus, and the processor reads the amplitude of its voltage. The current is 100 mA; during the synchronization cycle, the processor extracts the amplitude of the high-frequency response voltage corresponding to the target frequency point. The value is 5 volts; the processor substitutes the value into the above formula and performs a division operation to obtain the dynamic characteristic impedance of the current bus. The impedance is 50 ohms. After acquiring this dynamic characteristic impedance, the processor compares it numerically with the preset open-circuit impedance threshold.

[0037] After acquiring the dynamic characteristic impedance, the processor compares it with a preset open-circuit impedance judgment threshold. When the upstream incoming circuit breaker is physically open, the low-impedance physical path for the busbar to obtain power from the upstream power grid is broken, and the dynamic characteristic impedance rises accordingly. When the dynamic characteristic impedance exceeds the open-circuit impedance judgment threshold, the processor determines that the dynamic characteristic impedance exhibits open-circuit characteristics. This open-circuit impedance judgment threshold is determined comprehensively based on the leakage reactance parameters of the power supply transformer and the equivalent impedance test data of the busbar-to-ground distributed capacitance.

[0038] Based on the given conditions, the processor determines that the two-factor composite identification of the undervoltage fault is successful when it confirms that the voltage drop trend condition is met and the dynamic characteristic impedance exhibits open-circuit characteristics. The processor then switches the state of the control logic register to generate a fault state quantity representing the occurrence of the undervoltage fault, thereby completing the identification and elimination of residual voltage interference.

[0039] In this embodiment, after the processor sets the register status of the fault status quantity, it initiates the communication modulation and transmission process for that fault status quantity. The processor, at the communication transmitting end circuit, retrieves the current timestamp information of the system clock and generates a dynamically changing check mask based on a linear congruential algorithm pre-stored in memory. ; Where: Modulus ,multiplier Increment The initial seed is the unique serial number of the device, and a dynamic mask sequence is generated iteratively.

[0040] The processor, based on the digital baseband mapping rules, converts a single-bit fault status quantity into a high-frequency pulse sequence with a specific duty cycle parameter. Using its internal arithmetic logic unit, the processor performs a mixing operation on this high-frequency pulse sequence with the aforementioned check mask, thereby generating a high-frequency pseudo-differential pulse sequence as a trip instruction. The mathematical expression for the processor's mixing operation is as follows: ; in: This represents the high-frequency pseudo-differential pulse sequence output, which is output in real time through the processor's timer channel. This represents the high-frequency pulse sequence formed by the mapping, and this parameter is obtained by the processor in real time based on the Boolean value of the fault state quantity; This represents a checksum that changes dynamically over time. This parameter is calculated by the processor extracting the current timestamp and substituting it into a linear congruential algorithm. This represents the bitwise XOR logical operator.

[0041] The processor controls the communication transmitter circuit to output this high-frequency pseudo-differential pulse sequence. This sequence passes through the coupling circuit of the primary and secondary coils of the isolation transformer and is fed into the inter-cabinet physical bus. The isolation transformer constructs a physical electrical isolation barrier between the communication transmitter circuit and the inter-cabinet physical bus, cutting off the DC path at both ends.

[0042] In this invention, for the interaction scenario where the second incoming power distribution cabinet sends a command to the first incoming power distribution cabinet via the inter-cabinet physical bus, the processor controls the communication receiving circuit to continuously monitor the bus level. The communication receiving circuit extracts the level transition edges on the bus, converts them into digital quantities, and forms a receiving signal corresponding to the trip command. The processor then initiates collaborative verification logic based on this receiving signal.

[0043] The processor uses the local oscillator frequency parameter synchronized with the communication transmitting circuit to perform demodulation on the received signal, restoring the baseband waveform. The processor then defines a preset signal sliding verification window width (fixed at 20ms) and performs time integration on the demodulated signal within this window. The mathematical expression for this time integration operation is as follows: ; in: The integral result representing the time integration operation is expressed in volt-seconds. This parameter is obtained by iterative accumulation from the accumulator inside the processor. The starting scan time of the signal sliding verification window is determined based on the time point when the communication receiving circuit captures the first valid edge; This represents the preset width of the signal sliding verification window, in seconds. This parameter is calibrated based on an integer multiple of the reciprocal of the system communication baud rate. This represents the instantaneous amplitude of the demodulated signal, measured in volts. This parameter is obtained in real time from the processor's demodulation module.

[0044] The processor extracts the integration result and compares it with a preset minimum integration energy threshold. This minimum integration energy threshold is defined based on the peak background common-mode interference noise energy test data picked up by the distributed capacitance of the inter-cabinet physical bus under no-load conditions. When the integration result is greater than the minimum integration energy threshold, the processor confirms that the received signal has the continuous energy to maintain a certain level, thereby eliminating occasional transient interference spikes on the line.

[0045] After the condition that the integral result is greater than the minimum integral energy threshold is met, the processor locally calls a linear congruent algorithm derived from the second incoming power distribution cabinet to generate a local verification mask. The processor uses this local verification mask to perform feature matching verification on the baseband waveform corresponding to the received signal. When the processor's arithmetic comparison logic unit returns a matching status code, the feature matching verification result is confirmed as successful. Combining the results of the two operations—integrated energy reaching the threshold standard and successful feature matching—the processor determines that the currently received trip command is valid after collaborative verification.

[0046] In this embodiment, when the first incoming power distribution cabinet generates a fault state quantity representing a voltage loss fault, or when the received trip command is verified as valid, the system triggers the equipment power-off isolation logic. The processor controls the internal electronic switching devices to disconnect the power supply circuit between the first incoming power distribution cabinet and its busbar. After the power supply circuit is disconnected, the system switches the power supply link of the hardware control board, and the internal energy storage module provides the operating power separately to maintain the energy consumption required for the control chip's operation and the driving action of the peripheral circuits.

[0047] With the energy storage module continuously providing stable power support, the processor retrieves the configuration file in memory to obtain the pre-configured electrical attribute tags for each of the three-level load power supply circuits. The processor extracts the data fields contained in these electrical attribute tags and, based on the hardware electrical response characteristics, classifies the power supply circuits whose electrical attribute tags represent power equipment and inductive equipment into the first type of load set. Simultaneously, the processor classifies the power supply circuits whose electrical attribute tags represent lighting equipment and resistive equipment into the second type of load set, thus completing the system-level construction of the three-level load classification sets.

[0048] Based on the aforementioned three-level load classification set and the preset tiered delay sequence, the system executes load gradient shedding actions. The processor marks the time node when the aforementioned power supply link switching action is completed as the trigger moment. From this trigger moment, the processor's internal hardware timer starts counting, and after the preset first-stage action dead time interval (200ms), the time axis advances to the first moment. When the interrupt signal of the first moment is generated, the processor sends a primary tripping level to the relay control circuit, triggering the first output solid-state relay associated with the first type of load set to operate, physically disconnecting the power supply circuit of the power equipment and inductive equipment.

[0049] In this invention, after confirming the power failure of the first type of load set, the processor instructs the hardware timer to start a new round of timing span counting. Starting from the first moment, after a preset second-stage action dead time interval (100ms), the time axis advances to the second moment. When an interrupt signal is generated at the second moment, the processor sends a secondary tripping level to the relay control circuit, triggering the operation of the second output solid-state relay associated with the second type of load set. The second output solid-state relay performs a contact separation action, disconnecting the power supply circuits of the lighting equipment and resistive equipment, thereby completely completing the physical disconnection of all tertiary loads.

[0050] The processor internally includes action timing verification logic to standardize the parameter configuration of hardware timers. The processor extracts the dead time intervals of the first and second stages of the action, sums them, and sets the total time as the overall action execution cycle (300ms). The system limits this overall action execution cycle to be less than or equal to the maximum allowable fault clearance time window (500ms) of the upstream power supply and distribution network. The mathematical constraints for the processor's timing verification are as follows: ; in: This represents the overall execution cycle of the gradient cut-off process, in seconds. This parameter is obtained by the processor by summing the two timing phases. The dead zone time interval for the first stage of action is represented in seconds. This parameter is evaluated based on the time it takes for the induced electromotive force caused by the residual magnetic field inside the power equipment to decay naturally to a safe threshold. The dead time interval of the second stage action is represented in seconds. This parameter is calibrated based on the inherent dead time data required for the internal mechanical transmission and arc extinguishing components of the output solid-state relay to complete a single start-stop cycle. This represents the maximum fault clearance time window, measured in seconds. This parameter is obtained by reading the setting and coordination timing configuration file issued by the relay protection and control device of the superior substation.

[0051] After all tertiary load power supply circuits are disconnected, the system enters a state monitoring and recovery waiting loop. The processor controls the voltage acquisition circuit to continuously scan the potential changes at both ends of the first incoming distribution cabinet bus. In this embodiment, after all tertiary load power supply circuits are disconnected, the system enters a state monitoring and recovery waiting loop. The processor controls the voltage acquisition circuit to continuously scan the potential changes at both ends of the first incoming distribution cabinet bus. When the voltage level of the first incoming distribution cabinet bus recovers as the external upstream switch closes, the processor determines whether the current effective voltage value reaches the set normal operating voltage threshold (e.g., set to 380V × 95% = 361V). When the effective voltage value is higher than the normal operating voltage threshold, and the duration of the high-level state is greater than the preset anti-jitter reset time window (e.g., maintained at greater than or equal to 1 second), the processor determines that the power grid power supply link has been completely and stably rebuilt. The processor then writes a reset instruction to the internal register, clears the fault state quantity, and simultaneously drives the electronic switching device to close, restoring the power supply circuit connection between the first incoming distribution cabinet and the energy storage module and the first incoming distribution cabinet bus, and the system re-enters the float charging standby state. The processor then writes a reset instruction to the internal register to clear the fault status quantity, and at the same time drives the electronic switch to close, restoring the power supply circuit connection between the first incoming power distribution cabinet and the energy storage module and the first incoming power distribution cabinet bus, and the system re-enters the float charging standby state.

[0052] In this embodiment, based on the control logic and algorithm disclosed in the above stages, the present invention also provides a three-level load inter-cabinet linkage control system for low-voltage power distribution in subway depots to carry out the above control method. This linkage control system is physically manifested as an independent electronic control terminal deployed inside the incoming power distribution cabinet, mainly composed of a hardware circuit board and control software running on it.

[0053] This linkage control system integrates at least one processor and a memory that establishes a high-speed communication connection with the processor. The memory contains low-level hardware driver code and an application instruction set written for the aforementioned linkage control method. The memory employs a physical architecture composed of non-volatile read-only memory (NROM) chips and high-speed random access memory (RAM) chips. The NROM chips are divided into dedicated read-only sectors for permanently storing the absolute undervoltage threshold, minimum integral energy threshold, electrical attribute labels for each power supply circuit, and the reference seed file required to generate the dynamic verification mask.

[0054] The high-speed random access memory (RAM) chips inside the memory are allocated with a circular buffer. This circular buffer establishes a data transmission channel with an external analog-to-digital converter through a direct memory access controller, and is responsible for buffering the discrete voltage sampling point array continuously pushed by the voltage acquisition circuit in real time. The processor directly reads fixed-length data blocks in this circular buffer to obtain the basic data source required for performing time integration and root mean square (RMS) calculations.

[0055] In this invention, a high-performance microcontroller chip with a digital signal analysis core is selected as the processor. This processor is internally configured with independently operating hardware multiply-accumulate units and floating-point arithmetic coprocessing units, responsible for accelerating the fast Fourier transform matrix multiplication process required to calculate dynamic characteristic impedance. The aforementioned instructions are stored in memory. When a system interrupt is triggered, the instruction scheduler processor core executes the corresponding instruction fetch, decode, and execute actions. The processor sequentially executes voltage dip feature extraction, open-circuit impedance state determination, and modulation and demodulation of the inter-cabinet high-frequency pseudo-differential signal.

[0056] The linkage control system needs to isolate faults under extreme conditions of instantaneous power grid loss, and the data throughput rate and computing power planning of the hardware platform must adhere to strict time constraints. When the processor extracts data from the circular buffer and executes a single composite identification algorithm and inter-cabinet collaborative communication tasks, the overall hardware computation time is determined by both the internal clock frequency and the bus transmission bandwidth. The mathematical and physical model for evaluating this overall hardware computation time is set as follows: ; in: The time taken by the processor to complete a single complete linkage judgment logic is represented by the comprehensive hardware calculation time, in seconds. This parameter is obtained by the code analysis tool in the integrated development environment software during the development phase. This represents the total number of machine assembly instruction cycles corresponding to the processor completing a single complete linkage judgment logic. This parameter is determined by extracting the lengths of the execution paths of each loop branch in the assembly file and summing them up. This represents the clock frequency of the central processing unit inside the processor, measured in Hertz. This parameter is obtained based on the nominal frequency of the crystal oscillator on the system hardware motherboard and the configuration value of the phase-locked loop frequency multiplier register. The total number of bytes exchanged between the processor and memory in a single operation cycle, representing the sampled data, status flags, and checksum sequence. The physical throughput bandwidth of the high-speed data bus established between the processor and memory is expressed in bytes per second. This parameter is calculated based on the product of the data bus width and the synchronous clock frequency.

[0057] The watchdog timer within the linkage control system continuously monitors the aforementioned calculation process. The linkage control system writes the integrated hardware calculation time parameter into the timing calibration register. To prevent calculation delays from causing lag errors in trip determination, the system forcibly limits the integrated hardware calculation time. The value must be strictly smaller than the adjacent time step interval value of the voltage effective value acquisition in the preceding method steps.

[0058] Under the premise of meeting the aforementioned computing power response time constraints, the processor executes all program instructions smoothly and accurately. The processor sends action drive levels to the external relay control circuit by controlling the level changes of its own general-purpose input / output pins. This collaborative working logic between the hardware system and software instructions ensures that the power supply link switching strategy from a single-side perspective is physically implemented in a complete closed loop within the first incoming power distribution cabinet.

[0059] In this embodiment, based on the aforementioned control method and hardware architecture, the present invention also provides a computer-readable storage medium. This computer-readable storage medium internally allocates contiguous data sectors and instruction sectors, with the instruction sectors storing executable computer program instructions. The processor reads and executes these computer program instructions via its internal address bus to implement the control logic corresponding to the aforementioned steps.

[0060] In the specific process of the computer program instructions driving the processor to execute collaborative verification, to prevent the failure of the trip command due to channel errors caused by environmental electromagnetic interference, the system executes feature matching fault-tolerant verification logic based on discrete sequence comparison. The processor acquires the demodulated received signal and converts its waveform amplitude into a discrete received baseband bit stream. At the same time, the processor extracts the local verification mask generated by the internal algorithm and formats it into a local mask bit stream with the same data length.

[0061] The processor uses its internal arithmetic logic array to extract the received baseband bitstream and the local mask bitstream, performing a bitwise XOR operation. The processor then accumulates and counts the number of high-level bits in the XOR result to calculate the Hamming distance between the two data sequences. The mathematical expression for calculating this Hamming distance is defined as follows: ; In the above formula: Represents the calculated Hamming distance value; N represents the total bit length of the check sequence, in bits; i represents the index of the sequence in which the XOR operation is currently being performed; This represents the binary value corresponding to index i in the received baseband bitstream; This represents the binary value corresponding to the local mask bitstream at index i.

[0062] In a specific numerical comparison embodiment, the total bit length N of the verification sequence is set to 8 bits. The received baseband bitstream array extracted by the communication receiver... The mask bitstream array is [1,0,1,1,0,1,0,1], generated locally synchronously. The distance is [1,0,0,1,0,1,1,1]. After the processor performs a bitwise XOR operation, there are 2 bits of high level (i.e., the value is 1) output, from which the current Hamming distance is obtained. The value is 2. The processor extracts this Hamming distance value and compares it with a preset fault-tolerance bit threshold. When the Hamming distance value is less than or equal to the fault-tolerance bit threshold, the processor determines that the currently received instruction sequence is structurally complete and confirms that the feature matching verification is successful.

[0063] The system incorporates a Hamming distance evaluation mechanism in the verification stage of the communication receiver circuit, allowing for a few bit flips during data transmission on the physical bus. The processor, after eliminating bus background noise and occasional data variations, reconstructs the original trip command issued by the second incoming power distribution cabinet. This control mechanism maintains the timing consistency of the tripping actions of the first and second incoming power distribution cabinets, improving the reliability of the linkage control system in complex industrial environments.

[0064] In this embodiment, based on the aforementioned inter-level load control method for low-voltage power distribution in subway depots, the present invention provides an inter-level load control device for low-voltage power distribution in subway depots. This inter-level control device is configured in the processor inside the aforementioned first incoming power distribution cabinet via underlying software code or a programmable gate array. Logically, the inter-level control device includes a data acquisition and charging module, an impedance detection module, a two-factor identification module, a modulation and transmission module, and a gradient cutoff module.

[0065] The acquisition and charging module uses the first incoming power distribution cabinet bus to extract the digital quantity of the instantaneous voltage signal and executes the power supply circuit on / off control and energy storage maintenance logic of the energy storage module. The impedance detection module receives the voltage data sequence output by the acquisition and charging module, and when the voltage drop trend condition is met, it generates a trigger signal to instruct the external signal injection circuit to apply a detection current to the bus, and then calculates the dynamic characteristic impedance.

[0066] The two-factor identification module comprehensively compares the direct drop condition and the open-circuit characteristic state presented by the dynamic characteristic impedance. When a preset logical combination is met, it writes a fault state quantity representing a voltage loss fault into the register address space. The modulation and transmission module extracts this fault state quantity, calls a time-varying check mask to perform mixing operations, and outputs a trip command with check characteristics. The gradient cut-off module reads the internal fault state quantity and listens for the trip command demodulated by the receiver. Under the premise that the collaborative verification mechanism confirms its validity, it switches the power supply link and, in conjunction with the three-level load classification set and the stepped delay timing control of the peripheral relay array, performs a power-off operation.

[0067] In this invention, each module within the linkage control device relies on the processor's internal data bus to perform state parameter shifting and interaction. To ensure a real-time response mechanism for fault handling, the system constructs an end-to-end action response time constraint model for the entire process from abnormal signal input to physical contact separation for each module. The processor performs boundary condition calculations and timing checks for the end-to-end action response time according to the following mathematical expression: ; in: The end-to-end action response time from the completion of the drop detection to the power failure of the first target load is represented by milliseconds. This parameter is calculated by the processor's internal hardware monitor through the cumulative number of clock ticks. This represents the analog-to-digital conversion delay time in milliseconds required for the charging module to drive the analog-to-digital converter to complete the sampling of the instantaneous voltage signal. This parameter is obtained from the rated conversion rate parameter specified in the original datasheet of the analog-to-digital converter chip manufacturer. The time taken for the combined hardware computation of the two-factor identification module to perform logical judgment and impedance calculation is measured in milliseconds. This parameter is defined based on the average statistical data of code execution time in the system's historical operation log. The time taken by the modulation and transmission module to generate protocol packets and transport data using the high-frequency pseudo-differential pulse sequence is measured in milliseconds. This parameter is calculated by multiplying the reciprocal of the system communication baud rate by the total number of bytes in the data frame. The mechanical delay time, in milliseconds, represents the time it takes for the gradient cut-off module to send a drive level to the output solid-state relay to complete the physical contact separation. This parameter is calibrated based on the electromechanical operating characteristics of the relay components and factory test data.

[0068] The system requires that the end-to-end action response time of the arithmetic logic unit output must be within the protection coordination action time limit set by the upper-level power grid. The memory internally has dedicated program storage and data buffer areas. The program storage area contains the binary executable instruction code that constitutes each module of the aforementioned linkage control device. The data buffer area is responsible for storing intermediate variables such as the instantaneous rate of change, high-frequency response voltage amplitude, and integral results generated by each module during its operating cycle.

[0069] After power-on reset, the processor retrieves the executable instruction code from the program memory area and loads it into the internal instruction register. Following the system clock cycle, it sequentially executes the logic comparison operations and port level output steps corresponding to each of the aforementioned functional modules. Leveraging the modular logic architecture and the coordinated operation of the electronic hardware platform, the linkage control system, even in complex electrical environments with grid bus voltage loss and residual voltage interference from large-capacity inductive loads, relies on its self-sufficient energy storage to overcome dead zones and precisely complete the timing-based disconnection of load circuits at all levels.

Claims

1. A method for coordinated control of three-level load cabinets in low-voltage power distribution in subway depots, characterized in that: Applied to the first incoming line distribution cabinet, including: The instantaneous voltage signal of the first incoming power distribution cabinet bus is collected, and the energy storage module is charged using the first incoming power distribution cabinet bus. The voltage drop state is obtained based on the instantaneous voltage signal, and when the voltage drop state meets the drop trend condition, a detection current is injected into the busbar of the first incoming distribution cabinet to obtain the dynamic characteristic impedance. When the voltage drop state meets the direct drop condition, or when the drop trend condition is met and the dynamic characteristic impedance exhibits open circuit characteristics, the two-factor composite identification of the undervoltage fault is determined to be successful, and a fault state quantity characterizing the occurrence of the undervoltage fault is generated. When the fault status quantity is generated, the fault status quantity is modulated into a trip command with verification features and sent to the second incoming distribution cabinet. When the first incoming power distribution cabinet generates the fault status quantity, or receives a trip command sent by the second incoming power distribution cabinet and the collaborative verification is valid, the power supply circuit between the first incoming power distribution cabinet and the first incoming power distribution cabinet bus is cut off, the energy storage module provides working power, and according to the three-level load classification set and the preset stepped delay sequence, the corresponding three-level load power supply circuits are disconnected in sequence to perform load gradient shedding.

2. The inter-level load control method for low-voltage power distribution in subway depots according to claim 1, characterized in that, The step of charging the energy storage module using the first incoming power distribution cabinet busbar includes: The instantaneous voltage across the energy storage module is monitored in real time, and the energy storage module's reserve energy is calculated. The reserve energy is half the product of the energy storage module's capacitance value and the energy voltage factor. The energy voltage factor is the difference between the square of the instantaneous voltage across the energy storage module and the square of a preset minimum blocking voltage threshold. Under normal power supply conditions, the stored energy is maintained at a level greater than the rated dissipation energy required for a single complete tripping process.

3. The inter-level load control method for low-voltage power distribution in subway depots according to claim 1, characterized in that, The steps for determining whether the falling trend condition, the direct falling condition, and the open-circuit feature are met include: The effective value and instantaneous rate of change of the instantaneous voltage signal are calculated in real time. When the effective value is less than the preset absolute pressure loss action threshold, the direct fall condition is determined to be met. When the instantaneous rate of change is less than the preset drop slope threshold and the effective value is greater than or equal to the absolute pressure loss action threshold, the drop trend condition is determined to be met. When the obtained dynamic characteristic impedance is greater than the preset open-circuit impedance determination threshold, the dynamic characteristic impedance is determined to exhibit open-circuit characteristics.

4. The inter-level load control method for low-voltage power distribution in subway depots according to claim 1, characterized in that, The step of injecting a probe current into the busbar of the first incoming distribution cabinet to obtain the dynamic characteristic impedance includes: The frequency of the detection current is set to avoid the power frequency and power frequency harmonic frequency bands, and a high-frequency detection current is injected into the busbar of the first incoming distribution cabinet. The high-frequency response voltage fed back from the busbar of the first incoming power distribution cabinet is collected synchronously; The dynamic characteristic impedance is obtained by dividing the amplitude of the high-frequency response voltage by the amplitude of the probe current.

5. The inter-level load control method for low-voltage power distribution in subway depots according to claim 1, characterized in that, The step of modulating the fault status quantity into a trip command with verification features and sending it to the second incoming distribution cabinet includes: At the transmitting end of the first incoming power distribution cabinet, a verification mask that changes dynamically over time is introduced; The fault status quantity is mapped to a high-frequency pulse sequence, and the high-frequency pulse sequence is mixed with the verification mask to generate a high-frequency pseudo-differential pulse sequence as the trip command. The high-frequency pseudo-differential pulse sequence is coupled and transmitted to the inter-cabinet physical bus via an isolation transformer.

6. The inter-level load control method for low-voltage power distribution in subway depots according to claim 1, characterized in that, The collaborative verification is valid, as confirmed by the following steps: Receive the receiving signal corresponding to the trip command sent by the second incoming distribution cabinet; The received signal is demodulated, and the demodulated signal is integrated over time within a preset signal sliding verification window. When the integral result of the time integration operation is greater than the preset minimum integral energy threshold, and the result of feature matching verification of the received signal using the local verification mask is successful, the received trip command is determined to be valid after collaborative verification.

7. The inter-level load control method for low-voltage power distribution in subway depots according to claim 1, characterized in that, The three-level load classification set is constructed as follows: Obtain the pre-configured electrical attribute tags for each level 3 load power supply circuit; The electrical attribute labels characterize the power supply circuits of power equipment and inductive equipment as the first type of load set; The electrical attribute tags characterize the power supply circuits of lighting equipment and resistive equipment as a second type of load set.

8. The inter-level load control method for low-voltage power distribution in subway depots according to claim 7, characterized in that, The step of sequentially disconnecting the power supply circuits of the corresponding three-level loads according to the three-level load classification set and the preset stepped delay sequence to perform load gradient shelving includes: From the moment of triggering, after the first stage dead time interval, the first moment is reached, triggering the first output solid-state relay to disconnect the power supply circuit corresponding to the first type of load set; Starting from the first moment, after the second stage action dead time interval, the second time is reached, triggering the second output solid-state relay to disconnect the power supply circuit corresponding to the second type of load set, completing the removal of all three-level loads.

9. The inter-level load control method for low-voltage power distribution in subway depots according to claim 8, characterized in that, Also includes: The sum of the dead time intervals of the first stage action and the dead time intervals of the second stage action constitutes the overall action execution cycle, and the overall action execution cycle is limited to be less than or equal to the maximum fault elimination time window allowed by the upper-level power supply and distribution network. After all the level 3 loads have been disconnected, when the voltage of the first incoming distribution cabinet busbar recovers and remains above the set normal operating voltage threshold, the fault status quantity is reset, and the power supply circuit connection between the first incoming distribution cabinet and the energy storage module and the first incoming distribution cabinet busbar is restored.

10. A three-level load interlocking control system for low-voltage power distribution in a subway depot, characterized in that: include: At least one processor; as well as, A memory that is communicatively connected to the at least one processor; The memory stores instructions that can be executed by the at least one processor, which are executed by the at least one processor to enable the at least one processor to perform the steps of the inter-load control method for low-voltage power distribution in subway depots according to any one of claims 1 to 9.

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