Insulated gate bipolar transistor drive control method and device, and readable storage medium

Abstract

The application provides an insulated gate bipolar transistor drive control method and device and a readable storage medium. In view of the uneven voltage and uneven current problem caused by parameter dispersion and aging in series and parallel connection of high-power devices, the application establishes a switching transient physical state equation group as a base, collects device waveforms to extract feature vectors and inputs the feature vectors into a deviation identification neural network to online estimate a bottom physical parameter deviation amount; the deviation amount is compensated to the equation group for correction, optimal control variables are solved under a hard constraint and are executed; and a physical residual is used as a self-supervision signal to fine-tune network weights. The application can realize adaptive compensation of device characteristic drift in a whole life cycle and is mainly used for voltage and current equalization control of high-power equipment such as solid-state circuit breakers and medium and high voltage frequency converters.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a driving control method, apparatus, and readable storage medium for an insulated gate bipolar transistor. Background Technology

[0002] In high-voltage, high-power power electronic converters, due to the limitations of the voltage rating and current carrying capacity of a single IGBT device, multiple IGBT devices are often connected in series to increase the voltage rating, or in parallel to increase the current capacity. Typical applications include solid-state circuit breakers, high-voltage DC transmission converter valves, medium- and high-voltage frequency converters, and high-power pulse power supplies.

[0003] When multiple IGBT devices are connected in series, the dispersion of parameters (such as on-resistance, parasitic capacitance, threshold voltage, etc.) and differences in the drive signal transmission path can lead to uneven voltage distribution (i.e., voltage imbalance) during switching transients, potentially causing some devices to fail due to overvoltage breakdown. When multiple IGBT devices are connected in parallel, differences in saturation voltage drop, on-resistance, and parasitic inductance can result in uneven current distribution in each branch (i.e., current imbalance), causing some devices to fail prematurely due to overcurrent.

[0004] To address the above problems, there are two main types of solutions in the existing technology:

[0005] (1) Passive voltage / current sharing method: The traditional passive voltage sharing method suppresses overvoltage by connecting an RC snubber circuit or a TVS clamping circuit in parallel across the collector-emitter terminals of the IGBT. The passive current sharing method achieves current distribution by connecting a current sharing resistor or inductor in series with the emitter. This method absorbs energy through passive components and can play a certain role in static voltage and current sharing, but it introduces additional losses and reduces system efficiency; moreover, the voltage / current sharing accuracy is limited and it is difficult to adapt to a wide range of operating conditions; the effect of voltage and current sharing during dynamic switching transient processes is poor.

[0006] (2) Active voltage equalization method based on drive delay adjustment: Series voltage equalization is achieved by adjusting the gate drive signal delay time of each IGBT. The basic principle is to monitor the voltage waveform of each device in real time, identify the difference in turn-on and turn-off times, and apply delay compensation to the other devices based on a certain device to make the voltage of each device during the switching process tend to be consistent. This method only controls the switching sequence, and all control parameters need to be calibrated and fixed offline, and it does not have the ability to be updated online.

[0007] Therefore, there is an urgent need for a digital gate drive control (IGBT drive control) method based on Physics-Informed Neural Network (PINN) for the series-parallel application of high-power insulated gate bipolar transistors (IGBTs) to solve the problems existing in the current technology. Summary of the Invention

[0008] This invention provides an insulated gate bipolar transistor (IGBT) driving control method, apparatus, and readable storage medium, addressing the problems of existing technologies such as introducing additional switching losses, limited accuracy due to a single control dimension, and the complete inability to identify and adaptively compensate for the drift of physical parameter characteristics caused by device aging throughout the entire life cycle.

[0009] The core technology of this invention is to embed the transient physical state equations of IGBT switches into the control architecture as a deterministic base, use a deviation identification neural network to estimate the deviation of the basic physical parameters of each device from the nominal value online and compensate it into the physical equations, and use the residual between the predicted value of the physical equations and the measured waveform as a self-supervised signal to fine-tune the network weights online, so as to achieve adaptive compensation for the dispersion of device parameters and aging effects throughout the entire life cycle.

[0010] In a first aspect, the present invention provides a driving control method for an insulated gate bipolar transistor, the method comprising the following steps: A set of transient physical state equations for insulated gate bipolar transistor (IGBT) switching is established as a deterministic physical foundation. The set of physical state equations describes the switching electrical behavior of each device during the turn-on and turn-off phases based on the basic physical parameters and gate drive control variables of each device. Real-time acquisition of switching waveform data of each device and extraction of physical feature vectors from it; The physical feature vector is input into the deviation identification neural network, which then estimates the deviation of the basic physical parameters of each device from the nominal value online. The deviation is compensated to the corresponding basic physical parameters. Using the compensated basic physical parameters and the physical state equations, the optimal control variables that minimize the voltage and current deviations between devices are solved within the preset hard constraint boundary. The optimal control variables are then sent to the programmable gate drive circuits corresponding to each device for execution. During online operation, the physical residual between the predicted value of the physical state equation set and the measured switch waveform data is used as a self-supervised signal. When the preset trigger conditions are met, the weights of the deviation identification neural network are finely adjusted online to adaptively compensate for the dispersion of device parameters and the characteristic drift caused by aging.

[0011] Furthermore, the basic physical parameters include the input capacitance, Miller capacitance, gate resistance, threshold voltage, and transconductance of each device; The physical state equations include the turn-on current rate of change equation, the turn-on voltage rate of change equation, and the turn-on delay equation during the turn-on phase, as well as the turn-off voltage rate of change equation, the turn-off current rate of change equation, and the turn-off delay equation during the turn-off phase. The gate drive control variables include the turn-on drive voltage, the turn-off drive voltage, the turn-on delay compensation time, and the turn-off delay compensation time.

[0012] Furthermore, the physical feature vector includes turn-on delay time, turn-off delay time, turn-on voltage change rate, turn-off voltage change rate, turn-on current change rate, turn-off current change rate, turn-on loss, turn-off loss, junction temperature, collector current, and collector-emitter voltage extracted from the switching waveforms of each device.

[0013] Furthermore, the bias recognition neural network includes an input layer, multiple hidden layers, and an output layer connected in sequence; The input layer receives the physical feature vectors of each device; Each hidden layer uses the ReLU activation function; The output layer uses the tanh activation function and multiplies it by a preset deviation boundary factor to limit the output range of the deviation to a preset percentage of the nominal value.

[0014] Furthermore, the optimal control variables are solved using model predictive control algorithms or sequential quadratic programming algorithms; Hard constraints include that the collector-emitter voltage of each device does not exceed the preset maximum withstand voltage value and the collector current of each device does not exceed the preset maximum current value. The optimization objective is to ensure that the maximum voltage deviation and maximum current deviation between each device do not exceed the preset voltage equalization threshold and current equalization threshold, respectively, and to minimize the total switching loss.

[0015] Furthermore, the preset triggering conditions also include: the number of consecutive preset number of switching cycles of the physical residual exceeds a preset threshold, in order to distinguish between systematic model bias and random measurement noise; The current operating condition is in a steady state, and the rate of change of the operating condition is lower than the preset steady state judgment threshold; If the above conditions are not met, online fine-tuning will automatically pause, and the network weights will remain unchanged.

[0016] Furthermore, online fine-tuning employs a preset low learning rate to avoid sudden changes in weights; The physical state equations form soft guardrail constraints. When the deviation deviates from the reasonable physical range, the physical residual increases to pull the network weights back. Before the optimal control variable is issued, a range clamping check is performed independently of the online fine-tuning process to ensure that the optimal control variable does not exceed the physical boundary.

[0017] In a second aspect, the present invention provides an insulated gate bipolar transistor driving control device, comprising: Multiple digital drive units, each digital drive unit is connected to an insulated gate bipolar transistor and is located at a high voltage side floating ground potential. Each digital drive unit includes a voltage sampling module, a current sampling module, a programmable logic control module, a digital-to-analog converter module, an adjustable gate drive circuit and an isolated communication module; The voltage sampling module and the current sampling module are used to acquire the voltage waveform data and current waveform data of the corresponding devices in real time, respectively; The programmable logic control module is used to extract physical feature vectors from waveform data and generate PWM timing control signals; The digital-to-analog converter module and the adjustable gate drive circuit are used to output an adjustable gate drive voltage according to the received control signal to drive the gate of the corresponding device; The host computer controller is equipped with a deviation identification neural network and an optimization algorithm engine. It is used to receive the physical feature vectors uploaded by each digital drive unit, execute the insulated gate bipolar transistor drive control method as described above, and send the optimal control variables obtained by solving to each digital drive unit. The isolation communication module is located between the programmable logic control module and the host computer controller, serving as the only electrical isolation boundary between each digital drive unit and the host computer controller.

[0018] Thirdly, the present invention provides an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to execute the above-described insulated gate bipolar transistor drive control method.

[0019] Fourthly, the present invention provides a readable storage medium storing a computer program, the computer program including program code for controlling a process to execute the process, the process including the insulated gate bipolar transistor drive control method described above.

[0020] The main contributions and innovations of this invention are as follows: 1. This invention embeds the transient physical state equations of IGBT switches into a neural network, so that the output of the deviation identification subnetwork corresponds to a clear physical parameter deviation (such as input capacitance deviation, gate resistance deviation, threshold voltage deviation, etc.), which has physical interpretability and facilitates engineering debugging and fault diagnosis.

[0021] 2. This invention uses the residual between the predicted and measured values ​​of the physical equation as a self-supervised signal. By fine-tuning the network weights online with an extremely low learning rate, combined with the soft guardrail constraints formed by the physical equation and independent range clamping verification, it continuously compensates for the characteristic drift of the device caused by aging effects such as bond wire detachment and gate oxide layer degradation without offline retraining. This achieves adaptive voltage and current equalization control throughout the entire life cycle of the IGBT, overcoming the defect of the traditional offline solidification scheme where the control effect continues to deteriorate after the device ages.

[0022] 3. In this invention, the deviation identification sub-network only learns the low-dimensional deviation of each physical parameter relative to the nominal value, rather than directly learning the high-dimensional control strategy. The training sample requirement is reduced by one to two orders of magnitude compared with the black box neural network scheme, and the data efficiency is significantly improved.

[0023] 4. This invention adopts a distributed digital drive architecture with full integration on the high-voltage side and single-point communication isolation. Each drive unit integrates all functions of voltage sampling, current sampling, programmable logic control, digital-to-analog conversion and adjustable gate drive at the floating ground potential on the high-voltage side. It communicates with the host computer on the low-voltage side through only one isolated communication bus. The number of isolation devices is reduced by more than 70% compared with the traditional independent isolation scheme per channel.

[0024] 5. In this invention, the online inference of the bias identification subnetwork only requires one forward propagation, and the online fine-tuning only adds low-learning-rate gradient updates. The total processing time per cycle can meet the real-time closed-loop control requirements of switching frequencies above 10kHz. The model structure can be extended to any N-string M-parallel topology.

[0025] Details of one or more embodiments of the present invention are set forth in the following drawings and description, so that other features, objects and advantages of the invention will be more readily understood. Attached Figure Description

[0026] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a hardware architecture block diagram of the digital IGBT drive unit of the insulated gate bipolar transistor drive control device according to an embodiment of the present invention; Figure 2 This is the overall system architecture according to an embodiment of the present invention, taking a 2-series-2-parallel topology as an example; Figure 3 This is a schematic diagram of a Physical Information Neural Network (PINN) according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0027] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with one or more embodiments of this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of one or more embodiments of this specification as detailed in the appended claims.

[0028] It should be noted that the steps of the corresponding methods are not necessarily performed in the order shown and described in this specification in other embodiments. In some other embodiments, the methods may include more or fewer steps than described in this specification. Furthermore, a single step described in this specification may be broken down into multiple steps in other embodiments; and multiple steps described in this specification may be combined into a single step in other embodiments.

[0029] Example 1 This embodiment uses the voltage and current sharing control of a 2-series, 2-parallel insulated-gate bipolar transistor as an example to describe the specific implementation of the present invention in detail. Those skilled in the art will understand that the technical solution of the present invention is also applicable to any N-series, M-parallel topology.

[0030] like Figure 2 As shown, the Insulated Gate Bipolar Transistor (IGBT) power matrix consists of four IGBT devices (IGBT11~IGBT22) forming a 2-series 2-parallel topology. Each IGBT device is equipped with an independent digital drive unit (DU11~DU22), for a total of four drive units. The host computer controller is based on an ARM+DSP dual-core platform or an FPGA-SoC platform, and internally deploys a deviation identification neural network inference engine and an optimization algorithm engine. All drive units are connected to the host computer controller via an isolated communication bus, forming a closed-loop control device for distributed data acquisition and centralized optimization decision-making.

[0031] I. Hardware Architecture of Digital Drive Unit like Figure 1 As shown, each digital drive unit is located at a floating ground potential on the high-voltage side, with the reference point being the emitter of the corresponding IGBT device, and is powered by an isolated DC-DC module. Each digital drive unit includes a voltage sampling module, a current sampling module, a programmable logic control module, a digital-to-analog converter module, an adjustable gate drive circuit, and an isolated communication module.

[0032] 1.1 Voltage Sampling Module Collector-emitter voltage V of each IGBT device ceAfter being stepped down to the 0-2V range by a high-voltage resistor divider network, the voltage is directly fed into a high-precision successive approximation analog-to-digital converter (SARADC) for sampling. The voltage division ratio is approximately 1000:1, including a 2MΩ high-voltage metal film resistor with a withstand voltage greater than 5kV and a 2kΩ resistor with a parasitic capacitance less than 1pF and an equivalent bandwidth greater than 10MHz. The ADC model is AD4003, with 18-bit resolution and a 2MSPS sampling rate. The resistor divider network itself provides electrical isolation with a withstand voltage greater than 5kV. The ADC and the programmable logic control module are both located on the high-voltage side floating ground and are directly connected via an SPI interface, eliminating the need for an isolation amplifier. This design eliminates the bandwidth bottleneck of traditional isolation amplifiers, allowing the effective bandwidth of voltage sampling to be determined by the ADC sampling rate (Nyquist frequency of 1MHz) and the anti-aliasing filter (approximately 800kHz), which is sufficient to completely capture the IGBT switching transients. v / d t Spectral components of the waveform.

[0033] 1.2 Current Sampling Module The collector current Ic is converted into a millivolt-level voltage signal by a precision shunt connected in series with the emitter of each IGBT device. The shunt is a low-inductance sampling resistor with a resistance of 0.1~1mΩ and a parasitic inductance of less than 5nH. The millivolt-level voltage signal is amplified to the ADC input range by a high-speed instrumentation amplifier (model AD8421, programmable gain 100~1000 times, -3dB bandwidth greater than 2MHz@G=100), and then fed into an ADC (AD4003, 18-bit, 2MSPS) of the same model as the voltage sampling ADC, achieving strict synchronous sampling of the current and voltage channels. The shunt is naturally located at the floating ground reference point (emitter), and the ADC does not require isolation. At the same time, the shunt also functions as a current-sharing resistor, providing passive current sharing guarantee for each parallel branch under steady state.

[0034] The voltage sampling module and current sampling module described above are existing technologies and are not the technical points to be protected by this invention. Therefore, no accompanying drawings are shown, nor is a detailed structural description provided.

[0035] 1.3 Programmable Logic Control Module The programmable logic control module uses a Field-Programmable Gate Array (FPGA) as the core controller of the drive unit. It is located on the high-voltage side of the driver board, along with the ADC and DAC, and is independently powered by an isolated DC-DC module. The FPGA selected is an Intel MAX10 series 10M08, with approximately 8K logic cells and built-in user Flash memory. It requires no external configuration chip, operates immediately upon power-up, and has a clock frequency of at least 100MHz to achieve ±1ns PWM delay adjustment accuracy. The FPGA internally implements the following functional modules: an ADCSPI controller (dual-channel synchronous trigger sampling), a waveform feature real-time extraction engine (on / off delay measurement, d... i / d t With d v / d t Difference calculation, E on / E off The FPGA includes a trapezoidal numerical integral, an RS-485 communication protocol stack (DMA transfer), a PWM timing generator (±1ns resolution), and a DACSPI controller. Data exchange between the FPGA and the low-voltage side host controller is achieved through an isolated communication interface, forming the only electrical isolation boundary on the driver board.

[0036] The driver board is powered by an isolated DC-DC module with a 24VDC input (from the low-voltage side safety ground) and multiple outputs of +15V / -8V / +5V / +3.3V. The transformer isolation withstand voltage is no less than 5kV, and the total power is approximately 10W. Specifically, +15V is the positive power rail and gate turn-on drive voltage for the high-power op-amp; -8V is the gate turn-off negative voltage, used to accelerate turn-off and prevent false triggering; +5V is the analog power supply for the ADC; and +3.3V is the power supply for the FPGA digital core and I / O. The reference ground plane of the entire high-voltage side driver board is connected to the IGBT emitter. The ADC, FPGA, and DAC share the same ground reference, and signal transmission within the board requires no isolation.

[0037] 1.4 Digital-to-Analog Conversion Module and Adjustable Gate Drive Circuit A high-precision digital-to-analog converter (DAC) receives digital signals from an FPGA and outputs an analog reference voltage V. ref (0~2.5V). The DAC model is AD5686R, 16-bit resolution, 4-channel output, built-in 2.5V reference source, SPI interface, and a settling time of 5μs. ref The high-power operational amplifier OPA549 (±8A continuous output capability) is used as a programmable gate drive voltage source V. drive The output directly drives the gate (GE) of the IGBT devices. This is achieved by dynamically adjusting the turn-on drive voltage V of each IGBT device. drive,on and the turn-off drive voltage V drive,off By altering the charging and discharging behavior of the gate RC circuit, precise fine-tuning of the switching speed can be achieved.

[0038] 1.5 Isolation Communication Module The isolated communication module is the sole electrical connection between the high-voltage side driver board and the low-voltage side host controller, undertaking all isolation functions. It employs an isolated RS-485 transceiver ADM2582E with a data rate of 16Mbps and an isolation withstand voltage of at least 2.5kVrms. It integrates an isoPower isolated DC-DC converter, achieving both signal isolation and high-voltage side auxiliary power supply through a single device. During each switching cycle, each driver unit only needs to upload a compact feature vector (approximately 64 bytes / unit) pre-processed locally by the FPGA. For the four driver units, this totals 256 bytes. At a rate of 16Mbps, the pure data transmission delay is approximately 128μs, meeting the real-time closed-loop control requirements for switching frequencies above 10kHz. This solution simplifies the isolation boundary from the traditional approach of independently isolating each ADC channel to a single communication line per driver unit, requiring only one isolation device per driver unit.

[0039] The hardware design parameters of each digital drive unit are shown in Table 1.

[0040] Table 1 Hardware Design Parameters of Digital Drive Unit

[0041] II. IGBT Switching Transient Physical State Equations For the i-th IGBT device (where i = 1, 2, ..., N), its transient electrical behavior during turn-on and turn-off is described by the following continuous constant voltage source RC charging and discharging physical equations.

[0042] In this embodiment, the input control signal of the i-th IGBT device is defined as:

[0043] in, To turn on the drive voltage, To turn off the drive voltage, To compensate for the delay in opening, This is the time to compensate for the shutdown delay.

[0044] Opening phase: Equation for the rate of change of turn-on current:

[0045] Equation for the rate of change of turn-on voltage:

[0046] Opening delay equation:

[0047] Shutdown phase: Equation for the rate of change of turn-off voltage:

[0048] Equation for the rate of change of turn-off current:

[0049] Turn-off delay equation:

[0050] The above equations (1) to (6) constitute the deterministic physical foundation of the control algorithm of this invention. The physical meaning of each parameter is as follows: Basic physical parameters (internal parameters that are identified online by the deviation identification neural network and used to compensate for aging deviations, also known as underlying physical parameters): The intrinsic transconductance of the i-th device is expressed in Siemens (S). This represents the input capacitance of the i-th device, in farads (F). The Miller capacitance of the i-th device is expressed in farads (F). The equivalent gate resistance of the i-th device's turn-on circuit includes the external series resistance and the increase in parasitic internal resistance caused by bonding wire aging, and is expressed in ohms (Ω). This represents the equivalent gate resistance of the turn-off circuit of the i-th device, in ohms (Ω). This represents the threshold voltage of the i-th device affected by the gate oxide layer, expressed in volts (V). This represents the Miller plateau voltage of the i-th device, in volts (V).

[0051] Electrical state variables and active control variables: This indicates the current real-time gate voltage inside the device, measured in volts (V). and These represent the turn-on and turn-off drive voltages set by the programmable drive circuit for the i-th device, respectively, in volts (V). and These represent the actual turn-on delay time and turn-off delay time of the device under the current control signal, respectively, in seconds (s); and These represent the rate of change of the device's turn-on current and the rate of change of its turn-off current, respectively, in amperes per second (A / s). and These represent the rate of change of the device's turn-on voltage and the rate of change of its turn-off voltage, respectively, in volts per second (V / s).

[0052] Since the aforementioned underlying physical parameters specifically include the inherent transconductance of each device... Input capacitor Miller capacitors Internal equivalent gate resistance and threshold voltage Correspondingly, the estimated value of the deviation. Including transconductance deviation of each device Input capacitor deviation Miller capacitance deviation Gate resistance deviation and threshold voltage deviation Here, since gate aging is mainly manifested as the degradation of the parasitic resistance inside the device, the gate resistance deviation... As a unified aging increment, it is applicable to both the turn-on and turn-off drive circuits of the device.

[0053] III. Hard Constraints and Optimization Objectives For any i-th IGBT device in any k-th switching cycle, the following hard constraints must be satisfied simultaneously:

[0054]

[0055] in, The maximum collector-emitter withstand voltage value specified in the datasheet. This is the maximum collector current value specified in the datasheet.

[0056] The optimization objective is to ensure that the maximum voltage and current deviations between devices do not exceed preset voltage and current sharing thresholds, respectively, while minimizing total switching losses. Specifically, the voltage imbalance value... Composed of two IGBT devices connected in series The difference is the value of the non-uniform flow. Composed of two parallel loops The difference is obtained by subtraction. The voltage equalization threshold and current equalization threshold are generally taken as 10% of the maximum voltage and maximum current, respectively.

[0057] IV. Physical Effects of Physical Parameter Deviation The influence of parameter deviation on switching behavior can be quantitatively analyzed using equations (1) to (6). After obtaining the estimated value of the deviation, it is compensated to the corresponding nominal parameter (nominal parameter is represented by the subscript nom) to achieve parameter correction. Taking the current rise rate during the turn-on stage as an example, the nominal value of the gate resistance of the turn-on circuit is used. Its corresponding deviation After compensation and correction, the equation is as follows:

[0058] like (With a larger input capacitance), the rate of change of current under the same driving voltage will decrease significantly. This device will turn on slower than the nominal device and will withstand higher transient voltages in a series topology. Similarly, if the bond wire detaches... Increased size, or gate oxide degradation leading to Drift will cause inconsistencies in the switching characteristics of various devices. Traditional fixed-parameter control cannot detect this change, but the deviation identification neural network of this invention can accurately compensate for the above-mentioned deviation effect by adjusting the deviation amount online.

[0059] Similarly, for the turn-off phase, the correction method for the total gate resistance is as follows: By correcting this physical equation, a precise mapping between the physical mechanism of aging and the mathematical model was achieved.

[0060] V. Design and Online Fine-tuning Mechanism of Bias Identification Neural Network The physical information neural network of this invention adopts a hybrid architecture of "physical equations + neural network deviation compensation". Among them, the physical state equations (1) to (6) serve as a deterministic foundation, describing the explicit quantitative relationship between IGBT switching behavior and physical parameters and control variables; the deviation identification neural network ΔN is used to estimate the deviation of each device's physical parameters relative to the nominal value online, compensating for model errors caused by manufacturing dispersion and aging. The fusion of physical equations and neural networks is achieved in the following way: the deviation output by the neural network is compensated to the corresponding parameters in the physical equations, the compensated physical equations output predicted values, and the residual between the predicted values ​​and the measured values ​​is used as a self-supervised signal for backpropagation to fine-tune the network weights.

[0061] 5.1 Input State Definition For the i-th IGBT device, the physical feature vector extracted from the switching waveform is:

[0062] Each IGBT device has 11 input characteristics, corresponding to turn-on delay time, turn-on voltage change rate, turn-off voltage change rate, turn-on current change rate, turn-off current change rate, turn-on loss, turn-off loss, junction temperature, collector current, and collector-emitter voltage.

[0063] 5.2 Network Structure like Figure 3 As shown, the deviation identification network ΔN is deployed in the host computer controller. For a 2-series 2-parallel topology (4 IGBT devices), the physical feature vectors of all devices are concatenated to form a 44-dimensional input vector. The network consists of one input layer, four hidden layers, and one output layer, and its structural parameters are shown in Table 2.

[0064] Table 2. Structure parameters of the deviation identification network

[0065] The output layer uses the tanh activation function and multiplies it by a deviation boundary factor of 0.20 to limit the output deviation of each physical parameter to within ±20% of the nominal value, which is in line with the physical reasonable range of device parameters.

[0066] The deviation identification neural network outputs the deviation of the basic physical parameters of each device from their nominal values:

[0067] 5.3 Loss Function The loss function is defined as the difference between the predicted and measured values ​​of the physical equations of state:

[0068] in, The next period's state vector is predicted by the physical equations. This is the measured state vector for the next cycle.

[0069] 5.4 Enable conditions for online fine-tuning Fine-tuning is not mandatory in every switching cycle. It is triggered only when the following conditions are met simultaneously: (a) Loss function continuous One switching cycle (usually) =3~5) Exceeds the preset threshold This indicates the presence of systematic model bias (such as parameter drift caused by aging) rather than random measurement noise; (b) The current operating condition is in a steady state, and the rate of change of collector current and collector-emitter voltage is less than 10%, so as to avoid fine-tuning under transient operating conditions.

[0070] If the above conditions are not met, the fine-tuning will automatically pause, and the network weights will remain unchanged.

[0071] 5.5 Safety Assurance for Fine-tuning Online fine-tuning has the following triple security mechanisms: (1) The learning rate is extremely low. The weight changes are small within a single cycle, avoiding sudden weight changes caused by a single abnormal waveform. (2) The physical state equations form a soft guardrail constraint—if fine-tuning reduces the deviation Deviation from the reasonable physical range, physical residual It will increase immediately, and the backward gradient will pull the weights back; (3) Before the control variable is executed, the FPGA performs a range clamping check independent of the fine-tuning process to ensure that the control variable does not exceed the physical boundary in extreme cases.

[0072] Example 2 The following is combined with Figure 3 This embodiment provides a detailed description of the specific execution flow of the drive control method.

[0073] Step 1: Establish the transient physical state equations of the IGBT switch as a deterministic physical foundation.

[0074] As described in Part II above, equations (1) to (6) are established as the deterministic physical basis of the control algorithm. These equations describe the switching electrical behavior of each device during the turn-on and turn-off phases based on the basic physical parameters of each device and the gate drive control variables.

[0075] Step 2: Collect the switching waveform data of each device in real time and extract the physical feature vector from it.

[0076] Each FPGA in the digital drive unit acquires voltage and current waveform data via an ADCSPI controller using a dual-channel synchronous triggering method. The FPGA's internal real-time waveform feature extraction engine processes the acquired waveform data, extracting an 11-dimensional physical feature vector for each IGBT device. For a 2-series 2-parallel topology (4 IGBTs), the physical feature vectors of all devices are concatenated to form a 44-dimensional input vector. Each drive unit uploads the extracted physical feature vector to the host computer controller via an isolated communication bus.

[0077] Step 3: Input the physical feature vector into the deviation identification neural network to estimate the deviation of the basic physical parameters of each device from the nominal value online.

[0078] The host computer controller inputs the 44-dimensional physical feature vector uploaded in step two into the deviation identification neural network ΔN. After forward propagation, the network outputs the deviation of each device's basic physical parameters from their nominal values. Taking the current rise rate during the turn-on phase as an example, if... (With a larger input capacitance), the rate of change of current under the same driving voltage will decrease significantly, resulting in a slower turn-on speed for the device compared to the nominal device. In a series topology, it will withstand a higher transient voltage. The deviation identification neural network can estimate the aforementioned deviation online, providing a basis for subsequent compensation.

[0079] Step 4: Compensate the deviation to the corresponding basic physical parameters, and use the compensated basic physical parameters and the physical state equations to solve for the optimal control variables within the preset hard constraint boundary, and then issue the execution.

[0080] The host computer controller will use the deviation estimated in step three. Compensate to the corresponding nominal values ​​of the basic physical parameters to obtain the corrected physical parameters:

[0081] Substituting the corrected physical parameters into the physical state equations (1) to (6) of Example 1, and using optimization algorithms such as Model Predictive Control (MPC) or Sequential Quadratic Programming (SQP), the optimal control variables that minimize the voltage and current deviations between devices and the total switching loss are solved within the hard constraint boundary described in Part III above. .

[0082] The host computer controller sends the solved optimal control variables to each digital drive unit via an isolated communication bus. Upon receiving the optimal control variables, the FPGA in each drive unit sends the digital value to the DAC via the DACSPI controller. The DAC outputs the corresponding analog reference voltage, which is then used by the OPA549 high-power operational amplifier to generate an adjustable gate drive voltage, driving the gate of the corresponding IGBT device. Simultaneously, the PWM timing generator inside the FPGA adjusts the delay compensation amount... and Adjust the switching timing of each device.

[0083] Step 5: During online operation, the physical residual between the predicted value of the physical state equation set and the measured switch waveform data is used as a self-supervised signal to fine-tune the weights of the deviation identification neural network online when the preset triggering conditions are met.

[0084] After each switching action, the host computer controller substitutes the corrected physical parameters into the physical state equations (1)~(6) to calculate the predicted values ​​of each switching characteristic quantity. and compared with the measured value Compare and calculate physical residuals The physical residual serves as a self-monitoring signal, and when the enabling conditions described in Part 5 are met, it fine-tunes the weights of the deviation identification neural network online. Through this online fine-tuning mechanism, the deviation identification neural network can continuously track parameter changes caused by device aging (such as increased gate resistance due to bond wire detachment, and threshold voltage drift due to gate oxide degradation), achieving adaptive optimization of the control device throughout the entire IGBT lifecycle.

[0085] By adopting the technical solution of the present invention, the following effects can be achieved: (1) Pressure and flow equalization performance: The series pressure unevenness rate is reduced to below 1%, and the parallel flow unevenness rate is reduced to below 1.5%.

[0086] (2) Balanced switching losses: The maximum deviation of switching losses of each device is reduced to less than 5%, and the overall lifespan of each device tends to be consistent; the total switching loss is reduced by 8%~12%, and the system efficiency is improved.

[0087] (3) Full life cycle adaptive: Through the online fine-tuning mechanism, the device continuously compensates for device aging drift, and the control device maintains the optimal performance throughout the IGBT's life cycle, overcoming the time decay defect of the traditional offline curing solution.

[0088] (4) Simplified hardware isolation architecture: Each driver unit only needs one isolated RS-485 transceiver, which reduces the number of isolation devices by more than 70% compared to the independent isolation scheme for each channel.

[0089] (5) The computational efficiency meets the high-frequency requirements: forward inference is about 5~20μs, online fine-tuning is about 15μs, and the total processing time per cycle is less than 100μs, which meets the real-time closed-loop control requirements of switching frequencies above 10kHz.

[0090] The specific indicators are shown in Table 3: Table 3 Comparison of Performance Indicators

[0091] like Figure 4 As shown, after about 100 iterations, the pressure and current equalization effect of the scheme in this invention has been reduced to less than 1.5%, verifying the effectiveness of the scheme.

[0092] The specific implementation of the present invention has been described above using a 2-series, 2-parallel topology as an example. Those skilled in the art will understand that the technical solution of the present invention can be extended to any N-series, M-parallel IGBT topology. It only requires expanding the input dimension of the physical information neural network to 11×N×M dimensions (i.e., 11-dimensional features for each IGBT device), expanding the output dimension to 5×N×M dimensions (i.e., 5 physical parameter deviations for each IGBT device), and correspondingly expanding the control variable dimension to 4×N×M dimensions. The model can then be implemented on an FPGA-SoC.

[0093] Example 3 This embodiment also provides an electronic device, see reference. Figure 4 It includes a memory 404 and a processor 402, wherein the memory 404 stores a computer program and the processor 402 is configured to run the computer program to perform the steps in any of the above method embodiments.

[0094] Specifically, the processor 402 may include a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of the present invention.

[0095] Memory 404 may include a mass storage device for data or instructions. For example, and not limitingly, memory 404 may include a hard disk drive (HDD), a floppy disk drive, a solid-state drive (SSD), flash memory, an optical disk drive, a magneto-optical disk drive, magnetic tape, or a Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 404 may include removable or non-removable (or fixed) media. Where appropriate, memory 404 may be internal or external to a data processing device. In a particular embodiment, memory 404 is non-volatile memory. In a particular embodiment, memory 404 includes read-only memory (ROM) and random access memory (RAM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable read-only memory (PROM), an erasable read-only memory (EPROM), an electrically erasable read-only memory (EEPROM), an electrically alterable read-only memory (EAROM), or flash memory, or a combination of two or more of these. Where appropriate, the RAM can be Static Random-Access Memory (SRAM) or Dynamic Random-Access Memory (DRAM). DRAM can be Fast Page Mode Dynamic Random Access Memory (FPMDRAM), Extended Data Out Dynamic Random Access Memory (EDODRAM), Synchronous Dynamic Random-Access Memory (SDRAM), etc.

[0096] The memory 404 can be used to store or cache various data files that need to be processed and / or communicated, as well as possible computer program instructions executed by the processor 402.

[0097] The processor 402 reads and executes computer program instructions stored in the memory 404 to implement any of the insulated gate bipolar transistor driving control methods in the above embodiments.

[0098] Optionally, the electronic device may further include a transmission device 406 and an input / output device 408, wherein the transmission device 406 is connected to the processor 402, and the input / output device 408 is connected to the processor 402.

[0099] The transmission device 406 can be used to receive or send data via a network. Specific examples of the network described above may include wired or wireless networks provided by the communication provider of the electronic device. In one example, the transmission device includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 406 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0100] Input / output device 408 is used for inputting or outputting information. It can be a speaker, microphone, monitor, or keyboard.

[0101] Example 4 This embodiment also provides a readable storage medium storing a computer program, the computer program including program code for controlling a process to execute the process, the process including the insulated gate bipolar transistor driving control method according to Embodiment 1.

[0102] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementations, and will not be repeated here.

[0103] Generally, various embodiments can be implemented in hardware or dedicated circuitry, software, logic, or any combination thereof. Some aspects of the invention can be implemented in hardware, while others can be implemented by firmware or software executed by a controller, microprocessor, or other computing device, but the invention is not limited thereto. Although various aspects of the invention may be shown and described as block diagrams, flowcharts, or using some other graphical representation, it should be understood that, by way of non-limiting example, these blocks, apparatuses, systems, techniques, or methods described herein can be implemented in hardware, software, firmware, dedicated circuitry or logic, general-purpose hardware or controllers or other computing devices, or some combination thereof.

[0104] Embodiments of the present invention can be implemented by computer software, which may be executable by a data processor of a mobile device, such as a processor entity, or by hardware, or by a combination of software and hardware. Computer software or programs (also referred to as program products) including software routines, applets, and / or macros can be stored in any device-readable data storage medium, and they include program instructions for performing specific tasks. The computer program product may include one or more computer-executable components configured to perform the embodiments when the program is run. The one or more computer-executable components may be at least one piece of software code or a portion thereof. Additionally, it should be noted in this respect that, as Figure 3 Any box in the logical flow can represent a program step, or interconnected logic circuits, boxes and functions, or a combination of program steps and logic circuits, boxes and functions. Software can be stored on physical media such as memory chips or blocks of storage implemented within a processor, magnetic media such as hard disks or floppy disks, and optical media such as DVDs and their data variants, CDs, etc. The physical medium is a non-transient medium.

[0105] Those skilled in the art should understand that the technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments have been described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0106] The above embodiments are merely illustrative of several implementations of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the appended claims.

Claims

1. A driving control method for an insulated gate bipolar transistor, characterized in that, Includes the following steps: A set of transient physical state equations for insulated gate bipolar transistor (IGBT) switching is established as a deterministic physical foundation. The set of physical state equations describes the switching electrical behavior of each device during the turn-on and turn-off phases based on the basic physical parameters of each device and the gate drive control variables. Real-time acquisition of switching waveform data of each device and extraction of physical feature vectors from it; The physical feature vector is input into the deviation identification neural network, which then estimates the deviation of the basic physical parameters of each device from the nominal value online. The deviation is compensated to the corresponding basic physical parameters. Using the compensated basic physical parameters and the physical state equations, the optimal control variables that minimize the voltage and current deviations between devices are solved within the preset hard constraint boundary. The optimal control variables are then sent to the programmable gate drive circuits corresponding to each device for execution. During online operation, the physical residual between the predicted value of the physical state equation set and the measured switch waveform data is used as a self-supervised signal. When the preset triggering conditions are met, the weights of the deviation identification neural network are finely adjusted online to adaptively compensate for the dispersion of device parameters and the characteristic drift caused by aging.

2. The insulated gate bipolar transistor driving control method as described in claim 1, characterized in that, The basic physical parameters include the input capacitance, Miller capacitance, gate resistance, threshold voltage, and transconductance of each device. The physical state equation set includes the on-current rate of change equation, the on-voltage rate of change equation, and the on-delay equation for the on-phase, as well as the off-voltage rate of change equation, the off-current rate of change equation, and the off-delay equation for the off-phase. The gate drive control variables include the turn-on drive voltage, the turn-off drive voltage, the turn-on delay compensation time, and the turn-off delay compensation time.

3. The insulated gate bipolar transistor driving control method as described in claim 1, characterized in that, The physical feature vector includes turn-on delay time, turn-off delay time, turn-on voltage change rate, turn-off voltage change rate, turn-on current change rate, turn-off current change rate, turn-on loss, turn-off loss, junction temperature, collector current, and collector-emitter voltage extracted from the switching waveforms of each device.

4. The insulated gate bipolar transistor driving control method as described in claim 1, characterized in that, The bias identification neural network includes an input layer, multiple hidden layers, and an output layer connected in sequence. The input layer receives the physical feature vectors of each device; Each of the hidden layers uses the ReLU activation function; The output layer uses the tanh activation function and multiplies it by a preset deviation boundary factor to limit the output range of the deviation amount to a preset percentage range of the nominal value.

5. The insulated-gate bipolar transistor driving control method as described in claim 1, characterized in that, The optimal control variables are solved using model predictive control algorithm or sequential quadratic programming algorithm; The hard constraints include that the collector-emitter voltage of each device does not exceed the preset maximum withstand voltage value and that the collector current of each device does not exceed the preset maximum current value. The optimization objective is to ensure that the maximum voltage deviation and maximum current deviation between each device do not exceed the preset voltage equalization threshold and current equalization threshold, respectively, and to minimize the total switching loss.

6. The insulated gate bipolar transistor driving control method as described in claim 1, characterized in that, The preset triggering condition also includes: the switching cycles of the physical residual for a consecutive preset number of times exceed a preset threshold, in order to distinguish between systematic model bias and random measurement noise; The current operating condition is in a steady state, and the rate of change of the operating condition is lower than the preset steady state judgment threshold; If the above conditions are not met, the online fine-tuning will be automatically paused, and the network weights will remain unchanged.

7. The insulated-gate bipolar transistor driving control method as described in claim 1, characterized in that, The online fine-tuning uses a preset low learning rate to avoid sudden changes in weights; The physical state equations form a soft guardrail constraint. When the deviation deviates from the reasonable physical range, the physical residual increases to pull the network weights back. Before the optimal control variable is issued, a range clamping check is performed independently of the online fine-tuning process to ensure that the optimal control variable does not exceed the physical boundary.

8. A drive and control device for an insulated gate bipolar transistor, characterized in that, include: Multiple digital driving units, each of which is connected to an insulated gate bipolar transistor and is located at a high-voltage floating ground potential, and each of the digital driving units includes a voltage sampling module, a current sampling module, a programmable logic control module, a digital-to-analog converter module, an adjustable gate drive circuit, and an isolated communication module; The voltage sampling module and the current sampling module are used to collect the voltage waveform data and current waveform data of the corresponding devices in real time, respectively. The programmable logic control module is used to extract physical feature vectors from the waveform data and generate PWM timing control signals; The digital-to-analog converter module and the adjustable gate drive circuit are used to output an adjustable gate drive voltage according to the received control signal to drive the gate of the corresponding device. The host computer controller is internally deployed with the deviation identification neural network and optimization algorithm engine, used to receive the physical feature vectors uploaded by each of the digital drive units, execute the insulated gate bipolar transistor drive control method as described in any one of claims 1 to 7, and send the optimal control variables obtained by solving to each of the digital drive units. The isolation communication module is located between the programmable logic control module and the host computer controller, serving as the only electrical isolation boundary between each digital drive unit and the host computer controller.

9. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the insulated gate bipolar transistor driving control method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program code for controlling a process to execute the process, the process including the insulated gate bipolar transistor drive control method according to any one of claims 1 to 7.

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