Current-voltage optimization circuit for a dc-dc system exiting low power mode

Abstract

The application discloses a current-voltage optimization circuit for a DCDC system to quit a low-power mode, comprising an error amplifier EA, a fast-response voltage division circuit, a slow-response voltage division circuit, a small bias current Ibias1, a large current bias current circuit, a capacitor C1, an NMOS tube NM5, a delay device delay, an inverter INV1 and a capacitor C2. The application solves the coupling of vref when quitting the low-power mode, the fast establishment of ibias and the switching problem of two series of fb voltage division resistors.

Description

Technical Field

[0001] This invention relates to a current and voltage optimization circuit, and more particularly to a current and voltage optimization circuit for a DC-DC system when exiting low-power mode, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] In battery-powered, IoT, and automotive electronic systems, devices are mostly in a light-load or standby state. Traditional DC-DC power chips suffer from low efficiency and high static power consumption under light-load conditions, severely limiting system endurance and overall energy efficiency. Light-load low-power design, through optimized control strategies, reduced static current, and minimized switching and drive losses, can significantly improve the conversion efficiency of power chips across the entire load range, especially improving energy utilization under light-load conditions. Exiting light-load mode places comprehensive performance requirements on power chips, demanding rapid response, smooth switching, and stable reliability. The chip must possess a precise load change detection mechanism to promptly identify the transition from light to heavy load and quickly recover from PFM, Burst, or sleep modes to normal PWM operating mode. During the switching process, the output voltage should not experience significant drops or overshoots to avoid transient disturbances and loop oscillations caused by mode transitions. Simultaneously, the chip's internal bias circuit must have rapid wake-up capability, minimizing voltage coupling interference during module re-establishment to ensure stable system operation during load changes. To mitigate the impact of the current and voltage bias circuits on load dynamics when exiting low-power mode, some design optimization is required.

[0003] Traditional architecture such as Figure 3 As shown, the inputs of EA are the voltage divider fb of vref and VOUT, and the output comp determines the average load current. It also requires iref to provide the bias current ibias. In light load mode, EA and iref need to be turned off, as this will affect the establishment of internal nodes during recovery. The series resistance value of the voltage divider resistor of VOUT cannot be large, as this will affect the power consumption of the circuit, but it will also affect the following speed of fb.

[0004] In summary, the chip's voltage and current, as well as the follow-up speed of fb, determine whether comp changes in a timely manner when exiting low-power mode, indirectly affecting load dynamics. An optimization method is needed to solve the problems of current and fb setup speed, as well as the coupling problem of vref due to the switch. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a current and voltage optimization circuit for a DC-DC system when exiting low-power mode, which has fast fb response speed, fast iref establishment speed and reduces vref interference from switch coupling when exiting low-power mode.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0007] A current-voltage optimization circuit for exiting low-power mode in a DC-DC system includes an error amplifier EA, a fast-response voltage divider circuit, a slow-response voltage divider circuit, a small bias current Ibias1, a large current bias current circuit, a capacitor C1, an NMOS transistor NM5, a delay circuit, an inverter INV1, and a capacitor C2. The non-inverting input terminal of the error amplifier EA is connected to one end of capacitor C1, the source and drain of the NMOS transistor NM5, and a reference voltage vref. The gate of the NMOS transistor NM5 is connected to the input terminal of the delay circuit and a sleep signal is connected. The delay circuit dela... The output of y is connected to the input of inverter INV1 and generates the signal sleep_d. The output of inverter INV1 generates the signal sleep_b. The inverting input of error amplifier EA is connected to the outputs of the fast-response voltage divider circuit and the slow-response voltage divider circuit and generates the voltage divider signal fb. The output of error amplifier EA is connected to one end of capacitor C2 and generates the signal comp. The other ends of capacitor C1 and capacitor C2 are grounded. The first bias current terminal of error amplifier EA is connected to the small bias current Ibias1. The second bias current terminal of error amplifier EA is connected to the output of the large bias current circuit.

[0008] Furthermore, the fast-response voltage divider circuit includes resistors R3 and R4 and an NMOS transistor NM6. One end of resistor R3 is connected to the signal VOUT, and the other end of resistor R3 is connected to one end of resistor R4 and the source of NMOS transistor NM6. The other end of resistor R4 is grounded. The gate of NMOS transistor NM6 is connected to the signal sleep_dlyn, and the drain of NMOS transistor NM6 serves as the output terminal of the fast-response voltage divider circuit to generate a voltage divider signal fb.

[0009] Furthermore, the slow-response voltage divider circuit includes resistors R1 and R2, NMOS transistors NM7 and NMOS transistors NM8. One end of resistor R1 is connected to the signal VOUT, and the other end of resistor R1 is connected to one end of resistor R2 and the drain of NMOS transistor NM7. The other end of resistor R2 is grounded. The source of NMOS transistor NM7 is connected to the source of NMOS transistor NM8. The gates of NMOS transistor NM7 and NMOS transistor NM8 are connected to the signal sleep_dly. The drain of NMOS transistor NM8 serves as the output terminal of the slow-response voltage divider circuit and generates a voltage divider signal fb.

[0010] Furthermore, the resistance values ​​of resistors R1 and R2 are 400kΩ and 100kΩ, respectively, and the resistance values ​​of resistors R3 and R4 are 4MΩ and 1MΩ, respectively.

[0011] Furthermore, the signals sleep_d and sleep_dly are delayed signals of the signal sleep, and the delay of the signal sleep_dly is greater than that of the signal sleep_d, and the delay of the signal sleep_dly relative to the signal sleep is greater than 1µs.

[0012] Furthermore, the high-current bias circuit includes PMOS transistors PM1, PM2, PM3, PM4, PM5, NMOS transistors NM1, NM2, NM4, current source Ibias, and current source Ibias3. The sources of PMOS transistors PM1, PM2, and PM3 are connected to the power supply avdd. The drain of PMOS transistor PM3 serves as the output terminal of the high-current bias circuit and generates a high-bias current Ibias2. The gate of PMOS transistor PM1 is connected to the drain of PMOS transistor PM1, one end of current source Ibias3, the source of PMOS transistor PM5, the gate of PMOS transistor PM2, and the drain of PMOS transistor PM3. The gate of transistor 3 is connected and generates signal Vg1. The other end of current source Ibias3 is grounded. The drain of PMOS transistor PM2 is connected to the source of PMOS transistor PM4. The gate of PMOS transistor PM4 is connected to signal sleep_d. The drain of PMOS transistor PM4 is connected to the gate of PMOS transistor PM5 and the drain of NMOS transistor NM2 and generates signal Vg2. The drain of PMOS transistor PM5 is connected to the drain of NMOS transistor NM4. The gate of NMOS transistor NM4 is connected to signal sleep_b. The gate of NMOS transistor NM2 is connected to the gate of NMOS transistor NM1, the drain of NMOS transistor NM1 and one end of current source Ibias. The sources of NMOS transistor NM1, NMOS transistor NM2 and NMOS transistor NM4 are grounded.

[0013] Furthermore, the PMOS transistors PM1, PM2, and PM3 constitute a PMOS-type current mirror, and the current ratio flowing through PMOS transistors PM1, PM2, and PM3 is 1:1:1.

[0014] Furthermore, the NMOS transistors NM1 and NM2 constitute an NMOS-type current mirror, and the current ratio flowing through NMOS transistors NM1 and NMOS transistors NM2 is 1:4.

[0015] Furthermore, the small bias current Ibias1 is 50nA, the large bias current Ibias2 is greater than 1uA, and the bias current source Ibias3 is 50nA.

[0016] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a current and voltage optimization circuit for a DC-DC system to exit low-power mode, solving the problems of vref coupling, rapid establishment of ibias, and switching of the two string fb voltage divider resistors when exiting low-power mode; The present invention effectively solves the problem of rapid and stable recovery of various biases of EA when exiting low-power mode by retaining a small current to maintain the EA node voltage, rapidly discharging the current mirror gate when exiting low-power mode, and controlling the switching stability of fb in timing, thus ensuring the stability of comp and helping to solve the interference of current and voltage bias on the dynamic response of the load when exiting low-power mode. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a current and voltage optimization circuit for a DC-DC system when exiting low-power mode according to the present invention.

[0018] Figure 2 This is a schematic diagram of the switching timing of a current and voltage optimization circuit for a DC-DC system when exiting low-power mode according to the present invention.

[0019] Figure 3 This is a schematic diagram of the current and voltage optimization design of a current-voltage DC-DC system in the prior art. Detailed Implementation

[0020] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0021] like Figure 1As shown, the present invention discloses a current and voltage optimization circuit for exiting low-power mode in a DC-DC system, comprising an error amplifier EA, a fast-response voltage divider circuit, a slow-response voltage divider circuit, a small bias current Ibias1, a large current bias current circuit, a capacitor C1, an NMOS transistor NM5, a delay circuit, an inverter INV1, and a capacitor C2. The non-inverting input terminal of the error amplifier EA is connected to one end of the capacitor C1, the source and drain of the NMOS transistor NM5, and a reference voltage vref. The gate of the NMOS transistor NM5 is connected to the input terminal of the delay circuit and a sleep signal is connected. The delay circuit... The output of elay is connected to the input of inverter INV1 and generates the signal sleep_d. The output of inverter INV1 generates the signal sleep_b. The inverting input of error amplifier EA is connected to the outputs of the fast-response voltage divider circuit and the slow-response voltage divider circuit and generates the voltage divider signal fb. The output of error amplifier EA is connected to one end of capacitor C2 and generates the signal comp. The other ends of capacitors C1 and C2 are grounded. The first bias current terminal of error amplifier EA is connected to the small bias current Ibias1. The second bias current terminal of error amplifier EA is connected to the output of the large bias current circuit.

[0022] The fast-response voltage divider circuit includes resistors R3 and R4 and an NMOS transistor NM6. One end of resistor R3 is connected to the signal VOUT, and the other end of resistor R3 is connected to one end of resistor R4 and the source of NMOS transistor NM6. The other end of resistor R4 is grounded. The gate of NMOS transistor NM6 is connected to the signal sleep_dlyn. The drain of NMOS transistor NM6 serves as the output terminal of the fast-response voltage divider circuit, generating a voltage divider signal fb.

[0023] The slow-response voltage divider circuit includes resistors R1 and R2, NMOS transistors NM7 and NM8. One end of resistor R1 is connected to the signal VOUT, and the other end of resistor R1 is connected to one end of resistor R2 and the drain of NMOS transistor NM7. The other end of resistor R2 is grounded. The source of NMOS transistor NM7 is connected to the source of NMOS transistor NM8. The gates of NMOS transistor NM7 and NMOS transistor NM8 are connected to the signal sleep_dly. The drain of NMOS transistor NM8 serves as the output terminal of the slow-response voltage divider circuit and generates the voltage divider signal fb.

[0024] The resistors R1 and R2 have resistances of 400kΩ and 100kΩ, respectively, while R3 and R4 have resistances of 4MΩ and 1MΩ, respectively. The fast-response voltage divider circuit has low resistance and a fast response speed but high power consumption, and is used in non-low-power modes. The slow-response voltage divider circuit has high resistance and a slow response speed, but is used in low-power modes. Furthermore, when exiting low-power mode, the falling edge of `sleep_dly` must be at least 1µs later than the falling edge of `sleep` to ensure that NMOS transistors NM7 and NM8 are turned off and NMOS transistor NM6 is turned on only after the low-resistance voltage series has stabilized.

[0025] The signals sleep_d and sleep_dly are delayed versions of the signal sleep, with the delay of sleep_dly being greater than that of sleep_d, and the delay of sleep_dly relative to sleep being greater than 1µs.

[0026] The high-current bias circuit includes PMOS transistors PM1, PM2, PM3, PM4, and PM5, NMOS transistors NM1, NM2, and NM4, and current sources Ibias and Ibias3. The sources of PMOS transistors PM1, PM2, and PM3 are connected to the power supply avdd. The drain of PMOS transistor PM3 serves as the output of the high-current bias circuit and generates a large bias current Ibias2. The gates of PMOS transistors PM1 and PM2, one end of current source Ibias3, the source of PMOS transistor PM5, the gate of PMOS transistor PM2, and the gate of PMOS transistor PM3 are connected to the power supply avdd. Connect and generate signal Vg1. The other end of current source Ibias3 is grounded. The drain of PMOS transistor PM2 is connected to the source of PMOS transistor PM4. The gate of PMOS transistor PM4 is connected to signal sleep_d. The drain of PMOS transistor PM4 is connected to the gate of PMOS transistor PM5 and the drain of NMOS transistor NM2 and generates signal Vg2. The drain of PMOS transistor PM5 is connected to the drain of NMOS transistor NM4. The gate of NMOS transistor NM4 is connected to signal sleep_b. The gate of NMOS transistor NM2 is connected to the gate of NMOS transistor NM1, the drain of NMOS transistor NM1 and one end of current source Ibias. The sources of NMOS transistor NM1, NMOS transistor NM2 and NMOS transistor NM4 are grounded.

[0027] PMOS transistors PM1, PM2, and PM3 form a PMOS-type current mirror, with the current flowing through them in a 1:1:1 ratio. NMOS transistors NM1 and NM2 form an NMOS-type current mirror, with the current flowing through them in a 1:4 ratio. The small bias current Ibias1 is 50nA and is not turned off in low-power mode to ensure that the major node changes of EA do not become too large when exiting low-power mode, thus affecting the preceding stage vref. The large bias current Ibias2 is greater than 1uA, sourced from ibias3. In low-power mode, ibias3 is turned off, and the current flowing through PM2 is provided by ibias, which is not turned off. The bias current source Ibias3 has a current of 50nA. The branch current during low power consumption is interrupted by switches PM4 and NM4. When exiting low power consumption mode, ibias3, PM4, and NM4 are turned on. Vg2 is pulled low by NM2 at this time. Since the source terminal of PM5 is connected to avdd, the current flowing through PM5 will increase, quickly releasing the charge on the capacitor at point Vg1. ibias2 will be quickly established. The current flowing through PM2 (1uA) is much greater than the current on NM2 (200nA), so Vg2 is raised, turning off the current on PM5, allowing ibias2 to reach stability.

[0028] The working principle of the current and voltage optimization circuit for exiting low-power mode in a DC-DC system according to the present invention is as follows: To meet the requirements of low-power mode, two series of voltage divider resistors are needed. The low-resistance value has a fast response speed but high power consumption and is used in non-low-power mode. The high-resistance value has a slow response speed and is used in low-power mode. When exiting low-power mode, the falling edge of sleep_dly is guaranteed to release after dynamic stabilization. The current bias of EA consists of ibias1 and ibias2. ibias1 is a small current and is not turned off in low-power mode to ensure that the main node change of EA will not be too large when exiting low-power mode, thus affecting the front-end vref. ibias2 flowing through PM3 is a large current, which is provided by ibias3. ibias3 is turned off in low-power mode. The current flowing through PM2 is provided by ibias and is not turned off. The branch current in low-power mode is isolated by switches PM4 and NM4. When exiting low-power mode, the current bias is adjusted accordingly. In low-power mode, ibias3, PM4, and NM4 are enabled. VG2 is pulled low by NM2. Since the source of PM5 is connected to AVDD, the current flowing through PM5 increases, quickly releasing the charge on the capacitor at point VG1. ibias2 is quickly established. The current flowing through PM2 is greater than the current on NM2, so VG2 is raised. The current on PM5 is turned off, allowing ibias2 to stabilize. Because there is parasitic capacitance between VRef and the internal nodes of EA, to prevent the internal nodes of EA from raising VRef when exiting low-power mode, thus raising VRef, the switching coupling characteristics of NM5 are utilized to connect its source and drain. Utilizing the capacitance characteristics between the gate oxide and the channel, when exiting sleep, the gate of NM5 changes from high to low, using its capacitance characteristics to lower the coupling between the source and drain. At this time, EA is enabled again to counteract the upward coupling of VRef caused by the re-establishment of internal nodes of EA, ensuring the controllability of the comp amplitude.

[0029] like Figure 2 As shown, the sleep_d signal is a delay of the sleep signal, and the sleep_dly signal is a large delay of the sleep signal to ensure that the resistor string and EA voltage are fully restored. The sleep_dlyn and sleep_dly have a certain non-clock overlap.

[0030] This invention provides a current and voltage optimization circuit for a DC-DC system exiting low-power mode, solving the problems of vref coupling, rapid ibias establishment, and switching of the two string fb voltage divider resistors when exiting low-power mode. By retaining a small current to maintain the EA node voltage, rapidly discharging the current mirror gate when exiting low-power mode, and controlling the switching stability of fb, this invention effectively solves the problem of rapid and stable recovery of various biases of EA when exiting low-power mode, ensuring the stability of the comp, and helping to solve the interference of current and voltage biases on the dynamic response of the load when exiting low-power mode.

[0031] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A current and voltage optimization circuit for exiting low-power mode in a DC-DC system, characterized in that: The circuit includes an error amplifier EA, a fast-response voltage divider circuit, a slow-response voltage divider circuit, a small bias current Ibias1, a large current bias current circuit, a capacitor C1, an NMOS transistor NM5, a delay circuit, an inverter INV1, and a capacitor C2. The non-inverting input of the error amplifier EA is connected to one end of capacitor C1, the source and drain of the NMOS transistor NM5, and a reference voltage vref. The gate of the NMOS transistor NM5 is connected to the input of the delay circuit and the sleep signal. The output of the delay circuit is connected to the inverter INV1. The input terminal of the inverter INV1 is connected to generate the signal sleep_d, the output terminal of the inverter INV1 generates the signal sleep_b, the inverting input terminal of the error amplifier EA is connected to the output terminals of the fast response voltage divider circuit and the slow response voltage divider circuit to generate the voltage divider signal fb, the output terminal of the error amplifier EA is connected to one end of the capacitor C2 to generate the signal comp, the other end of the capacitor C1 and the other end of the capacitor C2 are grounded, the first bias current terminal of the error amplifier EA is connected to the small bias current Ibias1, and the second bias current terminal of the error amplifier EA is connected to the output terminal of the large bias current circuit.

2. The current and voltage optimization circuit for exiting low-power mode in a DC-DC system according to claim 1, characterized in that: The fast-response voltage divider circuit includes resistors R3 and R4 and an NMOS transistor NM6. One end of resistor R3 is connected to the signal VOUT, and the other end of resistor R3 is connected to one end of resistor R4 and the source of NMOS transistor NM6. The other end of resistor R4 is grounded. The gate of NMOS transistor NM6 is connected to the signal sleep_dlyn. The drain of NMOS transistor NM6 serves as the output terminal of the fast-response voltage divider circuit to generate a voltage divider signal fb.

3. The current and voltage optimization circuit for exiting low-power mode in a DC-DC system according to claim 2, characterized in that: The slow-response voltage divider circuit includes resistors R1 and R2, NMOS transistors NM7 and NM8. One end of resistor R1 is connected to the signal VOUT, and the other end of resistor R1 is connected to one end of resistor R2 and the drain of NMOS transistor NM7. The other end of resistor R2 is grounded. The source of NMOS transistor NM7 is connected to the source of NMOS transistor NM8. The gates of NMOS transistor NM7 and NMOS transistor NM8 are connected to the signal sleep_dly. The drain of NMOS transistor NM8 serves as the output terminal of the slow-response voltage divider circuit and generates a voltage divider signal fb.

4. The current and voltage optimization circuit for exiting low-power mode in a DC-DC system according to claim 3, characterized in that: The resistance values ​​of resistors R1 and R2 are 400kΩ and 100kΩ, respectively, and the resistance values ​​of resistors R3 and R4 are 4MΩ and 1MΩ, respectively.

5. The current and voltage optimization circuit for exiting low-power mode in a DC-DC system according to claim 3, characterized in that: The signals sleep_d and sleep_dly are delayed versions of the signal sleep, and the delay of the signal sleep_dly is greater than that of the signal sleep_d. The delay of the signal sleep_dly relative to the signal sleep is greater than 1µs.

6. The current and voltage optimization circuit for exiting low-power mode in a DC-DC system according to claim 1, characterized in that: The high-current bias circuit includes PMOS transistors PM1, PM2, PM3, PM4, and PM5, NMOS transistors NM1, NM2, and NM4, current sources Ibias and Ibias3. The sources of PMOS transistors PM1, PM2, and PM3 are connected to the power supply avdd. The drain of PMOS transistor PM3 serves as the output of the high-current bias circuit and generates a high-bias current Ibias2. The gate of PMOS transistor PM1 is connected to the drain of PMOS transistor PM1, one end of current source Ibias3, the source of PMOS transistor PM5, the gate of PMOS transistor PM2, and the gate of PMOS transistor PM3. The gate of PMOS transistor PM2 is connected to the source of PMOS transistor PM4, and the gate of PMOS transistor PM4 is connected to the signal sleep_d. The drain of PMOS transistor PM4 is connected to the gate of PMOS transistor PM5 and the drain of NMOS transistor NM2, and the signal Vg2 is generated. The drain of PMOS transistor PM5 is connected to the drain of NMOS transistor NM4, and the gate of NMOS transistor NM4 is connected to the signal sleep_b. The gate of NMOS transistor NM2 is connected to the gate of NMOS transistor NM1, the drain of NMOS transistor NM1, and one end of the current source Ibias. The sources of NMOS transistor NM1, NMOS transistor NM2, and NMOS transistor NM4 are grounded.

7. The current and voltage optimization circuit for exiting low-power mode in a DC-DC system according to claim 6, characterized in that: The PMOS transistors PM1, PM2, and PM3 form a PMOS-type current mirror, and the current ratio flowing through them is 1:1:

1.

8. The current and voltage optimization circuit for exiting low-power mode in a DC-DC system according to claim 6, characterized in that: The NMOS transistors NM1 and NM2 form an NMOS-type current mirror, and the current ratio flowing through NMOS transistors NM1 and NMOS transistors NM2 is 1:

4.

9. The current and voltage optimization circuit for exiting low-power mode in a DC-DC system according to claim 6, characterized in that: The small bias current Ibias1 is 50nA, the large bias current Ibias2 is greater than 1uA, and the bias current source Ibias3 is 50nA.

Images