Voltage converter, chip and electronic device

Abstract

The application relates to a voltage converter, a chip and an electronic device. The freewheeling switch of the voltage converter comprises a main freewheeling tube and a plurality of auxiliary freewheeling tubes connected in parallel. The voltage converter further comprises: a current sampling circuit for detecting a first detection voltage carrying information of an inductive current; a zero-crossing detection circuit for obtaining a zero-crossing detection signal according to the voltage across the freewheeling switch of the voltage converter; and a logic drive circuit for controlling the number of turned-on auxiliary freewheeling tubes according to the first detection voltage. The number of turned-on auxiliary freewheeling tubes is directly proportional to the voltage value of the first detection voltage. In this way, the logic drive circuit can drive the turn-off of a part or all of the auxiliary freewheeling tubes based on the first detection voltage in the low-load scenario of the voltage converter, so that the on-resistance of the freewheeling switch is increased, the detection error caused by the offset voltage of the comparator in the zero-crossing detection circuit is reduced, and the accuracy of the zero-crossing detection threshold is greatly improved.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a voltage converter, chip and electronic device. Background Technology

[0002] In switching converters, to improve efficiency under light loads, they are typically operated in discontinuous mode. In synchronous rectifier converters, to enable the control system to operate in discontinuous mode, a zero-crossing detection circuit for detecting inductor current must be used. In buck, boost, and buck-boost topologies, when the inductor current is detected to be at zero crossing, the freewheeling diode is immediately switched off to prevent reverse freewheeling and energy loss.

[0003] In traditional solutions, zero-crossing detectors (ZCDs) typically use a comparator to compare the voltage across the freewheeling diode to determine if the inductor current has crossed zero. However, due to the comparator's offset voltage, the zero-crossing detector has a detection error, the magnitude of which is the comparator's offset voltage divided by the freewheeling diode's on-resistance. In low-load scenarios, the on-resistance of the switching transistor is very small, resulting in a significant detection error that negatively impacts the circuit's normal operation. Summary of the Invention

[0004] The purpose of this application is to provide a voltage converter, chip, and electronic device that aims to solve the problem of large detection error in the zero-crossing detection circuit of traditional switching converters in low-load scenarios.

[0005] In a first aspect, embodiments of this application provide a voltage converter, which includes an input terminal, an output terminal, a main power transistor, a freewheeling switch module, and an inductor. A first end of the inductor is connected to the input terminal, and a second end of the inductor is connected to a first node. The freewheeling switch module is connected between the first node and the output terminal, and the main power transistor is connected between the first node and ground. Alternatively, the first end of the main power transistor is connected to the input terminal, and the second end of the main power transistor is connected to the first node. The inductor is connected between the first node and the output terminal, and the freewheeling switch module is connected between the first node and ground. The freewheeling switch module includes a main freewheeling transistor and multiple auxiliary freewheeling transistors connected in parallel. The voltage converter also includes a current sampling circuit, a zero-crossing detection circuit, and a logic driving circuit. The current sampling circuit is connected to the first node and is used to obtain a first detection voltage carrying inductor current information and / or output current information based on the electrical signal of the first node. The zero-crossing detection circuit is connected to both ends of the freewheeling switch module, and the zero-crossing detection signal is obtained based on the voltage across both ends of the freewheeling switch module. The logic driving circuit is connected to the current sampling circuit, the zero-crossing detection circuit, the main power transistor, and the freewheeling switch module. The logic driving circuit is used to control the number of the secondary freewheeling transistors turned on according to the first detection voltage, and to control the freewheeling switch module and the main power transistor to be turned on alternately according to the zero-crossing detection signal. The number of the secondary freewheeling transistors turned on is proportional to the voltage value of the first detection voltage.

[0006] In some embodiments, the logic driving circuit is configured to compare the first detected voltage with a plurality of reference voltages in an intermittent conduction mode to obtain a plurality of comparison results, and drive the corresponding secondary freewheeling diode to turn on and off based on the plurality of comparison results, wherein the voltage values ​​of each of the reference voltages increase sequentially.

[0007] In some embodiments, the current sampling circuit includes a sampling module, a current mirror module, and a filtering module; The sampling module is connected to the first node and the logic driving circuit, and is used to receive the voltage of the first node, and convert the voltage of the first node into a sampling current and output it based on the first driving signal output by the logic driving circuit to drive the main power transistor. The current mirror module is connected to the sampling module and is used to mirror the sampling current, convert it into a sampling voltage, and output it. The filtering module is connected to the current mirror module and is used to filter the sampled voltage to obtain the first detection voltage.

[0008] In some embodiments, the sampling module includes a first operational amplifier, a first NMOS transistor, and a second NMOS transistor; The non-inverting input of the first operational amplifier is connected to the first node, the inverting input of the first operational amplifier is connected to the source of the first NMOS transistor and the drain of the second NMOS transistor, the gate of the first NMOS transistor is connected to the output of the first operational amplifier, the drain of the first NMOS transistor is connected to the input of the current mirror module, the gate of the second NMOS transistor is connected to the control terminal of the main power transistor, and the source of the second NMOS transistor is connected to ground.

[0009] In some embodiments, the current mirror module includes a first PMOS transistor, a second PMOS transistor, and a first resistor. The gate, drain, and second gate of the first PMOS transistor are connected together, and the drain of the first NMOS transistor is connected to the power supply voltage. One end of the first resistor is connected to the drain of the second PMOS transistor and serves as the output terminal of the current mirror module, which is connected to the filter module. The other end of the first resistor is connected to ground.

[0010] In some embodiments, the filtering module includes a second resistor and a first capacitor. One end of the second resistor is connected to the drain of the second PMOS transistor, and the other end of the second resistor serves as the output terminal of the current sampling circuit. One end of the first capacitor is connected to the other end of the second resistor, and the other end of the first capacitor is connected to ground.

[0011] In some embodiments, the logic driving circuit includes a plurality of first comparators and a plurality of AND gates; The non-inverting input of each of the first comparators is connected to the output of the current sampling circuit. The inverting input of one of the first comparators is connected to a reference voltage source that outputs the reference voltage. The output of one of the first comparators is connected to the first input of an AND gate. The second input of each AND gate is connected to the control terminal of the main freewheeling diode. The output of one AND gate is connected to the control terminal of a secondary freewheeling diode.

[0012] In some embodiments, the logic driving circuit further includes a main power transistor driving module, a main freewheeling transistor driving module, and multiple secondary freewheeling transistor driving modules; The input terminal of the main power transistor drive module is connected to the main power transistor control signal, and the output terminal is connected to the control terminal of the main power transistor. The input terminal of the main freewheeling tube drive module is connected to the freewheeling tube control signal, and the output terminal is connected to the control terminal of the main freewheeling tube. The input terminal of one of the secondary freewheeling diode driving modules is connected to the output terminal of one of the AND gates, and the output terminal of one of the secondary freewheeling diode driving modules is connected to the control terminal of each of the secondary freewheeling diodes.

[0013] In some embodiments, the zero-crossing detection circuit includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a second comparator. The source of the third PMOS transistor is connected to the source of the fifth PMOS transistor, which is connected to both ends of the freewheeling switch module. The drain of the third PMOS transistor is connected to the non-inverting input of the second comparator. The drain of the fifth PMOS transistor is connected to the source of the fourth PMOS transistor. The gate of the fifth PMOS transistor is connected to the gate of the main freewheeling transistor. The gates of the third PMOS transistor and the fourth PMOS transistor are connected to a detection drive signal. The drain of the fourth PMOS transistor is connected to the inverting input of the second comparator. The output of the second comparator is used to output the zero-crossing detection signal.

[0014] Secondly, embodiments of this application provide a chip including the voltage converter as described above, wherein the inductor of the voltage converter is externally located on the chip.

[0015] Thirdly, embodiments of this application provide an electronic device, including the voltage converter or the chip described above.

[0016] The advantages of the embodiments in this application compared with related technologies are: The voltage converter in this embodiment is a buck circuit or a boost circuit. The freewheeling switch of the voltage converter includes a main freewheeling diode and multiple secondary freewheeling diodes connected in parallel. The voltage converter also includes a current sampling circuit, a zero-crossing detection circuit, and a logic driving circuit. The current sampling circuit is used to detect a first detection voltage carrying information about the inductor current. The zero-crossing detection circuit obtains a zero-crossing detection signal based on the voltage across the freewheeling switch of the voltage converter. The logic driving circuit is used to control the number of secondary freewheeling diodes turned on based on the first detection voltage, and to control the freewheeling switch module and the main power transistor to be turned on alternately based on the zero-crossing detection signal. The number of secondary freewheeling diodes turned on is proportional to the magnitude of the first detection voltage. In this way, under low load conditions, the logic driving circuit can drive some or all of the secondary freewheeling diodes to turn off based on the first detection voltage carrying information about the inductor current and / or the output current. This increases the on-resistance of the freewheeling switch and correspondingly increases its on-voltage drop, thereby reducing the detection error caused by the offset voltage of the comparator in the zero-crossing detection circuit and greatly improving the accuracy of the zero-crossing detection threshold. Attached Figure Description

[0017] Figure 1 This is a circuit diagram of a voltage converter provided in the first embodiment of this application.

[0018] Figure 2 This is a circuit diagram of a voltage converter provided in the second embodiment of this application.

[0019] Figure 3 for Figure 1 The diagram shows a first type of logic drive circuit in a voltage converter.

[0020] Figure 4 for Figure 1 The circuit diagram shown is of the current sampling circuit in the voltage converter.

[0021] Figure 5 for Figure 4 The diagram shows the waveforms of the various electrical parameters of the current sampling circuit.

[0022] Figure 6 for Figure 1 The diagram shows a second type of circuit diagram for the logic drive circuit in the voltage converter.

[0023] Figure 7 for Figure 1 The diagram shows the operation of the voltage converter with segmented switching of each freewheeling diode.

[0024] Figure 8 for Figure 1 The diagram shows a circuit diagram of the zero-crossing detection circuit in a voltage converter. Detailed Implementation

[0025] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0026] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0027] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0028] Please see Figure 1 and Figure 2 This application provides a voltage converter, which includes a voltage conversion circuit 10. The voltage conversion circuit 10 includes an input terminal VDD and an output terminal V. OUTThe system includes a main power transistor (NFET), a freewheeling switch module 11, and an inductor L. The freewheeling switch module 11 includes a main freewheeling transistor (PFET0) and multiple secondary freewheeling transistors (PFET1~PFETn), which are connected in parallel. VDD is also used to represent the input voltage. OUT It is also used to indicate output voltage.

[0029] The main power transistor NFET, freewheeling switch module 11, and inductor L can form either a boost circuit or a buck circuit. For the boost circuit configuration, see [link to relevant documentation]. Figure 1 The first end of inductor L is connected to the input terminal VDD, and the second end of inductor L is connected to the first node LX. The freewheeling switch module 11 is connected between the first node LX and the output terminal VDD. OUT Between these terminals, the main power transistor NFET is connected between the first node LX and ground. For the configuration of a buck converter, see [link to relevant documentation]. Figure 2 The first terminal of the main power transistor NFET is connected to the input terminal VDD, and the second terminal of the main power transistor NFET is connected to the first node LX. The inductor L is connected between the first node LX and the output terminal VDD. OUT Between these points, the freewheeling switch module 11 is connected between the first node LX and ground. It is understood that the voltage converter can also be a boost-buck circuit, which will not be elaborated further here.

[0030] In the aforementioned voltage converter, it can typically operate in Continuous Conduction Mode (CCM), Boundary Conduction Mode (BCM), and Discontinuous Conduction Mode (DCM). In DCM and BCM modes, a zero-crossing detection circuit is needed to detect the voltage across the freewheeling switch module 11 to determine whether its current has crossed zero (since the current of the freewheeling switch module 11 is related to the inductor current, it can also reflect whether the inductor current has crossed zero). This controls the zero-current turn-on and turn-off of the main power transistor NFET and the freewheeling switch module 11, thereby achieving switching protection while improving the efficiency of the voltage converter. Typically, the zero-crossing detection circuit sets a detection threshold; if the detected current or voltage is below the detection threshold, it is considered that the current or voltage has crossed zero.

[0031] The voltage converter provided in this embodiment further includes a current sampling circuit 20, a zero-crossing detection circuit 30, and a logic driving circuit 40. The current sampling circuit 20 is connected to the first node LX and is used to obtain a first detection voltage V carrying inductor current information and / or output current information based on the electrical signal of the first node LX. SNSThe zero-crossing detection circuit 30 is connected to both ends of the freewheeling switch module 11, and the zero-crossing detection signal V is obtained based on the voltage across the freewheeling switch module 11. ZCD The logic drive circuit 40 is connected to the current sampling circuit 20, the zero-crossing detection circuit 30, the main power transistor NFET, and the freewheeling switch module 11. The logic drive circuit 40 is used to determine the current based on the first detected voltage V. SNS Control the number of PFET1~PFETn conducting, and based on the zero-crossing detection signal V ZCD The control module 11 and the main power transistor NFET are alternately turned on, wherein the number of secondary freewheeling transistors PFET1~PFETn turned on is related to the first detection voltage V. SNS The voltage value is directly proportional to the magnitude of the voltage.

[0032] Understandably, the current sampling circuit 20 samples the electrical signal of the first node LX, for example, sampling the inductor current, the current flowing through the main power transistor NFET, or the current of the freewheeling switch module 11, and based on the inductor current and the output current I of the voltage converter... LOAD The relationship between them can also be used to obtain the output current I. LOAD Therefore, the first detection voltage V SNS In addition to carrying inductor current information, it can also carry output current information.

[0033] For example, the maximum output current I of the voltage converter LOAD For example, the zero-crossing detection signal V of the zero-crossing detection circuit 30 is 5A. ZCD The threshold is set to 100mA. The output current I... LOAD With a current rating of 5A, the voltage converter operates, for example, in CCM mode. Considering conduction losses, the freewheeling switch module 11 can turn on the main freewheeling transistor PFET0 and all the auxiliary freewheeling transistors PFET1~PFETn. At this time, the on-resistance of the freewheeling switch module 11 is at its minimum, approximately 10mΩ. Assuming the zero-crossing detection signal V from the zero-crossing detection circuit 30 is... ZCD If the threshold is set to 100mA, then the voltage drop of the freewheeling switch module 11 is about 1mV.

[0034] If a low-load scenario is entered at this time, such as when the voltage converter is operating under DCM, the on-resistance of the freewheeling switch module 11 continues to remain at around 10mΩ. This is because the comparator of the zero-crossing detection circuit 30 has an offset voltage V. OS For example, offset voltage V OS =3sigma=6mV, at this time the offset voltage V OS The impact on the zero-crossing current detection of the freewheeling switch module 11 will be approximately 6mV / 10mΩ = 600 mA, which exceeds the zero-crossing detection signal V. ZCDThe threshold value can lead to errors in zero-crossing detection. In this case, compared to a 100mA zero-crossing detection signal V, ZCD The threshold, offset voltage V OS The zero-crossing detection signal V of the zero-crossing detection circuit 30 ZCD The threshold value has a significant impact, greatly affecting the zero-crossing detection signal V. ZCD The accuracy.

[0035] In response, according to the voltage converter provided in the embodiments of this application, its logic drive circuit 40, when the voltage converter enters a low-load scenario, i.e., at this time, the first detected voltage V... SNS The voltage drops, shutting off a portion of the secondary freewheeling transistors PFET1~PFETn, thus increasing the on-resistance of the freewheeling switch module 11, for example, to 100mΩ, resulting in a voltage drop of approximately 10mV. At this time, the offset voltage V... OS The impact on the zero-crossing current detection of the freewheeling switch module 11 will be approximately 6mV / 100mΩ = 60 mA. Compared to the detection threshold of 100mA, the offset voltage V OS The impact on the detection threshold of the zero-crossing detection circuit 30 is small, which greatly improves the accuracy of the zero-crossing detection threshold.

[0036] Understandably, when the voltage converter is not in a low-load scenario, it operates in CCM mode, where the main freewheeling transistor PFET0 and all auxiliary freewheeling transistors PFET1~PFETn in the freewheeling switch module 11 can be fully turned on to reduce conduction losses and improve voltage conversion efficiency. However, when entering a low-load scenario, i.e., when its output current I... LOAD / The inductor current is below a certain threshold, i.e., the first detection voltage V SNS When the voltage is below a certain value, the voltage converter will operate in DCM mode, and the logic drive circuit 40 will operate according to the first detected voltage V. SNS The magnitude of the inductor current is used to control the number of PFETs (PFET1-PFETn) that are turned on. Specifically, when the inductor current is below a certain threshold, the smaller the inductor current, the fewer PFETs (PFET1-PFETn) that are turned on. That is, the first detection voltage V... SNS Below a certain voltage value, the first detection voltage V SNS The smaller the value, the fewer the number of secondary freewheeling transistors PFET1~PFETn that are turned on. In this way, the number of secondary freewheeling transistors PFET1~PFETn that are turned on is managed in segments according to the inductor current with a certain threshold. During zero-crossing detection, the detection error of the zero-crossing detection circuit 30 is reduced by increasing the on-resistance of the freewheeling switch module 11.

[0037] Among them, the output current I at a certain threshold LOAD For example, it is 10% of the maximum output current I.LOAD The inductor current at a certain threshold is, for example, the maximum output current I. LOAD 10% of the corresponding inductor current; a first detection voltage V of a certain voltage value. SNS The output current I is the aforementioned threshold value. LOAD / The sampled and converted value of the inductor current. It is understandable that users can adjust the maximum output current I by 5% to 20% depending on the voltage converter or application scenario. LOAD Any value between these ranges can be configured as the output current I under low-load scenarios. LOAD The upper limit.

[0038] Please see Figure 1 In some application scenarios, the main power transistor control signal DRVN is sent to the first control signal input terminal of the logic drive circuit 40 through an external controller, and the freewheeling transistor control signal DRVP is sent to the second control signal input terminal of the logic drive circuit 40. The logic drive circuit 40 receives the main power transistor control signal DRVN and the freewheeling transistor control signal DRVP, outputs the first drive signal NGATE to drive the main power transistor NFET, and outputs the second drive signal PGATE0 to drive the freewheeling switch module 11 to conduct alternately.

[0039] Please see Figures 1 to 3 In some embodiments, the logic driving circuit 40 is configured with multiple comparators CMP1~CMPn, which are used to convert the first detection voltage V in discontinuous conduction mode. SNS Multiple comparison results are obtained by comparing with multiple reference voltages VREF1~VREFn, and the corresponding secondary freewheeling transistors PFET1~PFETn are turned on and off based on the multiple comparison results. The voltage values ​​of each reference voltage increase sequentially.

[0040] Each comparator CMP1~CMPn converts the first detected voltage V to V. SNS Each reference voltage VREF1~~VREFn is compared separately, and the first detection voltage V is... SNS When the voltage is greater than the corresponding reference voltage, the output drives the corresponding secondary freewheeling transistors PFET1~PFETn to turn on. Therefore, for example, if the voltage converter is operating in DCM mode, the first detected voltage V... SNS Below a certain voltage value, the number of conducting secondary freewheeling diodes PFET1~PFETn is related to the first detection voltage V. SNS The voltage value is directly proportional to the voltage level. The first detected voltage V SNS At a certain voltage value, all of the secondary freewheeling diodes PFET1~PFETn can be turned on, for example, when the voltage converter is operating in CCM mode.

[0041] Please see Figure 1 , Figure 2 and Figure 4 In some embodiments, the current sampling circuit 20 includes a sampling module 21, a current mirror module 22, and a filtering module 23.

[0042] Sampling module 21 is connected to the first node LX and the logic drive circuit 40. Sampling module 21 is used to input the voltage V of the first node LX. LX And based on the first drive signal NGATE output by the logic drive circuit 40 to turn on the main power transistor NFET, the voltage V of the first node LX is... LX Converted to sampling current I SNS1 And output. The current mirror module 22 is connected to the sampling module 21, and the current mirror module 22 is used to sample the current I. SNS1 The sampled voltage V2 is mirrored and converted into a sampled voltage V2 and then output. The filter module 23 is connected to the current mirror module 22, and the filter module 23 is used to filter the sampled voltage V2 to obtain the first detection voltage V. SNS .

[0043] In this embodiment, the current sampling circuit 20 samples the inductor current flowing through the main power transistor NFET proportionally when the main power transistor NFET is turned on, thereby obtaining the sampling current I. SNS1 Then sample the current I. SNS1 The current is passed through a current mirror and converted into a sampling voltage V2 carrying inductor current information; the sampling voltage V2 is then filtered by filter module 23 to obtain the first detection voltage V. SNS The first detection voltage V SNS It also carries output current information. This embodiment is based on a boost circuit to elaborate on the current sampling circuit 20. It is understood that in other embodiments, the voltage converter can also be a buck circuit, and the principle of the current sampling circuit 20 is similar to that in this embodiment. In other embodiments, the current sampling circuit 20 can be directly connected across the inductor L to sample the current, see [link to relevant documentation]. Figure 2 Similarly, it can be understood that in this embodiment, the current sampling circuit 20 performs current sampling when the main power transistor NFET is turned on; in other embodiments, the current sampling circuit 20 may also perform current sampling when the freewheeling switch module 11 is turned on.

[0044] Please see Figure 4In some embodiments, the sampling module 21 includes a first operational amplifier 211, a first NMOS transistor N1, and a second NMOS transistor N2. The non-inverting input of the first operational amplifier 211 is connected to the first node LX, the inverting input of the first operational amplifier 211 is connected to the source of the first NMOS transistor N1 and the drain of the second NMOS transistor N2, the gate of the first NMOS transistor N1 is connected to the output of the first operational amplifier 211, the drain of the first NMOS transistor N1 is connected to the input of the current mirror module 22, the gate of the second NMOS transistor N2 is connected to the control terminal of the main power transistor NFET and is driven by the first drive signal NGATE, and the source of the second NMOS transistor N2 is connected to ground.

[0045] Combination Figure 4 and Figure 5 Assume the connection node between the source of the first NMOS transistor N1 and the drain of the second NMOS transistor N2 is node V1, where V1 also represents the voltage at this node. The first operational amplifier 211 is used to clamp the voltages at the first node LX and node V1, making their voltages the same, i.e., V1 = V. LX .

[0046] Assume the on-resistance of the main power transistor NFET is R. NFET When the main power transistor NFET is turned on, the inductor current I flowing through the main power transistor NFET is... L = V LX / R NFET When the freewheeling switch module 11 is turned on, the main power transistor NFET is turned off, and the inductor current I flowing through the main power transistor NFET... L =0. The width-to-length ratio of the main power transistor NFET is 1 / k1 times the width-to-length ratio of the second NMOS transistor N2 (k1 < 1), that is, the on-resistance R of the second NMOS transistor N2 is 0. SNS =R NFET / k1. When the main power transistor NFET is turned on, the current I flowing through the second NMOS transistor N2 is... SNS1 =V1 / R SNS =k1* V LX / R NFET =k1*I L .

[0047] Please see Figure 4In some embodiments, the current mirror module 22 includes a first PMOS transistor P1, a second PMOS transistor P2, and a first resistor R1. The gate and drain of the first PMOS transistor P1, the gate of the second PMOS transistor P2, and the drain of the first NMOS transistor N1 are connected together. The sources of the first PMOS transistor P1 and the second PMOS transistor P2 are connected to a power supply voltage, such as the input terminal VDD. One end of the first resistor R1 is connected to the drain of the second PMOS transistor P2 and serves as the output terminal of the current mirror module 22, connected to the filter module 23. The other end of the first resistor R1 is connected to ground.

[0048] Combination Figure 4 and Figure 5 The current I flowing through the second NMOS transistor N2 SNS1 The mirror current I obtained after current mirror module 22 SNS2 =k1*k2*I L k2 is the mirror coefficient of the current mirror module 22. The mirrored current I... SNS2 The sampled voltage V2 is obtained by flowing through the first resistor R1. When the main power transistor NFET of the voltage converter is turned on, V2 = k1 * k2 * I L *R1, where R1 also represents the resistance value of the first resistor R1; when the freewheeling switch module 11 of the voltage converter is turned on, the sampling voltage V2=0.

[0049] Please see Figure 4 In some embodiments, the filter module 23 includes a second resistor R2 and a first capacitor C1. One end of the second resistor R2 is connected to the drain of the second PMOS transistor P2, and the other end of the second resistor R2 serves as the output terminal of the current sampling circuit 20. One end of the first capacitor C1 is connected to the other end of the second resistor R2, and the other end of the first capacitor C1 is connected to ground, thus forming a low-pass filter.

[0050] Combination Figure 4 and Figure 5 When the voltage converter operates in CCM mode, the switching cycle of the voltage converter is T, the conduction time of the main power transistor NFET is D*T, and the conduction time of the freewheeling switch module 11 is (1-D)*T, where D<1. The sampled voltage V2 passes through the filtering module 23 (i.e., the low-pass filter) to obtain the first detection voltage V. SNS =(1-D)*V2=(1-D)*k1*k2*I L *R1, in the voltage converter, due to the inductor current I L =I LOAD / (1-D), therefore V SNS =*k1*k2*I LOAD *R1, where I LOAD It also represents the output current I. LOADThe current value, or the current value of the load current.

[0051] Please continue reading. Figure 3 In some embodiments, the logic driving circuit 40 includes multiple first comparators CMP1~CMPn and multiple AND gates and1~andn; the non-inverting input of each first comparator CMP1~CMPn is connected to the output of the current sampling circuit 20, the inverting input of one first comparator CMP1~CMPn is connected to a reference voltage source for output reference voltages VREF1~VREFn, the voltage values ​​of each reference voltage VREF1~VREFn change sequentially, the output of one first comparator CMP1~CMPn is connected to the first input of one AND gate and1~andn, the second input of each AND gate and1~andn is connected to the control terminal of the main freewheeling transistor PFET0, and the output of one AND gate and1~andn is connected to the control terminal of a secondary freewheeling transistor PFET1~PFETn.

[0052] In this embodiment, the voltage values ​​of multiple reference voltages VREF1~VREFn increase sequentially. The second input terminals of each AND gate AND1~ANDn are connected to the second control signal input terminal of the logic drive circuit 40 through the control terminal of the main freewheeling transistor PFET0, and are controlled by the freewheeling transistor control signal DRVP. Each first comparator CMP1~CMPn converts the first detected voltage V SNS Compared with the corresponding reference voltages VREF1~VREFn, the first detection voltage V SNS When the voltage is greater than the corresponding reference voltage VREF1~VREFn, the output high level is sent to the first input terminal of the AND gate and1~andn connected to it. Then, the AND gate and1~andn outputs the corresponding secondary freewheeling control signal DRVP1~DRVPn, driving the corresponding secondary freewheeling transistors PFET1~PFETn to turn on.

[0053] Please see Figure 3 and Figure 6 In some embodiments, the logic driving circuit 40 further includes a main power transistor driving module 41, a main freewheeling transistor driving module 42, and multiple secondary freewheeling transistor driving modules 43_1 to 43_n.

[0054] The input terminal of the main power transistor driver module 41 is connected to the first control signal input terminal, and the main power transistor control signal DRVN is input. The output terminal of the main power transistor driver module 41 is connected to the control terminal of the main power transistor NFET. The main power transistor driver module 41 is used to output the first drive signal NGATE according to the main power transistor control signal DRVN to drive the main power transistor NFET to turn on or off.

[0055] The input terminal of the main freewheeling diode driver module 42 is connected to the second control signal input terminal, and the freewheeling diode control signal DRVP is input. The output terminal of the main freewheeling diode driver module 42 is connected to the control terminal of the main freewheeling diode PFET0. The main freewheeling diode driver module 42 is used to output the second drive signal PGATE0 according to the freewheeling diode control signal DRVP to drive the main freewheeling diode PFET0 to turn on or off.

[0056] The input of each secondary freewheeling diode driver module 43_1~43_n is connected to the output of an AND gate and1~andn, and the output of each secondary freewheeling diode driver module 43_1~43_n is connected to the control terminal of each secondary freewheeling diode PFET1~PFETn. The secondary freewheeling diode driver modules 43_1~43_n are used to output corresponding secondary freewheeling diode drive signals PGATE1~PGATEn based on the secondary freewheeling diode control signals DRVP1~DRVPn output from the AND gate and1~andn, thereby driving the corresponding secondary freewheeling diodes PFET1~PFETn to turn on or off.

[0057] Please see Figures 3 to 6 In some embodiments, the logic driving circuit 40 includes n comparators (including first comparator CMP1 to nth comparator CMPn), n AND gates (including first AND gate and1 to nth AND gate andn), a main power transistor driving module 41, a main freewheeling transistor driving module 42, and n secondary freewheeling transistor driving modules (including secondary freewheeling transistor driving modules 43_1 to 43_n).

[0058] The non-inverting input terminals of the first comparator CMP1 to the nth comparator CMPn are all connected to the output terminal of the current sampling circuit 20 and are connected to the first detection voltage V. SNS The inverting inputs of the first comparator CMP1 through the nth comparator CMPn are connected to the reference voltages VREF1 through VREFn, respectively. The outputs of the first comparator CMP1 through the nth comparator CMPn are connected to the first inputs of the first AND gate and1 through the nth AND gate andn, respectively. The second inputs of the first AND gate and1 through the nth AND gate andn are all connected to the freewheeling diode control signal DRVP. The outputs of the first AND gate and1 through the nth AND gate andn are connected to the inputs of the secondary freewheeling diode drive modules 43_1 through 43_n, respectively.

[0059] The working principle of the logic driver circuit 40 is as follows: the first comparator CMP1 to the nth comparator CMPn of the logic driver circuit 40 respectively convert the first detected voltage V SNSThe voltages VREF1 to VREFn are compared with multiple reference voltages. The comparison results are logically processed with the freewheeling control signal DRVP through the first AND gate and1 to the nth AND gate andn to obtain the secondary freewheeling control signals DRVP1 to DRVPn. Then, the corresponding secondary freewheeling drive signals PGATE1 to PGATEn are output through the secondary freewheeling drive modules 43_1 to 43_n to drive the corresponding secondary freewheeling transistors PFET1 to PFETn to turn on or off, thus completing the segmented switching function of the freewheeling switch module 11.

[0060] During the conduction period of the freewheeling switch module 11 of the voltage converter, the freewheeling control signal DRVP is high; during the de-conduction period of the freewheeling switch module 11 of the voltage converter, the freewheeling control signal DRVP is low. Taking the first secondary freewheeling transistor PFET1 as an example, when the first secondary freewheeling transistor PFET1 of the voltage converter is turned on, if the first detected voltage V... SNS If the voltage is greater than the first reference voltage VREF1, the first comparator CMP1 outputs a high level, the first secondary freewheeling diode control signal DRVP1 is high, and thus the corresponding secondary freewheeling diode drive signal PGATE1 (e.g., outputting a low level) is output to control the first secondary freewheeling diode PFET1 to turn on; if the first detection voltage V SNS When the voltage is less than the first reference voltage VREF1, the first comparator CMP1 outputs a low level, the first secondary freewheeling diode control signal DRVP1 goes low, and then stops outputting the corresponding secondary freewheeling diode drive signal PGATE1 (e.g., outputting a high level) to control the first secondary freewheeling diode PFET1 to turn off.

[0061] The input terminal of the main power transistor driver module 41 is connected to the first control signal input terminal of the logic driver circuit 40, and the output terminal of the main power transistor driver module 41 is connected to the main power transistor NFET. When the output first drive signal NGATE is high, the main power transistor NFET is turned on; when the first drive signal NGATE is low, the main power transistor NFET is turned off. The input terminal of the main freewheeling transistor driver module 42 is connected to the second control signal input terminal of the logic driver circuit 40, and the output terminal of the main freewheeling transistor driver module 42 is connected to the main freewheeling transistor PFET0. When the output second drive signal PGATE0 is low, the main freewheeling transistor PFET0 is turned on; when the second drive signal PGATE0 is high, the main freewheeling transistor PFET0 is turned off.

[0062] The input terminals of the secondary freewheeling diode driver modules 43_1~43_n are connected to the output terminals of gates and1~andn respectively, and the output terminals of the secondary freewheeling diode driver modules 43_1~43_n are connected to the secondary freewheeling diodes PFET1~PFETn respectively. When the secondary freewheeling diode drive signals PGATE1~PGATEn are low, the secondary freewheeling diodes PFET1~PFETn are turned on, and when the secondary freewheeling diode drive signals PGATE1~PGATEn are high, the secondary freewheeling diodes PFET1~PFETn are turned off.

[0063] Please see Figure 7 The first detection voltage V output by the current sampling circuit 20 SNS With output current LOAD They are directly proportional, with reference voltage VREF1 < VREF1 < ... < VREFn. As the output current I... LOAD The first detection voltage V increases continuously. SNS The value keeps increasing, the first detection voltage V SNS After comparison with reference voltages VREF1~VREFn, the drive signals PGATE1~PGATEn of the secondary freewheeling diodes are sequentially turned low, thereby controlling the secondary freewheeling diodes PFET1~PFETn to conduct sequentially, i.e., the output current I... LOAD The magnitude of the voltage is related to the number of PFET1~PFETn conducting in the secondary freewheeling diodes, and is also directly proportional to them.

[0064] It should be noted that the second drive signal PFET0 of the main freewheeling transistor PFET0 is not affected by the output current I. LOAD Control. Regardless of the output current I. LOAD Regardless of the change, when the freewheeling diode control signal DRVP is high, the second drive signal PGATE0 is always low, and the main freewheeling diode PFET0 is always on.

[0065] Please see Figure 1 and Figure 8In some embodiments, the zero-crossing detection circuit 30 includes a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a second comparator CMP. The sources of the third PMOS transistor P3 and the fifth PMOS transistor P5 are respectively connected to the two ends of the freewheeling switch module 11. The drain of the third PMOS transistor P3 is connected to the non-inverting input of the second comparator CMP, the drain of the fifth PMOS transistor P5 is connected to the source of the fourth PMOS transistor P4, and the gate of the fifth PMOS transistor P5 is connected to the gate of the main freewheeling transistor PFET0 and is controlled by the second drive signal PGATE0. The gates of the third PMOS transistor P3 and the fourth PMOS transistor P4 are connected to the detection drive signal VGGD. The drain of the fourth PMOS transistor is connected to the inverting input of the second comparator CMP, and the output of the second comparator CMP is used to output the zero-crossing detection signal VGGD. ZCD .

[0066] Under low load, output current I LOAD In very small cases, the voltage converter operates in DCM mode. At this time, only the main freewheeling transistor PFET0 is turned on. The zero-crossing detection circuit 30 detects the current flowing through the main freewheeling transistor PFET0, and the second comparator CMP compares the voltages V3 and V4 at the two input terminals to determine the zero-crossing detection signal V. ZCD The threshold. V3 = V LX -I LOAD *R PFET0 -I b *R P3 V4 = V LX -(R P5 +R P4 )*I b , where R P4 =R P3 I b R represents the current at the two input terminals of the second comparator CMP. PFET0 The on-resistance of the main freewheeling transistor PFET0, R P3 R3 is the on-resistance of the third PMOS transistor P3, and R5 is the on-resistance of the fifth PMOS transistor P5. When V3 = V4, the current through the freewheeling transistor PFET0 can be set as the zero-crossing detection signal V. ZCD The threshold, I ZCD =I b *R P5 / R PFET0 .

[0067] For example, the voltage converter in this embodiment can carry a large current of 5A. Considering the conduction loss, all the secondary freewheeling transistors PFET1~PFETn of the freewheeling switch module 11 are turned on. At this time, the on-resistance of the freewheeling switch module 11 is about 10mΩ, and the zero-crossing detection signal V ZCDThe threshold is set to approximately 100mA, and the output voltage V of the voltage converter is... OUT The voltage drop between the first node LX and the second comparator is approximately 1mV. If a low-load scenario is entered at this point, the on-resistance of the freewheeling switch module 11 remains at approximately 10mΩ, and the offset voltage V of the second comparator CMP... OS =3sigma=6mV, the voltage drop generated by the freewheeling switch module 11 is compared to the offset voltage V of the second comparator CMP. OS The value is too small, making its zero-crossing detection signal V... ZCD The threshold deviation is relatively large. Therefore, the voltage converter in this embodiment adopts segmented driving of the secondary freewheeling diodes PFET1~PFETn. For example, the second drive signal PGATE0 and the detection drive signal VGGD are both low, and the zero-crossing detection signal V... ZCD When the threshold is reached, only the main freewheeling transistor PFET0 is turned on. The on-resistance of the main freewheeling transistor PFET0 is 10 times the on-resistance of the freewheeling switch module 11, which is approximately 100mΩ, resulting in a voltage drop of approximately 10mV. Thus, the offset voltage of the second comparator CMP affects the zero-crossing detection signal V. ZCD The threshold has a relatively small impact, which greatly improves the accuracy of the zero-crossing detection threshold.

[0068] Secondly, embodiments of this application provide a chip including the voltage converter as described above, wherein the inductor L of the voltage converter is externally located on the chip.

[0069] Thirdly, embodiments of this application provide an electronic device, including the voltage converter or the chip described above.

[0070] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A voltage converter, characterized in that, The voltage converter includes an input terminal, an output terminal, a main power transistor, a freewheeling switch module, and an inductor. A first end of the inductor is connected to the input terminal, and a second end of the inductor is connected to a first node. The freewheeling switch module is connected between the first node and the output terminal, and the main power transistor is connected between the first node and ground. Alternatively, the first end of the main power transistor is connected to the input terminal, the second end of the main power transistor is connected to the first node, the inductor is connected between the first node and the output terminal, and the freewheeling switch module is connected between the first node and ground. The freewheeling switch module includes a main freewheeling transistor and multiple auxiliary freewheeling transistors connected in parallel. The voltage converter also includes a current sampling circuit, a zero-crossing detection circuit, and a logic driving circuit. The current sampling circuit is connected to the first node and is used to obtain a first detection voltage carrying inductor current information and / or output current information based on the electrical signal of the first node. The zero-crossing detection circuit is connected to both ends of the freewheeling switch module, and the zero-crossing detection signal is obtained based on the voltage across both ends of the freewheeling switch module. The logic driving circuit is connected to the current sampling circuit, the zero-crossing detection circuit, the main power transistor, and the freewheeling switch module. The logic driving circuit is used to control the number of the secondary freewheeling transistors turned on according to the first detection voltage, and to control the freewheeling switch module and the main power transistor to be turned on alternately according to the zero-crossing detection signal. The number of the secondary freewheeling transistors turned on is proportional to the voltage value of the first detection voltage.

2. The voltage converter as described in claim 1, characterized in that, The logic driving circuit is used to compare the first detected voltage with multiple reference voltages in the intermittent conduction mode to obtain multiple comparison results, and drive the corresponding secondary freewheeling tube to turn on and off based on the multiple comparison results, wherein the voltage values ​​of each reference voltage increase sequentially.

3. The voltage converter as described in claim 1 or 2, characterized in that, The current sampling circuit includes a sampling module, a current mirror module, and a filtering module; The sampling module is connected to the first node and the logic driving circuit, and is used to receive the voltage of the first node, and convert the voltage of the first node into a sampling current and output it based on the first driving signal output by the logic driving circuit to drive the main power transistor. The current mirror module is connected to the sampling module and is used to mirror the sampling current, convert it into a sampling voltage, and output it. The filtering module is connected to the current mirror module and is used to filter the sampled voltage to obtain the first detection voltage.

4. The voltage converter as described in claim 3, characterized in that, The sampling module includes a first operational amplifier, a first NMOS transistor, and a second NMOS transistor; The non-inverting input of the first operational amplifier is connected to the first node, the inverting input of the first operational amplifier is connected to the source of the first NMOS transistor and the drain of the second NMOS transistor, the gate of the first NMOS transistor is connected to the output of the first operational amplifier, the drain of the first NMOS transistor is connected to the input of the current mirror module, the gate of the second NMOS transistor is connected to the control terminal of the main power transistor, and the source of the second NMOS transistor is connected to ground.

5. The voltage converter as described in claim 4, characterized in that, The current mirror module includes a first PMOS transistor, a second PMOS transistor, and a first resistor. The gate, drain, and second gate of the first PMOS transistor are connected together. The source of the first PMOS transistor and the source of the second PMOS transistor are connected to the power supply voltage. One end of the first resistor is connected to the drain of the second PMOS transistor and serves as the output terminal of the current mirror module, which is connected to the filter module. The other end of the first resistor is connected to ground.

6. The voltage converter as described in claim 5, characterized in that, The filtering module includes a second resistor and a first capacitor. One end of the second resistor is connected to the drain of the second PMOS transistor, and the other end of the second resistor serves as the output terminal of the current sampling circuit. One end of the first capacitor is connected to the other end of the second resistor, and the other end of the first capacitor is connected to ground.

7. The voltage converter as described in claim 2, characterized in that, The logic driving circuit includes multiple first comparators and multiple AND gates; The non-inverting input of each of the first comparators is connected to the output of the current sampling circuit. The inverting input of one of the first comparators is connected to a reference voltage source that outputs the reference voltage. The output of one of the first comparators is connected to the first input of an AND gate. The second input of each AND gate is connected to the control terminal of the main freewheeling diode. The output of one AND gate is connected to the control terminal of a secondary freewheeling diode.

8. The voltage converter as described in claim 7, characterized in that, The logic driving circuit also includes a main power transistor driving module, a main freewheeling transistor driving module, and multiple secondary freewheeling transistor driving modules; The input terminal of the main power transistor drive module is connected to the main power transistor control signal, and the output terminal is connected to the control terminal of the main power transistor. The input terminal of the main freewheeling tube drive module is connected to the freewheeling tube control signal, and the output terminal is connected to the control terminal of the main freewheeling tube. The input terminal of one of the secondary freewheeling diode driving modules is connected to the output terminal of one of the AND gates, and the output terminal of one of the secondary freewheeling diode driving modules is connected to the control terminal of each of the secondary freewheeling diodes.

9. The voltage converter as claimed in claim 7, characterized in that, The zero-crossing detection circuit includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a second comparator. The source of the third PMOS transistor is connected to the source of the fifth PMOS transistor, which is connected to both ends of the freewheeling switch module. The drain of the third PMOS transistor is connected to the non-inverting input of the second comparator. The drain of the fifth PMOS transistor is connected to the source of the fourth PMOS transistor. The gate of the fifth PMOS transistor is connected to the gate of the main freewheeling transistor. The gates of the third and fourth PMOS transistors are connected to a detection drive signal. The drain of the fourth PMOS transistor is connected to the inverting input of the second comparator. The output of the second comparator is used to output the zero-crossing detection signal.

10. A chip, characterized in that, The voltage converter includes the voltage converter as described in any one of claims 1 to 9, wherein the inductor of the voltage converter is externally located on the chip.

11. An electronic device, characterized in that, Includes the voltage converter as described in any one of claims 1 to 9 or the chip as described in claim 10.

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