A dual-channel buck-boost control circuit based on peak current control low-ripple output and current protection in full duty cycle range

Abstract

The application discloses a dual-channel buck-boost control circuit based on peak current control low-ripple output and current protection in full duty cycle range, and belongs to the technical field of analog integrated circuit design, comprising a dual-channel DC-DC converter, each channel having a main power tube, a secondary power tube, an inductor and an off-chip sampling resistor; a current detection module generates a peak current reference voltage and a valley current reference voltage; an error amplification module generates an error signal Vcomp; a first comparator outputs a peak current detection signal; a second comparator outputs a valley current detection signal; a logic control module receives the above signals and a clock signal to generate a driving signal. The application realizes a low output voltage ripple <1% in the full duty cycle range, effectively limits the inductor current under the condition of small duty cycle, and prevents the power tube from burning out.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit design technology, specifically to a dual-channel buck-boost control circuit based on peak current control for low ripple output and current protection across the full duty cycle range. Background Technology

[0002] In the field of analog chip design, buck and boost topologies are two of the most basic DC-DC conversion forms. Peak current control mode is widely used due to its advantages such as ease of loop compensation and ability to achieve cycle-by-cycle fixed-frequency control. Designing a chip that can simultaneously support both buck and boost applications and employ peak current sensing is of great significance for simplifying system design and improving user-friendliness. Especially for solutions using off-chip power transistors, using sampling resistors for current sensing becomes a necessary implementation method for a dual-path buck-boost control approach based on peak current control with low ripple output and current protection across the entire duty cycle.

[0003] However, traditional peak current control modes have inherent limitations under extremely small duty cycle conditions. A detailed analysis follows: The instant the main power transistor turns on, parasitic inductances in the chip package and PCB board induce strong voltage ringing on the power supply, ground, and power transistor switching nodes. To ensure the peak current comparator is not erroneously toggled due to this ringing interference, the system typically sets a "blanking time." During this period, the comparator's output is forcibly invalidated. This blanking time, combined with subsequent propagation delays, drive turn-off times, and other factors, constitutes a minimum turn-on time for the main power transistor.

[0004] When the system application requires the main power transistor to have a conduction time shorter than the minimum turn-on time, the main power transistor will be forced to operate for that minimum time. This will cause peak current control to fail, specifically: the output voltage will rise uncontrollably and continue to rise, even until it reaches the overvoltage protection (OVP) threshold before being turned off, resulting in huge output voltage ripple; at the same time, the inductor current will accumulate over multiple switching cycles, far exceeding the set peak current protection threshold, posing a risk of burning out the power transistor.

[0005] To address the aforementioned issues, existing technologies offer a dual-path buck-boost control solution based on peak current control for low ripple output and current protection across the entire duty cycle. This solution detects the output signal Vcomp of the error amplifier. When Vcomp falls below a preset minimum value, the output voltage is determined to be too high. At this point, several switching cycles are skipped, the upper and lower transistors are turned off, and normal operation resumes after the output voltage decreases. The drawback of this solution is that the Vcomp signal, due to the characteristics of its compensation network, is a slowly changing signal. When it drops to its minimum value, the output voltage has already experienced a significant overshoot, resulting in still high output ripple and delayed current protection response.

[0006] Therefore, there is an urgent need for a new dual-path buck-boost control method based on low ripple output and current protection across the entire duty cycle range of peak current control. This method can effectively solve the technical problems of control failure, large output ripple, and current runaway under extremely small duty cycles without sacrificing the advantages of peak current control under normal operating conditions. Summary of the Invention

[0007] The purpose of this invention is to provide a dual-path buck-boost control circuit with low ripple output and current protection based on peak current control across the full duty cycle range. This aims to solve the problem that existing peak current control fails when the main power transistor's on-time is less than the minimum on-time, leading to increased output ripple and uncontrolled inductor current.

[0008] To achieve the above objectives, the present invention provides the following technical solution: a dual-channel buck-boost control circuit based on low ripple output and current protection across the entire duty cycle range controlled by peak current, the dual-channel buck-boost control circuit comprising: The first DC-DC converter and the second DC-DC converter, wherein each DC-DC converter includes a main power transistor, a secondary power transistor, an inductor L, and an off-chip sampling resistor Rsense connected in series with the inductor L; The current detection module is connected to both ends of the external sampling resistor Rsense and is used to amplify the voltage across the external sampling resistor Rsense into the peak current reference voltage Vsen_pk and the valley current reference voltage Vsen_valley. The error amplification module is used to generate an amplified error signal Vcomp based on the reference voltage Vref and the output feedback voltage Vfb. The first comparator (COMP1) is used to compare the peak current reference voltage with the error signal Vcomp and output the peak current detection signal Peak_trigger; The second comparator (COMP2) is used to compare the error signal Vcomp with the valley current reference voltage and output the valley current detection signal CONT; The logic control module receives the peak current detection signal Peak_trigger, the valley current detection signal CONT, and a periodic clock signal, and generates drive signals to control the main power transistor and the secondary power transistor in each channel. The logic control module is configured as follows: During a switching cycle, when the main power transistor is turned on, the peak current detection signal Peak_trigger is enabled to turn off the main power transistor; When the conduction time of the main power transistor is less than the system's predetermined minimum conduction time, the peak current control fails. At this time, during the conduction period of the secondary power transistor, the valley current detection signal CONT is enabled. During the conduction of the secondary power transistor, if the valley current detection signal CONT indicates that the current of inductor L has not yet dropped to the valley threshold set by the control voltage Vcomp, the secondary power transistor is kept on until the current of inductor L drops below the valley threshold, and then the next switching cycle is triggered.

[0009] Preferably, the logic control module includes: D flip-flop D1 is used to convert the clock signal into clock signals CLK_0 and CLK_180 with a phase difference of 180 degrees, which are respectively provided to the first DC-DC converter and the second DC-DC converter. For each DC-DC converter, there are D flip-flops D2, D flip-flops D3, D flip-flops D4, and SR flip-flops SR1. The set terminal S of the SR flip-flop SR1 is connected to the output terminal Q of the D flip-flop D4, the reset terminal R of the SR flip-flop SR1 is connected to the peak current detection signal Peak_trigger, and the output terminal Q of the SR flip-flop SR1 is used to generate the signal PH_ON to control the main power transistor and the secondary power transistor. The clock input of the D flip-flop D2 is connected to the clock signal CLK_0, the data input D of the D flip-flop D2 is connected to the valley current detection signal CONT, and the output Q of the D flip-flop D2 is connected to the data input D of the D flip-flop D4. The clock input of the D flip-flop D3 is connected to the clock signal CLK_0, the data input D of the D flip-flop D3 is connected to a high level, and the output Q of the D flip-flop D3 is used to generate a minimum conduction pre-trigger signal. The clock input of the D flip-flop D4 is connected to the result of the logic operation between the minimum conduction pre-trigger signal and the valley current detection signal CONT, and the output Q of the D flip-flop D4 is used to generate the drive signal CLK_DRV. The reset terminals of D flip-flops D2, D3, and D4 are all controlled by the falling edge pulse of the drive signal CLK_DRV.

[0010] Preferably, the current detection module includes an amplifier AMP1, the input terminal of which is connected to both ends of the external sampling resistor Rsense, for generating the peak current reference voltage Vsen_pk and the valley current reference voltage Vsen_valley; The error amplification module includes an error amplifier AMP2. The input terminals of the error amplifier AMP2 are respectively connected to the reference voltage Vref and the output voltage feedback signal Vfb, and its output terminal outputs the error signal Vcomp. The positive input of the first comparator (COMP1) is connected to the sum of the peak current reference voltage Vsen_pk and the slope compensation voltage, and its negative input is connected to the error signal Vcomp. The positive input of the second comparator (COMP2) is connected to the error signal Vcomp, and its negative input is connected to the valley current reference voltage Vsen_valley.

[0011] Preferably, the dual-channel buck-boost control circuit further includes a curve construction circuit, which ensures that under the same error signal Vcomp, the valley current setting value corresponding to the valley current detection signal CONT is always greater than the peak current setting value corresponding to the peak current detection signal Peak_trigger, thereby constructing a relationship in which the valley current-error signal curve is always above the peak current-error signal curve.

[0012] Preferably, the curve construction circuit includes: The positive current processing path includes PMOS transistor MP0, PMOS transistors MP1 and MP2 that mirror the current of PMOS transistor MP0, and a fixed bias current source Ioffset; The negative current processing path includes NMOS transistor MN0, NMOS transistors MN1 and MN2 mirroring the current of NMOS transistor MN0, and the fixed bias current source Ioffset; Wherein, the mirror ratio of PMOS transistor MP1 and PMOS transistor MP2 is set such that, under positive current conditions, the slope of the valley current reference voltage Vsen_valley changing with the error signal Vcomp is greater than the slope of the peak current reference voltage Vsen_pk changing with the error signal Vcomp. Furthermore, the mirror ratio of the NMOS transistor MN1 and the NMOS transistor MN2 is set such that, under negative current conditions, the slope of the valley current reference voltage Vsen_valley changing with the error signal Vcomp is less than the slope of the peak current reference voltage Vsen_pk changing with the error signal Vcomp.

[0013] Preferably, in the positive current processing path, the mirror image factor of the PMOS transistor MP1 is greater than that of the PMOS transistor MP2; in the negative current processing path, the mirror image factor of the NMOS transistor MN1 is greater than that of the NMOS transistor MN2.

[0014] Preferably, the dual-channel buck-boost control circuit is configured to operate in a bidirectional mode: When operating in boost mode, current flows from the first terminal to the second terminal. The first terminal is connected to the battery voltage, and the second terminal is connected to the bus voltage. The main power transistors are M0 and M2, and the secondary power transistors are M1 and M3. When operating in buck mode, current flows from the second terminal to the first terminal. The second terminal is connected to the bus voltage, and the first terminal is connected to the battery voltage. The main power transistors are M1 and M3, and the secondary power transistors are M0 and M2.

[0015] Preferably, the minimum conduction time is determined by the cumulative delay of the following factors: the first comparator (COMP1) being forced to zero within the shielding time after the main power transistor is turned on, the toggling delay of the first comparator (COMP1), the response time of the level shifter, and the turn-off delay of the drive transistor.

[0016] Preferably, the current detection module outputs the peak current reference voltage Vsen_pk during the main power transistor's conduction period and the valley current reference voltage Vsen_valley during the secondary power transistor's conduction period.

[0017] Compared with the prior art, the beneficial effects of the present invention are: 1. Achieve low output voltage ripple across the full duty cycle range; experimental data shows that with this invention, the output voltage ripple can always be controlled within 1%; while without this invention, the output ripple will be greater than 10% under extremely small duty cycle conditions.

[0018] 2. Provides effective current protection under extremely low duty cycle conditions; valley current control ensures that the upper limit of the inductor current is clamped within the designed safe value, avoiding the risk of inductor current runaway and burning out the power transistor in traditional solutions.

[0019] 3. The control logic is clear. The valley current control only intervenes automatically and smoothly when the peak control fails, without affecting the peak current control performance under normal operating conditions. Attached Figure Description

[0020] Figure 1 This is a block diagram of a dual-path buck-boost power stage in an embodiment of the present invention.

[0021] Figure 2 This is a circuit diagram of the full duty cycle external inductor current detection and control logic in an embodiment of the present invention.

[0022] Figure 3 This is a circuit structure diagram used to construct the relationship between Vcomp and Ipeak / Ivalley curves in an embodiment of the present invention.

[0023] Figure 4 This is a graph showing the relationship between the control voltage Vcomp and the peak current and valley current in an embodiment of the present invention.

[0024] Figure 5 This is a timing diagram of the control logic in an embodiment of the present invention, where (a) is the normal operating condition with a large duty cycle and (b) is the failure operating condition with a very small duty cycle.

[0025] Figure 6 This is a logic diagram illustrating the generation of the minimum conduction time of the main power transistor in an embodiment of the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0027] Figure 1 This is a block diagram of a dual-channel buck-boost power stage in an embodiment of the present invention. It includes two DC-DC converters. Current from left to right is for the boost converter (bst_select=1, vout selects the vbus voltage, and vbat is connected to the input power supply voltage). M0 / M2 are the primary power transistors, and M1 / M3 are the secondary power transistors. Current from right to left is for the buck converter (buck_select=1, vout selects the vbat voltage, and vbus is connected to the input power supply voltage). M1 / M3 are the primary power transistors, and M0 / M2 are the secondary power transistors. Both channels use an external circuit, Rsense, to sample the inductor current.

[0028] Figure 2 This is a circuit diagram of the full duty cycle external inductor current detection and control logic in an embodiment of the present invention.

[0029] Peak current detection control method: The input of amplifier AMP1 is the voltage across the external sampling resistor Rsense, which is amplified to the peak current reference voltage Vsen_pk. The input of amplifier AMP2 is the reference voltage Vref and the output feedback voltage Vfb, resulting in the amplified error signal Vcomp. The positive terminal voltage of comparator COMP1 is the sum of the peak current reference voltage and the stress compensation voltage, and the negative terminal is Vcomp. When the positive terminal voltage of COMP1 is greater than the negative terminal voltage, it indicates that the peak inductor current has reached the set value, at which point the main power transistor is turned off. Different Vcomp values ​​represent different peak inductor current values, and a curve of Vcomp versus peak current Ipeak can be plotted. Peak current detection is enabled when the main power transistor is operating and disabled when the main power transistor is turned off.

[0030] Dual-channel frequency signal: The main power transistor is turned on when the periodic frequency signal is high. The dual-channel structure has a common frequency signal CLK, which generates two frequency signals CLK_0 and CLK_180 with a 180-degree phase difference through a D flip-flop D1.

[0031] Valley current detection: The valley current reference voltage Vsen_valley is used at the output of amplifier AMP1. The positive input of comparator COMP2 is Vcomp, and the negative input is Vsen_valley. Only when the valley current of the inductor is less than a set value does the output CONT become 1, which serves as the input signal in the generation of the final frequency signal CLK_DRV sent to each channel. Different Vcomp values ​​represent different valley currents, and the curve of Vcomp versus valley current Ivalley can be plotted. Valley current detection is enabled when the secondary transistor is operating and disabled when the secondary transistor is off.

[0032] The SR trigger SR1 uses CLK_DRV as the set signal and Peak_trigger as the reset signal. CLK_DRV=1 and PH_ON=1 enable the main power transistor. Peak_trigger=1 and PH_ON=0 disable the main power transistor, and DH_ON=1 enable the secondary power transistor.

[0033] The generation of the frequency signal CLK_DRV for each channel is as follows: D flip-flop D2 outputs CLK_NORMAL to D flip-flop D4 if the CONT signal is 1 on the rising edge of CLK_0, causing D4 to output CL_DRV high. If CONT is 0 on the rising edge of CLK_0, CLK_NORMAL is 0. However, D flip-flop D3 outputs CLK_MINON_PRE as 1 at this time. When CONT changes from 0 to 1, CLK_MINON toggles to 1, and D4's output signal CLK_DRV also goes high, turning on the main power transistor. The reset signal for D2 / D3 / D4 is a pulse on the falling edge of CLK_DRV, ensuring operation in each cycle.

[0034] The curve of valley current versus Vcomp is always greater than that of peak current versus Vcomp. Under normal conditions where the minimum on-time of the main transistor is not triggered, peak current control is effective because the curve of valley current versus Vcomp is greater than that of peak current versus Vcomp. When the secondary power transistor is turned on, the output signal CONT of COMP2 immediately becomes 1. When the next cycle of the CLK_0 signal arrives, the CLK_DRV signal is output to turn on the main power transistor.

[0035] When the duty cycle is very small, the main power transistor needs to be on for a period shorter than the minimum on-time to ensure stable output voltage and current. However, due to the system's minimum on-time setting, the main power transistor must be on for a minimum on-time, at which point peak current control fails. Without frequency reduction, both inductor current and output voltage will drift high. When the secondary power transistor is on, with CLK_0 high (without frequency reduction), the inductor current has not yet dropped below the set valley current, and the comparator COMP2 output CONT is 0. Only when the valley current drops below the set value does CONT flip high. During this period, the secondary power transistor remains on until CONT=1, at which point it turns off and the main power transistor turns on to enter the next cycle. In this case of peak current failure, valley current control achieves frequency reduction, stabilizing inductor current and output ripple. The lower limit of the current is always limited by the valley current curve, so the main power transistor is only on for a minimum on-time, preventing the inductor current from running out of control and burning out the power transistor.

[0036] Figure 4 This is a graph showing the relationship between the control voltage Vcomp and the peak current and valley current in an embodiment of the present invention.

[0037] Specifically, the valley current versus Vcomp curve must always be greater than the peak current versus Vcomp curve. This is to ensure that valley current control only operates when peak current control fails. When Vcomp = 1.2V, both the peak and valley current curves are 0. When Vcomp > 1.2V, the slope of the valley current curve (Valley_curve) is greater than the slope of the peak current curve (Peak_curve). When Vcomp < 1.2V, the slope of the valley current curve (Valley_curve) is less than the slope of the peak current curve (Peak_curve).

[0038] To construct this curve, the circuit structure is as follows: Figure 3 As shown. MP0 equals the current Ipos, i.e., the positive current. Ipos equals (CSA-CSB) / R0 in buck mode and (CSB-CSA) / R0 in boost mode. MP1 and MP2 mirror the current of MP0, and Ioffset is a fixed current. When it is a positive current, the sampled peak current voltage equals Ioffset*R1+IMP1*R1, and the valley current voltage equals Ioffset*R2+IMP2*R2. Let R1=R2, the mirror factor of MP1 is greater than that of MP2, i.e., IMP1>IMP2, which satisfies the condition that the slope of the valley current with respect to Vcomp is greater than the slope of the peak current with respect to Vcomp when it is a positive current. When controlling peak current, DC point Vcomp = Vsen_pk; when controlling valley current, DC point Vcomp = Vsen_valley. Assuming the system adjusts Vcomp = V1, the corresponding peak current is Ipos1. Since IMP1 > IMP2, the valley current corresponding to Ipos2 will be greater than Ipos1 in the equilibrium state. Thus, the curves of peak and valley current versus Vcomp under positive current conditions can be constructed.

[0039] MN0 equals the current of Ineg, i.e., the negative current. Ineg equals (CSB-CSA) / R0 in buck mode and (CSA-CSB) / R0 in boost mode. MN1 and MN2 mirror the current of MN0, and Ioffset is a fixed current. When the current is positive, the sampled peak current voltage equals Ioffset*R1 + IMN2*R1, and the valley current voltage equals Ioffset*R2 + IMN1*R2. Let R1 = R2. The mirror factor of MN1 is greater than that of MN2, i.e., IMN1 > IMN2. This satisfies the condition that the slope of the valley current with respect to Vcomp is less than the slope of the peak current with respect to Vcomp when the current is negative. The principle is similar to that when the current is positive.

[0040] Figure 5 This is a timing diagram of the control logic in an embodiment of the present invention, where (a) is the normal operating condition with a large duty cycle and (b) is the failure operating condition with a very small duty cycle.

[0041] Figure 5 Part (a) shows a schematic diagram when the required main tube conduction time is greater than or equal to the minimum conduction time, i.e., when the duty cycle is large. Peak current control is effective. When the main tube is off and the secondary tube is on, the valley current detection current is less than the set valley current curve, and CONT=1. When CLK_0 is high in one cycle, CONT=1, CKK_MINTON_PRE=0, and the frequency output signal CLK_DRV of each branch is determined by CLK_0, maintaining the frequency unchanged by the period of CLK_0.

[0042] Figure 5 Part (b) shows a diagram where the required main transistor on-time is less than the minimum on-time, i.e., when the duty cycle is small. In this case, the main transistor's on-time is limited by the minimum on-time. Because the main transistor's on-time is a fixed value, peak current control fails. The output voltage and current will drift. When the secondary transistor is on, because the inductor current is very high, the secondary transistor needs to remain on until the inductor current is less than the set valley current value before CONT goes high. During this period, CLK_0 is a periodic signal, and several signals may have already been generated (depending on the period of CLK_0 and the on-time of the secondary transistor). When CLK_0 is high, CONT is always 0, CLK_NORMAL is always 0, and CLK_DRV is always 0. However, when the first CLK_0 is high, CLK_MINTON_PRE is set high through D3 until CONT=1. The output of the AND gate makes CLK_MINTON=1, and the frequency output signal CLK_DRV of each branch is determined by CLK_MINTON. The frequency is adaptively adjusted to the frequency required by the system to maintain the output voltage ripple and inductor current.

[0043] Figure 6 This is a logic diagram illustrating the minimum on-time of the main power transistor in an embodiment of the present invention. When the main power transistor is turned on, the voltage across the detection resistor at the power supply, ground, and main / secondary transistor connection points will ring. The comparator COMP1 will erroneously toggle during the ringing time, affecting system operation. Therefore, a blanking time is set after the main power transistor is turned on, forcing the output signal Peak_trigger of COMP1 to be 0. This time, plus the toggle time of COMP1, the level shifter, and the turn-off delay of the driver transistor, forces the main power transistor to be turned on for a minimum time. Even if the system requires the main power transistor to be on for less than this minimum time, the main power transistor will still be on for this minimum time.

[0044] This invention achieves low output voltage ripple across the entire duty cycle range. Experimental data shows that, with this invention, the output voltage ripple can always be controlled within 1%; while without this invention, the output ripple can exceed 10% under extremely small duty cycle conditions.

[0045] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0046] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A dual-channel buck-boost control circuit based on low ripple output and current protection across the entire duty cycle range under peak current control, characterized in that, The dual-channel buck-boost control circuit includes: The first DC-DC converter and the second DC-DC converter, wherein each DC-DC converter includes a main power transistor, a secondary power transistor, an inductor L, and an off-chip sampling resistor Rsense connected in series with the inductor L; The current detection module is connected to both ends of the external sampling resistor Rsense and is used to amplify the voltage across the external sampling resistor Rsense into the peak current reference voltage Vsen_pk and the valley current reference voltage Vsen_valley. The error amplification module is used to generate an amplified error signal Vcomp based on the reference voltage Vref and the output feedback voltage Vfb. A first comparator is used to compare the peak current reference voltage with the error signal Vcomp, and output a peak current detection signal Peak_trigger; The second comparator is used to compare the error signal Vcomp with the valley current reference voltage and output the valley current detection signal CONT; The logic control module receives the peak current detection signal Peak_trigger, the valley current detection signal CONT, and a periodic clock signal, and generates drive signals to control the main power transistor and the secondary power transistor in each channel. The logic control module is configured as follows: During a switching cycle, when the main power transistor is turned on, the peak current detection signal Peak_trigger is enabled to turn off the main power transistor; When the conduction time of the main power transistor is less than the system's predetermined minimum conduction time, the peak current control fails. At this time, during the conduction period of the secondary power transistor, the valley current detection signal CONT is enabled. During the conduction of the secondary power transistor, if the valley current detection signal CONT indicates that the current of inductor L has not yet dropped to the valley threshold set by the control voltage Vcomp, the secondary power transistor is kept on until the current of inductor L drops below the valley threshold, and then the next switching cycle is triggered.

2. The dual-channel buck-boost control circuit according to claim 1, characterized in that, The logic control module includes: D flip-flop D1 is used to convert the clock signal into clock signals CLK_0 and CLK_180 with a phase difference of 180 degrees, which are respectively provided to the first DC-DC converter and the second DC-DC converter. For each DC-DC converter, there are D flip-flops D2, D flip-flops D3, D flip-flops D4, and SR flip-flops SR1. The set terminal S of the SR flip-flop SR1 is connected to the output terminal Q of the D flip-flop D4, the reset terminal R of the SR flip-flop SR1 is connected to the peak current detection signal Peak_trigger, and the output terminal Q of the SR flip-flop SR1 is used to generate the signal PH_ON to control the main power transistor and the secondary power transistor. The clock input of the D flip-flop D2 is connected to the clock signal CLK_0, the data input D of the D flip-flop D2 is connected to the valley current detection signal CONT, and the output Q of the D flip-flop D2 is connected to the data input D of the D flip-flop D4. The clock input of the D flip-flop D3 is connected to the clock signal CLK_0, the data input D of the D flip-flop D3 is connected to a high level, and the output Q of the D flip-flop D3 is used to generate a minimum conduction pre-trigger signal. The clock input of the D flip-flop D4 is connected to the result of the logic operation between the minimum conduction pre-trigger signal and the valley current detection signal CONT, and the output Q of the D flip-flop D4 is used to generate the drive signal CLK_DRV. The reset terminals of D flip-flops D2, D3, and D4 are all controlled by the falling edge pulse of the drive signal CLK_DRV.

3. The dual-channel buck-boost control circuit according to claim 1, characterized in that, The current detection module includes an amplifier AMP1, the input of which is connected to both ends of the external sampling resistor Rsense, and is used to generate the peak current reference voltage Vsen_pk and the valley current reference voltage Vsen_valley. The error amplification module includes an error amplifier AMP2. The input terminals of the error amplifier AMP2 are respectively connected to the reference voltage Vref and the output voltage feedback signal Vfb, and its output terminal outputs the error signal Vcomp. The positive input terminal of the first comparator is connected to the sum of the peak current reference voltage Vsen_pk and the slope compensation voltage, and its negative input terminal is connected to the error signal Vcomp; The positive input of the second comparator is connected to the error signal Vcomp, and its negative input is connected to the valley current reference voltage Vsen_valley.

4. The dual-channel buck-boost control circuit according to claim 1, characterized in that, It also includes a curve construction circuit, which ensures that, under the same error signal Vcomp, the valley current setting value corresponding to the valley current detection signal CONT is always greater than the peak current setting value corresponding to the peak current detection signal Peak_trigger, thereby constructing a relationship in which the valley current-error signal curve is always above the peak current-error signal curve.

5. The dual-channel buck-boost control circuit according to claim 4, characterized in that, The curve construction circuit includes: The positive current processing path includes PMOS transistor MP0, PMOS transistors MP1 and MP2 that mirror the current of PMOS transistor MP0, and a fixed bias current source Ioffset; The negative current processing path includes NMOS transistor MN0, NMOS transistors MN1 and MN2 mirroring the current of NMOS transistor MN0, and the fixed bias current source Ioffset; Wherein, the mirror ratio of PMOS transistor MP1 and PMOS transistor MP2 is set such that, under positive current conditions, the slope of the valley current reference voltage Vsen_valley changing with the error signal Vcomp is greater than the slope of the peak current reference voltage Vsen_pk changing with the error signal Vcomp. Furthermore, the mirror ratio of the NMOS transistor MN1 and the NMOS transistor MN2 is set such that, under negative current conditions, the slope of the valley current reference voltage Vsen_valley changing with the error signal Vcomp is less than the slope of the peak current reference voltage Vsen_pk changing with the error signal Vcomp.

6. The dual-channel buck-boost control circuit according to claim 5, characterized in that, In the positive current processing path, the mirror image factor of PMOS transistor MP1 is greater than that of PMOS transistor MP2; in the negative current processing path, the mirror image factor of NMOS transistor MN1 is greater than that of NMOS transistor MN2.

7. The dual-channel buck-boost control circuit according to claim 1, characterized in that, The dual-channel buck-boost control circuit is configured for bidirectional operation. When operating in boost mode, current flows from the first terminal to the second terminal. The first terminal is connected to the battery voltage, and the second terminal is connected to the bus voltage. The main power transistors are M0 and M2, and the secondary power transistors are M1 and M3. When operating in buck mode, current flows from the second terminal to the first terminal. The second terminal is connected to the bus voltage, and the first terminal is connected to the battery voltage. The main power transistors are M1 and M3, and the secondary power transistors are M0 and M2.

8. The dual-channel buck-boost control circuit according to claim 1, characterized in that, The minimum conduction time is determined by the cumulative delay of the following factors: the first comparator being forced to zero within the shielding time after the main power transistor is turned on, the toggle delay of the first comparator, the response time of the level shifter, and the turn-off delay of the drive transistor.

9. The dual-channel buck-boost control circuit according to claim 1, characterized in that, The current detection module outputs the peak current reference voltage Vsen_pk during the main power transistor's conduction period and the valley current reference voltage Vsen_valley during the secondary power transistor's conduction period.

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