A three-path synthesized deep back-off digital power amplifier

Abstract

The application discloses a three-path synthesized deep backoff digital power amplifier, which comprises a digital decoding circuit, a frequency division circuit, a switching power amplifier circuit and an output matching network. The frequency division circuit divides the input radio frequency signal to generate a fundamental wave and a three-frequency division square wave signal. The digital decoding circuit controls the working state and working frequency of the power amplifier according to an input amplitude control signal. The switching power amplifier comprises three groups of differential pairs with equal power ratios and adopts a voltage type D class digital amplification structure. The output matching network is internally provided with a three-path power synthesis transformer, which completes matching and three-path differential signal synthesis output. In the 0dB-9.5dB backoff interval, tuning backoff is realized through frequency division driving. In the 9.5dB-15.5dB deep backoff interval, Doherty mode backoff is realized through load modulation. Through the combination of three-path synthesis and hybrid backoff mechanism, the working efficiency of the deep backoff area of the power amplifier is significantly improved under a compact area.

Description

Technical Field

[0001] This invention relates to the field of radio frequency integrated circuit technology, and more specifically, to a three-channel synthesized deep back-off digital power amplifier. Background Technology

[0002] With the rapid development of wireless communication technology, modern communication systems place higher performance demands on radio frequency (RF) transmitters, such as high efficiency, high output power, and wide dynamic range. As a key module in RF transmitters, the performance of the power amplifier (PA) directly affects the power efficiency, linearity, and energy utilization efficiency of the entire system. Therefore, maintaining high efficiency over a wide power back-off range has become an important research direction for RF power amplifiers.

[0003] Traditional analog power amplifiers typically employ Class-AB, Class-F, and Doherty architectures to improve efficiency. Among these, the Doherty power amplifier, through a load modulation mechanism between the main and auxiliary amplifiers, maintains high efficiency near a certain power back-off point, and is therefore widely used in communication systems. However, traditional Doherty power amplifiers usually operate in analog mode, placing high demands on device linearity, bias circuitry, and analog control precision. Furthermore, they still suffer from efficiency degradation in the deep power back-off region.

[0004] In recent years, with the development of CMOS technology, digital power amplifiers (DPAs) have gradually become a research hotspot. Based on the research in "S.-M. Yoo, JS Walling, EC Woo, B. Jann and DJAllstot, 'A Switched-Capacitor RF Power Amplifier,'" in IEEE Journal of Solid-State Circuits, vol. 46, no. 12, pp. 2977-2987, Dec. 2011, some researchers have proposed switched-capacitor power amplifiers (SCPA). These amplifiers amplify radio frequency signals by digitally controlling the switching states of transistors to charge and discharge the load capacitor. Compared with traditional analog power amplifiers, switched-capacitor digital power amplifiers have advantages such as simple structure, ease of integration with digital circuits, and higher efficiency. According to the research "A. Zhang and MS-W. Chen, 'A Subharmonic Switching Digital Power Amplifier for Power Back-Off Efficiency Enhancement,'" in IEEE Journal of Solid-State Circuits, vol. 54, no. 4, pp. 1017-1028, April 2019," some researchers have proposed using frequency division of the input PM signal to achieve a 9.5dB back-off for back-off design. According to the research "Y. Yin, L. Xiong, Y. Zhu, B. Chen, H. Min and H. Xu, 'A Compact Dual-Band Digital Polar Doherty Power Amplifier Using Parallel-Combining Transformer,'" in IEEE Journal of Solid-State Circuits, vol. 54, no. 6, pp. 1575-1585, June 2019," some researchers have proposed incorporating Doherty back-off technology into the SCPA architecture to achieve a 6dB back-off efficiency enhancement.However, most existing technologies employ a two-way power combining structure, which is relatively simple. Furthermore, switched-capacitor digital power amplifiers still face issues of efficiency degradation and low structural utilization in the power back-off region, especially under deep back-off conditions, where overall efficiency is difficult to maintain at a high level. In addition, traditional digital power amplifiers typically use a single drive frequency, limiting their ability to optimize efficiency at different power back-off points.

[0005] Therefore, how to design a digital power amplifier structure that can maintain high efficiency over a wide power back-off range while also being simple in structure and easy to integrate has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] To overcome the problems of efficiency degradation and low utilization of power combining structures in existing digital power amplifiers under deep power back-off conditions, this invention provides a three-channel combined deep back-off digital power amplifier. This power amplifier achieves efficient power combining of the three power amplification units through the design of a three-in-one parallel combining transformer (PCT), and combines frequency division control with load modulation for power back-off, maintaining high efficiency at multiple power back-off points, thereby improving the overall performance of the digital power amplifier over a wide power dynamic range.

[0007] The present invention is achieved by at least one of the following technical solutions.

[0008] A three-channel synthesized deep back-off digital power amplifier includes a digital decoding circuit, a frequency divider circuit, a switching power amplifier circuit, and an output matching network. The output terminals of the digital decoding circuit and the frequency divider circuit are both connected to the switching power amplifier circuit, and the switching power amplifier circuit is connected to the output matching network. The phase control word output by the digital decoding circuit selects the square wave signal output by the frequency divider circuit. The selected square wave signal is logically ANDed with the current amplitude control word, thereby changing the driving frequency and switching state of the switching power amplifier circuit and realizing power back-off control.

[0009] Furthermore, the digital decoding circuit includes a classic serial-to-parallel converter circuit of a digital IC and a decoder. The input signal first passes through the classic serial-to-parallel converter circuit of the digital IC to obtain an amplitude control signal. The decoder generates corresponding amplitude control words and phase control words according to the input amplitude control signal, which are used to control the switching power amplifier circuit and realize output adjustment at different power levels.

[0010] Furthermore, the frequency divider circuit includes a single-ended to differential converter and a three-way frequency divider module. The single-ended to differential converter first converts the input RF PM signal into a differential RF signal, and the output is a differential RF signal. The differential RF signal then enters the three-way frequency divider module to generate multiple fundamental frequency signals and frequency divider signals. The fundamental frequency signals and frequency divider signals are used to realize drive control under different power back-off modes.

[0011] Furthermore, the frequency divider module includes a multi-stage cascaded D flip-flops and logic gates, using a radio frequency signal as the flip-flop clock.

[0012] Furthermore, the switching power amplifier circuit includes multiple differential pairs with identical structures and a multiplexer. The multiplexer is input to the phase control word generated by the decoder of the digital decoding circuit, which is used to select the driving signal generated by the frequency divider circuit. The selected driving signal is then ANDed with the amplitude control word and finally input to the differential pair.

[0013] Furthermore, each differential pair is constructed using a circuit with multiple amplifier tubes connected in series with capacitors at one end, and the amplifier tubes adopt a Class D amplifier structure.

[0014] Furthermore, the output matching network adopts a parallel transformer structure to synthesize the multiple differential power signals output by the switching power amplifier circuit into a single-ended output signal and realize the impedance transformation function.

[0015] Furthermore, the transformer structure is combined into multiple sets of differential input terminals and a set of single-ended output terminals coupled together, and a filter capacitor is connected in series to achieve the parallel combination of multiple power sources.

[0016] Furthermore, in deep power back-off mode, the switching power amplifier circuit achieves Doherty power back-off through load modulation between the main amplifier and the auxiliary amplifier.

[0017] Furthermore, the main amplifier is the positive power amplifier for each differential pair, and the auxiliary amplifier is the negative power amplifier for each differential pair.

[0018] Compared with the prior art, the present invention has the following beneficial effects: This invention achieves efficient power combining of three power amplifier units by designing a three-in-one parallel transformer, improving power combining efficiency and area utilization. Simultaneously, it implements tuned power back-off through frequency division control, maintaining high efficiency in the medium power back-off region. Furthermore, it introduces a Doherty load modulation mechanism in the deep power back-off region, ensuring the power amplifier maintains high efficiency across a wide power back-off range. Therefore, this invention significantly improves the efficiency performance of digital power amplifiers over a wide dynamic range and offers advantages such as simple structure, ease of integration, and suitability for CMOS process implementation. Attached Figure Description

[0019] Figure 1 This embodiment provides an overall structural block diagram of a three-channel synthesized deep back-off digital power amplifier; Figure 2 This is a schematic diagram of the digital decoding circuit provided in this embodiment; Figure 3 This is a schematic diagram of the circuit structure of the frequency divider circuit provided in this embodiment; Figure 4 This is a schematic diagram of the frequency divider module in the frequency divider circuit provided in this embodiment; Figure 5 This is a schematic diagram of the circuit structure of the switching power amplifier circuit provided in this embodiment; Figure 6 This is a schematic diagram of the differential pair structure in the switching power amplifier circuit provided in this embodiment; Figure 7 This is a schematic diagram of the structure of the three-in-one parallel composite transformer (PCT) provided in this embodiment; Figure 8 This is a schematic diagram of the power amplifier's operating state in fallback mode provided in this embodiment; Figure 9 The simulation results curves showing the relationship between the output power and efficiency of the power amplifier provided in this embodiment are shown. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort should fall within the scope of protection of the present invention.

[0021] The terms "first," "second," "third," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0022] The present invention will be further explained and described below with reference to the accompanying drawings and embodiments.

[0023] like Figure 1As shown, this invention provides a three-channel synthesized deep back-off digital power amplifier, which mainly includes a digital decoding circuit 10, a frequency divider circuit 20, a switching power amplifier circuit 30, and an output matching network 40. The output terminals of the digital decoding circuit 10 and the frequency divider circuit 20 are both connected to the switching power amplifier circuit 30, and the switching power amplifier circuit 30 is connected to the output matching network 40.

[0024] like Figure 2 As shown, the digital decoding circuit 10 includes a classic serial-to-parallel converter 110 of a digital IC and a decoder 120. The input modulation signal AM_S first passes through the classic serial-to-parallel converter 110 of the digital IC to obtain a 10-bit parallel signal of amplitude control signal AM_D. The decoder 120 generates corresponding amplitude control words and phase control words according to the input amplitude control signal AM_D, and controls the switching power amplifier circuit 30 to achieve output adjustment at different power levels.

[0025] The amplitude control signal AM_D contains the amplitude information of the signal, and the clock signal frequency is 200MHz.

[0026] As shown in Table 3, AM in the figure represents the output signal AM_D of the serial-to-parallel converter 110. Generally, AM is a 10-bit or higher binary parallel signal. For ease of explanation, AM in the figure is a 4-bit parallel signal. A1, A2, and A2 in the figure represent a group of single-ended PA units. They are independently controlled by three signals and together form a group of single-ended units. The difference between A1 and A2 is the output voltage, which is achieved by changing the size (W / L) of the amplifier tube. The output voltage of A1: the output voltage of A2 is 1:2. At the same time, B1, B2, and B2 are a group of differential terminals, which together with A1, A2, and A2 form a differential pair. In actual circuits, each group of single-ended units contains hundreds of PA units, and the size of the amplifier tube will have more complex ratios. For ease of understanding, the figure uses 6 PA units as an example. The signal input terminal in the figure contains three types of signals. "1" indicates that the PA unit is driven by the fundamental frequency square wave signal. At this time, the amplitude control word corresponding to the PA unit is state 1, and the phase control word is state 2. 1. “1 / 3” indicates that the PA unit is driven by a three-way square wave signal. In this case, the amplitude control word corresponding to the PA unit is state 1 and the phase control word is state 0. “0” indicates that the PA unit is grounded and does not output. In this case, the amplitude control word corresponding to the PA unit is state 0 and the phase control word is state 0. As shown in the figure, when AM = “1111”, all PA units operate under the fundamental frequency square wave, i.e., in saturated output. When AM = “0101”, all PA units operate under the three-way square wave. When AM = “0000”, all PA units are grounded and stop working, i.e., in the off state. The decoder 120 of the actual digital circuit is more complex due to the scale of the circuit. Digital IC tools are used to implement the decoding function of the decoder 120 according to the actual circuit requirements.

[0027] Table 1 Truth Table of Decoders in Digital Decoding Circuits

[0028] like Figure 3As shown, the frequency divider circuit 20 includes a single-ended to differential converter 220 and a three-way frequency divider module 210. The single-ended to differential converter 220 is connected to a frequency generator, which generates corresponding 2.4GHz and 0.8GHz signals. The input signal PM (phase modulation signal) of the single-ended to differential converter 220 has a frequency of 2.4GHz and carries the phase information of the signal. The single-ended to differential converter 220 first performs single-ended to differential conversion on the input RF PM signal. The single-ended to differential converter 220 uses a traditional non-overlapping (two-phase non-overlapping clock generation circuit), and the output is differential RF signals PM+ and PM-. The differential RF signals PM+ and PM- then enter the three-way frequency divider module 210 to generate multiple fundamental frequency signals (A+, A-, B+, B-, C+, C-) and frequency divider signals (a+, a-, b+, b-, c+, c-). In this embodiment, the fundamental frequency signal and the three-way frequency divider signal generated by the frequency divider circuit 20 can be used to implement drive control under different power back-off modes. When the system is in different power back-off states, the digital decoding circuit 10 can select square wave signals of different frequencies output by the frequency divider circuit 20 in the switching power amplifier circuit 30 by the phase control word. The square wave signal and the amplitude control word are logically ANDed to change the drive frequency and switching state of the switching power amplifier circuit 30, thereby realizing power back-off control.

[0029] like Figure 4As shown, the frequency divider module 210 includes multi-stage cascaded D flip-flops and logic gates, using radio frequency signals PM+ and PM- as the flip-flop clocks. In one embodiment, the multi-stage cascaded D flip-flops employ six D flip-flops, with the bottom three being FF1, FF2, and FF3, forming a synchronous frequency divider counter. The clock inputs of all flip-flops are uniformly connected to a 2.4GHz positive-phase differential clock PM+. The D input of FF1 is the AND operation of its own inverted output Q1 and the inverted output Q2 of FF2. The non-inverted output of FF1... Output OUT1 is connected to the D terminal of FF2, and the non-inverting output of FF2 is connected to the D terminal of FF3, forming a state closed loop. A complete cycle is completed every 3 PM+ clock cycles. Therefore, the frequency of the OUT1, OUT3, and OUT5 signals output by FF1 is 1 / 3 of the input clock, i.e., 2.4GHz / 3 = 0.8GHz. The phases of the three signals are successively separated by 1 PM+ clock cycle, corresponding to a 120° phase difference of the 0.8GHz signal, generating three reference phase signals of 0°, 120°, and 240°. The clock terminals of the three D flip-flops FF4, FF5, and FF6 in the top row are all connected to a 2.4GHz inverted differential clock PM-. The D terminal of FF4 is connected to the output OUT1 of FF1, the D terminal of FF5 is connected to the output OUT3 of FF2, and the D terminal of FF6 is connected to the output OUT5 of FF3. The rising edge of PM- falls exactly in the middle of the two rising edges of PM+, and is 0.5 2.4GHz clock cycles later than the rising edge of PM+, which corresponds to the 60° fixed phase offset of the 0.8GHz signal. The three flip-flops in the top row use the PM- clock to synchronously sample the OUT1, OUT3, and OUT5 outputs of the bottom row divided by 3, and output OUT2, OUT4, and OUT6. The final result is six 0.8GHz square wave signals, all with a duty cycle of 1 / 3 and phases that are precisely staggered by 60°, fully covering the entire cycle from 0° to 360°: OUT1: 0°, OUT2: 60°, OUT3: 120°, OUT4: 180°, OUT5: 240°, OUT6: 300°.

[0030] a+, a- (0° phase differential pair): a+ is generated by ANDing OUT1 (0°) and OUT2 (60°), with a duty cycle of 50% and a phase of 0°; a- is generated by ANDing OUT4 (180°) and OUT5 (240°), with a duty cycle of 50% and a phase of 180°. Together, they form a complete 0° differential output. b+, b- (120° phase differential pair): b+ is generated by ANDing OUT2 (120°) and OUT3 (180°), with a duty cycle of 50% and a phase of 120°; b- is generated by ANDing OUT1 (0°) and OUT6 (300°), with a duty cycle of 50% and a center phase of -60°. Together, they form a complete 120° differential output. c+, c- (240° phase differential pair): c+ is generated by ANDing OUT5 (240°) and OUT6 (300°), with a duty cycle of 50% and a phase of 240°; c- is generated by ANDing OUT2 (60°) and OUT3 (120°), with a duty cycle of 50% and a phase of 60°. Together, they form a complete 240° differential output. This ensures that the 0.8GHz signals of the three signals 1+, 1-, 2+, 2-, 3+, and 3- are ultimately canceled out by phase difference during the synthesis process, resulting in a final output signal of only the 2.4GHz fundamental frequency.

[0031] PM+ and PM- are delayed to obtain signals A+, B+, C+ and differential signals A-, B-, C-, whose frequencies remain consistent with PM+ and PM-. The purpose of the delay is to align with the frequency division signals.

[0032] like Figure 5 As shown, the switching power amplifier circuit 30 includes three differential pairs (differential pair one 310, differential pair two 320, and differential pair three 330) and multiplexers (340, 350, 360, 370, 380, and 390). Each differential pair is constructed using a circuit with 55 amplifier tubes connected in series with capacitors at one end, and the amplifier tubes adopt a Class D amplifier structure.

[0033] The multiplexer inputs a multi-bit phase control word generated by the decoder 120 of the digital decoding circuit, which is used to select the drive signal generated by the frequency divider circuit 20. The output of the multiplexer is then ANDed with the multi-channel amplitude control word generated by the decoder 120 of the digital decoding circuit, and finally fed to the differential pair amplifier tube to charge and discharge the capacitor. Finally, the three channels are combined in the output matching network.

[0034] For example, the input terminals of differential pair 310 input the drive signals S1[0:54] and S2[0:54] of selector 340, and the output terminals of differential pair 310 output differential signals 1+ and 1-, which serve as inputs to the output matching network 40. Similarly, the output signals 2+, 2-, 3+, and 3- of differential pair 320 and differential pair 330 are also processed in this way.

[0035] like Figure 6 As shown, the input terminal of the switching power amplifier circuit 30 receives square wave drive signals (A+, A-, B+, B-, C+, C-, a+, a-, b+, b-, c+, c-) from the frequency divider circuit 20 and amplitude control words and phase control words from the digital decoding circuit 10. Taking one single-ended group of differential pair 310 as an example, there are a total of 55 parallel lines. The signal selected by the input multiplexer in each line is the fundamental frequency square wave A+ and the three-way frequency square wave a+. Each line outputs the corresponding square wave signal under the selection of the corresponding phase control word. The output square wave signal is then logically ANDed with the current amplitude control word. All lines obtain S1[0:54], that is, 55 parallel control signals. The 55 parallel control signals are input to a group of single-ended amplifier tubes in differential pair 310. By controlling the switching of the transistors to turn on and off, the periodic charging and discharging of the load capacitor is realized, thereby realizing the radio frequency power amplification function. Among them, S1[0:54] and S2[0:54] are the input drive signals of differential pair 1 310, and S3[0:54], S4[0:54], S5[0:54] and S6[0:54] are similar. Differential pair 1 310, differential pair 2 320 and differential pair 330 with the same structure constitute a three-way parallel power amplifier structure.

[0036] In one embodiment, the power output ratio of the three differential pairs (310, 320, 330) is 1:1:1, and all three differential pairs adopt the same structure.

[0037] The digital decoding circuit (10) selects the working state according to the input amplitude control signal, controls all power amplifier sub-units in the three differential pairs to work at the current frequency or ground, and selects the driving signal of different frequencies generated by the frequency divider circuit (20) in the switching power amplifier circuit (30).

[0038] In the voltage-type Class-D switching power amplifier structure adopted by the switching power amplifier circuit 30 of the present invention, the power transistor operates in a switching state, and converts the digital drive signal into an RF power output signal by periodically charging and discharging the load capacitor. Since the transistor mainly operates in a switching state, high power efficiency can be achieved.

[0039] The output matching network 40 is used to synthesize multiple power signals and perform impedance matching. In this embodiment, the output matching network 40 adopts a three-in-one parallel combining transformer (PCT) structure to synthesize three differential power signals 1+, 1-, 2+, 2-, 3+, and 3- into a single-ended output signal and to perform impedance transformation.

[0040] like Figure 7 As shown, the three-in-one parallel transformer structure of the output matching network 40 consists of three sets of differential input terminals (410, 420, 430) and one set of single-ended output terminals coupled together, and connected in series with filter capacitors (450, 460, 470) to achieve parallel synthesis of three power paths.

[0041] The output terminals of the three differential pairs (310, 320, 330) of the switching power amplifier circuit (30) are respectively connected to the three differential input terminals (410, 420, 430) of the output matching network (40), and the power synthesis of multiple signals is realized through magnetic coupling. The output signals (1+, 1-, 2+, 2-, 3+, 3-) of the switching power amplifier circuit 30 are synthesized by the transformer in parallel and then output to the load terminal, while realizing impedance matching.

[0042] To achieve wide-range, high-efficiency power back-off, this invention employs a combination of tuned back-off and Doherty back-off.

[0043] like Figure 8 As shown, in tuned back-off mode (0dB-9.5dB), by selecting the three-way square wave signal output by the frequency divider circuit 20, the switching power amplifier circuit 30 operates at a lower frequency, thereby changing the fundamental amplitude of the output matching network 40. Tuned power back-off is achieved by reducing the drive frequency. In this embodiment, higher efficiency can be obtained at power back-off points of approximately 3.5dB and 9.5dB.

[0044] Under deeper power back-off conditions (9.5dB-15.5dB), this invention employs Doherty load modulation to improve efficiency. In this mode, the positive terminals (1+, 2+, 3+) of the three differential pairs (310, 320, 330) of the switching power amplifier circuit 30 form the main power amplification path, while the negative terminals (1-, 2-, 3-) form the auxiliary power amplification path. High-efficiency output under deep power back-off is achieved through load modulation of the output matching network 40. The Doherty power amplification structure is formed by load modulation between the main and auxiliary amplification paths, thereby improving efficiency in the deep power back-off region. In this embodiment, this structure can achieve high efficiency at a power back-off point of approximately 15.5 dB.

[0045] Figure 9 The simulation results curve of the relationship between the output power and efficiency of the power amplifier provided in this embodiment is shown. By combining the above-mentioned tuning back-off and Doherty back-off method, the present invention can maintain a high power-added efficiency over a wide power back-off range, thereby improving the overall efficiency performance of the digital power amplifier under peak-to-average power ratio signal conditions.

[0046] In summary, this invention provides a three-channel synthesized deep backoff digital power amplifier. By employing a three-in-one parallel synthesized transformer structure to achieve multi-channel power synthesis, and combining a hybrid power control method of tuned backoff and Doherty backoff, the power amplifier can maintain high efficiency under a wide range of power backoff conditions, and has good application value.

[0047] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A three-channel synthesized deep back-off digital power amplifier, characterized in that: It includes a digital decoding circuit (10), a frequency divider circuit (20), a switching power amplifier circuit (30), and an output matching network (40). The output terminals of the digital decoding circuit (10) and the frequency divider circuit (20) are connected to the switching power amplifier circuit (30), and the switching power amplifier circuit (30) is connected to the output matching network (40). The phase control word output by the digital decoding circuit (10) selects the frequency divider circuit (20) to output square wave signals of different frequencies. The selected square wave signal and the current amplitude control word are logically ANDed to change the driving frequency and switching state of the switching power amplifier circuit (30) and realize power back-off control.

2. The three-channel synthesized deep back-off digital power amplifier according to claim 1, characterized in that: The digital decoding circuit (10) includes a classic serial-to-parallel converter (110) of a digital IC and a decoder (120). The input signal first passes through the classic serial-to-parallel converter (110) of the digital IC to obtain an amplitude control signal. The decoder (120) generates corresponding amplitude control words and phase control words according to the input amplitude control signal, which are used to control the switching power amplifier circuit (30) to realize output adjustment under different power levels.

3. A three-channel synthesized deep back-off digital power amplifier according to claim 1, characterized in that: The frequency divider circuit (20) includes a single-ended to differential converter (220) and a three-way frequency divider module (210). The single-ended to differential converter (220) first converts the input RF PM signal to a differential signal and outputs a differential RF signal. The differential RF signal then enters the three-way frequency divider module (210) to generate multiple fundamental frequency signals and frequency divider signals. The fundamental frequency signals and frequency divider signals are used to realize drive control under different power back-off modes.

4. A three-channel synthesized deep back-off digital power amplifier according to claim 3, characterized in that: The frequency divider module (210) includes a multi-level cascaded D flip-flops and logic gates, with the radio frequency signal as the flip-flop clock.

5. A three-channel synthesized deep back-off digital power amplifier according to claim 3, characterized in that: The switching power amplifier circuit (30) includes multiple differential pairs with the same structure and a multiplexer. The multiplexer is input to the phase control word generated by the decoder (120) of the digital decoding circuit, which is used to select the driving signal generated by the frequency divider circuit (20). The selected driving signal is then ANDed with the amplitude control word and finally input to the differential pair.

6. A three-channel synthesized deep back-off digital power amplifier according to claim 5, characterized in that: Each differential pair is constructed using a circuit with multiple amplifier tubes connected in series with capacitors at one end, and the amplifier tubes adopt a Class D amplifier structure.

7. A three-channel synthesized deep back-off digital power amplifier according to claim 3, characterized in that: The output matching network (40) adopts a parallel transformer structure to synthesize the multiple differential power signals output by the switching power amplifier circuit (30) into a single-ended output signal and realize the impedance transformation function.

8. A three-channel synthesized deep back-off digital power amplifier according to claim 7, characterized in that: The transformer structure is composed of multiple sets of differential input terminals and a set of single-ended output terminals coupled together, and a series filter capacitor is connected to achieve parallel synthesis of multiple power sources.

9. The three-channel synthesized deep back-off digital power amplifier according to claim 5, characterized in that: In deep power back-off mode, the switching power amplifier circuit (30) achieves Doherty power back-off through load modulation between the main amplifier and the auxiliary amplifier.

10. The three-channel synthesized deep back-off digital power amplifier according to claim 9, characterized in that: The main amplifier is the positive power amplifier for each differential pair, and the auxiliary amplifier is the negative power amplifier for each differential pair.

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