Gain amplifier for signal repeater using a fully complementary mos process

Abstract

A gain amplifier and a signal repeater are disclosed. The gain amplifier includes a gain stage, a transimpedance amplification stage, and a feedback stage. The gain stage includes a first resistor, a second resistor, first and second PMOS transistors, and first and second NMOS transistors. A first end of the first PMOS transistor and a first end of the second PMOS transistor are connected to the first resistor. A first end of the first NMOS transistor and a first end of the second NMOS transistor are connected to the second resistor. A second end of the first PMOS transistor is connected to a second end of the first NMOS transistor. A gate end of the first PMOS transistor is connected to a gate end of the first NMOS transistor. A second end of the second PMOS transistor is connected to a second end of the second NMOS transistor. A gate end of the second PMOS transistor is connected to a gate end of the second NMOS transistor.

Description

Technical Field

[0001] This invention relates to a variable gain amplifier (VGA), and more particularly to a variable gain amplifier that can be used in a signal repeater. Background Technology

[0002] In today's information-exploding world, electronic systems are transmitting ever larger amounts of data at ever-increasing speeds. High-speed signals tend to attenuate over distances, necessitating the development of signal repeaters (or re-timers) to compensate for this attenuation. Linear re-drivers offer higher signal linearity and are therefore widely used in signal repeater circuits.

[0003] However, linear signal repeaters have high requirements for signal oscillation linearity. Traditionally, linear signal repeaters are mostly implemented using Bipolar Complementary Metal-Oxide Semiconductor (BiCMOS) technology to achieve the high transconductance (gm) advantage of Bipolar Junction Transistor (BJT) devices. However, a disadvantage of BiCMOS is that its voltage headroom requirement is much higher than that of Complementary Metal-Oxide Semiconductor (CMOS) devices, which contradicts today's demands for low voltage and low power consumption. Furthermore, circuits using BiCMOS technology, which simultaneously employ BiCMOS and Bipolar Junction Transistors, have higher circuit costs than those using fully Complementary Metal-Oxide Semiconductor (CMOS) technology. Summary of the Invention

[0004] Therefore, the main objective of this invention is to propose a novel variable gain amplifier (VGA) for signal repeaters that can be implemented using all-complementary metal-oxygen semiconductor (all-CMOS) technology, in order to solve the above-mentioned problems.

[0005] An embodiment of the present invention discloses a gain amplifier, comprising a gain stage, a transimpedance amplifier stage (TIA stage), and a feedback stage. The TIA stage is coupled to the gain stage, and the feedback stage is coupled to both the gain stage and the TIA stage. The gain stage includes a first resistor, a second resistor, a first P-type metal-oxide-semiconductor (MOSFET), a first N-type MOSFET, a second P-type MOSFET, and a second N-type MOSFET. The first P-type MOSFET has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the first resistor. The first N-type MOSFET has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the second resistor, the second terminal is connected to the second terminal of the first P-type MOSFET, and the gate terminal is connected to the gate terminal of the first P-type MOSFET. The second P-type metal-oxide-semiconductor (MOSFET) has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the first resistor. The second N-type MOSFET has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the second resistor, the second terminal is connected to the second terminal of the second P-type MOSFET, and the gate terminal is connected to the gate terminal of the second P-type MOSFET.

[0006] Another embodiment of the present invention discloses a signal repeater, comprising an equalizer, a gain amplifier, and a transmitter. The gain amplifier is coupled to the equalizer, and the transmitter is coupled to the gain amplifier. The gain amplifier includes a gain stage, a transimpedance amplification stage, and a feedback stage. The transimpedance amplification stage is coupled to the gain stage, and the feedback stage is coupled to both the gain stage and the transimpedance amplification stage. The gain stage includes a first resistor, a second resistor, a first P-type MOSFET, a first N-type MOSFET, a second P-type MOSFET, and a second N-type MOSFET. The first P-type MOSFET has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the first resistor. The first N-type MOSFET has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the second resistor, the second terminal is connected to the second terminal of the first P-type MOSFET, and the gate terminal is connected to the gate terminal of the first P-type MOSFET. The second P-type metal-oxide-semiconductor (MOSFET) has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the first resistor. The second N-type MOSFET has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the second resistor, the second terminal is connected to the second terminal of the second P-type MOSFET, and the gate terminal is connected to the gate terminal of the second P-type MOSFET. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a typical variable gain amplifier.

[0008] Figure 2 This is a schematic diagram of a signal repeater according to Embodiment 1 of the present invention.

[0009] Figure 3 A detailed embodiment of the variable gain amplifier of the present invention is shown.

[0010] Figure 4 A detailed implementation of the gain stage and feedback stage of this invention is shown.

[0011] Figure 5 A detailed embodiment of the transimpedance amplifier stage of the present invention is shown.

[0012] Figure 6 The transconductance values ​​of P-type and N-type metal-oxide-semiconductor transistors are shown within a voltage range of the input signal.

[0013] Figure 7 The gain stage and feedback stage implemented using high-voltage and low-voltage components are shown.

[0014] Figure 8 A transimpedance amplifier stage implemented using high-voltage and low-voltage components is shown.

[0015] The reference numerals in the attached figures are explained as follows:

[0016] 10, 204 Variable Gain Amplifier

[0017] CS_A, CS_B, CS1~CS5 Current Sources

[0018] Load resistors RL_A, RL_B, RL1, RL2

[0019] M_A, M_B bipolar junction transistors

[0020] RS variable resistor

[0021] VIN+, VIN- Input Signals

[0022] VO+, VO- Output Signals

[0023] 20 signal repeaters

[0024] 202 Equalizer

[0025] 206 Transmitter

[0026] VDD supply voltage

[0027] 302 Gain Stage

[0028] 304 Transimpedance Amplifier Stage

[0029] 306 Feedback Level

[0030] VM+, VM- intermediate signals

[0031] MP1~MP4, M_CS1~M_CS5 P-type metal-oxide-semiconductor transistors

[0032] MN1~MN4 N-type metal-oxide-semiconductor transistors

[0033] RS_G1, RS_G2, RS_FB1, RS_FB2 source decay resistors

[0034] 410, 510 common-mode control circuit

[0035] 412 and 512 operational amplifiers

[0036] RCM1~RCM4 common mode feedback resistors

[0037] VREF1, VREF2 reference voltages

[0038] INV1, INV2 Inverters

[0039] GND grounding voltage

[0040] g mp g mn transconductance Detailed Implementation

[0041] Figure 1 This is a schematic diagram of a general variable gain amplifier (VGA) 10. The VGA 10 includes two current sources CS_A and CS_B, two load resistors RL_A and RL_B, two bipolar junction transistors (BJTs) M_A and M_B, and a variable resistor RS. The BJTs M_A and M_B are input transistors used to receive differential input signals VIN+ and VIN- to generate differential output signals VO+ and VO-. The VGA 10 can provide high gain for high-speed signals, and its gain can be calculated as follows:

[0042]

[0043] Among them, R L Let R be the resistance values ​​of load resistors RL_A and RL_B. S Let g be the resistance value of the variable resistor RS. mThese are the transconductance values ​​of bipolar junction transistors M_A and M_B.

[0044] Generally, current sources CS_A and CS_B are implemented using complementary metal-oxide-semiconductor (CMOS) transistors (hereinafter referred to as metal-oxide-semiconductor transistors). Therefore, the variable gain amplifier 10 is implemented using bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. Due to the high transconductance g of bipolar junction transistors M_A and M_B... m Due to its characteristics, the variable gain amplifier 10 is suitable for high-gain applications, such as linear signal repeaters. However, as mentioned above, the bipolar complementary metal-oxide-semiconductor (BISM) process is associated with higher circuit costs, and the bipolar junction transistors M_A and M_B have significant voltage margin requirements, limiting the supply voltage of the variable gain amplifier 10. For example, as Figure 1 As shown, the supply voltage needs to be greater than or equal to 3.3V, which consumes more power and is not conducive to the application of advanced processes.

[0045] Therefore, this invention proposes a novel variable gain amplifier structure and its associated signal repeater implemented using a fully complementary metal-oxide-semiconductor (MOS) process. All transistor components utilize MOS transistors, avoiding the voltage margin issues of bipolar junction transistors (BJTs), thereby supporting lower supply voltages and achieving a wider supply voltage range. Simultaneously, circuit costs are reduced without using BJTs. Furthermore, with appropriate circuit design, high bandwidth and high oscillation linearity can also be achieved.

[0046] Figure 2 This is a schematic diagram of a signal repeater 20 according to an embodiment of the present invention. The signal repeater 20 includes an equalizer 202, a variable gain amplifier 204, and a transmitter 206. The signal received by the signal repeater 20 is first processed by the equalizer 202, which can be used to compensate for high-frequency attenuation of the received signal. The variable gain amplifier 204 is used to amplify the signal swing while maintaining the linearity of the signal. After the signal compensation and amplification are completed, the transmitter 206 can provide sufficient drive capability to output the signal. In addition, the design of the transmitter 206 must also meet the impedance matching requirements.

[0047] like Figure 2 As shown, signal repeater 20 supports a wide supply voltage range of 1.8V to 3.3V VDD. It should be noted that the variable gain amplifier in the signal repeater is implemented using a bipolar complementary metal-oxide-semiconductor process (such as...). Figure 1The variable gain amplifier 10 in the original design can only support higher supply voltages, such as 3.3V, due to its voltage margin limitations. In contrast, the variable gain amplifier 204 and signal repeater 20 of the present invention can be implemented using a fully complementary metal-oxide-semiconductor process, thus supporting lower supply voltage levels and a wider supply voltage range.

[0048] To achieve high signal linearity, this invention proposes a suitable circuit design for the signal repeater 20. Generally, the equalizer 202 (which may be, for example, a continuous time linear equalizer (CTLE)) typically uses source degeneration to compensate for high-frequency signal attenuation. Source degeneration achieved using a large resistor improves signal linearity, thus the equalizer 202 does not have a linearity problem. However, the variable gain amplifier 204 is required to provide high DC gain, thus limiting the strength of source degeneration. This means that the variable gain amplifier 204 typically has a linearity problem that needs to be addressed, especially when the signal oscillates significantly.

[0049] This invention proposes a novel variable gain amplifier structure to improve signal linearity. Figure 3 A detailed embodiment of the variable gain amplifier 204 of the present invention is shown. The variable gain amplifier 204 includes a gain stage 302, a transimpedance amplifier stage (TIA stage) 304, and a feedback stage 306.

[0050] Gain stage 302 can receive differential input signals VIN+ and VIN- to generate intermediate signals VM+ and VM-. Gain stage 302 is the main circuit stage of variable gain amplifier 204, used to provide high gain for signal amplification.

[0051] Transimpedance amplifier stage 304 receives intermediate signals VM+ and VM- to generate output signals VO+ and VO-. More specifically, the positive input of transimpedance amplifier stage 304 is coupled to the negative output of gain stage 302 to receive the intermediate signal VM-; the negative input of transimpedance amplifier stage 304 is coupled to the positive output of gain stage 302 to receive the intermediate signal VM+. Transimpedance amplifier stage 304 can be used to increase gain bandwidth while providing a stable signal for gain stage 302, that is, stabilizing the voltages of intermediate signals VM+ and VM- at the output of gain stage 302. It should be noted that the purpose of gain stage 302 is to provide high gain, therefore the intermediate signals VM+ and VM- output by gain stage 302 exhibit significant signal oscillation. In this case, by controlling transimpedance amplifier stage 304, intermediate signals VM+ and VM- can be maintained at a stable common-mode voltage, thereby improving gain linearity and increasing signal bandwidth.

[0052] Feedback stage 306 is coupled to gain stage 302 and transimpedance amplifier stage 304 to form a feedback path. More specifically, the positive input of feedback stage 306 is coupled to the positive output of transimpedance amplifier stage 304, and the negative input of feedback stage 306 is coupled to the negative output of transimpedance amplifier stage 304. Furthermore, the positive output of feedback stage 306 is coupled to the negative input of transimpedance amplifier stage 304, and the negative output of feedback stage 306 is coupled to the positive input of transimpedance amplifier stage 304. This configuration of feedback stage 306 can also be used to increase signal bandwidth and improve gain linearity.

[0053] Figure 4 This illustration shows a detailed embodiment of the gain stage 302 and feedback stage 306 of the present invention. The gain stage 302 includes two P-type metal-oxide-semiconductor transistors (MOSFETs) MP1 and MP2, and two N-type MOSFETs MN1 and MN2 for transmitting signals. Specifically, the gate terminals of the P-type MOSFETs MP1 and MN1 are interconnected to receive the input signal VIN+; the gate terminals of the P-type MOSFETs MP2 and MN2 are interconnected to receive the input signal VIN-. Furthermore, the drain terminals of the P-type MOSFETs MP1 and MN1 are interconnected to output the intermediate signal VM-; the drain terminals of the P-type MOSFETs MP2 and MN2 are interconnected to output the intermediate signal VM+.

[0054] like Figure 4As shown, gain stage 302 also includes a pair of P-type metal-oxide-semiconductor transistors M_CS1 and M_CS2, a pair of current sources CS1 and CS2, two source decay resistors RS_G1 and RS_G2, and a common-mode control circuit 410. The source terminal of P-type metal-oxide-semiconductor MP1 is further connected to one end of source decay resistor RS_G1, and the source terminal of P-type metal-oxide-semiconductor MP2 is further connected to the other end of source decay resistor RS_G1. The source terminal of N-type metal-oxide-semiconductor MN1 is further connected to one end of source decay resistor RS_G2, and the source terminal of N-type metal-oxide-semiconductor MN2 is further connected to the other end of source decay resistor RS_G2. In one or more embodiments, source decay resistors RS_G1 and RS_G2 can be variable resistors whose resistance values ​​can be adjusted or switched appropriately to determine the gain of gain stage 302, thereby determining the gain of variable gain amplifier 204. P-type metal-oxide-semiconductor (MOSFET) M_CS1 is coupled between the source terminal of P-type MOSFET MP1 and the common-mode control circuit 410, and P-type MOSFET M_CS2 is coupled between the source terminal of P-type MOSFET MP2 and the common-mode control circuit 410. MOSFETs M_CS1 and M_CS2 can act as current sources to supply current to transistors MP1, MN1, MP2, and MN2. Current sources CS1 and CS2 correspondingly draw current from transistors MP1, MN1, MP2, and MN2.

[0055] The common-mode control circuit 410 includes an operational amplifier 412 and two common-mode feedback resistors RCM1 and RCM2. Common-mode feedback resistor RCM1 is coupled between the drain terminals of P-type MOSFET MP1, N-type MOSFET MN1, and an input terminal of operational amplifier 412. Common-mode feedback resistor RCM2 is coupled between the drain terminals of P-type MOSFET MP2, N-type MOSFET MN2, and the input terminal of operational amplifier 412. Operational amplifier 412 can further receive a reference voltage VREF1 through another input terminal. Generally, common-mode feedback resistors RCM1 and RCM2 can be designed to have the same resistance value; therefore, the common-mode voltages of intermediate signals VM+ and VM- can be controlled to be equal to the reference voltage VREF1. By appropriately setting the reference voltage VREF1, the intermediate signals VM+ and VM- can oscillate at a level well controlled by the reference voltage VREF1, regardless of the voltages of the differential input signals VIN+ and VIN-, thereby maintaining gain linearity.

[0056] Please continue to refer to this. Figure 4Feedback stage 306 includes two P-type MOSFETs MP3 and MP4 and two N-type MOSFETs MN3 and MN4 for signal transmission. It also includes a pair of P-type MOSFETs M_CS3 and M_CS4, a pair of current sources CS3 and CS4, and two source decay resistors RS_FB1 and RS_FB2, with a structure similar to gain stage 302. Specifically, the gate of P-type MOSFET MP3 is connected to the gate of N-type MOSFET MN3 to receive the output signal VO+; the gate of P-type MOSFET MP4 is connected to the gate of N-type MOSFET MN4 to receive the output signal VO-. Furthermore, the drain of P-type MOSFET MP3 is connected to the drain of N-type MOSFET MN3 to output the intermediate signal VM-; the drain of P-type MOSFET MP4 is connected to the drain of N-type MOSFET MN4 to output the intermediate signal VM+. The source terminals of P-type metal-oxide-semiconductor transistors MP3 and MP4 are further connected to the source decay resistor RS_FB1, and the source terminals of N-type metal-oxide-semiconductor transistors MN3 and MN4 are further connected to the source decay resistor RS_FB2. P-type metal-oxide-semiconductor transistors M_CS3 and M_CS4 can also be used as current sources, which, together with current sources CS3 and CS4, are used to supply current to transistors MP3, MN3, MP4, and MN4.

[0057] In the fully complementary metal-oxide-semiconductor process, all transistors in the gain stage 302 and the feedback stage 306 (including the transistors used to implement current sources CS1 to CS4 and operational amplifier 412) are complementary metal-oxide-semiconductor transistors, and no bipolar junction transistors are used, thus reducing process complexity and related circuit costs.

[0058] Figure 5 A detailed embodiment of the transimpedance amplifier stage 304 of the present invention is shown. Please refer to... Figure 5 Matching Figure 3 As shown, the transimpedance amplifier stage 304 can be used to receive intermediate signals VM+ and VM- and output signals VO+ and VO-. The transimpedance amplifier stage 304 includes two inverters INV1 and INV2, two load resistors RL1 and RL2, a current source CS5, and a common-mode control circuit 510. The common-mode control circuit 510 includes an operational amplifier 512, a P-type metal-oxide-semiconductor transistor M_CS5, and two common-mode feedback resistors RCM3 and RCM4. Figure 5As shown, inverter INV1 is coupled between the positive input and negative output of transimpedance amplifier stage 304 to convert the intermediate signal VM+ into the output signal VO-, and load resistor RL1 is connected in parallel with inverter INV1. Inverter INV2 is coupled between the negative input and positive output of transimpedance amplifier stage 304 to convert the intermediate signal VM- into the output signal VO+, and load resistor RL2 is connected in parallel with inverter INV2. Inverters INV1 and INV2 are further coupled to P-type metal-oxide-semiconductor transistor M_CS5 and current source CS5 to receive current from P-type metal-oxide-semiconductor transistor M_CS5 and current source CS5.

[0059] In the common-mode control circuit 510, common-mode feedback resistor RCM3 is coupled between the output of inverter INV1 and an input of operational amplifier 512, and common-mode feedback resistor RCM4 is coupled between the output of inverter INV2 and the same input of operational amplifier 512. Operational amplifier 512 can further receive a reference voltage VREF2 through another input. Similarly, common-mode feedback resistors RCM3 and RCM4 can be designed to have the same resistance value, so the common-mode voltages of output signals VO+ and VO- can be controlled to be equal to the reference voltage VREF2. By appropriately setting the reference voltage VREF2, the output signals VO+ and VO- can oscillate at a level well controlled by the reference voltage VREF2, unaffected by the supply voltage VDD level, thus achieving a wide range of supply voltage VDD.

[0060] In one exemplary embodiment, the reference voltage VREF2 can be equal to 0.8V, so the output signals VO+ and VO- can be differential signals oscillating at a level of 0.8V. In this case, regardless of the level of the supply voltage VDD, the output signals VO+ and VO- can be maintained at the required level, allowing the supply voltage VDD to have a wide range, for example, from 1.8V to 3.3V. Furthermore, the transimpedance amplifier stage 304 isolates the output node of the variable gain amplifier 204 from the intermediate node. Therefore, the output signals VO+ and VO- at the output node can have a wide range of signal oscillations, while the signal oscillations at the intermediate node can be well controlled and stabilized by the common-mode control circuit 410. In other words, the intermediate signals VM+ and VM- between the gain stage 302 and the transimpedance amplifier stage 304 do not require large signal oscillations. Therefore, even if the variable gain amplifier 204 has a large input oscillation, the transistors MP1, MN1, MP2, and MN2 in the gain stage 302 can still operate in the saturation region, thereby achieving high signal linearity.

[0061] Therefore, based on Figure 4 and Figure 5 Given the circuit structure, the gain of the variable gain amplifier 204 can be calculated as follows:

[0062]

[0063] Among them, g mp G represents the transconductance values ​​of P-type metal-oxide-semiconductor transistors MP1 and MP2. mn R represents the transconductance values ​​of N-type metal-oxide-semiconductor transistors MN1 and MN2. S1 R is the resistance value of the source decay resistor RS_G1. S2 R is the resistance value of the source decay resistor RS_G2. L Let RL1 and RL2 be the resistance values ​​of the load resistors RL1 and RL2 in the transimpedance amplifier stage 304. Assume g mp equal to g mn And R S1 Equal to R S2 Equation (2) can be rearranged as follows:

[0064]

[0065] Comparing equation (3) with equation (1), it can be seen that the gain of the variable gain amplifier 204 proposed in this invention is twice the gain of a general variable gain amplifier implemented using bipolar complementary metal-oxide-semiconductor (BOS) technology (if the two variable gain amplifiers have the same transconductance and resistance values). Although the transconductance of the complementary BOS component is usually smaller than that of the bipolar junction transistor component in a general variable gain amplifier, the difference in transconductance can be compensated by the combination of the high-side P-type BOS transistors MP1 and MP2 and the low-side N-type BOS transistors MN1 and MN2 in the variable gain amplifier 204, thereby meeting the high gain requirement of the signal repeater.

[0066] The combination of high-side P-type metal-oxide-semiconductor transistors MP1 and MP2 and low-side N-type metal-oxide-semiconductor transistors MN1 and MN2 can also be used to improve the linearity of signal oscillation. Figure 6 The transconductance values ​​g of P-type metal-oxide-semiconductor transistors MP1 and MP2 are shown within a voltage range of input signals VIN+ and VIN- (e.g., between ground voltage GND and supply voltage VDD). mp The transconductance values ​​g of N-type metal-oxide-semiconductor transistors MN1 and MN2 mn .like Figure 6 As shown, N-type metal-oxide-semiconductor transistors MN1 and MN2 have higher transconductance values ​​g at higher voltages. mn N-type metal-oxide-semiconductor transistors MN1 and MN2 provide an optimal operating range with high gain at higher voltages close to the supply voltage VDD; while P-type metal-oxide-semiconductor transistors MP1 and MP2 have higher transconductance g at lower voltages. mpP-type metal-oxide-semiconductor transistors MP1 and MP2 can provide an optimal operating range with high gain at relatively low voltages close to ground voltage GND. Therefore, the combination of the above transconductance values ​​(i.e., g...) mp +g mn It can achieve a flat high gain over a wide range between the supply voltage VDD and the ground voltage GND, which means that the signal has a large amplitude oscillation range with high linearity.

[0067] It is worth noting that the purpose of this invention is to propose a novel variable gain amplifier architecture implemented using a fully complementary metal-oxide-semiconductor process, which can be used in signal repeaters. Those skilled in the art will be able to modify or vary this architecture, but are not limited thereto. For example, in the above embodiments, the source decay resistor can be a variable resistor, which can be adjusted or fine-tuned to achieve a variable gain value. In another embodiment, one or part of the source decay resistor can be implemented using one or more fixed resistors. Furthermore, the design of the resistors and transistors is not intended to limit the scope of this invention. For example, in one or more embodiments, transistors MP1, MN1, MP2, and MN2 can be well designed to have the desired transconductance value g. mp and g mn Furthermore, the source decay resistors RS_G1 and RS_G2 can be designed to have the same or different resistance values, for example, based on g mp and g mn The design is based on numerical values ​​to achieve a flat, high-gain voltage across a wide voltage swing range.

[0068] In one or more embodiments, if the variable gain amplifier 204 operates under high-speed applications, the transistor used for signal transmission should preferably be implemented using a low-voltage component. The low-voltage component can be an on-chip core device, which typically has a lower voltage rating and a faster operating speed. Therefore, the variable gain amplifier 204 can be well designed to isolate the signal transmission transistor from the supply voltage VDD, allowing the supply voltage VDD to have a wide range of voltage ratings unrestricted by the signal transmission transistor.

[0069] An exemplary embodiment of the high-voltage and low-voltage components in gain stage 302 and feedback stage 306 is shown in Figure 7 In it, it shows the same as Figure 4 Because of the same circuit structure, the same signals or components are represented by the same symbols. For example... Figure 7As shown, operational amplifier 412 and P-type metal-oxide-semiconductor transistors M_CS1 to M_CS4 can both be implemented using high-voltage components. These high-voltage components can be input / output devices (I / O devices) that can withstand higher voltages (e.g., 3.3V), allowing variable gain amplifier 204 to support supply voltages up to 3.3V VDD. Signal transmission transistors (such as transistors MP1, MN1, MP2, and MN2 in gain stage 302 and transistors MP3, MN3, MP4, and MN4 in feedback stage 306) can be implemented using low-voltage components. These low-voltage components can be core components, operating at higher speeds to meet the demands of high-speed transmission. Furthermore, in gain stage 302, the reference voltage VREF1 can be well-designed to control the common-mode voltages of intermediate signals VM+ and VM-, allowing VM+ and VM- to oscillate at levels consistent with the withstand voltages of the low-voltage components.

[0070] The 304 transimpedance amplifier stage can also be implemented in a suitable way to achieve high-speed transmission, such as... Figure 8 As shown. The operational amplifier 512 and the P-type metal-oxide-semiconductor transistor M_CS5 can be implemented using high-voltage components (such as input / output components) to receive a wide range of supply voltages VDD from 1.8V to 3.3V. The transistors in the inverters INV1 and INV2 used to transmit signals can be implemented using low-voltage components (such as core components) to achieve high-speed signal transmission.

[0071] In the above embodiments, the use of high-voltage components allows the variable gain amplifier 204 to operate at higher supply voltages VDD, such as up to 3.3V. In another embodiment, if the supply voltage VDD received by the variable gain amplifier is less than 1.4V, low-voltage components can also be used. For example, all transistors in the gain stage, transimpedance amplification stage, and feedback stage can be implemented using core components, thus further reducing circuit area and circuit cost.

[0072] In summary, this invention proposes a novel variable gain amplifier structure that can be implemented using a fully complementary metal-oxide-semiconductor (MOSFET) process. This structure eliminates the need for any bipolar junction transistors (BJTs), thus avoiding the need for significant margins required for BJTs. This allows the variable gain amplifier to support a wide range of supply voltages (VDD), surpassing the performance of variable gain amplifiers implemented using a fully complementary MOSFET process. Furthermore, the signal transmission transistor can be implemented using a high-side P-type MOSFET connected to a low-side N-type MOSFET, achieving high gain and high linearity to compensate for the lower transconductance of fully complementary MOSFETs.

[0073] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A gain amplifier, characterized in that, include: A gain stage, including: First resistor; A second resistor; A first P-type metal-oxide-semiconductor transistor has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the first resistor; A first N-type metal-oxide-semiconductor has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the second resistor, the second terminal is connected to the second terminal of the first P-type metal-oxide-semiconductor, and the gate terminal is connected to the gate terminal of the first P-type metal-oxide-semiconductor. A second P-type metal-oxide-semiconductor transistor has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the first resistor; and A second N-type metal-oxide-semiconductor has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the second resistor, the second terminal is connected to the second terminal of the second P-type metal-oxide-semiconductor, and the gate terminal is connected to the gate terminal of the second P-type metal-oxide-semiconductor. A transimpedance amplifier stage is coupled to the gain stage; and A feedback stage is coupled to the gain stage and the transimpedance amplifier stage.

2. The gain amplifier as described in claim 1, characterized in that, The gate terminals of the first P-type metal-oxide-semiconductor and the first N-type metal-oxide-semiconductor are used to receive a first input signal, and the gate terminals of the second P-type metal-oxide-semiconductor and the second N-type metal-oxide-semiconductor are used to receive a second input signal.

3. The gain amplifier as described in claim 1, characterized in that, A positive input terminal of the transimpedance amplifier stage is coupled to a negative output terminal of the gain stage, and a negative input terminal of the transimpedance amplifier stage is coupled to a positive output terminal of the gain stage.

4. The gain amplifier as described in claim 1, characterized in that, A positive input terminal of the feedback stage is coupled to a positive output terminal of the transimpedance amplifier stage, a negative input terminal of the feedback stage is coupled to a negative output terminal of the transimpedance amplifier stage, a positive output terminal of the feedback stage is coupled to a negative input terminal of the transimpedance amplifier stage, and a negative output terminal of the feedback stage is coupled to a positive input terminal of the transimpedance amplifier stage.

5. The gain amplifier as claimed in claim 1, characterized in that, This feedback level includes: A third resistor; A fourth resistor; A third P-type metal-oxide-semiconductor transistor has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the third resistor; A third N-type metal-oxide-semiconductor transistor has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the fourth resistor, the second terminal is connected to the second terminal of the third P-type metal-oxide-semiconductor transistor, and the gate terminal is connected to the gate terminal of the third P-type metal-oxide-semiconductor transistor. A fourth P-type metal-oxide-semiconductor transistor has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the third resistor; and A fourth N-type metal-oxide-semiconductor transistor has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the fourth resistor, the second terminal is connected to the second terminal of the fourth P-type metal-oxide-semiconductor transistor, and the gate terminal is connected to the gate terminal of the fourth P-type metal-oxide-semiconductor transistor.

6. The gain amplifier as claimed in claim 1, characterized in that, This gain stage also includes: A first common-mode control circuit, comprising: An operational amplifier; A fifth resistor is coupled between the second terminal of the first P-type metal-oxide-semiconductor, the second terminal of the first N-type metal-oxide-semiconductor, and the operational amplifier; and A sixth resistor is coupled between the second terminal of the second P-type metal-oxide-semiconductor, the second terminal of the second N-type metal-oxide-semiconductor, and the operational amplifier.

7. The gain amplifier as claimed in claim 6, characterized in that, This gain stage also includes: A fifth P-type metal-oxide-semiconductor transistor is coupled to the first terminal of the first P-type metal-oxide-semiconductor transistor and the first common-mode control circuit; and A sixth P-type metal-oxide-semiconductor is coupled to the first terminal of the second P-type metal-oxide-semiconductor and the first common-mode control circuit.

8. The gain amplifier as claimed in claim 7, characterized in that, The fifth P-type metal-oxide-semiconductor, the sixth P-type metal-oxide-semiconductor, and the operational amplifier are implemented using high-voltage components, while the first P-type metal-oxide-semiconductor, the first N-type metal-oxide-semiconductor, the second P-type metal-oxide-semiconductor, and the second N-type metal-oxide-semiconductor are implemented using low-voltage components.

9. The gain amplifier as claimed in claim 1, characterized in that, This transimpedance amplifier stage includes: A second common-mode control circuit, comprising: An operational amplifier; and A control transistor is coupled to the operational amplifier; A first inverter is coupled between a positive input terminal of the transimpedance amplifier stage, a negative output terminal of the transimpedance amplifier stage, and the second common-mode control circuit; and A second inverter is coupled between a negative input terminal of the transimpedance amplifier stage, a positive output terminal of the transimpedance amplifier stage, and the second common-mode control circuit.

10. A signal repeater, characterized in that, include: One equalizer; A gain amplifier, coupled to the equalizer, includes: A gain stage, including: First resistor; A second resistor; A first P-type metal-oxide-semiconductor transistor has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the first resistor; A first N-type metal-oxide-semiconductor has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the second resistor, the second terminal is connected to the second terminal of the first P-type metal-oxide-semiconductor, and the gate terminal is connected to the gate terminal of the first P-type metal-oxide-semiconductor. A second P-type metal-oxide-semiconductor transistor has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the first resistor; and A second N-type metal-oxide-semiconductor has a first terminal, a second terminal, and a gate terminal, wherein the first terminal is connected to the second resistor, the second terminal is connected to the second terminal of the second P-type metal-oxide-semiconductor, and the gate terminal is connected to the gate terminal of the second P-type metal-oxide-semiconductor. A transimpedance amplifier stage is coupled to the gain stage; and A feedback stage, coupled to the gain stage and the transimpedance amplifier stage; and A transmitter is coupled to the gain amplifier.

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