A voter applied to high speed clock

Abstract

The application discloses a kind of voters applied to high-speed clock, solve the problem of slow voter, impedance mismatch, poor anti-radiation capability in prior art, realize high-speed synchronous judgment, positive feedback fast latching and anti-single event upset;The circuit includes: positive phase voting circuit, inverting voting circuit and latching circuit;Voter sequentially executes following three stages when working: discharge phase: the original phase signal and the inverted signal of input signal are input to inverting voting circuit and positive phase voting circuit respectively, and it discharges according to the majority logic value of input signal to ground at its output end;The internal signal path of inverting, positive phase voting circuit is completely symmetrical;Trigger stage: when the absolute value of voltage difference between the output end of inverting voting circuit and the output end of positive phase voting circuit reaches the positive feedback trigger threshold of latching circuit, latching circuit starts positive feedback, and establishes complementary output signal;Maintenance stage: latching circuit maintains positive feedback latching state, and keeps output stable.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and more particularly to a voting device for high-speed clocks. Background Technology

[0002] In high-speed digital electronic systems, the integrity of the clock signal is crucial to overall performance. As integrated circuit technology advances to the nanometer scale and system operating frequencies continuously increase, clock signals inevitably become susceptible to various factors during long-distance transmission, such as signal attenuation, reflection, crosstalk, and phase shift, leading to inconsistencies or jitter between multiple clock sources. To ensure the synchronization and reliability of the critical path, the industry commonly employs a voting mechanism with multiple clock inputs to generate a stable and reliable output clock signal.

[0003] Traditional clock voting circuits are primarily implemented directly using static logic gates and transistors. While majority voting circuits composed of simple Complementary Metal-Oxide-Semiconductor (CMOS) inverters and NAND gates offer advantages such as simple structure and low power consumption, they suffer from significant limitations in high-speed applications. Firstly, the response speed of static logic gates is limited by the switching delay of transistors, making it difficult to meet the processing requirements of GHz-level clock signals. Secondly, traditional designs are highly sensitive to power supply noise and process variations, exhibiting poor stability under different operating conditions. Furthermore, changes in the impedance and load of transistor-based majority voters affect the output waveform. Additionally, the clock phase changes due to single-event effects, leading to alterations in the charging path impedance.

[0004] Most existing voting circuits are difficult to adapt flexibly to the needs of different application scenarios. Especially in fields such as high-speed serial communication, high-performance computing, and networks on chip (NoC), there is a need for a voter architecture that can quickly respond to changes in multiple inputs while effectively suppressing noise interference and maintaining high stability.

[0005] Therefore, how to design a voting device with high-speed response capability and a certain degree of radiation resistance has become an urgent problem to be solved. Summary of the Invention

[0006] This invention provides a voting device for high-speed clocks, which solves the problems of slow speed, impedance mismatch, and poor radiation resistance in existing voting devices, and achieves high-speed synchronization judgment, positive feedback fast latching, and resistance to single-event disturbances.

[0007] This invention provides a voting device for high-speed clocks, the circuit comprising: a positive voting circuit, an inverting voting circuit, and a latching circuit; The voting device executes the following three phases sequentially during operation: Discharge phase: The original phase signal and the inverted phase signal of the input signal are synchronously input to the inverted voting circuit and the non-inverted voting circuit, respectively. The inverted voting circuit and the non-inverted voting circuit simultaneously discharge their output terminals to ground according to the majority logic value of the input signal. The signal paths inside the inverted voting circuit and the non-inverted voting circuit are completely symmetrical, and the discharge start time of the two output terminals is the same and the discharge path impedance is equal. Triggering phase: When the absolute value of the voltage difference between the output terminal of the inverting voting circuit and the output terminal of the non-inverting voting circuit reaches the positive feedback trigger threshold of the latch circuit, the latch circuit starts positive feedback, and the latch circuit pulls up the high voltage side of the voltage difference to the power supply voltage and pulls down the low voltage side to ground to establish a complementary output signal; Hold phase: The latching circuit maintains a positive feedback latching state, keeping the level corresponding to the complementary output signal.

[0008] One or more technical solutions provided in this invention have at least the following technical effects or advantages: This invention employs a discharge phase: the original and inverted phase signals of the input signal are synchronously input to the inverting voting circuit and the non-inverting voting circuit, respectively. Both circuits simultaneously discharge their outputs to ground based on the majority logic value of the input signal. The signal paths within the inverting and non-inverting voting circuits are completely symmetrical, with the discharge start times at both outputs being identical and the discharge path impedances being equal. The beneficial effect of this phase is that, by utilizing completely symmetrical signal paths and equal discharge path impedances, it fundamentally eliminates the inherent mismatch caused by transistor stacking in traditional voters, avoids delay differences and timing competition between different input signal paths, ensures that the edges of each input signal can be synchronously judged, thereby supporting GHz-level high-speed clock processing and reducing signal jitter and phase deviation caused by path mismatch. The trigger phase: when the absolute value of the voltage difference between the outputs of the inverting and non-inverting voting circuits reaches the positive feedback trigger threshold of the latch circuit, the latch circuit initiates positive feedback, pulling the high-voltage side of the voltage difference up to the power supply voltage and the low-voltage side down to ground, establishing complementary output signals. The beneficial effect of this stage is that, through the positive feedback mechanism of the latch circuit, the tiny differential voltage generated by the preceding voting circuit is rapidly amplified to a full-swing digital level, significantly shortening the settling time of the output flip and avoiding the propagation delay introduced by multi-stage amplification or complex logic gates. This allows the voter to output a stable complementary clock signal with extremely fast response speed, while consuming dynamic power only at the moment of triggering, keeping the overall power consumption at a low level. Hold stage: The latch circuit maintains the positive feedback latch state, keeping the output stable. The beneficial effect of this stage is that the positive feedback of the latch circuit firmly locks the output level. Even if the output of the positive or negative voting circuit experiences a momentary voltage disturbance due to single-event effect bombardment, as long as the disturbance amplitude does not exceed the hold range of the positive feedback, the latch circuit will automatically restore the disturbance node to the original latch level, thereby effectively suppressing single-event transient effects and ensuring the continuous stability and functional reliability of the output clock signal under radiation conditions. Furthermore, this latch structure requires no additional bias or control circuitry, further simplifying system design and reducing static power consumption. Attached Figure Description

[0009] Figure 1 A circuit diagram for a high-speed clock voting circuit provided for an embodiment of the present invention; Figure 2 The output waveform simulation curve is provided for the embodiments of the present invention; Figure 3 This is a simulation curve of receiving a single-particle bombardment provided in an embodiment of the present invention; Figure 4 Phase response diagram of a phase-locked loop after a single-event upset occurs in a conventional unreinforced phase detector, as provided in an embodiment of the present invention; Figure 5Phase response diagram of the phase-locked loop after a single-event upset occurs in the phase detector reinforced by the voter provided in this embodiment of the invention. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0011] This invention provides a voting device for high-speed clocks, the circuit comprising: a positive voting circuit, an inverting voting circuit, and a latching circuit; The voting machine executes the following three phases sequentially during operation: Discharge stage: The original phase signal and the inverted phase signal of the input signal are synchronously input to the inverted voting circuit and the non-inverted voting circuit, respectively. The inverted voting circuit and the non-inverted voting circuit discharge to ground at the same time according to the majority logic value of the input signal. The signal paths inside the inverted voting circuit and the non-inverted voting circuit are completely symmetrical. The discharge start time of the two output terminals is the same and the discharge path impedance is equal.

[0012] Triggering phase: When the absolute value of the voltage difference between the output terminals of the inverting voting circuit and the non-inverting voting circuit reaches the positive feedback trigger threshold of the latch circuit, the latch circuit starts positive feedback. The latch circuit pulls the high voltage side of the voltage difference up to the power supply voltage and pulls the low voltage side down to ground to establish a complementary output signal.

[0013] Hold phase: The latch circuit maintains the positive feedback latch state, keeping the level corresponding to the complementary output signal.

[0014] For example, see Figure 1 This embodiment provides a voting device for high-speed clocks, the circuit structure of which is as follows: The positive-phase voting circuit is composed of NMOS transistors N13 to N24, the negative-phase voting circuit is composed of NMOS transistors N1 to N12, and the latching circuit is composed of PMOS transistors P1 and P2.

[0015] The working sequence of this embodiment is divided into three stages: Discharge stage: The original phase signal of the input signal , , and its inverted signal , , The inputs are synchronously fed to the inverting voting circuit and the non-inverting voting circuit, respectively. Each circuit discharges its output to ground based on the majority logic value of the input signal. Because the signal paths within the circuits are completely symmetrical, the discharge start times of the two outputs are the same, and the discharge path impedances are equal, ensuring the synchronicity of high-speed judgment.

[0016] Triggering Phase: As the discharge proceeds, a voltage difference is formed between the output terminals of the inverting voting circuit and the non-inverting voting circuit. When the absolute value of this voltage difference reaches the positive feedback trigger threshold of the latch circuit, the latch circuit activates positive feedback, pulling the high-voltage side up to the power supply voltage and the low-voltage side down to ground, quickly establishing a pair of complementary output signals OUT and OUT_N.

[0017] Hold Phase: After the output is established, the latch circuit maintains a positive feedback latch state, stabilizing the level corresponding to the complementary output signal until the next input signal change. Even if subjected to a single-event disturbance, the positive feedback of the latch circuit can automatically restore the output to its original level.

[0018] Input combination , , For example (most logic values ​​are 1): the inverting voting circuit detects that the two original phase signals are high and pulls down their output; the non-inverting voting circuit outputs a high level due to the combination of inverted signals; the voltage difference between the two triggers positive feedback of the latch, and finally OUT outputs a high level and OUT_N outputs a low level.

[0019] Here, the positive feedback of the latching circuit enables the output terminals of the inverting voting circuit and the non-inverting voting circuit to automatically recover to the levels corresponding to the complementary output signals when subjected to single-event disturbances.

[0020] Here, both the positive-phase voting circuit and the negative-phase voting circuit are composed of NMOS transistors.

[0021] Here, both the positive-phase voting circuit and the negative-phase voting circuit adopt a fully symmetrical cross-coupled transistor pair structure, so that the impedance to ground of each input signal path is equal.

[0022] Here, the latching circuit is composed of two PMOS transistors cross-coupled. The sources of the two PMOS transistors are connected to the power supply voltage, and the gates and drains of the two PMOS transistors are cross-coupled to the output terminals of the positive voting circuit and the negative voting circuit, respectively.

[0023] For example, the voting device of the present invention includes a positive-phase voting circuit, a negative-phase voting circuit, and a latching circuit. The positive-phase and negative-phase voting circuits adopt a cross-interconnection structure to judge the input signal and determine the output signal. The latching circuit is connected through cross-coupling to latch the voting device circuit. Compared with traditional voting devices, the high-speed voting device of the present invention adopts a cross-interconnection structure and uses a completely symmetrical differential pair structure to replace the traditional stacked configuration, ensuring that the impedance of each input path is completely consistent, fundamentally eliminating the inherent mismatch caused by transistor stacking. The voting device circuit is composed only of NMOS transistors, which has a higher operating speed than traditional voting devices containing PMOS transistors. The latching circuit has strong resistance to single-event effects. When the circuit is bombarded by a single event and a signal error occurs, the signal can remain unchanged through positive feedback. The voting device circuit of the present invention has a simple structure composed only of transistors, high symmetry, and does not require multi-stage amplification or complex logic judgment. It can maintain high-speed performance while maintaining low static and dynamic power consumption.

[0024] The positive phase voting circuit includes: NMOS transistors N13, NMOS transistor N14, NMOS transistor N15, NMOS transistor N16, NMOS transistor N17, NMOS transistor N18, NMOS transistor N19, NMOS transistor N20, NMOS transistor N21, NMOS transistor N22, NMOS transistor N23, and NMOS transistor N24.

[0025] The gate of NMOS transistor N13 is connected to the fourth input signal. The drain of NMOS transistor N13 is connected to the source of NMOS transistor N15; the source of NMOS transistor N13 is grounded; the gate of NMOS transistor N14 is connected to the fifth input signal. The drain of NMOS transistor N14 is connected to the source of NMOS transistor N16; the source of NMOS transistor N14 is grounded; the gate of NMOS transistor N15 is connected to the fifth input signal. The drain of NMOS transistor N15 is connected to the output of the positive-inverting voting circuit; the gate of NMOS transistor N16 is connected to the fourth input signal. The drain of NMOS transistor N16 is connected to the output of the positive-inverting voting circuit; the gate of NMOS transistor N17 is connected to the fourth input signal. The drain of NMOS transistor N17 is connected to the source of NMOS transistor N19; the source of NMOS transistor N17 is grounded; the gate of NMOS transistor N18 is connected to the sixth input signal. The drain of NMOS transistor N18 is connected to the source of NMOS transistor N20; the source of NMOS transistor N18 is grounded; the gate of NMOS transistor N19 is connected to the sixth input signal. The drain of NMOS transistor N19 is connected to the output of the positive-inverting voting circuit; the gate of NMOS transistor N20 is connected to the fourth input signal. The drain of NMOS transistor N20 is connected to the output of the positive-inverting voting circuit; the gate of NMOS transistor N21 is connected to the fifth input signal. The drain of NMOS transistor N21 is connected to the source of NMOS transistor N23; the source of NMOS transistor N21 is grounded; the gate of NMOS transistor N22 is connected to the sixth input signal. The drain of NMOS transistor N22 is connected to the source of NMOS transistor N24; the source of NMOS transistor N22 is grounded; the gate of NMOS transistor N23 is connected to the sixth input signal. The drain of NMOS transistor N23 is connected to the output of the positive-inverting voting circuit; the gate of NMOS transistor N24 is connected to the fifth input signal. The drain of NMOS transistor N24 is connected to the output of the positive phase voting circuit; the output of the positive phase voting circuit is the common connection point of the drains of NMOS transistors N15, NMOS transistor N16, NMOS transistor N19, NMOS transistor N20, NMOS transistor N23, and NMOS transistor N24.

[0026] Here, the positive-phase voting circuit is composed only of NMOS transistors, which has a higher operating speed compared to traditional voting circuits that include PMOS transistors. The MOS transistors with the same input signal adopt a cross-interconnection structure, which enhances impedance matching and reduces signal mismatch.

[0027] The inverting voting circuit includes: NMOS transistors N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, NMOS transistor N7, NMOS transistor N8, NMOS transistor N9, NMOS transistor N10, NMOS transistor N11, and NMOS transistor N12; The gate of NMOS transistor N1 is connected to the first input signal. The drain of NMOS transistor N1 is connected to the source of NMOS transistor N3; the source of NMOS transistor N1 is grounded; the gate of NMOS transistor N2 is connected to the second input signal. The drain of NMOS transistor N2 is connected to the source of NMOS transistor N4; the source of NMOS transistor N2 is grounded; the gate of NMOS transistor N3 is connected to the second input signal. The drain of NMOS transistor N3 is connected to the output of the inverting voting circuit; the gate of NMOS transistor N4 is connected to the first input signal. The drain of NMOS transistor N4 is connected to the output of the inverting voting circuit; the gate of NMOS transistor N5 is connected to the first input signal. The drain of NMOS transistor N5 is connected to the source of NMOS transistor N7; the source of NMOS transistor N5 is grounded; the gate of NMOS transistor N6 is connected to the third input signal. The drain of NMOS transistor N6 is connected to the source of NMOS transistor N8; the source of NMOS transistor N6 is grounded; the gate of NMOS transistor N7 is connected to the third input signal. The drain of NMOS transistor N7 is connected to the output of the inverting voting circuit; the gate of NMOS transistor N8 is connected to the first input signal. The drain of NMOS transistor N8 is connected to the output of the inverting voting circuit; the gate of NMOS transistor N9 is connected to the second input signal. The drain of NMOS transistor N9 is connected to the source of NMOS transistor N11; the source of NMOS transistor N9 is grounded; the gate of NMOS transistor N10 is connected to the third input signal. The drain of NMOS transistor N10 is connected to the source of NMOS transistor N12; the source of NMOS transistor N10 is grounded; the gate of NMOS transistor N11 is connected to the third input signal. The drain of NMOS transistor N11 is connected to the output of the inverting voting circuit; the gate of NMOS transistor N12 is connected to the second input signal. The drain of NMOS transistor N12 is connected to the output of the inverting voting circuit; the output of the inverting voting circuit is the common connection point of the drains of NMOS transistors N3, NMOS transistor N4, NMOS transistor N7, NMOS transistor N8, NMOS transistor N11, and NMOS transistor N12.

[0028] Here, the inverting voting circuit is composed only of NMOS transistors, which has a higher operating speed than traditional voting circuits that include PMOS transistors. The MOS transistors with the same input signal adopt a cross-coupling structure, which enhances impedance matching and reduces signal mismatch.

[0029] The latching circuit includes: PMOS transistor P1 and PMOS transistor P2; The source of PMOS transistor P1 is connected to the power supply voltage; the gate of PMOS transistor P1 is connected to the output of the positive voting circuit; the drain of PMOS transistor P1 is connected to the output of the negative voting circuit. The source of PMOS transistor P2 is connected to the power supply voltage; the gate of PMOS transistor P2 is connected to the output of the inverting voting circuit; and the drain of PMOS transistor P2 is connected to the output of the non-inverting voting circuit.

[0030] Here, the latch circuit reduces the impact of single-event effects on the output signal of the voting circuit through positive feedback, ensuring signal stability.

[0031] For example, in another implementation, the NMOS transistors in the positive and negative voting circuits can be designed with different aspect ratios to optimize the balance between speed and power consumption. For instance, the aspect ratio of the NMOS transistors involved in discharging (such as N13, N14, N17, N18, N21, N22) can be set to 0.5μm / 0.18μm, while the aspect ratio of the NMOS transistors at the output (such as N15, N16, N19, N20, N23, N24) can be set to 0.8μm / 0.18μm to accelerate the voltage slew rate of the output node. The aspect ratio of the PMOS transistors P1 and P2 in the latch circuit can be set to 0.6μm / 0.18μm to ensure sufficient gain in the positive feedback loop. The above dimensional parameters can be adjusted according to specific process and speed requirements and are not intended to limit the invention.

[0032] The simulation experimental components of this invention are manufactured using SMIC 180nm CMOS technology, and the simulation circuit of this invention is built on the Cadence IC618 simulation experimental platform.

[0033] The circuit of this invention was simulated using the Spectre RF simulation tool, with a given power supply voltage VDD of 1.8V and an operating temperature of 27 degrees Celsius.

[0034] Simulation 1: Under the above working conditions, the present invention was simulated and verified. The results are as follows. Figure 2 As shown, Figure 2 This is a graph showing the output waveform in Simulation 1. Figure 2 The horizontal axis in the graph represents time, with the unit being μs. Figure 2 The vertical axis represents the output signal voltage, in volts (V). During simulation, this is achieved by setting... , , The correct output waveform can be obtained from three input waveforms.

[0035] Simulation 2: Under the above working conditions, a single-particle simulation of the present invention was performed, and the results are as follows. Figure 3 As shown, a single-particle bombardment is performed on the gate of NMOS transistor N1 in branch one. Figure 3 The horizontal axis in the graph represents time, with the unit being μs. Figure 3 The vertical axis represents the output signal voltage, in V. From Figure 3 The simulation results show that the output waveform of the present invention remains normal after being bombarded by a single particle, thus possessing a certain degree of radiation resistance.

[0036] See Figure 4 The phase response of a conventional, unhardened phase detector after a single-event flip is presented. Figure 5 The phase response of the phase detector after a single-event upset (SEE) is given. Figure 4 During the laser scanning of the entire circuit, after a single-event flip occurred every 0.2µs, the phase detector, which was not reinforced with a voter, detected a total of 235 periodic transitions. Figure 5 After the phase detector was hardened using a voting device, only two periodic transitions were detected under the same scanning conditions. Experimental results show that the circuit's resistance to single-event upsets is significantly improved after hardening with a voting device. It can effectively reduce the probability of periodic transitions caused by single-event upsets, accelerate phase recovery, reduce circuit jitter, and thus improve the reliability and radiation resistance of the phase-locked loop system.

[0037] Compared with the prior art, the present invention has the following beneficial technical effects: First, the present invention uses a completely symmetrical differential pair structure to replace the traditional stacking configuration, ensuring that the impedance of each input path to ground is completely consistent, thus fundamentally eliminating the inherent mismatch caused by transistor stacking.

[0038] Second, the present invention adopts a three-level cross-coupling structure to dynamically compensate through redundant paths, avoiding the possibility that a single-event breakdown may cause a certain MOS transistor to be momentarily turned on / off, resulting in clock phase change or charge sharing.

[0039] Third, the present invention has a simple structure and high symmetry, does not require multi-stage amplification or complex logic judgment, can maintain high-speed performance while maintaining low static and dynamic power consumption, and has a certain degree of radiation resistance.

[0040] Fourth, the latching circuit of this invention can form positive feedback, which can further suppress glitches and single-event effects, and improve the robustness and functional continuity of the voting device in a radiation environment.

[0041] Fifth, the voting circuit of this invention is composed only of NMOS transistors, which has a higher operating speed compared to traditional voting circuits that contain PMOS transistors.

[0042] The embodiments given above are preferred examples for implementing the present invention, and the present invention is not limited to the above embodiments. Any non-essential additions or substitutions made by those skilled in the art based on the technical features of the present invention are within the protection scope of the present invention. The various embodiments described in this specification are presented in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. All or part of this invention can be used in numerous general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, mobile communication terminals, multiprocessor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices, etc.

[0043] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present invention.

Claims

1. A voting device for high-speed clocks, characterized in that, include: Positive voting circuit, negative voting circuit, and latch circuit; The voting device executes the following three phases sequentially during operation: Discharge phase: The original phase signal and the inverted phase signal of the input signal are synchronously input to the inverted voting circuit and the non-inverted voting circuit, respectively. The inverted voting circuit and the non-inverted voting circuit simultaneously discharge their output terminals to ground according to the majority logic value of the input signal. The signal paths inside the inverted voting circuit and the non-inverted voting circuit are completely symmetrical, and the discharge start time of the two output terminals is the same and the discharge path impedance is equal. Triggering phase: When the absolute value of the voltage difference between the output terminal of the inverting voting circuit and the output terminal of the non-inverting voting circuit reaches the positive feedback trigger threshold of the latch circuit, the latch circuit starts positive feedback, and the latch circuit pulls up the high voltage side of the voltage difference to the power supply voltage and pulls down the low voltage side to ground to establish a complementary output signal; Hold phase: The latching circuit maintains a positive feedback latching state, keeping the level corresponding to the complementary output signal.

2. The voting device for a high-speed clock according to claim 1, characterized in that, The positive feedback of the latch circuit enables the output terminals of the inverting voting circuit and the non-inverting voting circuit to automatically recover to the level corresponding to the complementary output signal when subjected to a single-event disturbance.

3. The voting device for a high-speed clock according to claim 1, characterized in that, Both the positive-phase voting circuit and the negative-phase voting circuit are composed of NMOS transistors.

4. The voting device for a high-speed clock according to claim 1, characterized in that, Both the positive-phase voting circuit and the negative-phase voting circuit adopt a fully symmetrical cross-coupled transistor pair structure, so that the impedance to ground of each input signal path is equal.

5. The voting device for a high-speed clock according to claim 1, characterized in that, The latching circuit is composed of two cross-coupled PMOS transistors. The sources of the two PMOS transistors are connected to the power supply voltage, and the gates and drains of the two PMOS transistors are respectively cross-connected to the output terminals of the positive voting circuit and the negative voting circuit.

6. The voting device for a high-speed clock according to claim 1, characterized in that, The positive phase voting circuit includes: NMOS transistors N13, NMOS transistor N14, NMOS transistor N15, NMOS transistor N16, NMOS transistor N17, NMOS transistor N18, NMOS transistor N19, NMOS transistor N20, NMOS transistor N21, NMOS transistor N22, NMOS transistor N23, and NMOS transistor N24; The gate of the NMOS transistor N13 is connected to the fourth input signal. The drain of NMOS transistor N13 is connected to the source of NMOS transistor N15; the source of NMOS transistor N13 is grounded. The gate of the NMOS transistor N14 is connected to the fifth input signal. The drain of the NMOS transistor N14 is connected to the source of the NMOS transistor N16; the source of the NMOS transistor N14 is grounded. The gate of the NMOS transistor N15 is connected to the fifth input signal. The drain of the NMOS transistor N15 is connected to the output terminal of the positive-phase voting circuit. The gate of the NMOS transistor N16 is connected to the fourth input signal. The drain of the NMOS transistor N16 is connected to the output terminal of the positive-phase voting circuit. The gate of the NMOS transistor N17 is connected to the fourth input signal. The drain of the NMOS transistor N17 is connected to the source of the NMOS transistor N19; the source of the NMOS transistor N17 is grounded. The gate of the NMOS transistor N18 is connected to the sixth input signal. The drain of the NMOS transistor N18 is connected to the source of the NMOS transistor N20; the source of the NMOS transistor N18 is grounded. The gate of the NMOS transistor N19 is connected to the sixth input signal. The drain of the NMOS transistor N19 is connected to the output terminal of the positive-phase voting circuit. The gate of the NMOS transistor N20 is connected to the fourth input signal. The drain of the NMOS transistor N20 is connected to the output terminal of the positive-phase voting circuit. The gate of the NMOS transistor N21 is connected to the fifth input signal. The drain of the NMOS transistor N21 is connected to the source of the NMOS transistor N23; the source of the NMOS transistor N21 is grounded. The gate of the NMOS transistor N22 is connected to the sixth input signal. The drain of the NMOS transistor N22 is connected to the source of the NMOS transistor N24; the source of the NMOS transistor N22 is grounded. The gate of the NMOS transistor N23 is connected to the sixth input signal. The drain of the NMOS transistor N23 is connected to the output terminal of the positive-phase voting circuit. The gate of the NMOS transistor N24 is connected to the fifth input signal. The drain of the NMOS transistor N24 is connected to the output terminal of the positive-phase voting circuit. The output terminal of the positive phase voting circuit is the common connection point of the drains of NMOS transistors N15, NMOS transistor N16, NMOS transistor N19, NMOS transistor N20, NMOS transistor N23, and NMOS transistor N24.

7. The voting device for a high-speed clock according to claim 1, characterized in that, The inverted voting circuit includes: NMOS transistors N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, NMOS transistor N7, NMOS transistor N8, NMOS transistor N9, NMOS transistor N10, NMOS transistor N11, and NMOS transistor N12; The gate of the NMOS transistor N1 is connected to the first input signal. The drain of the NMOS transistor N1 is connected to the source of the NMOS transistor N3; the source of the NMOS transistor N1 is grounded. The gate of the NMOS transistor N2 is connected to the second input signal. The drain of the NMOS transistor N2 is connected to the source of the NMOS transistor N4; the source of the NMOS transistor N2 is grounded. The gate of the NMOS transistor N3 is connected to the second input signal. The drain of the NMOS transistor N3 is connected to the output of the inverting voting circuit. The gate of the NMOS transistor N4 is connected to the first input signal. The drain of the NMOS transistor N4 is connected to the output of the inverting voting circuit. The gate of the NMOS transistor N5 is connected to the first input signal. The drain of the NMOS transistor N5 is connected to the source of the NMOS transistor N7; the source of the NMOS transistor N5 is grounded. The gate of the NMOS transistor N6 is connected to the third input signal. The drain of NMOS transistor N6 is connected to the source of NMOS transistor N8; the source of NMOS transistor N6 is grounded. The gate of the NMOS transistor N7 is connected to the third input signal. The drain of the NMOS transistor N7 is connected to the output of the inverting voting circuit. The gate of the NMOS transistor N8 is connected to the first input signal. The drain of the NMOS transistor N8 is connected to the output of the inverting voting circuit. The gate of the NMOS transistor N9 is connected to the second input signal. The drain of NMOS transistor N9 is connected to the source of NMOS transistor N11; the source of NMOS transistor N9 is grounded. The gate of the NMOS transistor N10 is connected to the third input signal. The drain of the NMOS transistor N10 is connected to the source of the NMOS transistor N12; the source of the NMOS transistor N10 is grounded. The gate of the NMOS transistor N11 is connected to the third input signal. The drain of the NMOS transistor N11 is connected to the output of the inverting voting circuit. The gate of the NMOS transistor N12 is connected to the second input signal. The drain of the NMOS transistor N12 is connected to the output of the inverting voting circuit. The output terminal of the inverting voting circuit is the common connection point of the drains of NMOS transistors N3, NMOS transistor N4, NMOS transistor N7, NMOS transistor N8, NMOS transistor N11, and NMOS transistor N12.

8. The voting device for a high-speed clock according to claim 1, characterized in that, The latching circuit includes: PMOS transistor P1 and PMOS transistor P2; The source of the PMOS transistor P1 is connected to the power supply voltage; the gate of the PMOS transistor P1 is connected to the output terminal of the positive voting circuit; and the drain of the PMOS transistor P1 is connected to the output terminal of the negative voting circuit. The source of the PMOS transistor P2 is connected to the power supply voltage; the gate of the PMOS transistor P2 is connected to the output terminal of the inverting voting circuit; and the drain of the PMOS transistor P2 is connected to the output terminal of the non-inverting voting circuit.

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