Active miller clamp circuit, control method thereof and IGBT driving circuit

Abstract

The application discloses an active Miller clamp circuit, a control method thereof and an IGBT driving circuit, and through the cooperative architecture of a voltage monitoring module, a logic control module and a clamp driving module, a digital latch control logic with a D flip-flop unit as a core is constructed; the voltage monitoring module collects IGBT gate voltage in real time and outputs a judgment signal; in the logic control module, a first inverter unit converts an external driving signal into a reset signal and inputs the reset signal into a reset end of the D flip-flop unit; a data input end of the D flip-flop unit is fixedly connected with a high-level power supply, a clock input end receives an output signal of the voltage monitoring module, and an output end outputs a first logic control signal to the clamp driving module, so that the timing control of starting the clamp as needed only in the IGBT off stage is realized; the circuit discards the traditional analog control logic, effectively avoids the false triggering problem caused by process deviation, temperature drift and parameter discreteness, and greatly improves the working stability under the high-frequency switching and electromagnetic interference environment.

Description

Technical Field

[0001] This application relates to the field of IGBT drive circuit technology, and in particular to an active Miller clamp circuit and its control method, and an IGBT drive circuit. Background Technology

[0002] With the rapid development of power electronics technology, semiconductor process technology, and high-frequency power conversion control technology, power semiconductor devices have become core components in modern energy conversion systems. Among them, the Insulated Gate Bipolar Transistor (IGBT) combines the advantages of high input impedance and high drive efficiency of the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) with the advantages of low on-state voltage drop and high current carrying capacity of the Bipolar Junction Transistor (BJT), thus finding widespread application in medium- and high-voltage, high-power applications. Currently, IGBTs have become key power switching devices in new energy vehicle drive systems, rail transit traction systems, industrial frequency converters, photovoltaic inverters, wind power converters, uninterruptible power supplies (UPS), energy storage converters, and flexible DC transmission systems.

[0003] Existing active Miller clamping circuits mostly use analog control logic. The circuit's operating characteristics are easily affected by semiconductor device process deviations, ambient temperature drift, and device parameter dispersion. In high-frequency switching conditions and electromagnetic interference environments, false triggering problems are prone to occur. Summary of the Invention

[0004] The technical problem to be solved by this application is that existing active Miller clamping circuits mostly use analog control logic. The circuit operating characteristics are easily affected by semiconductor device process deviations, ambient temperature drift, and device parameter dispersion. In high-frequency switching conditions and electromagnetic interference environments, false triggering problems are likely to occur.

[0005] To address the aforementioned issues, this application provides an active Miller clamping circuit and its control method, as well as an IGBT driving circuit.

[0006] In a first aspect, the present invention discloses an active Miller clamping circuit, which includes a voltage monitoring module, a logic control module, and a clamping drive module. The voltage monitoring module is connected to the clamping drive module and the logic control module, and the clamping drive module is connected to the logic control module. The logic control module includes a D flip-flop unit and a first inverter unit. The first inverter unit acquires an external drive signal, and its output signal is connected to the reset terminal of the D flip-flop unit. The clock input terminal of the D flip-flop unit is connected to the voltage monitoring module, the data input terminal of the D flip-flop unit acquires a high-level power supply, and the output terminal of the D flip-flop unit outputs a first logic control signal to the clamping drive module.

[0007] Preferably, the voltage monitoring module includes a high-speed comparator unit and a reference voltage generation unit, and the high-speed comparator unit and the reference voltage generation unit are connected. The reference voltage generation unit outputs a reference voltage, the inverting input of the high-speed comparator unit obtains the real-time gate voltage of the IGBT, and the non-inverting input obtains the reference voltage.

[0008] Preferably, the clamping drive module includes a power clamping transistor unit, a high-position NMOS transistor unit, a low-position NMOS transistor unit, and a second inverter unit. The power clamping transistor unit is connected to the high-position NMOS transistor unit and the low-position NMOS transistor unit, respectively, and the second inverter unit is connected to the low-position NMOS transistor unit. The high-order NMOS transistor unit acquires the logic control signal, the second inverter unit acquires the logic control signal and outputs the second logic control signal, and the low-order NMOS transistor unit acquires the second logic control signal. The high-order NMOS transistor unit and the low-order NMOS transistor unit perform fast charge and discharge control on the gate of the power clamping transistor unit.

[0009] Secondly, the present invention discloses an IGBT driving circuit, including the above-mentioned active Miller clamping circuit.

[0010] Preferably, it includes a PWM input module, a gate main drive module, a gate voltage detection module, a programmable threshold module, a high-speed Miller disturbance detection module, and a fault linkage control module. The PWM input module is connected to the gate main drive module, and the gate voltage detection module is also connected to the gate main drive module. The gate voltage detection module is further connected to the active Miller clamp circuit and the fault linkage control module. The programmable threshold module is connected to the fault linkage control module and the gate main drive module respectively.

[0011] Preferably, the gate main drive module includes a gate drive unit, a pull-up drive unit, a pull-down drive unit, and a soft turn-off unit, with the gate drive unit connected to the pull-up drive unit, the pull-down drive unit, and the soft turn-off unit, respectively.

[0012] Preferably, the fault linkage control module includes a fault linkage control unit, an overcurrent detection unit, and an overtemperature detection unit, with the fault linkage control unit connected to the overcurrent detection unit and the overtemperature detection unit respectively.

[0013] Preferably, the high-speed Miller disturbance detection module includes a comparator unit and a Miller disturbance detection unit, and the gate voltage detection module is connected to the comparator unit and the Miller disturbance detection unit respectively.

[0014] Preferably, the programmable threshold module generates a rapid disturbance threshold, an overcurrent threshold, and an overtemperature threshold; the overcurrent threshold is configured to the overcurrent detection unit, and the overtemperature threshold is configured to the overtemperature detection unit. A fast disturbance threshold is configured in the high-speed Miller disturbance detection module. When the high-speed Miller disturbance detection module detects that the actual gate voltage exceeds the fast disturbance threshold, it outputs a disturbance trigger signal.

[0015] Thirdly, this invention discloses an active Miller clamp circuit control method, applicable to the aforementioned active Miller clamp circuit, comprising, When the external drive signal is high, the IGBT is turned on. As the external drive signal transitions from high to low, the IGBT gate voltage continuously decreases. This process includes the following steps: When the IGBT gate voltage is higher than 2V, the output signal of the high-speed comparator unit remains low, and the power clamping transistor unit remains off. When the IGBT gate voltage is below 2V, the high-speed comparator unit output signal generates a rising edge, triggering the D flip-flop unit to flip, the logic control signal changes from low level to high level, the high-order NMOS transistor unit is turned on, the low-order NMOS transistor unit is turned off, the gate level of the power clamp transistor unit rises rapidly, driving the power clamp transistor unit into a strong conduction state.

[0016] The technical solution provided in this application has the following advantages compared with the prior art: This invention discloses an active Miller clamp circuit and its control method, as well as an IGBT driving circuit. The active Miller clamp circuit describes a digital latch control logic centered on a D flip-flop unit, constructed through a collaborative architecture of a voltage monitoring module, a logic control module, and a clamp driving module. The voltage monitoring module acquires the IGBT gate voltage in real time and outputs a judgment signal. In the logic control module, a first inverter unit converts the external driving signal into a reset signal and connects it to the reset terminal of the D flip-flop unit. The data input terminal of the D flip-flop unit is fixedly connected to a high-level power supply, the clock input terminal receives the output signal from the voltage monitoring module, and the output terminal outputs the first logic control signal to the clamp driving module. This achieves timing control that enables clamping only during the IGBT turn-off phase. This circuit abandons traditional analog control logic, effectively avoiding false triggering problems caused by process deviations, temperature drift, and parameter dispersion, and significantly improving the working stability under high-frequency switching and electromagnetic interference environments.

[0017] The IGBT driver circuit mentions that by integrating the aforementioned active Miller clamp circuit, a driver architecture that combines reliable driving and Miller suppression capabilities is constructed. Utilizing the digital latching control characteristics of the active Miller clamp circuit, it can accurately respond to gate voltage changes and quickly discharge Miller current during the IGBT turn-off phase. At the same time, it can forcibly disable the clamping function during the IGBT turn-on phase to avoid interference with the normal driving process. This not only solves the problems of easy false triggering and poor reliability of analog clamping in traditional driver circuits, but also eliminates the need for additional complex auxiliary circuits such as negative voltage power supplies. It achieves a dual improvement in driving performance and system integration, making it suitable for high-frequency, high-reliability power electronic equipment application scenarios.

[0018] The active Miller clamping circuit control method mentions that precise triggering and execution of the clamping function are achieved through staged timing control. When the external drive signal is high, the IGBT is turned on, and the clamping function is in a forced off state. When the external drive signal turns low, in the initial turn-off phase when the IGBT gate voltage is higher than 2V, the high-speed comparator unit outputs a low level, and the power clamping transistor unit remains off, without affecting the normal turn-off process of the device. When the gate voltage is lower than 2V, the rising edge of the output of the high-speed comparator unit triggers the D flip-flop unit to flip, the high-order NMOS transistor unit is turned on, and the low-order NMOS transistor unit is turned off, causing the gate level of the power clamping transistor unit to rise rapidly and enter a strong conduction state, discharging the IGBT gate to ground with low impedance. This method achieves precise and stable triggering of the clamping function through clear voltage threshold determination and digital latching logic. From the control process level, it completely avoids the problem of false triggering caused by environmental interference that is easily affected by analog control logic, ensuring the Miller suppression effect and operational reliability during the IGBT turn-off phase.

[0019] Furthermore, it can effectively suppress IGBT parasitic conduction without relying on a negative voltage power supply; at the same time, it has high clamping current capability and fast response characteristics to adapt to high dv / dt application environments. In addition, the solution has good threshold control accuracy and process consistency, thereby ensuring stable operation under different temperature and operating conditions.

[0020] Furthermore, this technical solution balances EMI performance and device safety, avoiding additional voltage spikes caused by premature clamping. At the same time, its circuit structure is simple and can be fully integrated under standard BCD technology, thereby reducing the number of external components and reducing system design complexity. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A structural block diagram of an active Miller clamp circuit provided in this application; Figure 2 A circuit diagram of an active Miller clamp circuit provided in this application; Figure 3 A structural block diagram of an IGBT driver circuit provided in this application; Figure 4 A circuit diagram of an IGBT drive circuit provided in this application.

[0024] Explanation of reference numerals in the attached figures: 100. IGBT drive circuit; 1. Active Miller clamping circuit; 11. Voltage monitoring module; 111. High-speed comparator unit; 12. Logic control module; 121. D flip-flop unit; 122. First inverter unit; 13. Clamping drive module; 131. Power clamping transistor unit; 132. High-position NMOS transistor unit; 133. Low-position NMOS transistor unit; 134. Second inverter unit; 2. PWM input module; 3. Gate main drive module; 31. Gate drive unit; 32. Pull-up drive unit; 33. Pull-down drive unit; 34. Soft turn-off unit; 4. Gate voltage detection module; 5. Programmable threshold module; 6. High-speed Miller disturbance detection module; 61. Comparator unit; 62. Miller disturbance detection unit; 7. Fault linkage control module; 71. Fault linkage control unit; 72. Overcurrent detection unit; 73. Overtemperature detection unit. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] Firstly, see reference Figures 1-2 This invention discloses an active Miller clamping circuit 1, which includes a voltage monitoring module 11, a logic control module 12, and a clamping drive module 13. The voltage monitoring module 11 is connected to the clamping drive module 13 and the logic control module 12, and the clamping drive module 13 is connected to the logic control module 12. The voltage monitoring module 11 is used to detect the change of IGBT gate potential in real time. The logic control module 12 is used to identify the current working state of the device and generate a clamping control signal according to the detection result. The clamping drive module 13 is used to quickly establish a low-impedance discharge path when the trigger condition is met, so as to realize the rapid absorption of Miller current.

[0027] The logic control module 12 includes a D flip-flop unit 121 and a first inverter unit 122. The first inverter unit acquires an external drive signal, and its output signal is connected to the reset terminal of the D flip-flop unit 121. The clock input terminal of the D flip-flop unit 121 is connected to the voltage monitoring module 11. The data input terminal of the D flip-flop unit 121 acquires a high-level power supply, and the output terminal of the D flip-flop unit 121 outputs a first logic control signal to the clamping drive module 13.

[0028] Specifically, through the collaborative architecture of voltage monitoring module 11, logic control module 12, and clamping drive module 13, a digital latching control logic with D flip-flop unit 121 as the core is constructed: voltage monitoring module 11 collects IGBT gate voltage in real time and outputs a judgment signal; in logic control module 12, first inverter unit 122 converts external drive signal into reset signal and connects it to the reset terminal of D flip-flop unit 121; the data input terminal of D flip-flop unit 121 is fixedly connected to a high-level power supply, the clock input terminal receives the output signal of voltage monitoring module 11, and the output terminal outputs the first logic control signal to clamping drive module 13, realizing the timing control of clamping only when needed during IGBT turn-off. This circuit abandons traditional analog control logic, effectively avoids the false triggering problems caused by process deviation, temperature drift, and parameter dispersion, and greatly improves the working stability under high-frequency switching and electromagnetic interference environments.

[0029] Furthermore, it can effectively suppress IGBT parasitic conduction without relying on a negative voltage power supply; at the same time, it has high clamping current capability and fast response characteristics to adapt to high dv / dt application environments. In addition, the solution has good threshold control accuracy and process consistency, thereby ensuring stable operation under different temperature and operating conditions.

[0030] Furthermore, this technical solution balances EMI performance and device safety, avoiding additional voltage spikes caused by premature clamping. At the same time, its circuit structure is simple and can be fully integrated under standard BCD technology, thereby reducing the number of external components and reducing system design complexity.

[0031] Specifically, in the logic control module 12, the data input terminal D of the D flip-flop unit 121 is connected to the logic high-level power supply VDD, its clock input terminal CLK is connected to the comparator output terminal, and its reset terminal R receives the inverted signal of the external drive signal DRV. When the external drive signal DRV is high, it indicates that the IGBT is in the on state. At this time, the inverted signal of the external drive signal is low, and the D flip-flop unit 121 is forcibly reset, and its output terminal SW1 remains low. In this state, the entire Miller clamp circuit is in the off mode, so it will not interfere with the normal conduction process of the IGBT, nor will it increase the driver output current burden. When the external drive signal DRV flips from high to low, the IGBT begins to enter the turn-off process. At this time, the inverted signal of the external drive signal becomes high, the D flip-flop unit 121 is released from the reset restriction, and the logic control module enters the ready-to-trigger state. Subsequently, when the comparator in the voltage detection unit detects that the gate voltage is lower than 2V, its output generates a rising edge and drives the D flip-flop unit 121 to flip. Since the D terminal is always connected to a high level, the output terminal SW1 is latched to a high level state after triggering.

[0032] The logic control module 12 offers the following advantages: First, it ensures that the clamping action is only triggered after the IGBT enters the turn-off phase, thus avoiding malfunctions during conduction. Second, it utilizes a latching structure to maintain a stable clamping state, preventing repeated flipping in high-frequency noise environments. Third, it improves the consistency and reliability of the clamping action, avoiding functional abnormalities caused by threshold drift in traditional analog schemes. Furthermore, the logic control structure in this embodiment employs an asynchronous reset method, so when the external drive signal DRV returns to a high level, the clamping function can be immediately disabled, ensuring that it does not affect the next IGBT conduction process. In addition, the logic control module 12 in this embodiment can automatically complete state switching according to the system timing, thus achieving adaptive operation without additional software control, making it suitable for high-speed power drive scenarios.

[0033] The voltage monitoring module 11 includes a high-speed comparator unit 111 and a reference voltage generation unit. The high-speed comparator unit 111 is connected to the reference voltage generation unit. The reference voltage generation unit outputs a reference voltage. The inverting input terminal of the high-speed comparator unit 111 obtains the real-time gate voltage of the IGBT and the non-inverting input terminal obtains the reference voltage.

[0034] Specifically, the inverting input of the high-speed comparator unit 111 is connected to the IGBT gate sampling node CLAMP for real-time acquisition of the actual gate voltage VGE of the power device. The non-inverting input of the high-speed comparator unit 111 is connected to the internal reference voltage VREF. In this embodiment, the reference voltage is preferably set to 2V.

[0035] The high-speed comparator unit 111 can adopt a high-speed, low-offset structure to improve the response capability in high dv / dt environments. Furthermore, to improve system noise immunity, a small hysteresis window can be introduced inside the comparator to prevent false triggering caused by parasitic oscillations or noise spikes. In actual operation, when the voltage of the sampling node CLAMP is higher than 2V, the comparator output remains low. When the CLAMP node voltage drops below 2V, the comparator output flips to high and outputs a trigger signal to the subsequent logic control module. In this embodiment, the trigger threshold is set near 2V, not through simple empirical setting, but through comprehensive optimization combining the IGBT turn-off characteristic curve and system EMI performance. Since the typical turn-on threshold of industrial-grade IGBT devices is usually between 4V and 6V, the 2V threshold ensures that the clamping action occurs after the device has essentially completed turn-off, and also establishes a discharge path in time before high dv / dt interference occurs on the opposite bridge arm. Compared to some traditional high-threshold clamping schemes, this embodiment avoids premature activation of the clamping MOS during the rapid decline of the IGBT current, thereby effectively reducing the VCE voltage spike problem caused by the increase of di / dt. Furthermore, the comparator output in this embodiment is directly connected to the clock input of the logic control module, thus enabling the rapid generation of an edge-triggered signal when the gate voltage exceeds the threshold, improving the dynamic response speed of the entire system.

[0036] Clamp drive module 13 includes power clamp transistor unit 131 ( Figure 2 N1 in the middle), high-position NMOS transistor unit 132 ( Figure 2 N2 in the middle), low-position NMOS transistor unit 133 ( Figure 2 The N3), the second inverter unit 134, and the power clamping transistor unit 131 are respectively connected to the high-level NMOS transistor unit 132 and the low-level NMOS transistor unit 133. The second inverter unit is connected to the low-level NMOS transistor unit 133. The high-level NMOS transistor unit 132 obtains the logic control signal, the second inverter unit 134 obtains the logic control signal and outputs the second logic control signal, and the low-level NMOS transistor unit 133 obtains the second logic control signal. The high-level NMOS transistor unit 132 and the low-level NMOS transistor unit 133 perform fast charge and discharge control on the gate of the power clamping transistor unit 131.

[0037] Specifically, in this embodiment, the clamping drive unit mainly includes a high-level NMOS transistor unit 132, a low-level NMOS transistor unit 133, and a power clamping transistor unit 131. The high-level NMOS transistor unit 132 and the low-level NMOS transistor unit 133 form a complementary push-pull drive structure for fast charging and discharging control of the gate node SW3 of the power clamping transistor unit 131. The drain of the high-level NMOS transistor unit 132 is connected to a high potential VHB, its gate receives the output signal SW1 from the logic control module, and its source outputs the control signal SW3. The drain of the low-level NMOS transistor unit 133 is connected to the SW3 node, its gate receives the reverse signal SW2 of SW1, and its source is grounded. When SW1 is low, the high-level NMOS transistor unit 132 is turned off, the low-level NMOS transistor unit 133 is turned on, and SW3 is quickly pulled low to ground, thereby keeping the power clamping transistor unit 131 in a turned-off state. When SW1 flips to a high level, the low-level NMOS transistor unit 133 is quickly turned off, while the high-level NMOS transistor unit 132 is turned on, and the SW3 node is quickly raised to a high level, causing the power clamping transistor unit 131 to quickly enter the conducting state.

[0038] Compared to traditional single-stage MOS driving methods, the dual NMOS push-pull driving structure of this invention significantly improves the gate driving speed of the power transistor, thereby effectively reducing the turn-on delay time of the power clamping transistor unit 131 and improving the response capability to transient Miller current. Furthermore, the power clamping transistor unit 131 preferably uses a low on-resistance LDMOS device, with its drain connected to the CLAMP sampling node and its source directly grounded. After the power clamping transistor unit 131 is turned on, an extremely low impedance discharge path can be formed between the IGBT gate and emitter, allowing the Miller current to preferentially discharge to ground through the power clamping transistor unit 131 without creating a significant voltage drop across the external gate resistor RG or the internal impedance of the driver.

[0039] In this embodiment, the device size of the power clamping transistor unit 131 has been specially optimized to provide a transient peak discharge capability of not less than 3A, thus making it suitable for high bus voltage, high power and high dv / dt application environments.

[0040] Furthermore, since the high-position NMOS transistor unit 132 adopts a source follower output structure, it can naturally limit the voltage of the SW3 node, thereby ensuring that the gate-source voltage of the power clamp transistor unit 131 operates within a safe range and improving the long-term operational reliability of the chip.

[0041] Secondly, see Figures 3-4This invention discloses an IGBT driving circuit 100, including the aforementioned active Miller clamp circuit 1, PWM input module 2, gate main drive module 3, gate voltage detection module 4, programmable threshold module 5, high-speed Miller disturbance detection module 6, and fault linkage control module 7. The PWM input module 2 is connected to the gate main drive module 3, the gate voltage detection module 4 is connected to the gate main drive module 3, the gate voltage detection module 4 is connected to both the active Miller clamp circuit and the fault linkage control module 7, and the programmable threshold module 5 is connected to both the fault linkage control module 7 and the gate main drive module 3.

[0042] Specifically, the PWM input module receives external pulse width modulation signals, completes electrical isolation and dead-time timing processing, and outputs IGBT turn-on / turn-off commands to the gate main drive module 3, serving as the timing and control signal source for the entire drive circuit. The gate main drive module 3 receives control commands from the PWM input module, enabling normal IGBT turn-on, normal turn-off, and soft turn-off under fault conditions, and completing the charging and discharging of the gate charge; it is the core execution unit for driving IGBT switching actions. The gate voltage detection module 4 collects IGBT data in real time. The actual gate voltage is fed back to the gate main drive module 3 for auxiliary condition judgment, and simultaneously sent to the active Miller clamp circuit 1 and the fault linkage control module 7 to provide raw sampling data for clamp triggering and fault determination. The programmable threshold module 5 integrates a multi-Vref architecture, which provides multiple completely independent reference voltage sources unaffected by power supply fluctuations. The programmable threshold module 5 is used to independently configure the clamping on threshold V_CL_EN, fast disturbance threshold V_CL_FAST, overcurrent threshold V_OC, and overtemperature threshold T_OT. The high-speed Miller disturbance detection module 6 is used to detect the rise amplitude or rise slope of the gate voltage in the off state. When the actual gate voltage exceeds the fast disturbance threshold V_CL_FAST, or its rate of change exceeds the preset slope, a disturbance trigger signal is output. The active Miller clamp circuit 1 receives the sampling signal from the gate voltage detection module 4, and accurately triggers the clamping path based on digital logic to quickly discharge Miller current and suppress IGBT. Parasitic false triggering avoids the defects of analog circuits being prone to false triggering; the fault linkage control module 7 relies on programmable threshold and gate voltage detection signal to judge fault states such as overcurrent and overtemperature. When a fault occurs, it links the gate main drive module 3 to perform soft shutdown and controls the active Miller clamp circuit 1 to continue working, thus constructing a complete fault protection link to prevent device damage and secondary false triggering.

[0043] It is understandable that the IGBT drive circuit 100, by integrating the aforementioned active Miller clamp circuit 1, constructs a drive architecture that combines reliable drive and Miller suppression capabilities. Utilizing the digital latching control characteristics of the active Miller clamp circuit 1, it can accurately respond to changes in gate voltage and quickly discharge Miller current during the IGBT turn-off phase. At the same time, it can forcibly disable the clamping function during the IGBT turn-on phase to avoid interference with the normal drive process. This solves the problems of easy false triggering and poor reliability of analog clamping in traditional drive circuits, and eliminates the need for additional complex auxiliary circuits such as negative voltage power supplies. It achieves a dual improvement in drive performance and system integration, making it suitable for high-frequency, high-reliability power electronic equipment application scenarios.

[0044] The gate main drive module 3 includes a gate drive unit 31, a pull-up drive unit 32, a pull-down drive unit 33, and a soft turn-off unit 34. The gate drive unit 31 is connected to the pull-up drive unit 32, the pull-down drive unit 33, and the soft turn-off unit 34, respectively.

[0045] Specifically, the gate drive unit 31 serves as the core control terminal and is connected to the pull-up drive unit 32, the pull-down drive unit 33, and the soft turn-off unit 34, respectively. The gate drive unit 31 receives front-end control commands and coordinates the work of each branch. The pull-up drive unit 32 is responsible for charging the IGBT gate to achieve normal device conduction. The pull-down drive unit 33 completes the gate charge discharge under normal operating conditions to achieve normal device turn-off. The soft turn-off unit 34 slowly releases the gate charge under fault conditions to suppress turn-off voltage spikes.

[0046] The fault linkage control module 7 includes a fault linkage control unit 71, an overcurrent detection unit 72, and an overtemperature detection unit 73. The fault linkage control unit 71 is connected to the overcurrent detection unit 72 and the overtemperature detection unit 73 respectively.

[0047] Specifically, the fault linkage control module 7 consists of a fault linkage control unit 71, an overcurrent detection unit 72, and an overtemperature detection unit 73. The fault linkage control unit 71 is connected to the overcurrent detection unit 72 and the overtemperature detection unit 73 respectively. The overcurrent detection unit 72 monitors the main circuit current in real time, and the overtemperature detection unit 73 monitors the device operating temperature in real time. The two transmit the detection results to the fault linkage control unit 71. The fault linkage control unit 71 triggers the protection logic in a coordinated manner according to the fault signal, and links the back-end circuit to perform soft shutdown and clamping protection actions.

[0048] The high-speed Miller disturbance detection module 6 includes a comparator unit 61 and a Miller disturbance detection unit 62. The gate voltage detection module 4 is connected to the comparator unit 61 and the Miller disturbance detection unit 62 respectively.

[0049] Specifically, the high-speed Miller disturbance detection module 6 includes a comparator unit 61 and a Miller disturbance detection unit 62. The gate voltage detection module 4 is connected to both the comparator unit 61 and the Miller disturbance detection unit 62, providing real-time gate voltage sampling signals to both units. The comparator unit 61 determines the gate voltage amplitude by combining a threshold value, and the Miller disturbance detection unit 62 detects the rate of change of the gate voltage. The two work together to identify voltage abnormal disturbances caused by the Miller effect.

[0050] Programmable threshold module 5 generates fast disturbance threshold, overcurrent threshold and overtemperature threshold. Overcurrent threshold is configured to overcurrent detection unit 72, overtemperature threshold is configured to overtemperature detection unit, and fast disturbance threshold is configured to high-speed Miller disturbance detection module 6. High-speed Miller disturbance detection module 6 detects that the actual gate voltage exceeds the fast disturbance threshold and outputs a disturbance trigger signal.

[0051] Specifically, the programmable threshold module 5 is responsible for generating the fast disturbance threshold, overcurrent threshold, and overtemperature threshold. The overcurrent threshold is sent to the overcurrent detection unit 72, the overtemperature threshold is sent to the overtemperature detection unit 73, and the fast disturbance threshold is configured to the high-speed Miller disturbance detection module 6. When the high-speed Miller disturbance detection module 6 detects that the actual gate voltage exceeds the fast disturbance threshold, it will output a disturbance trigger signal to start subsequent Miller suppression related actions.

[0052] Thirdly, this invention discloses an active Miller clamp circuit control method, applicable to the aforementioned active Miller clamp circuit, comprising, Step S1: When the external drive signal is high, the IGBT is turned on; Step S2: The external drive signal changes from high level to low level, and the IGBT gate voltage continues to decrease.

[0053] Specifically, in step S1, when the external drive signal is high, the circuit drives the IGBT to enter the conduction state, the D flip-flop unit is forcibly reset, SW1 remains at a low level, and since the high-order NMOS transistor unit N2 is off and the low-order NMOS transistor unit N3 is on, the SW3 node is pulled low, and the power clamping transistor unit N1 remains off. During this stage, the active Miller clamping circuit presents a high impedance state with the IGBT gate, so it will not affect the gate charging process during the normal conduction of the IGBT, nor will it reduce the device conduction speed. At this time, the clamping-related logic remains silent and will not intervene in the gate circuit, which ensures the normal and stable turn-on of the IGBT and avoids the clamping circuit from adding extra drive load and affecting the device conduction performance.

[0054] Specifically, in step S2, after the external drive signal switches from high level to low level, the IGBT enters the turn-off process, the gate charge begins to be released, and the gate voltage gradually decreases. This stage is the starting process of normal IGBT turn-off. The circuit continuously monitors the gate voltage change to prepare for the triggering of subsequent clamping actions.

[0055] Step S2 is followed by: when the system enters the next conduction cycle, DRV flips back to high level. At this time, the D flip-flop is asynchronously reset again, SW1 returns to low level, the high-order NMOS transistor N2 is turned off, the low-order NMOS transistor N3 is turned on, and the SW2 node is quickly pulled low.

[0056] Subsequently, the power clamping transistor unit N1 is turned off, and the Miller clamping function is automatically released. Since the entire state switching process is completed automatically by hardware logic, stable operation can be achieved without additional control programs.

[0057] Step S2 specifically includes the following steps: Step S21: When the IGBT gate voltage is higher than 2V, the output signal of the high-speed comparator unit remains low, and the power clamping transistor unit remains off; Step S22: When the IGBT gate voltage is lower than 2V, the output signal of the high-speed comparator unit generates a rising edge, triggering the D flip-flop unit to flip, the logic control signal changes from low level to high level, the high-order NMOS transistor unit is turned on, the low-order NMOS transistor unit is turned off, the gate level of the power clamp transistor unit rises rapidly, driving the power clamp transistor unit into a strong conduction state.

[0058] Specifically, during the IGBT turn-off process, if the gate voltage is higher than 2V, the high-speed comparator unit continuously outputs a low level, and the power clamping transistor unit remains in the off state. During this stage, the clamping path is not activated, which can avoid the clamping action interfering with the normal turn-off trajectory of the IGBT in advance, effectively preventing the generation of high voltage spikes due to excessive turn-off current change rate, and ensuring the electromagnetic compatibility performance of the circuit. When the IGBT gate voltage drops below 2V, the high-speed comparator unit outputs a rising edge signal and triggers the state of the D flip-flop unit to flip. The logic control signal jumps to a high level synchronously, turning on the high-order NMOS transistor unit and turning off the low-order NMOS transistor unit, quickly raising the gate potential of the power clamping transistor unit, and making the power clamping transistor fully turn on. This action can establish a low-impedance discharge path in time after the IGBT is turned off, quickly conduct Miller current, suppress the gate voltage being raised by the Miller effect, completely eliminate IGBT parasitic mis-turn-on and bridge arm shoot-through faults, and improve the reliability of switch operation.

[0059] It is understandable that the active Miller clamping circuit control method achieves precise triggering and execution of the clamping function through staged timing control. When the external drive signal is high, the IGBT is turned on, and the clamping function is in a forced off state. When the external drive signal turns low, in the initial turn-off phase when the IGBT gate voltage is higher than 2V, the high-speed comparator unit outputs a low level, and the power clamping transistor unit remains off, without affecting the normal turn-off process of the device. When the gate voltage is lower than 2V, the rising edge of the output of the high-speed comparator unit triggers the D flip-flop unit to flip, the high-order NMOS transistor unit is turned on, and the low-order NMOS transistor unit is turned off, causing the gate level of the power clamping transistor unit to rise rapidly and enter a strong conduction state, discharging the IGBT gate to ground with low impedance. This method achieves precise and stable triggering of the clamping function through clear voltage threshold determination and digital latching logic. From the control process level, it completely avoids the problem of false triggering caused by environmental interference that is easily affected by analog control logic, and ensures the Miller suppression effect and operational reliability during the IGBT turn-off phase.

[0060] The specific work process is as follows: When the external drive signal DRV is high, the IGBT is in the ON state. At this time, the D flip-flop unit is forcibly reset, and SW1 remains low. Since the high-order NMOS transistor N2 is off and the low-order NMOS transistor N3 is on, the SW3 node is pulled low, and the power clamp transistor N1 remains off. During this stage, the active Miller clamp circuit in this embodiment presents a high impedance state with the IGBT gate, thus not affecting the gate charging process during normal IGBT conduction, nor reducing the device turn-on speed.

[0061] When the external drive signal DRV flips from high to low, the IGBT enters the turn-off phase. At this time, the gate charge is gradually released through the main drive circuit, and the real-time gate voltage VGE begins to decrease. Since the gate voltage is still higher than 2V during this phase, the high-speed comparator unit output remains low, the logic control module has not yet been triggered, and the power clamp unit N1 remains off. During this phase, the IGBT is in a rapidly decreasing current range, and the di / dt ratio in the system is relatively large. If the clamping action intervenes too early, it may further accelerate the gate discharge rate, resulting in an increased VCE voltage spike. Therefore, this invention keeps the clamp off during this phase to avoid interfering with the normal turn-off trajectory of the IGBT.

[0062] As the IGBT is further turned off, when the real-time gate voltage VGE drops below 2V, the high-speed comparator unit output generates a rising edge, triggering the D flip-flop unit to flip. Subsequently, SW1 switches from low to high, the high-order NMOS transistor N2 quickly turns on, and the low-order NMOS transistor N3 turns off. Under the action of the push-pull drive structure, the SW3 node is quickly pulled high, thereby driving the power clamp transistor N1 into a strong conduction state. At this time, a low-impedance discharge path is formed between the IGBT gate and ground. When the opposite bridge arm begins high-speed switching and generates a high dv / dt, the Miller current generated by the Miller capacitance coupling will preferentially flow to ground through the power clamp transistor N1, without forming a significant voltage drop on RG or the driver's internal impedance, thus effectively preventing the gate potential from being raised again. In this way, the present invention can clamp the IGBT gate stably near a low level, fundamentally suppressing parasitic conduction.

[0063] When the system enters the next conduction cycle, the external drive signal DRV flips back to high level. At this time, the D flip-flop unit is asynchronously reset again, SW1 returns to the low level, the high-order NMOS transistor unit N2 is turned off, the low-order NMOS transistor unit N3 is turned on, and the SW3 node is quickly pulled low. Subsequently, the power clamping transistor unit N1 is turned off, and the Miller clamping function is automatically released. Since the entire state switching process is automatically completed by hardware logic, stable operation can be achieved without additional control programs.

[0064] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0065] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0066] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0067] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0068] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0069] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0070] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Since these modifications and variations fall within the scope of the claims and their equivalents, this invention also intends to include these modifications and variations.

[0071] The above description describes specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An active Miller clamp circuit, characterized by It includes a voltage monitoring module, a logic control module, and a clamping drive module. The voltage monitoring module is connected to the clamping drive module and the logic control module, and the clamping drive module is connected to the logic control module. The logic control module includes a D flip-flop unit and a first inverter unit. The first inverter unit acquires an external drive signal, and the output signal of the first inverter unit is connected to the reset terminal of the D flip-flop unit. The clock input terminal of the D flip-flop unit is connected to the voltage monitoring module, the data input terminal of the D flip-flop unit acquires a high-level power supply, and the output terminal of the D flip-flop unit outputs a first logic control signal to the clamping drive module. The voltage monitoring module collects the IGBT gate voltage in real time and obtains a preset reference voltage. The real-time collected IGBT gate voltage is compared with the preset reference voltage. When the real-time collected IGBT gate voltage is lower than the preset reference voltage, a judgment signal is output. The first inverter unit converts the external drive signal into a reset signal and connects it to the reset terminal of the D flip-flop unit. The data input terminal of the D flip-flop unit is fixedly connected to a high-level power supply, the clock input terminal receives the output signal of the voltage monitoring module, and the output terminal outputs the first logic control signal to the clamping drive module, realizing the timing control of clamping only when needed during the IGBT turn-off phase. The clamping drive module includes a power clamping transistor unit, a high-position NMOS transistor unit, a low-position NMOS transistor unit, and a second inverter unit. The power clamping transistor unit is connected to both the high-position NMOS transistor unit and the low-position NMOS transistor unit, and the second inverter unit is connected to the low-position NMOS transistor unit. The high-order NMOS transistor unit acquires the logic control signal, the second inverter unit acquires the logic control signal and outputs the second logic control signal, and the low-order NMOS transistor unit acquires the second logic control signal. The high-order NMOS transistor unit and the low-order NMOS transistor unit perform fast charge and discharge control on the gate of the power clamping transistor unit.

2. The active Miller clamping circuit according to claim 1, characterized in that, The voltage monitoring module includes a high-speed comparator unit and a reference voltage generation unit, which are connected together. The reference voltage generation unit outputs a reference voltage, the inverting input of the high-speed comparator unit obtains the real-time gate voltage of the IGBT, and the non-inverting input obtains the reference voltage.

3. The active Miller clamping circuit according to claim 1, characterized in that, The high-position NMOS transistor unit and the low-position NMOS transistor unit form a complementary push-pull drive structure, which is used to control the gate node of the power clamping transistor unit for fast charging and discharging. The drain of the high-position NMOS transistor unit is connected to a high potential, its gate receives the output signal of the logic control module, and its source outputs the control signal. The drain of the low-position NMOS transistor unit is connected to the gate node of the power clamp transistor unit, the gate of the low-position NMOS transistor unit receives the inverted signal of the logic control module output signal, and the source of the low-position NMOS transistor unit is grounded. When the logic control module outputs a low signal, the high-order NMOS transistor unit is turned off, the low-order NMOS transistor unit is turned on, and the gate node of the power clamp transistor unit is quickly pulled low to ground, thereby keeping the power clamp transistor unit in the off state. When the output signal of the logic control module flips to a high level, the low-order NMOS transistor unit is quickly turned off, while the high-order NMOS transistor unit is turned on, and the gate node of the power clamp transistor unit is quickly raised to a high level, so that the power clamp transistor unit quickly enters the conduction state.

4. An IGBT driving circuit, comprising the active Miller clamping circuit of any one of claims 1-3.

5. The IGBT driving circuit according to claim 4, characterized in that, It includes a PWM input module, a gate main drive module, a gate voltage detection module, a programmable threshold module, a high-speed Miller disturbance detection module, and a fault linkage control module. The PWM input module is connected to the gate main drive module, and the gate voltage detection module is also connected to the gate main drive module. The gate voltage detection module is further connected to the active Miller clamp circuit and the fault linkage control module. The programmable threshold module is connected to the fault linkage control module and the gate main drive module respectively.

6. The IGBT driving circuit according to claim 4, characterized in that, The gate main drive module includes a gate drive unit, a pull-up drive unit, a pull-down drive unit, and a soft turn-off unit. The gate drive unit is connected to the pull-up drive unit, the pull-down drive unit, and the soft turn-off unit, respectively.

7. The IGBT driving circuit according to claim 4, characterized in that, The fault linkage control module includes a fault linkage control unit, an overcurrent detection unit, and an overtemperature detection unit. The fault linkage control unit is connected to the overcurrent detection unit and the overtemperature detection unit, respectively.

8. The IGBT driving circuit according to claim 4, characterized in that, The high-speed Miller disturbance detection module includes a comparator unit and a Miller disturbance detection unit. The gate voltage detection module is connected to the comparator unit and the Miller disturbance detection unit respectively.

9. The IGBT driving circuit according to claim 4, characterized in that, The programmable threshold module generates a fast disturbance threshold, an overcurrent threshold, and an overtemperature threshold. The overcurrent threshold is configured to the overcurrent detection unit, and the overtemperature threshold is configured to the overtemperature detection unit. A fast disturbance threshold is configured in the high-speed Miller disturbance detection module. When the high-speed Miller disturbance detection module detects that the actual gate voltage exceeds the fast disturbance threshold, it outputs a disturbance trigger signal.

10. A control method for an active Miller clamp circuit, applicable to the active Miller clamp circuit according to any one of claims 1-3, characterized in that, include, When the external drive signal is high, the IGBT is turned on. As the external drive signal transitions from high to low, the IGBT gate voltage continuously decreases, specifically including the following steps. When the IGBT gate voltage is higher than 2V, the output signal of the high-speed comparator unit remains low, and the power clamping transistor unit remains off. When the IGBT gate voltage is below 2V, the high-speed comparator unit output signal generates a rising edge, triggering the D flip-flop unit to flip, the logic control signal changes from low level to high level, the high-order NMOS transistor unit is turned on, the low-order NMOS transistor unit is turned off, the gate level of the power clamp transistor unit rises rapidly, driving the power clamp transistor unit into a strong conduction state.

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