Transistor drive circuit, DC-DC converter, drive chip and electronic device
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIPU (SHANGHAI) TECH CO LTD
- Filing Date
- 2026-04-29
- Publication Date
- 2026-08-07
AI Technical Summary
[0003]同步整流拓扑需设置非重叠时间（Nonoverlap时间）规避上下管直通短路风险，但非重叠时间内体二极管续流会产生显著导通与反向恢复损耗，严重制约效率提升，高频工况下损耗占比进一步放大
Smart Images
Figure CN122533567A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a transistor driving circuit, a DC-DC converter, a driving chip, and an electronic device. Background Technology
[0002] With the rapid development of consumer electronics, new energy, industrial automation and other fields, electronic devices are continuously upgrading towards higher frequency, smaller size and higher power density, which puts forward stringent requirements on the conversion efficiency and operational reliability of DC-to-DC converters. Synchronous rectification topology has become the mainstream architecture of power systems because it can significantly reduce follow current loss.
[0003] Synchronous rectification topologies require setting a nonoverlap time to avoid the risk of short circuit between the upper and lower diodes. However, the freewheeling current of the body diode during the nonoverlap time will generate significant conduction and reverse recovery losses, which severely restricts efficiency improvement. Under high-frequency operating conditions, the proportion of losses is further amplified.
[0004] Therefore, how to reduce the non-overlap time and improve the conversion efficiency of DC-DC converters has become a technical problem that urgently needs to be solved. Summary of the Invention
[0005] In view of this, this disclosure proposes a transistor driving circuit used in a DC-DC converter to generate a gate driving signal for the freewheeling transistor in the power conversion module of the DC-DC converter. The DC-DC converter converts an input voltage into a target output voltage. The power conversion module includes a main power transistor, an energy storage inductor, and the freewheeling transistor. Both the main power transistor and the freewheeling transistor are connected to the energy storage inductor at a common node.
[0006] The transistor driving circuit is used to: detect the node voltage of the common node, and when the node voltage drops to a preset voltage, generate the gate driving signal to turn on the freewheeling transistor.
[0007] In one possible implementation, the transistor driving circuit includes a current-limiting resistor, a clamping diode, a first transistor, a second transistor, a third transistor, a fourth transistor, an RS flip-flop, a delay unit, and a low-side gate driver, wherein...
[0008] The first end of the current-limiting resistor is connected to the common node to receive the node voltage.
[0009] The second end of the current-limiting resistor is connected to the cathode of the clamping diode, the gate of the first transistor, and the gate of the second transistor.
[0010] The source of the first transistor is connected to the power supply voltage.
[0011] The drain of the first transistor is connected to the drain of the second transistor and the input of the RS flip-flop.
[0012] The source of the second transistor is connected to the drain of the fourth transistor.
[0013] The drain of the third transistor, the gate of the third transistor, and the gate of the fourth transistor are all used to connect to a reference current.
[0014] The reset terminal of the RS flip-flop is used to receive a preset reset signal.
[0015] The output of the RS flip-flop is connected to the input of the delay unit.
[0016] The output of the delay unit is connected to the first input of the low-side gate driver.
[0017] The second input terminal of the low-side gate driver is used to receive PWM control signals.
[0018] The output terminal of the low-side gate driver is used to output the gate drive signal of the freewheeling transistor.
[0019] The anode of the clamping diode, the source of the fourth transistor, and the source of the third transistor are all grounded.
[0020] In one possible implementation, the transistor driving circuit includes a reference current source for providing the reference current.
[0021] In one possible implementation, the delay duration of the delayer is 0 to 5 nanoseconds.
[0022] In one possible implementation, the first transistor is a PMOS transistor, and the second, third, and fourth transistors are all NMOS transistors.
[0023] In one possible implementation, the preset voltage is less than the turn-on voltage of the first transistor.
[0024] In one possible implementation, the DC-DC converter further includes an output capacitor, a voltage feedback unit, an error amplifier circuit, a reset signal generation circuit, a PWM logic circuit, and a high-side gate driver, wherein...
[0025] The drain of the main power transistor is used to connect to the input voltage.
[0026] The gate of the main power transistor is connected to the output terminal of the high-side gate driver to receive the gate drive signal of the main power transistor.
[0027] The source of the main power transistor, the first terminal of the energy storage inductor, and the drain of the freewheeling transistor are connected as the common node.
[0028] The source of the freewheeling transistor, the first terminal of the output capacitor, and the first terminal of the voltage feedback unit are connected together to serve as the output terminal of the DC-DC converter to output the target output voltage.
[0029] The first input terminal of the error amplifier circuit is used to receive the feedback voltage output by the voltage feedback unit.
[0030] The second input terminal of the error amplifier circuit is used to receive the reference voltage.
[0031] The output of the error amplifier circuit is connected to the first input of the reset signal generation circuit.
[0032] The second and third input terminals of the reset signal generation circuit are respectively connected to the two ends of the main power transistor to detect the inductor current of the energy storage inductor. The reset signal generation circuit is used to generate a ramp compensation voltage based on the inductor current and a preset ramp voltage, and to generate a reset signal based on the ramp compensation voltage and the error signal output by the error amplifier circuit.
[0033] The output of the reset signal generation circuit is connected to the input of the PWM logic circuit.
[0034] The clock signal input terminal of the PWM logic circuit is used to receive the clock signal.
[0035] The output of the PWM logic circuit is used to output the PWM control signal.
[0036] The second terminal of the output capacitor and the second terminal of the energy storage inductor are both grounded.
[0037] The high-side gate driver is used to generate the gate drive signal of the main power transistor based on the PWM control signal and the gate drive signal of the freewheeling transistor.
[0038] The low-side gate driver is further configured to generate the gate drive signal of the freewheeling transistor based on the output signal of the delay and the PWM control signal.
[0039] According to another aspect of this disclosure, a DC-DC converter is provided, the DC-DC converter including the aforementioned transistor drive circuit.
[0040] According to another aspect of this disclosure, a driver chip is provided, the chip including the aforementioned DC-DC converter.
[0041] According to another aspect of this disclosure, an electronic device is provided, the electronic device including the aforementioned driver chip.
[0042] The transistor driving circuit of this disclosure embodiment can generate a gate driving signal to turn on the freewheeling transistor when the node voltage of the common node in the DC-DC converter drops to a preset voltage, thereby reducing the non-overlapping time and improving the conversion efficiency of the DC-DC converter.
[0043] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description
[0044] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.
[0045] Figure 1 A schematic diagram of an application scenario of a transistor driving circuit according to an embodiment of the present disclosure is shown.
[0046] Figure 2 A schematic diagram of a DC-DC converter according to an embodiment of the present disclosure is shown.
[0047] Figure 3 A schematic diagram of the signal from a DC-DC converter is shown.
[0048] Figure 4 A schematic diagram of a transistor driving circuit according to an embodiment of the present disclosure is shown. Detailed Implementation
[0049] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.
[0050] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.
[0051] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.
[0052] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.
[0053] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.
[0054] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.
[0055] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.
[0056] Please see Figure 1 , Figure 1 A schematic diagram of an application scenario of a transistor driving circuit according to an embodiment of the present disclosure is shown.
[0057] like Figure 1 As shown, the transistor driving circuit 20 is applied in the DC-DC converter 10 to generate the gate drive signal S2 of the freewheeling transistor Q2 in the power conversion module of the DC-DC converter 10. The DC-DC converter 10 converts the input voltage Vin into a target output voltage (the output voltage at the output terminal of the DC-DC converter 10 is denoted as Vout). The power conversion module includes a main power transistor Q1, an energy storage inductor L, and the freewheeling transistor Q2. Both the main power transistor Q1 and the freewheeling transistor Q2 are connected to the energy storage inductor L at a common node SW.
[0058] The transistor driving circuit 20 is used to: detect the node voltage Vsw of the common node SW, and when the node voltage Vsw drops to a preset voltage, generate the gate driving signal to turn on the freewheeling transistor Q2.
[0059] The transistor driving circuit 20 of this disclosure embodiment can generate a gate driving signal to turn on the freewheeling transistor Q2 when the node voltage Vsw of the common node SW of the main power transistor Q1, the energy storage inductor L and the freewheeling transistor Q2 in the DC-DC converter 10 drops to a preset voltage, thereby reducing the non-overlapping time and improving the conversion efficiency of the DC-DC converter.
[0060] The nonoverlap time, also known as the dead time, is used to prevent the upper and lower transistors (main power transistor Q1 and freewheeling transistor Q2) of the DC-DC converter 10 from being turned on simultaneously. It should be understood that the longer the nonoverlap time, the greater the power loss of the system. Therefore, the present disclosure embodiments can improve the conversion efficiency of the DC-DC converter by reducing the nonoverlap time.
[0061] The present invention does not limit the specific value of the preset voltage. Those skilled in the art can set it according to actual conditions and needs. For example, the preset voltage can be set to be less than the turn-on voltage of the PMOS transistor (e.g., -0.7V).
[0062] This disclosure does not limit the specific type and implementation method of the DC-DC converter. Those skilled in the art can refer to relevant technologies to implement it according to actual conditions and needs. For example, the DC-DC converter may include a boost DC-DC converter, a buck DC-DC converter, a buck-boost DC-DC converter, etc.
[0063] The following example uses a buck-boost DC-DC converter to illustrate the operation of the transistor drive circuit 20.
[0064] Please see Figure 2 , Figure 2 A schematic diagram of a DC-DC converter 10 according to an embodiment of the present disclosure is shown.
[0065] In one possible implementation, such as Figure 2 As shown, the DC-DC converter 10 may further include an output capacitor C. OUT The circuit includes a voltage feedback unit 110, an error amplifier circuit 120, a reset signal generation circuit 130, a PWM logic circuit 140, and a high-side gate driver HS_Driver.
[0066] The drain of the main power transistor Q1 is used to connect to the input voltage Vin.
[0067] The gate of the main power transistor Q1 is connected to the output of the high-side gate driver HS_Driver, and is used to receive the gate drive signal S1 of the main power transistor Q1.
[0068] The source of the main power transistor Q1, the first terminal of the energy storage inductor L, and the drain of the freewheeling transistor Q2 are connected to form the common node SW.
[0069] The source of the freewheeling transistor Q2 and the output capacitor C OUT The first terminal is connected to the first terminal of the voltage feedback unit 110, and serves as the output terminal of the DC-DC converter 10 to output the target output voltage (the output voltage of the output terminal of the DC-DC converter 10 is denoted as Vout).
[0070] The first input terminal of the error amplifier circuit 120 is used to receive the feedback voltage VFB output by the voltage feedback unit 110.
[0071] The second input terminal of the error amplifier circuit 120 is used to receive the reference voltage (VREFB).
[0072] The output terminal of the error amplifier circuit 120 is connected to the first input terminal of the reset signal generation circuit 130.
[0073] The second and third input terminals of the reset signal generation circuit 130 are respectively connected to the two ends of the main power transistor Q1 to detect the inductor current of the energy storage inductor L. The reset signal generation circuit is used to generate a ramp compensation voltage based on the inductor current and a preset ramp voltage, and to generate a reset signal based on the ramp compensation voltage and the error signal output by the error amplifier circuit.
[0074] The output of the reset signal generation circuit 130 is connected to the input of the PWM logic circuit 140.
[0075] The clock signal input terminal of the PWM logic circuit 140 is used to receive the clock signal CLK.
[0076] The output of the PWM logic circuit 140 is used to output the PWM control signal pwm.
[0077] The output capacitor C OUT Both the second terminal of the inductor and the second terminal of the energy storage inductor L are grounded.
[0078] The high-side gate driver HS_Driver is used to generate the gate drive signal S1 of the main power transistor Q1 based on the PWM control signal pwm and the gate drive signal S2 of the freewheeling transistor Q2.
[0079] The transistor driving circuit 20 is also used to receive the PWM control signal pwm output by the PWM logic circuit 140, for example, as Figure 4 As shown, the low-side gate driver Driver_LS in the transistor driving circuit 20 is also used to generate the gate driving signal S2 of the freewheeling transistor Q2 according to the output signal (VC) of the delay in the transistor driving circuit and the PWM control signal pwm.
[0080] For example, such as Figure 2 As shown, in a buck-boost DC-DC converter, the main power transistor Q1 and the freewheeling transistor Q2 are a PMOS transistor and an NMOS transistor, respectively.
[0081] The present disclosure does not limit the specific implementation of the voltage feedback unit 110, the error amplifier circuit 120, and the reset signal generation circuit 130. Those skilled in the art can implement them according to the actual situation and needs, referring to relevant technologies. The following is an exemplary description.
[0082] For example, such as Figure 2 As shown, the voltage feedback unit 110 may include a first feedback resistor R1 and a second feedback resistor R2. The first terminal of the first feedback resistor R1 is used to receive a reference voltage (VREFA). The second terminals of the first feedback resistor R1 and the first terminal of the second feedback resistor R2 are used to output a feedback voltage VFB. The second terminal of the second feedback resistor R2 serves as the first terminal of the voltage feedback unit 110 and is connected to the source of the freewheeling transistor Q2 and the output capacitor C. OUT The first end.
[0083] For example, such as Figure 2 As shown, the error amplifier circuit 120 may include an error amplifier EA, an integrating resistor Rint, an integrating capacitor Cint, and a filter capacitor Cp. The non-inverting input (+) of the error amplifier EA serves as the first input of the error amplifier circuit 120 to receive the feedback voltage VFB output by the voltage feedback unit 110. The inverting input (-) of the error amplifier EA serves as the second input of the error amplifier circuit 120 to receive the reference voltage (VREFB). The output of the error amplifier EA, the first end of the integrating resistor Rint, and the first end of the filter capacitor Cp are connected to form the output of the error amplifier circuit 120. The second end of the integrating resistor Rint is grounded through the integrating capacitor Cint, and the second end of the filter capacitor Cp is grounded.
[0084] For example, such as Figure 2As shown, the reset signal generation circuit 130 includes a current detection circuit 1310, a ramp voltage generation circuit RAMP, and a reset comparator HCOMP. The current detection circuit 1310 can be implemented using a current sensor (such as a Hall sensor or current mirror) from related technologies. When the main power transistor Q1 is turned on, it can detect the inductor current i_hs of the energy storage inductor L. For example, the first input terminal of the current detection circuit 1310 (serving as the second input terminal of the reset signal generation circuit 130) is connected to the drain of the main power transistor Q1, and the second input terminal of the current detection circuit 1310 (serving as the third input terminal of the reset signal generation circuit 130) is connected to the source of the main power transistor Q1. The ramp voltage generation circuit RAMP can be implemented with reference to related technologies and may include, for example, a resistor, an adder, and an inductor. The current i_hs passes through the resistor to obtain a ramp voltage with the same waveform as the inductor current i_hs. The two input terminals of the adder receive this ramp voltage and a preset ramp voltage respectively to obtain the ramp compensation voltage Vramp, which is then output to the inverting input (-) of the reset comparator HCOMP. The non-inverting input (+) of the reset comparator HCOMP receives the error signal (EA_OUT) output by the error amplifier circuit 120. Thus, the reset comparator HCOMP compares the ramp compensation voltage Vramp with the error signal, thereby outputting a reset signal. This reset signal is used to determine the reset time of the PWM control signal PWM, thereby adjusting the duty cycle of PWM. The clock signal CLK is the set signal of the PWM control signal PWM (for example, the start of the PWM control signal PWM is triggered by the falling edge of CLK).
[0085] The specific implementation of the PWM logic circuit 140 in this disclosure is not limited. Those skilled in the art can implement it according to the actual situation and needs by referring to relevant technologies. For example, the PWM logic circuit 140 may include an RS flip-flop, which can receive a reset signal and a clock signal CLK to generate a PWM control signal pwm. For example, when the falling edge of the clock signal CLK arrives, the PWM control signal pwm is set, and when the rising edge of the reset signal arrives, the PWM is reset.
[0086] This disclosure does not limit the specific implementation of the high-side gate driver HS_Driver. Those skilled in the art can implement it according to the actual situation and needs, referring to relevant technologies. For example, the high-side gate driver HS_Driver may include a level conversion unit and a push-pull circuit. On the one hand, the HS_Driver completes level shifting and conversion through the level conversion unit, converting the low-voltage control signal of the logic domain of the PWM control signal pwm into a high-voltage domain drive level adapted to Q1, ensuring that Q1 meets the Vgs voltage difference requirement for complete turn-on / reliable turn-off. On the other hand, through the high-current push-pull circuit, it provides several amperes of transient sink / pull current to quickly complete the charging and discharging of the Q1 gate capacitor. Of course, those skilled in the art can implement the specific implementation of the level conversion unit and the push-pull circuit by referring to relevant technologies. Of course, the high-side gate driver HS_Driver may also include undervoltage lockout (UVLO), over-temperature protection, gate voltage clamping, and other circuits. This disclosure does not limit the implementation of these circuits.
[0087] In this embodiment, the high-side gate driver HS_Driver can combine the PWM control signal pwm and the gate drive signal S2 output by the transistor drive circuit 20 to output the gate drive signal S1 to turn on the main power transistor Q1. For example, during the energy storage stage of the energy storage inductor (when the main power transistor Q1 is turned on), if the PWM control signal PWM flips from 0 to 1, the high-side gate driver HS_Driver does not immediately output S1=0 to turn on the main power transistor Q1. The HS_Driver first detects the S2 status signal, and only outputs S1=0 to turn on the main power transistor Q1 when it confirms that S2=0 (the freewheeling transistor Q2 has been completely turned off). Unlike the case where the main power transistor Q1 is turned on, during the freewheeling stage (when the freewheeling transistor Q2 is turned on), the PWM control signal PWM flips from 1 to 0. At this time, the high-side gate driver HS_Driver directly outputs S1=1 to turn off the main power transistor Q1 without detecting the S2 status signal.
[0088] This disclosure embodiment is illustrated through... Figure 2 The possible implementations of buck-boost DC-DC converters have been exemplarily described, but the embodiments disclosed herein are not limited thereto. Those skilled in the art can modify the implementation of buck-boost DC-DC converters according to actual conditions and needs, referring to relevant technologies.
[0089] For example, such as Figure 2As shown, the main power transistor Q1 can be a PMOS transistor, and the freewheeling transistor Q2 can be an NMOS transistor. For example, assuming that when PWM=1 (high level), S1=S2=0, the main power transistor Q1 is turned on, and the freewheeling transistor Q2 is turned off; when PWM=0 (low level), S1=S2=1, the main power transistor Q1 is turned off, and the freewheeling transistor Q2 is turned on. The freewheeling current of the inductor is achieved by switching the main power transistor Q1 and the freewheeling transistor Q2 on and off, and this provides current to the output capacitor C. OUT The charging process ensures that the output reaches the predetermined target value of Vout.
[0090] Please see Figure 3 , Figure 3 A signal schematic diagram of the DC-DC converter 10 is shown.
[0091] For example, such as Figure 3 As shown, in stage T1, the gate control signal S1 rises, the main power transistor Q1 turns off, and the voltage Vsw of the common node SW drops rapidly. In stage T2, due to the effect of the parasitic diode of the freewheeling transistor Q2 and the continuity of the inductor current of the energy storage inductor L, the voltage Vsw of the common node SW is maintained at a voltage value of Vout-Vdio (the transistor's turn-on voltage, such as 0.7V). The rate at which the voltage Vsw of the common node SW drops depends on the rate at which S1 turns off. The larger the driver of S1, the faster it turns off, and the faster the voltage Vsw of the common node SW will drop, and vice versa.
[0092] For example, such as Figure 3 As shown, in stage T2, S1 is high and S2 is low, so both the main power transistor Q1 and the freewheeling transistor Q2 are off. The duration of T2 is a part of the nonoverlap time. The duration of T2 depends on the off time of the main power transistor Q1 and the on time of the freewheeling transistor Q2. The smaller the interval, the smaller the efficiency loss. Similarly, the nonoverlap time of T3 depends on the off time of the freewheeling transistor Q2 and the on time of the main power transistor Q1. The smaller the interval, the smaller the efficiency loss.
[0093] In traditional solutions, the PWM control signal PWM controls the on / off state of the main power transistor Q1 and the freewheeling transistor Q2. Specifically, the control logic for Q1 and Q2 in related technologies includes: if the main power transistor Q1 is already off, the S1 signal and PWM are sent to the low-side driver of the freewheeling transistor Q2 (related technologies only include...). Figure 4The low-side gate driver Driver_LS receives the PWM control signal PWM and the gate drive signal S1 output by the high-side gate driver HS_Driver to generate the gate drive signal S2. For example, if S1=1 and PWM=0, then S2=1, turning on the lower freewheeling transistor Q2. Similarly, if the lower transistor is off, the S2 signal and PWM are sent to the high-side gate driver HS_Driver of the main power transistor Q1. In this case, S2=0 and PWM=1, then S1=1, turning on the upper transistor. The advantage of this approach is that the system is less prone to shoot-through, avoiding device damage or unnecessary switching losses caused by instantaneous high current. However, since the gate drive signals of the main power transistor Q1 and the freewheeling transistor Q2, as well as the PWM control signal PWM, must work together, and the lower transistor must be turned on only when SW drops to Vout and the upper transistor only when Vsw rises to VDD, the control time and cost are increased, leading to an increase in the nonoverlap time of the system and additional efficiency losses.
[0094] The transistor driving circuit 20 of this disclosure embodiment can directly generate a gate driving signal to turn on the freewheeling transistor Q2 when the node voltage Vsw of the common node SW of the main power transistor Q1, the energy storage inductor L and the freewheeling transistor Q2 in the DC-DC converter 10 drops to a preset voltage, thereby reducing the non-overlapping time (duration of the T2 stage) and improving the conversion efficiency of the DC-DC converter.
[0095] Please see Figure 4 , Figure 4 A schematic diagram of a transistor driving circuit 20 according to an embodiment of the present disclosure is shown.
[0096] In one possible implementation, such as Figure 4 As shown, the transistor driving circuit 20 may include a current-limiting resistor R21, a clamping diode D1, a first transistor Q21, a second transistor Q22, a third transistor Q23, a fourth transistor Q24, an RS flip-flop RS, a delay timer Delay, and a low-side gate driver Driver_LS, wherein,
[0097] The first end of the current-limiting resistor R21 is connected to the common node SW and is used to receive the node voltage Vsw.
[0098] The second end of the current-limiting resistor R21 is connected to the cathode of the clamping diode D1, the gate of the first transistor Q21, and the gate of the second transistor Q22.
[0099] The source of the first transistor Q21 is connected to the power supply voltage Vdd.
[0100] The drain of the first transistor Q21 is connected to the drain of the second transistor Q22 and the input terminal of the RS flip-flop RS.
[0101] The source of the second transistor Q22 is connected to the drain of the fourth transistor Q24.
[0102] The drain of the third transistor Q23, the gate of the third transistor Q23, and the gate of the fourth transistor Q24 are all used to connect to a reference current.
[0103] The reset terminal of the RS flip-flop is used to receive a preset reset signal.
[0104] The output of the RS flip-flop RS is connected to the input of the delay timer Delay.
[0105] The output of the delay unit Delay is connected to the first input of the low-side gate driver Driver_LS, and is used to delay the trigger signal VB output from the output of the RS flip-flop RS, outputting a delayed signal VC.
[0106] The second input terminal of the low-side gate driver Driver_LS is used to receive the PWM control signal pwm.
[0107] The output of the low-side gate driver Driver_LS is used to output the gate drive signal S2 of the freewheeling transistor Q2.
[0108] The anode of the clamping diode D1, the source of the fourth transistor Q24, and the source of the third transistor Q23 are all grounded.
[0109] For example, such as Figure 4 As shown, the current-limiting resistor R21 is used to limit the current flowing into node VA to prevent the first transistor Q21 and the second transistor Q22 from being burned out due to excessive instantaneous current.
[0110] For example, such as Figure 4 As shown, the clamping diode D1 is used to clamp the voltage at node VA. For example, in conjunction with... Figure 3If the gate drive signal S1 of the main power transistor Q1 changes from low level (0) to high level (1), the main power transistor Q1 is turned off. At this time, the voltage Vsw of node SW begins to drop and will quickly drop to the voltage value of Vout-Vdio. As mentioned above, the duration of the voltage Vsw is part of the Nonoverlap. During the drop of SW, due to the clamping effect of clamping diode D1, the voltage of node VA is limited to a preset voltage (such as Vdio). The first transistor Q21 is a PMOS and the second transistor Q22 is an NMOS. Therefore, the first transistor Q21 is turned on and the second transistor Q22 is turned off. Then set=1, VB=1, VC=1. Once VC=1, S2 will quickly become high, causing the freewheeling transistor Q2 to turn on. In this way, the embodiment of this disclosure can shorten the time required for the voltage to drop. Figure 3 The time period T2 in the middle achieves a reduction in non-overlapping time.
[0111] Of course, when VC=0, that is, at other times, S2 is... Figure 2 The PWM control signal pwm output by the PWM logic circuit 140 is determined. For example, when the PWM control signal pwm is 1, VC=0, then S2=0; if the PWM control signal pwm is 0, then VC=1, S2=1. Of course, for the specific implementation method, please refer to the control scheme of the DC-DC converter 10 in the relevant technology, which will not be elaborated here.
[0112] In one possible implementation, such as Figure 4 As shown, the transistor driving circuit 20 includes a reference current source Ibias, which is used to provide the reference current. The specific implementation of the reference current source Ibias is not limited in this embodiment. Those skilled in the art can implement it using relevant technologies according to actual conditions and needs.
[0113] The embodiments disclosed herein do not limit the specific implementation of the RS flip-flop RS, the delay timer Delay, and the low-side gate driver Driver_LS. Those skilled in the art can implement them by referring to relevant technologies according to actual conditions and needs.
[0114] The present invention does not limit the specific duration of the delay time of the delay unit Delay. Those skilled in the art can set it according to actual conditions and needs. For example, in one possible implementation, the delay time of the delay unit Delay is 0 to 5 nanoseconds.
[0115] For example, the delay duration of the delay unit Delay in this embodiment of the disclosure is configurable. Those skilled in the art can adaptively adjust the delay duration by sending delay parameters to the delay unit Delay through the control component according to actual conditions and needs. The control component can be the controller of the DC-DC converter 10. In one example, the control component includes, but is not limited to, a separate processor, discrete components, or a combination of a processor and discrete components. The processor can include a controller in an electronic device with instruction execution capabilities. The processor can be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Within the processor, the executable instructions can be executed through hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.
[0116] This disclosure does not limit the specific transistor types of the first transistor Q21, the second transistor Q22, the third transistor Q23, and the fourth transistor Q24. Those skilled in the art can configure them according to actual circumstances and needs. For example, ... Figure 4 As shown, in one possible implementation, the first transistor Q21 can be a PMOS transistor, and the second transistor Q22, the third transistor Q23, and the fourth transistor Q24 can all be NMOS transistors.
[0117] In one possible implementation, the preset voltage is less than the turn-on voltage of the first transistor Q21 (e.g., -0.7V).
[0118] According to another aspect of this disclosure, a DC-DC converter 10 is provided, the DC-DC converter 10 including the transistor drive circuit 20 described above.
[0119] According to another aspect of this disclosure, a driver chip is provided, the chip including the aforementioned DC-DC converter 10.
[0120] According to another aspect of this disclosure, an electronic device is provided, the electronic device including the aforementioned driver chip.
[0121] This disclosure does not limit the specific type of electronic device. Those skilled in the art can configure it according to actual circumstances and needs. For example, the electronic device may include terminal devices and servers. The terminal device may be user equipment (UE), mobile device, user terminal, terminal, handheld device, computing device, or in-vehicle device, etc. Examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MID), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and wireless terminals in vehicle-to-everything (V2X) networks, etc. For example, the server may be a local server or a cloud server.
[0122] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. A transistor driving circuit, characterized in that, The transistor driving circuit is used in a DC-DC converter to generate the gate drive signal for the freewheeling transistor in the power conversion module of the DC-DC converter. The DC-DC converter converts the input voltage into a target output voltage. The power conversion module includes a main power transistor, an energy storage inductor, and the freewheeling transistor. The main power transistor and the freewheeling transistor are both connected to the energy storage inductor at a common node. The transistor driving circuit is used to: detect the node voltage of the common node, and when the node voltage drops to a preset voltage, generate the gate driving signal to turn on the freewheeling transistor.
2. The transistor driving circuit according to claim 1, characterized in that, The transistor driving circuit includes a current-limiting resistor, a clamping diode, a first transistor, a second transistor, a third transistor, a fourth transistor, an RS flip-flop, a delay circuit, and a low-side gate driver, wherein... The first end of the current-limiting resistor is connected to the common node to receive the node voltage. The second end of the current-limiting resistor is connected to the cathode of the clamping diode, the gate of the first transistor, and the gate of the second transistor. The source of the first transistor is connected to the power supply voltage. The drain of the first transistor is connected to the drain of the second transistor and the input of the RS flip-flop. The source of the second transistor is connected to the drain of the fourth transistor. The drain of the third transistor, the gate of the third transistor, and the gate of the fourth transistor are all used to connect to a reference current. The reset terminal of the RS flip-flop is used to receive a preset reset signal. The output of the RS flip-flop is connected to the input of the delay unit. The output of the delay unit is connected to the first input of the low-side gate driver. The second input terminal of the low-side gate driver is used to receive PWM control signals. The output terminal of the low-side gate driver is used to output the gate drive signal of the freewheeling transistor. The anode of the clamping diode, the source of the fourth transistor, and the source of the third transistor are all grounded.
3. The transistor driving circuit according to claim 2, characterized in that, The transistor driving circuit includes a reference current source for providing the reference current.
4. The transistor driving circuit according to claim 2, characterized in that, The delay duration of the delay device is 0 to 5 nanoseconds.
5. The transistor driving circuit according to claim 2, characterized in that, The first transistor is a PMOS transistor, and the second transistor, the third transistor, and the fourth transistor are all NMOS transistors.
6. The transistor driving circuit according to claim 2, characterized in that, The preset voltage is less than the turn-on voltage of the first transistor.
7. The transistor driving circuit according to any one of claims 2-6, characterized in that, The DC-DC converter further includes an output capacitor, a voltage feedback unit, an error amplifier circuit, a reset signal generation circuit, a PWM logic circuit, and a high-side gate driver. The drain of the main power transistor is used to connect to the input voltage. The gate of the main power transistor is connected to the output terminal of the high-side gate driver to receive the gate drive signal of the main power transistor. The source of the main power transistor, the first terminal of the energy storage inductor, and the drain of the freewheeling transistor are connected as the common node. The source of the freewheeling transistor, the first terminal of the output capacitor, and the first terminal of the voltage feedback unit are connected together to serve as the output terminal of the DC-DC converter to output the target output voltage. The first input terminal of the error amplifier circuit is used to receive the feedback voltage output by the voltage feedback unit. The second input terminal of the error amplifier circuit is used to receive the reference voltage. The output of the error amplifier circuit is connected to the first input of the reset signal generation circuit. The second and third input terminals of the reset signal generation circuit are respectively connected to the two ends of the main power transistor to detect the inductor current of the energy storage inductor. The reset signal generation circuit is used to generate a ramp compensation voltage based on the inductor current and a preset ramp voltage, and to generate a reset signal based on the ramp compensation voltage and the error signal output by the error amplifier circuit. The output of the reset signal generation circuit is connected to the input of the PWM logic circuit. The clock signal input terminal of the PWM logic circuit is used to receive the clock signal. The output of the PWM logic circuit is used to output the PWM control signal. The second terminal of the output capacitor and the second terminal of the energy storage inductor are both grounded. The high-side gate driver is used to generate the gate drive signal of the main power transistor based on the PWM control signal and the gate drive signal of the freewheeling transistor. The low-side gate driver is further configured to generate the gate drive signal of the freewheeling transistor based on the output signal of the delay and the PWM control signal.
8. A DC-DC converter, characterized in that, The DC-DC converter includes a transistor drive circuit as described in any one of claims 1-7.
9. A driver chip, characterized in that, The chip includes the DC-DC converter as described in claim 8.
10. An electronic device, characterized in that, The electronic device includes the driver chip as described in claim 9.