A SiGe BiCMOS high-speed logic circuit operating at 1.8V low power supply voltage

Abstract

The application relates to the technical field of chip design, in particular to a SiGe BiCMOS high-speed logic circuit working under 1.8V low power voltage; the SiGe BiCMOS high-speed logic circuit comprises a differential input unit, a closed-loop control unit, a bias unit and a differential output unit; the closed-loop control unit is arranged to fix the common-mode potential of the output signal of the whole circuit at a certain reference potential level set according to requirements, so that the whole latch circuit can work in a low power voltage environment of 1.7V at the lowest and at the highest working speed.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip technology, and more specifically, to a SiGe BiCMOS high-speed logic circuit operating at a low power supply voltage of 1.8V. Background Technology

[0002] With over half a century of progress and evolution in the semiconductor chip industry, the power supply for digital circuits processing digital logic signals within chips has gradually decreased, from 5V in the early days to 3.3V, 2.5V, and so on. The power supply for digital circuits built with CMOSFETs (Complementary Metal-Oxide-Semiconductor Field-Effect Transistors) has continued to decline from 3.3V and 2.5V to 1.8V, 1.2V, 0.7V, and so on. However, the power supply for digital circuits built with silicon or silicon germanium (SiGe) bipolar transistors is unlikely to decrease further beyond 3.3V and 2.5V. This presents significant obstacles in the pursuit of lower chip power consumption.

[0003] The SiGe BiCMOS high-speed logic circuit unit series mainly includes latches, D-type flip-flops, XOR gates, AND gates, OR gates, and multiplexers. D-type flip-flops are composed of two cascaded latches, and the main structures of XOR gates, AND gates, OR gates, and multiplexers are consistent with those of latches.

[0004] Figure 1 This is a SiGe BiCMOS latch circuit structure for use with standard power supplies of 3.3V or 2.5V. The DC bias current of the circuit, i.e., the tail current Itail, depends on... Figure 1 The three factors are the DC voltage bias setting, temperature (which strongly affects the voltage drop from the base to the emitter of the transistor), and the resistance value of Rtail. The minimum supply voltage required for this structure depends on the minimum sum of the five voltage values ​​V1, V2, V3, V4, and V5 shown in the diagram.

[0005] Considering the requirements of actual circuit operation on the performance and DC bias of bipolar transistors, and the influence of operating temperature and manufacturing process tolerances on transistor characteristics, the approximate minimum allowable values ​​for V1, V2, V3, V4, and V5 are: V1 = ~0.2V (minimum), V2 = ~0.7V (minimum), V3 = ~0.7V (minimum), V4 = ~0.7V (minimum), and V5 = ~0.1V (minimum); the sum of these five values ​​is: V1 + V2 + V3 + V4 + V5 = ~2.4V (minimum); that is to say, like... Figure 1The SiGeBiCMOS high-speed logic cell circuit structure shown includes latches, D-type flip-flops, XOR gates, AND gates, OR gates, multiplexers, etc., and their operating power supply voltage cannot be lower than 2.4V. Therefore, these high-speed logic cell circuits can operate at industrial standard power supply voltages such as 3.3V or 2.5V, but cannot operate at an industrial standard power supply voltage lower than 2.5V, i.e., 1.8V.

[0006] Lowering the power supply voltage will directly reduce the circuit's power consumption; the two are directly proportional. However, continuing to use... Figure 1 The structure of SiGe BiCMOS high-speed logic cell circuits prevents them from operating below the industry standard supply voltage of 2.5V. Therefore, it is impossible to further reduce the power consumption of digital logic circuits by lowering the supply voltage. Summary of the Invention

[0007] This invention addresses the problem that existing SiGe BiCMOS high-speed logic cell circuits cannot operate at industrial standard power supply voltages below 2.5V. It proposes a SiGe BiCMOS high-speed logic circuit that operates at a low power supply voltage of 1.8V. The circuit includes a differential input unit, a closed-loop control unit, a bias unit, and a differential output unit. By setting the closed-loop control unit, the common-mode potential of the entire circuit's output signal is fixed at a reference potential level that can be set as needed. This allows the entire latch circuit to operate in a low power supply voltage environment of at least 1.7V while maintaining the highest operating speed.

[0008] The specific implementation details of this invention are as follows: A SiGe BiCMOS high-speed logic circuit operating at a low power supply voltage of 1.8V includes a differential input unit, a closed-loop control unit, a bias unit, and a differential output unit. The differential input unit receives a differential signal at its input terminal, the controlled terminal of the differential input unit is connected to the closed-loop control unit, and the output terminal of the differential input unit is connected to the input terminal of the differential output unit. The bias unit receives a bias voltage at its input terminal and its output terminal is connected to the differential input unit. The positive input terminal of the closed-loop control unit is connected to the differential output unit, and the negative input terminal of the closed-loop control unit receives the reference voltage.

[0009] To better realize the present invention, the closed-loop control unit further includes an operational amplifier and an NMOS transistor M1; The positive input terminal of the operational amplifier is connected to the differential output unit, the negative input terminal of the operational amplifier is input with a set reference voltage, and the output terminal of the operational amplifier is connected to the gate of the NMOS transistor M1. The source of the NMOS transistor M1 is connected to ground, and the drain of the NMOS transistor M1 is connected to the differential input unit.

[0010] To better realize the present invention, the differential input unit further includes a first differential input unit and a second differential input unit; The first differential input unit includes transistor Q1, transistor Q3, capacitor C1, and capacitor C2; The base of transistor Q1 is connected to the first positive differential input port through capacitor C1, the emitter of transistor Q1 is connected to the drain of NMOS transistor M1, and the collector of transistor Q1 is connected to the second differential input unit. The base of transistor Q3 is connected to the first negative differential input port through capacitor C2. The emitter of transistor Q3 is connected between the drain of NMOS transistor M1 and the emitter of transistor Q1. The collector of transistor Q3 is connected to the second differential input unit. The output terminal of the second differential input unit is connected to the input terminal of the differential output unit.

[0011] To better realize the present invention, the second differential input unit further includes transistors Q2, Q4, Q5, and Q6; The base of transistor Q2 is connected to the second positive differential input port, the emitter of transistor Q2 is connected to the collector of transistor Q1, and the collector of transistor Q2 is connected to the differential output unit. The base of transistor Q4 is connected to the second negative differential input port, the emitter of transistor Q4 is connected between the collector of transistor Q1 and the emitter of transistor Q2, and the collector of transistor Q4 is connected to the differential output unit. The base of transistor Q5 is connected between the differential output unit and the collector of transistor Q4, the emitter of transistor Q5 is connected to the collector of transistor Q3, and the collector of transistor Q5 is connected to the differential output unit. The base of transistor Q6 is connected between the differential output unit and the collector of transistor Q2, the emitter of transistor Q6 is connected between the collector of transistor Q3 and the emitter of transistor Q5, and the collector of transistor Q6 is connected between the collector of transistor Q5 and the differential output unit.

[0012] To better realize the present invention, the biasing unit further includes resistor R1 and resistor R2; One end of the resistor R1 is fed with a bias voltage, and the other end is connected between the base of the transistor Q3 and the capacitor C2. One end of the resistor R2 is fed with a bias voltage, and the other end is connected between the base of the transistor Q1 and the capacitor C1.

[0013] To better realize the present invention, the differential output unit further includes resistor RS1, resistor RS2, resistor r1, and resistor r2; One end of the resistor RS1 is connected to the positive input terminal of the operational amplifier, and the other end is connected between the collector of the transistor Q2 and the second differential output port. One end of the resistor RS2 is connected between the positive input terminal of the operational amplifier and the resistor RS1, and the other end is connected between the collector of the transistor Q4 and the first differential output port. One end of the resistor r1 is connected to the power supply, and the other end is connected between the second differential output port and the resistor RS1; One end of the resistor r2 is connected to the power supply, and the other end is connected between the first differential output port and the resistor RS2.

[0014] The present invention has the following beneficial effects: In the latch circuit structure proposed in this invention, the bias current circuit at the bottom of the circuit only requires a very low supply voltage. In this way, the overall supply voltage requirement of the latch circuit can be controlled to a very low level, considering the supply voltage requirements of other circuit parts above the bottom bias current circuit. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a common circuit structure for SiGe BiCMOS latches used with standard power supply voltages of 3.3V or 2.5V.

[0016] Figure 2 For the reason Figure 1 A schematic diagram of the latch circuit structure after modification of method one.

[0017] Figure 3 For the reason Figure 1 A schematic diagram of the latch circuit structure after modification according to method two.

[0018] Figure 4 For the reason Figure 1 A schematic diagram of the latch circuit structure after modification in method three.

[0019] Figure 5 For the reason Figure 1 A schematic diagram of the latch circuit structure after modification in method four.

[0020] Figure 6 A schematic diagram of a SiGe BiCMOS high-speed logic circuit structure operating at a low power supply voltage of 1.8V is provided for the present invention. Detailed Implementation

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments, and therefore should not be regarded as a limitation on the scope of protection. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0023] Before describing the embodiments, let me briefly explain four existing methods for reducing power supply voltage.

[0024] The method is the same Figure 2 As shown, the port with signal input 1 is not used. Figure 1 Instead of high-speed NPN transistors, high-speed NMOSFETs (N-type metal-oxide-semiconductor field-effect transistors) are used to reduce the V3 voltage, thereby reducing the required power supply voltage. However, because the speed of NMOSFETs in SiGe BiCMOS wafer fabrication is significantly slower than that of high-speed NPN transistors, and the transconductance of NMOSFETs is also significantly weaker than that of high-speed NPN transistors, this makes... Figure 2 The circuit shown is difficult to meet the required operating speed.

[0025] Method Two Figure 3 As shown, the bottom (tail) of the circuit is formed by a simple resistor Rtail. The voltage drop across the entire circuit from top to bottom becomes V1+V2+V3+V45, which is significantly less than V1+V2+V3+V45. Figure 1The voltage drop from top to bottom in the circuit is V1+V2+V3+V4+V5, which allows for a reduction in the required power supply voltage. The DC bias current Itail of this circuit is determined by Rtail, the common-mode voltage of differential signal input 1, and temperature. Temperature variations significantly affect the base-emitter voltage drop of the NPN transistor at signal input 1, thus strongly influencing the voltage across Rtail and the current Itail flowing through it. Therefore, temperature changes severely impact the DC bias current and the amplitude of the output voltage signal, a significant drawback of this circuit. Such problems should be avoided as much as possible in high-speed logic circuits.

[0026] Method 3 Figure 4 As shown, the current bias circuit at the bottom of the circuit is replaced by an NMOSFET current mirror. The source-drain voltage Vds of the NMOSFET transistor M, i.e., V45 in the figure, is approximately 0.6V. Therefore, the minimum allowable values ​​of V1, V2, V3, and V45 are approximately: V1 = ~0.2V (minimum), V2 = ~0.7V (minimum), V3 = ~0.7V (minimum), and V45 = ~0.6V (minimum). The sum of these four values ​​is: V1 + V2 + V3 + V45 = ~2.2V (minimum). In other words, Figure 4 The circuit shown has a power supply voltage that cannot be lower than approximately 2.2V. This is consistent with... Figure 1 Compared to the minimum operating power supply voltage of 2.4V, the circuit shown has decreased, but the decrease is not large enough to enable this circuit structure to operate in the next standard power supply voltage level below the standard power supply voltage of 2.5V, namely 1.8V.

[0027] Four methods Figure 5 As shown, its circuit structure is significantly different from the previous methods one, two, and three. The input port 1 circuit and the input port 2 circuit have been changed from the original... Figure 1 The stacked structure was changed from vertical to horizontal arrangement. Thus, the original... Figure 1 The voltage drops V2 and V3, which are connected in series, become Figure 5 A voltage drop of V23. Due to Figure 5 The voltage value of V23 in the middle is significantly smaller than that in the middle. Figure 1 V2+V3 in the middle, which makes Figure 5 The circuit in this design is expected to operate at very low supply voltages. However, this circuit structure has two significant drawbacks. First, in high-speed operation, the input 1 signal cannot shut off the current flowing through the NPN transistors Q1 / Q2 or Q3 / Q4 at an extremely fast speed, which prevents it from achieving high-quality high-speed performance. Second, Figure 5The circuit in this paper requires two current sources to operate simultaneously under normal conditions, which is different from previous circuit structures (including...). Figure 1 The original common circuit structure shown in the figure consumes twice the current, making it impossible to reduce the total power consumption.

[0028] Example 1:

[0029] This embodiment proposes a SiGe BiCMOS high-speed logic circuit operating at a low power supply voltage of 1.8V, including a differential input unit, a closed-loop control unit, a bias unit, and a differential output unit. The differential input unit receives a differential signal at its input terminal, the controlled terminal of the differential input unit is connected to the closed-loop control unit, and the output terminal of the differential input unit is connected to the input terminal of the differential output unit. The bias unit receives a bias voltage at its input terminal and its output terminal is connected to the differential input unit. The positive input terminal of the closed-loop control unit is connected to the differential output unit, and the negative input terminal of the closed-loop control unit receives the reference voltage.

[0030] Working principle: This embodiment takes into account the requirements of actual circuit working principle on the performance of bipolar transistors and their DC bias, as well as the influence of transistor characteristics on operating temperature and manufacturing process tolerances. Figure 6 The minimum allowable values ​​for V1, V2, V3 and V45 are approximately: V1 = ~0.2V (minimum), V2 = ~0.7V (minimum), V3 = ~0.7V (minimum), and V45 = ~0.1V (minimum); the sum of the above four quantities is: V1 + V2 + V3 + V45 = ~1.7V (minimum).

[0031] Compared to Figure 1 The latch circuit structure in the middle, Figure 6 The structure shown has its own characteristics in establishing the bias current at the bottom of the circuit, which will be described in the following embodiments.

[0032] Example 2:

[0033] This embodiment is based on the above embodiment 1, such as... Figure 6 As shown, the structure of the closed-loop control unit is illustrated with a specific embodiment.

[0034] The closed-loop control unit includes an operational amplifier and an NMOS transistor M1; The positive input terminal of the operational amplifier is connected to the differential output unit, the negative input terminal of the operational amplifier is input with a set reference voltage, and the output terminal of the operational amplifier is connected to the gate of the NMOS transistor M1. The source of the NMOS transistor M1 is connected to ground, and the drain of the NMOS transistor M1 is connected to the differential input unit.

[0035] Working principle: This embodiment uses an operational amplifier to form a closed-loop negative feedback loop to control the Vgs of the NMOSFET at the bottom of the entire circuit, thereby controlling the bias current I. tail This is to fix the common-mode potential of the entire circuit's output signal at a reference potential Vref that is set as needed. In this way, the amplitude of its output signal is determined and stabilized during normal operation of the entire circuit. Thanks to the effect of closed-loop negative feedback, the bias current I... tail The formation and determination of the bias current Igs do not depend on the Vds of the NMOSFET at the bottom of the entire circuit. In other words, when temperature causes a significant change in the Vbe of the NPN transistor Q1, although the Vds of the NMOSFET also changes significantly, the closed-loop negative feedback adjusts the Vgs of the NMOSFET in a timely manner to ensure the bias current Igs. tail And the amplitude stability of the entire circuit output signal. In this embodiment, the NMOSFET transistor is in an extremely linear state, with Vds (i.e., V45) of approximately ~0.1V at room temperature.

[0036] Furthermore, the operational amplifiers mentioned here do not need to be used in every latch or other similar high-speed logic circuit unit (such as flip-flops, XOR gates, AND gates, OR gates, multiplexers, etc.) operating at a standard 1.8V power supply voltage. This is only necessary as long as the drain voltage of the bottom NMOSFET within the same group of high-speed logic circuit units (i.e., ...) is maintained. Figure 6 If the voltage of node net1 is consistent, then this group of circuit units can share the same operational amplifier to form its bias current I. tail And the control of the amplitude of the output signal of the entire circuit.

[0037] The other parts of this embodiment are the same as those in Embodiment 1 above, so they will not be described again.

[0038] Example 3:

[0039] This embodiment is based on any one of Embodiments 1-2 above, such as Figure 6 As shown, the structure of the differential input unit is illustrated with a specific embodiment.

[0040] The differential input unit includes a first differential input unit and a second differential input unit; The first differential input unit includes transistor Q1, transistor Q3, capacitor C1, and capacitor C2; The base of transistor Q1 is connected to the first positive differential input port through capacitor C1, the emitter of transistor Q1 is connected to the drain of NMOS transistor M1, and the collector of transistor Q1 is connected to the second differential input unit. The base of transistor Q3 is connected to the first negative differential input port through capacitor C2. The emitter of transistor Q3 is connected between the drain of NMOS transistor M1 and the emitter of transistor Q1. The collector of transistor Q3 is connected to the second differential input unit. The output terminal of the second differential input unit is connected to the input terminal of the differential output unit.

[0041] The second differential input unit includes transistors Q2, Q4, Q5, and Q6; The base of transistor Q2 is connected to the second positive differential input port, the emitter of transistor Q2 is connected to the collector of transistor Q1, and the collector of transistor Q2 is connected to the differential output unit. The base of transistor Q4 is connected to the second negative differential input port, the emitter of transistor Q4 is connected between the collector of transistor Q1 and the emitter of transistor Q2, and the collector of transistor Q4 is connected to the differential output unit. The base of transistor Q5 is connected between the differential output unit and the collector of transistor Q4, the emitter of transistor Q5 is connected to the collector of transistor Q3, and the collector of transistor Q5 is connected to the differential output unit. The base of transistor Q6 is connected between the differential output unit and the collector of transistor Q2, the emitter of transistor Q6 is connected between the collector of transistor Q3 and the emitter of transistor Q5, and the collector of transistor Q6 is connected between the collector of transistor Q5 and the differential output unit.

[0042] The other parts of this embodiment are the same as any one of the above embodiments 1-2, so they will not be described again.

[0043] Example 4:

[0044] This embodiment is based on any one of embodiments 1-3 above, such as Figure 6 As shown, the structure of the bias unit is illustrated with a specific embodiment.

[0045] The bias unit includes resistors R1 and R2; One end of the resistor R1 is fed with a bias voltage, and the other end is connected between the base of the transistor Q3 and the capacitor C2. One end of the resistor R2 is fed with a bias voltage, and the other end is connected between the base of the transistor Q1 and the capacitor C1.

[0046] Working principle: Figure 6 The selection of the resistance values ​​of resistors R1 and R2, and the capacitance values ​​of capacitors C1 and C2, requires careful consideration. Firstly, the RC product (i.e., the time constant) must be sufficiently large relative to the low-frequency signal component of input signal 1 in the diagram. This ensures that the low-frequency signal component can pass through capacitor C with almost no attenuation and reach the base of NPN transistor Q1. Therefore, when input 1 is a narrow-bandwidth or approximately single-frequency clock signal, the RC product does not need to be too large. However, when input 1 is a wideband NRZ data signal, the RC product needs to be sufficiently large. Secondly, after selecting the RC product, the selection of the resistance values ​​of resistor R and capacitor C requires careful consideration of the total layout area occupied by resistors R and C, as well as a separate consideration of the resistance value of resistor R. This stems from... Figure 6 The base current of NPN transistor Q1 will cause a voltage drop across resistor R. This voltage drop cannot be too large, otherwise it will cause a significant decrease in the base voltage and emitter voltage (i.e., the voltage at node net1) of NPN transistor Q1, thus causing... Figure 6 The bottom bias current of the entire circuit is difficult to maintain due to the low drain voltage of the NMOSFET. In addition, the voltage drop across resistor R increases with increasing ambient temperature because the current amplification factor of NPN transistor Q1 decreases significantly at this time, resulting in a significant increase in its base current. This temperature-related effect also needs to be considered in the circuit design.

[0047] In determining Figure 6 When setting the DC bias voltage Vbias, two factors need to be considered. First, the bias voltage Vias cannot be too high, otherwise it will cause the NPN transistor Q1 to operate in the saturation region that we want to avoid (i.e., a large positive bias voltage appears between the base and collector of Q1); second, the bias voltage Vias cannot be too low, otherwise it will cause the emitter voltage of the NPN transistor Q1 to (i.e., Figure 6 The voltage at node net1 dropped significantly, thus causing... Figure 6 The bottom bias current of the entire circuit is difficult to maintain due to the excessively low drain voltage of the NMOSFET; this phenomenon is more pronounced at low temperatures because the Vbe of the NPN transistor Q1 increases significantly, causing the drain voltage of the NMOSFET to drop to an extremely low point. At this point, the operational amplifier's negative feedback loop will push up the gate voltage of the NMOSFET (the specific gate voltage value depends on the set bias current target, the size of the NMOSFET, and its drain voltage). When the gate voltage of the NMOSFET is pushed up to the highest voltage that the operational amplifier output stage can support, the control function of the entire operational amplifier's negative feedback loop reaches its limit. This process determines... Figure 6 The lower limit of the DC bias voltage Vias.

[0048] The other parts of this embodiment are the same as any one of the embodiments 1-3 above, so they will not be described again.

[0049] Example 5:

[0050] This embodiment is based on any one of embodiments 1-4 above, such as Figure 6 As shown, the structure of the differential output unit is illustrated with a specific embodiment.

[0051] The differential output unit includes resistors RS1, RS2, r1, and r2; One end of the resistor RS1 is connected to the positive input terminal of the operational amplifier, and the other end is connected between the collector of the transistor Q2 and the second differential output port. One end of the resistor RS2 is connected between the positive input terminal of the operational amplifier and the resistor RS1, and the other end is connected between the collector of the transistor Q4 and the first differential output port. One end of the resistor r1 is connected to the power supply, and the other end is connected between the second differential output port and the resistor RS1; One end of the resistor r2 is connected to the power supply, and the other end is connected between the first differential output port and the resistor RS2.

[0052] Working principle: Figure 6 The two resistors Rs at the top of the circuit are used to obtain the common-mode potential of the entire circuit's output signal. Once this common-mode potential is determined, the amplitude of the entire circuit's output signal is also determined. The level of this common-mode potential depends on the bias current I of the NMOSFET at the bottom of the circuit. tail To elaborate further, this bias current I tail It also depends on the size of the NMOSFET and its Vgs and Vds. Figure 6 The principle for selecting the values ​​of resistors Rs and r is Rs >> r. The load resistor r usually has a resistance of tens of ohms, while the resistance of Rs is at the level of tens of kilohms (from an electrical performance point of view, it is perfectly acceptable for the resistance of Rs to be significantly greater than tens of kilohms, but considering the layout area it occupies, the resistance of Rs does not need to be too large in actual circuit design).

[0053] The other parts of this embodiment are the same as any one of the embodiments 1-4 above, so they will not be described again.

[0054] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications or equivalent changes made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the present invention.

Claims

1. A high-speed SiGe BiCMOS logic circuit operating at a low power supply voltage of 1.8V, characterized in that, It includes a differential input unit, a closed-loop control unit, a bias unit, and a differential output unit; The differential input unit receives a differential signal at its input terminal, the controlled terminal of the differential input unit is connected to the closed-loop control unit, and the output terminal of the differential input unit is connected to the input terminal of the differential output unit. The bias unit receives a bias voltage at its input terminal and its output terminal is connected to the differential input unit. The positive input terminal of the closed-loop control unit is connected to the differential output unit, and the negative input terminal of the closed-loop control unit receives the reference voltage.

2. The SiGe BiCMOS high-speed logic circuit operating at a low power supply voltage of 1.8V according to claim 1, characterized in that, The closed-loop control unit includes an operational amplifier and an NMOS transistor M1; The positive input terminal of the operational amplifier is connected to the differential output unit, the negative input terminal of the operational amplifier is input with a set reference voltage, and the output terminal of the operational amplifier is connected to the gate of the NMOS transistor M1. The source of the NMOS transistor M1 is connected to ground, and the drain of the NMOS transistor M1 is connected to the differential input unit.

3. The SiGe BiCMOS high-speed logic circuit operating at a low power supply voltage of 1.8V according to claim 2, characterized in that, The differential input unit includes a first differential input unit and a second differential input unit; The first differential input unit includes transistor Q1, transistor Q3, capacitor C1, and capacitor C2; The base of transistor Q1 is connected to the first positive differential input port through capacitor C1, the emitter of transistor Q1 is connected to the drain of NMOS transistor M1, and the collector of transistor Q1 is connected to the second differential input unit. The base of transistor Q3 is connected to the first negative differential input port through capacitor C2. The emitter of transistor Q3 is connected between the drain of NMOS transistor M1 and the emitter of transistor Q1. The collector of transistor Q3 is connected to the second differential input unit. The output terminal of the second differential input unit is connected to the input terminal of the differential output unit.

4. The SiGe BiCMOS high-speed logic circuit operating at a low power supply voltage of 1.8V according to claim 3, characterized in that, The second differential input unit includes transistors Q2, Q4, Q5, and Q6; The base of transistor Q2 is connected to the second positive differential input port, the emitter of transistor Q2 is connected to the collector of transistor Q1, and the collector of transistor Q2 is connected to the differential output unit. The base of transistor Q4 is connected to the second negative differential input port, the emitter of transistor Q4 is connected between the collector of transistor Q1 and the emitter of transistor Q2, and the collector of transistor Q4 is connected to the differential output unit. The base of transistor Q5 is connected between the differential output unit and the collector of transistor Q4, the emitter of transistor Q5 is connected to the collector of transistor Q3, and the collector of transistor Q5 is connected to the differential output unit. The base of transistor Q6 is connected between the differential output unit and the collector of transistor Q2, the emitter of transistor Q6 is connected between the collector of transistor Q3 and the emitter of transistor Q5, and the collector of transistor Q6 is connected between the collector of transistor Q5 and the differential output unit.

5. A SiGe BiCMOS high-speed logic circuit operating at a low power supply voltage of 1.8V according to claim 3, characterized in that, The bias unit includes resistors R1 and R2; One end of the resistor R1 is fed with a bias voltage, and the other end is connected between the base of the transistor Q3 and the capacitor C2. One end of the resistor R2 is fed with a bias voltage, and the other end is connected between the base of the transistor Q1 and the capacitor C1.

6. A SiGe BiCMOS high-speed logic circuit operating at a low power supply voltage of 1.8V according to claim 4, characterized in that, The differential output unit includes resistors RS1, RS2, r1, and r2; One end of the resistor RS1 is connected to the positive input terminal of the operational amplifier, and the other end is connected between the collector of the transistor Q2 and the second differential output port. One end of the resistor RS2 is connected between the positive input terminal of the operational amplifier and the resistor RS1, and the other end is connected between the collector of the transistor Q4 and the first differential output port. One end of the resistor r1 is connected to the power supply, and the other end is connected between the second differential output port and the resistor RS1; One end of the resistor r2 is connected to the power supply, and the other end is connected between the first differential output port and the resistor RS2.

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