Comparator offset voltage calibration method and system for analog-to-digital conversion devices

Abstract

The present application relates to the technical field of digital-analog hybrid integrated circuit design, and provides a comparator offset voltage calibration method and system of an analog-digital conversion device, which comprises: in a sampling stage of a calibration mode, loading a common-mode voltage to a lower plate in a quantization capacitor array and a lower plate in a calibration capacitor array, so that the positive input end and the negative input end of the comparator are both common-mode voltage, and an output result of the comparator is obtained; in a quantization stage of the calibration mode, according to the output result, a logic control unit controls the voltage loaded to the lower plate in the calibration capacitor array, successive approximation operation is performed, and an offset code is generated; and when entering a normal working mode, the logic control unit controls the voltage loaded to the lower plate in the calibration capacitor array according to the offset code, so as to compensate for the input offset voltage of the comparator. The technical problem solved by the present application is how to improve the conversion precision of the analog-digital conversion device and reduce the cost.

Description

Technical Field

[0001] This invention relates to the field of mixed-signal integrated circuit design technology, and in particular to a comparator offset voltage calibration method and system for an analog-to-digital converter. Background Technology

[0002] In related technologies, analog-to-digital converters (ADCs) play a crucial role in digital signal processing (DSP), especially in portable devices where data processing is primarily performed in the digital domain. However, ADCs are often the performance bottleneck of DSP-based systems. To improve performance, ADCs need to balance high speed and low power consumption. Compared to traditional high-speed, high-precision pipelined ADCs, successive approximation register analog-to-digital converters (SAR ADCs) offer advantages such as simple structure, small size, low power consumption, and low cost. Driven by continuous miniaturization of process feature sizes and technologies such as time interleaving and multi-bit shifting, they have achieved high-speed conversion capabilities, thus demonstrating great potential in high-speed, low-power applications.

[0003] The core modules of a SAR ADC include a comparator (CMP), a digital-to-analog converter (DAC), register units, and a logic control unit. The comparator directly determines the ADC's speed, accuracy, and power consumption. An ideal comparator outputs high and low levels with equal probability when the voltages at both input terminals are equal. However, practical comparators suffer from input offset voltage (Voffset) due to manufacturing mismatches, achieving probability balance only when the input difference equals Voffset. In a single-channel SAR ADC, this offset primarily causes DC shift, compressing the effective quantization range and narrowing the input signal window. In a multi-comparator architecture, it introduces nonlinear errors, severely degrading overall performance. While mismatch can be suppressed by increasing the input transistor size, this significantly increases power consumption, making it difficult to meet low-power requirements.

[0004] Some existing technologies disclose comparator offset voltage calibration methods that use a calibration capacitor array with a total capacitance value equivalent to that of the quantization capacitor array for compensation. This calibration method samples the common-mode voltage in calibration mode and then short-circuits the upper and lower plates of the calibration capacitor array during quantization, intending to eliminate the influence of the calibration capacitors on the main signal path. However, this short-circuiting operation introduces several insurmountable problems: the calibration capacitors participate normally in charge sampling during the sampling phase, but are forcibly short-circuited during the quantization phase, resulting in an inconsistency in the total effective capacitance between the two phases, thus compromising the linearity of the analog-to-digital converter.

[0005] Therefore, there is an urgent need for a comparator offset voltage calibration method and system for analog-to-digital converters to improve the above-mentioned problems. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a comparator offset voltage calibration method and system for an analog-to-digital converter, which can fundamentally eliminate nonlinear distortion caused by capacitor switching and improve the linearity of the analog-to-digital converter.

[0007] According to a first aspect of the present invention, a comparator offset voltage calibration method for an analog-to-digital converter (ADC) is provided. The ADC includes a comparator, a logic control unit, a quantization capacitor array, and a calibration capacitor array. The quantization capacitor array includes symmetrically distributed first M capacitors and last M capacitors. The calibration capacitor array includes symmetrically distributed first N capacitors and last N capacitors. M and N are both positive integers greater than 1. Each capacitor includes a lower plate and an upper plate. The comparator has a positive input terminal and a negative input terminal. The upper plates of the first M capacitors in the quantization capacitor array and the upper plates of the first N capacitors in the calibration capacitor array are connected to the positive input terminals. The upper plates of the last M capacitors in the quantization capacitor array and the upper plates of the last N capacitors in the calibration capacitor array are connected to the negative input terminals. The lower plate is connected to the logic control unit. The method includes: a sampling phase in calibration mode, where a common-mode voltage is applied to the lower plate in the quantization capacitor array and the lower plate in the calibration capacitor array, so that both the positive and negative input terminals of the comparator are common-mode voltages, thus obtaining the comparator's output; a quantization phase in calibration mode, where, based on the output, the logic control unit controls the voltage applied to the lower plate in the calibration capacitor array to perform successive approximation operations and generate an offset code; the offset code is used to characterize the comparator's input offset voltage; and in normal operating mode, the logic control unit controls the voltage applied to the lower plate in the calibration capacitor array according to the offset code to compensate for the comparator's input offset voltage.

[0008] Its beneficial effect is that by applying a controlled voltage to the lower plate of the calibration capacitor array during both the sampling and quantization stages, and combining a complete calibration process of common-mode voltage sampling, successive approximation quantization, and dynamic compensation, a calibration system that coordinates capacitor state and compensation mechanism is constructed, which fundamentally eliminates nonlinear distortion caused by capacitor switching and improves the linearity of the analog-to-digital converter.

[0009] In one implementation, the total capacitance of the calibration capacitor array is less than the total capacitance of the quantization capacitor array.

[0010] Its beneficial effect is that by making the total capacitance of the calibration capacitor array less than the total capacitance of the quantization capacitor array, and by dynamically controlling the voltage of the lower plate of the calibration capacitor array according to the offset code in normal working mode, the operation of sampling in the calibration stage and short-circuiting the calibration capacitor in the quantization stage, as is done in the prior art, is avoided.

[0011] In one embodiment, the first N capacitors and the last N capacitors include four minimum calibration capacitors with a capacitance of 1 unit and two capacitors with a capacitance of 2 units. N-2 The maximum calibration capacitance is 1 unit; the first M capacitors and the last M capacitors include 4 minimum quantization capacitors with a capacitance of 1 unit and 2 capacitors with a capacitance of 2 units. M-2 The maximum quantization capacitance per unit; the logic control unit includes 2M+2N-4 plate switches, each of which is connected to the lower plate of one of the 2M+2N-4 capacitors; after entering the normal operating mode, the method includes: entering the sampling stage of the normal operating mode, and inputting the differential signal V in and V ip A common-mode voltage V is applied to the upper plates of the quantization capacitor array and the calibration capacitor array, corresponding to the lower plates of the first M capacitors and the last M capacitors loaded onto the quantization capacitor array. cm When the sampling phase is complete, stop applying the common-mode voltage V to the upper plates of the quantization capacitor array and the calibration capacitor array. cm This causes the upper plate to float, maintaining the charge stored during the sampling phase. During the holding phase of the normal operating mode, based on the offset code obtained in the calibration mode, the switches of each plate in the calibration capacitor array are controlled to reverse the potential applied to the lower plate corresponding to the valid bit of the offset code. This causes the voltage applied to the lower plate of the capacitor corresponding to the offset code in the calibration capacitor array to change from the common-mode voltage V. cm Switching to the reference voltage introduces a compensation voltage at the comparator input node that has the opposite polarity to the comparator input offset voltage; the magnitude of the compensation voltage is determined by the capacitance of the capacitor where the lower plate of the reverse switching is located and the difference between the reference voltage and the common-mode voltage.

[0012] Its beneficial effect lies in that, by setting the calibration capacitor array to remain connected in both calibration and normal operation modes without short-circuiting, the total effective capacitance of the DAC network remains constant across different operating stages, fundamentally eliminating nonlinear errors introduced by sudden capacitance changes. Simultaneously, the parasitic capacitance of the lower plate of the calibration capacitor exists in the same manner during both sampling and quantization phases, preventing sudden coupling to the upper plate node due to short-circuiting operations, effectively maintaining the stability of the upper plate node voltage. After sampling, the connection to the upper plate and common-mode voltage is first stopped, allowing the charge to float and latch. Then, the potential loaded on the lower plate corresponding to the effective bit of the offset code is reversed, ensuring that the integrity of the sampled charge is not affected. Based on the offset code obtained in calibration mode, by controlling the lower plate of the corresponding calibration capacitor to switch from common-mode voltage to reference voltage, a compensation voltage with the opposite polarity to the offset voltage is precisely introduced at the comparator input node, achieving high-precision offset compensation while avoiding increased area and power consumption due to excessively large calibration capacitors.

[0013] In one implementation, after the hold phase, the method includes: entering a quantization phase, whereby a comparator compares the voltages at the positive and negative input terminals to obtain a comparison result; based on the comparison result, a logic control unit sequentially switches the potential connected to the lower plate of the quantization capacitor array to perform a successive approximation operation; when the voltage switching on the lower plate of the least significant capacitor in the quantization capacitor array is complete, all quantization codes are output to complete the analog-to-digital conversion; the quantization codes are the conversion result after eliminating the influence of the comparator input offset voltage.

[0014] Its beneficial effect lies in the fact that, since a compensation voltage with the opposite polarity to the offset voltage has been introduced at the comparator input node through the calibration capacitor array during the hold phase, the input signal of the comparator has already eliminated the influence of the offset voltage before entering the quantization phase. Therefore, the comparator can perform accurate comparison based on the true input differential signal, avoiding interference from the offset voltage on the comparison result. The logic control unit switches the potential of the lower plate of the quantization capacitor array successively according to the accurate comparison result, ensuring that each step of the successive approximation operation is based on correct judgment. The final output quantized code can truly reflect the amplitude of the input signal, realizing high-precision conversion throughout the entire process from sampling, calibration to quantization, effectively improving the overall conversion accuracy and reliability of the ADC.

[0015] In one embodiment, the analog-to-digital converter employs a single-ended sampling structure, wherein one input of the comparator is connected to a quantization capacitor array and a calibration capacitor array, and the other input is connected to a positive reference voltage; during the sampling phase of calibration mode, a common-mode voltage V is applied to the lower plates of all capacitors in the quantization capacitor array and all capacitors in the calibration capacitor array. cm Simultaneously, the corresponding plate switches are closed, and a common-mode voltage V is applied to the upper plates of the quantization capacitor array and the calibration capacitor array.cm .

[0016] Its advantages lie in simplifying the circuit architecture and reducing hardware complexity and area overhead by adopting a single-ended sampling structure. During the sampling phase of the calibration mode, a common-mode voltage V is simultaneously applied to the lower and upper plates of all capacitors in the quantization capacitor array and the calibration capacitor array. cm This ensures that the voltage difference across each capacitor is zero, achieving a zero-charge initial state. This guarantees that only the comparator's inherent input offset voltage is captured during sampling, avoiding external signal interference. Simultaneously, a positive reference voltage is connected to the other input of the comparator, providing a stable reference potential for the comparison operation. This sampling method, with the upper and lower plates at the same potential, effectively eliminates the influence of the capacitor's initial charge on calibration accuracy, laying a reliable foundation for subsequent accurate compensation based on offset codes and improving the accuracy and consistency of the calibration process.

[0017] In one embodiment, the analog-to-digital converter employs a dual-ended sampling structure, wherein the positive and negative input terminals of the comparator are respectively connected to a symmetrically arranged quantization capacitor array and a calibration capacitor array; during the sampling phase of the calibration mode, a common-mode voltage V is applied to the lower plates of all capacitors in the quantization and calibration capacitor arrays. cm Simultaneously, the corresponding plate switches are closed, and a common-mode voltage V is applied to the upper plates of the vectorized capacitor array and the calibration capacitor array. cm .

[0018] Its beneficial effect lies in the fact that by employing a dual-ended sampling structure and coordinating symmetrically arranged quantization and calibration capacitor arrays, the positive and negative input terminals of the comparator form a completely symmetrical signal path, effectively suppressing common-mode interference and enhancing the differential signal extraction capability. During the sampling phase of calibration mode, a common-mode voltage V is simultaneously applied to the upper and lower plates of all capacitors. cm This approach brings the voltage difference across the capacitor to zero, achieving a zero-charge initial state. This ensures that only the comparator's inherent input offset voltage is captured during sampling, without introducing additional initial errors. This symmetrical structure not only improves the matching accuracy of the capacitor array but also allows the parasitic parameter effects at the positive and negative input terminals to cancel each other out, thereby significantly improving the accuracy of calibration and the overall linearity of analog-to-digital conversion. This lays a solid foundation for subsequent high-precision offset compensation.

[0019] In one implementation, during calibration mode, the sampled charge amounts in the quantization capacitor array and the calibration capacitor array satisfy the following: (1); in, This refers to the amount of sampling charge carried by the upper plates of the quantization capacitor array and calibration capacitor array connected to the positive input terminal of the comparator. This refers to the amount of sampling charge carried by the upper plates of the quantization capacitor array and calibration capacitor array connected to the negative input terminal of the comparator. Common-mode voltage, and These are the input voltages applied to the negative input terminal and the positive input terminal, respectively. This is the sum of the total capacitances of the calibration capacitor array and the quantization capacitor array.

[0020] Its beneficial effect is that the sampling charge carried by the positive and negative input terminals is proportional to the difference between their respective input voltages and common-mode voltages, and the proportionality coefficient is the same as that of the total capacitance. This indicates that the quantization capacitor array and the calibration capacitor array achieve symmetrical modeling of the charge domain in terms of structure; because, and The difference stems solely from the input voltage difference, while the common-mode voltage... The signals are completely canceled out, so the comparator actually responds to a pure differential input signal, effectively suppressing the effects of common-mode noise and power supply disturbances. At the same time, this relationship provides a theoretical basis for subsequently introducing reverse compensation charge through a calibration capacitor array to cancel the offset. By precisely controlling the amount of charge contributed by the calibration capacitor, a compensation voltage corresponding to the offset voltage can be equivalently injected at the input, thereby achieving highly robust offset correction without relying on high-precision analog components.

[0021] In one embodiment, the potential loaded on the lower plate corresponding to the effective bit of the offset code is reversed, causing the lower plate of the capacitor corresponding to the offset code in the capacitor calibration array to switch from the common-mode voltage V. cm Switching to the reference voltage introduces a compensation voltage at the comparator input node with the opposite polarity to the comparator input offset voltage. At this point, the sampled charge of the capacitor array satisfies: (2); in, This refers to the amount of sampling charge carried by the upper plates of the quantization capacitor array and calibration capacitor array connected to the positive input terminal of the comparator. This refers to the amount of sampling charge carried by the upper plates of the quantization capacitor array and calibration capacitor array connected to the negative input terminal of the comparator. Let be the capacitance value of the i-th capacitor in the capacitor array, sorted from largest to smallest. Let be the potential connected to the lower plate of the i-th capacitor, and let be the positive reference voltage of this potential. or negative reference voltage , for The reverse potential.

[0022] Its beneficial effect lies in the fact that by switching the lower plate of the mismatched capacitor from the common-mode voltage to the reference voltage, a compensation voltage with the opposite polarity to the offset voltage and an amplitude equal to the minimum effective voltage of that bit is introduced at the comparator input node, thereby directly canceling the static error caused by capacitor mismatch in the charge domain; by using the known capacitance value of the calibration capacitor array and the controllable reference voltage, precise compensation charge is actively injected during the sampling stage, so that the equivalent offset at the comparator input is zeroed; this mechanism does not require an additional calibration cycle or digital post-processing, but completes the offset correction within a single conversion process, which not only ensures the conversion accuracy, but also maintains the timing simplicity and high-speed characteristics of the successive approximation structure.

[0023] In one implementation, after the sampling phase ends, a holding phase begins, during which the lower plates of all capacitors in the capacitor array are connected. The input voltage of the comparator satisfy: (3); Among them, V p V is the node analog potential connected to the upper plate of the comparator's positive input terminal. n The node simulation potential is connected to the upper plate of the comparator's negative input terminal. and These are the input voltages applied to the negative input terminal and the positive input terminal, respectively. This refers to the amount of sampling charge carried by the upper plates of the quantization capacitor array and calibration capacitor array connected to the positive input terminal of the comparator. V represents the amount of sampling charge carried by the upper plates of the quantization capacitor array and calibration capacitor array connected to the negative input terminal of the comparator. offset The offset voltage of the comparator. Let be the capacitance value of the i-th capacitor in the capacitor array, sorted from largest to smallest. Let be the potential connected to the lower plate of the i-th capacitor, and let be the positive reference voltage of this potential. or negative reference voltage , for The reverse potential.

[0024] Its beneficial effect lies in maintaining the common-mode voltage connected to the lower plates of all capacitors during the hold phase, keeping the capacitor array in a high-resistance state to maintain the sampling charge. The comparator input voltage is determined by dividing the difference in charge carried by the quantization and calibration capacitors by the total capacitance, and explicitly includes a negative feedback term for the offset voltage. The compensation term is precisely the compensation voltage injected in the previous calibration mode, which is equal in amplitude and opposite in phase to the offset. Therefore, during the hold phase, this compensation voltage directly cancels out the original offset voltage, allowing the comparator to actually compare a purely differential input signal. - This allows for the real-time elimination of offset effects in the analog domain without the need for additional circuitry or timing overhead, significantly improving conversion accuracy and stability.

[0025] According to a second aspect of the present invention, a comparator offset voltage calibration system for an analog-to-digital converter is provided, for a method according to any one of the first aspects, comprising: a comparator having a positive input terminal and a negative input terminal, for comparing input voltages and outputting a comparison result; a quantization capacitor array including symmetrically distributed first M capacitors and last M capacitors, the upper plates of the first M capacitors being connected to the positive input terminal of the comparator, and the upper plates of the last M capacitors being connected to the negative input terminal of the comparator; and a calibration capacitor array including symmetrically distributed first N capacitors and last N capacitors, the upper plates of the first N capacitors being connected to the positive input terminal of the comparator. The upper plates of the last N capacitors are connected to the negative input of the comparator. The total capacitance of the calibration capacitor array is less than that of the quantization capacitor array. The logic control unit is connected to the lower plates of all capacitors in the quantization and calibration capacitor arrays. It controls the voltage source connected to each lower plate, generates an offset code based on the comparator's output, and controls the voltage of the lower plate of the calibration capacitor array based on the offset code in normal operating mode to compensate for the comparator's input offset voltage. The voltage source module provides a common-mode voltage to the lower plates of the quantization and calibration capacitor arrays.

[0026] In one embodiment, the first N capacitors and the last N capacitors include four minimum calibration capacitors with a capacitance of 1 unit and two capacitors with a capacitance of 2 units. N-2 The maximum calibration capacitance is 1 unit; the first M capacitors and the last M capacitors include 4 minimum quantization capacitors with a capacitance of 1 unit and 2 capacitors with a capacitance of 2 units. M-2 The maximum quantization capacitance is 1 unit; the logic control unit includes 2M+2N-4 plate switches, and the 2M+2N-4 plate switches are connected one-to-one with the lower plates of the 2M+2N-4 capacitors; after entering the normal operating mode, the system is configured to: enter the sampling stage of the normal operating mode, and input differential signal V in and V ip A common-mode voltage V is applied to the upper plates of the quantization capacitor array and the calibration capacitor array, corresponding to the lower plates of the first M capacitors and the last M capacitors loaded onto the quantization capacitor array. cm When the sampling phase is complete, stop applying the common-mode voltage V to the upper plates of the quantization capacitor array and the calibration capacitor array. cmThis keeps the upper plate in a floating state to maintain the charge stored during the sampling phase. During the holding phase of the normal operating mode, based on the offset code obtained from the calibration mode, the switches of each plate in the calibration capacitor array are controlled to reverse the potential applied to the lower plate corresponding to the valid bit of the offset code. This causes the voltage applied to the lower plate of the capacitor corresponding to the offset code in the calibration capacitor array to change from the common-mode voltage V. cm Switching to the reference voltage introduces a compensation voltage at the comparator input node that has the opposite polarity to the comparator input offset voltage; the magnitude of the compensation voltage is determined by the capacitance of the capacitor where the lower plate of the reverse switching is located and the difference between the reference voltage and the common-mode voltage. Attached Figure Description

[0027] Figure 1 This is a flowchart illustrating a comparator offset voltage calibration method for an analog-to-digital converter according to an exemplary embodiment.

[0028] Figure 2 This is a schematic diagram of a SAR ADC capacitor array based on lower plate sampling, according to an exemplary embodiment.

[0029] Figure 3 This is a schematic diagram of the connection structure between the capacitor array and the plate switch during the sampling phase of a calibration mode, according to another exemplary embodiment.

[0030] Figure 4 This is a schematic diagram illustrating the connection structure of the capacitor array and the plate switch during the quantization stage of a calibration mode according to an exemplary embodiment.

[0031] Figure 5 This is a schematic diagram illustrating the connection structure of the capacitor array and the plate switch during the sampling phase of a normal operating mode, according to another exemplary embodiment.

[0032] Figure 6 This is a schematic diagram of the connection structure between the capacitor array and the plate switch during the quantization stage of a normal operating mode, according to another exemplary embodiment.

[0033] Explanation of the reference numerals in the figure: 1. Quantization capacitor array; 2. Calibration capacitor array; 3. Logic control unit; 4. Comparator. Detailed Implementation

[0034] Unless otherwise defined, the technical or scientific terms used in this specification should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. Specific embodiments of the invention will be described below with reference to the accompanying drawings. It should be noted that, in order to provide a concise description, this specification cannot provide a detailed description of all features of the actual embodiments. Without departing from the spirit and scope of the invention, those skilled in the art can make modifications and substitutions to the embodiments of the invention, and the resulting embodiments are also within the protection scope of the invention.

[0035] In related technologies, a comparative example provides a comparator offset voltage calibration method that uses a calibration capacitor array with the same total capacitance value as the quantization capacitor array to eliminate the comparator offset voltage. Step 1: Connect the upper plates of all capacitors in the calibration and quantization capacitor arrays to a common-mode voltage, and sample 0 using the lower plates of all capacitors in the calibration and quantization capacitor arrays. Step 2: Connect the lower plates of all capacitors in the quantization capacitor array to the common-mode voltage, connect the lower plates of all capacitors in the calibration capacitor array to their upper plates, and disconnect the upper plates of all capacitors in the quantization and calibration capacitor arrays from the common-mode voltage. The comparator starts comparing and switches the potential connected to the lower plate of each capacitor in the quantization capacitor array according to the comparison result, until the least significant capacitor in the quantization capacitor array has been switched, thus obtaining the offset codeword of the successive approximation analog-to-digital converter. Step 3: Connect the lower plates of all capacitors in the quantization capacitor array to the input voltage. Switch the lower plates of all capacitors in the calibration capacitor array according to the inverted signal of the offset codeword obtained in Step 2. Connect the upper plates of all capacitors in the quantization and calibration capacitor arrays to the common-mode voltage. Step 4: Connect the lower plates of all capacitors in the quantization capacitor array to the common-mode voltage. Connect the lower plates of all capacitors in the calibration capacitor array to their upper plates. Disconnect the upper plates of all capacitors in the quantization and calibration capacitor arrays from the common-mode voltage. The comparator starts comparing and switches the potential connected to the lower plate of each capacitor in the quantization capacitor array according to the comparison result. This continues until the least significant capacitor in the quantization capacitor array is switched, resulting in the output quantization codeword of the successive approximation analog-to-digital converter. The output quantization codeword is the result of eliminating the comparator offset voltage.

[0036] This scheme, after sampling to 0 in calibration mode, connects the lower plate of the quantization capacitor array to the common-mode voltage, then connects the lower plates of all capacitors in the calibration capacitor array to their upper plates, and finally disconnects the upper plates of both the quantization and calibration capacitor arrays from the common-mode voltage. Here, if the lower plates of the quantization capacitors are connected to the common-mode voltage first, and then the upper plates are disconnected, the input signal sampled by the lower plates is immediately erased, significantly affecting the acquired input signal. Connecting the lower and upper plates of the calibration capacitor array during quantization introduces nonlinearity into the analog-to-digital converter's quantization process.

[0037] The comparative method involves a calibration capacitor during sampling, while during quantization, the upper and lower plates of the calibration capacitor array are connected to reduce the influence of the calibration capacitor during quantization. However, the comparative method ignores the problem that this method will cause the total capacitance of the analog-to-digital converter to be inconsistent between the sampling and quantization stages, which will lead to nonlinearity, charge injection and other problems that cause gain error.

[0038] First, due to the parasitic capacitances of the upper and lower plates of the capacitors, the influence of these parasitic capacitances must be considered when analyzing the digital-to-analog converter (DAC) of a Successive Approximation Register Analog-to-Digital Converter (SAR ADC). The parasitic capacitance of each upper plate of the calibration capacitor array to ground is equivalent to a single capacitor C. ui Where i is the index of the capacitors in the capacitor array from largest to smallest, and the parasitic capacitance of the lower plate of each capacitor in the calibration capacitor array to ground is equivalent to a capacitor C. bi The capacitance of the calibration capacitor array is represented as C. ci The capacitance of the quantized capacitor array is represented as C. i For half-side DAC analysis, during the sampling phase of calibration mode, the upper plates of all capacitors in the calibration capacitor array and quantization capacitor array are connected to a common-mode voltage, while the lower plates of all capacitors in the calibration capacitor array and quantization capacitor array are sampled to 0. The total sampled charge is: ; Connect the lower plate of all capacitors in the calibration capacitor array to their upper plate. At this time, the parasitic capacitance C of the lower plate... bi Parasitic capacitance C of the upper plate ui The parallel connection increases the equivalent parasitic capacitance of the upper plate, resulting in the following voltage: ; It can be seen that the total capacitance value during sampling is not consistent with the total capacitance value during quantization, which will greatly affect its judgment of comparator offset voltage.

[0039] Similarly, in normal operating mode, assuming the offset voltage is 0 for ease of calculation, the lower plate of the calibration capacitor array is still connected to the common-mode voltage. The total sampled charge is then: ; During the quantization process, since all the lower plates of the capacitors in the calibration capacitor array are connected to their upper plates, the parasitic capacitance C of the lower plate is... bi Parasitic capacitance C of the upper plate ui Parallel connection increases the equivalent parasitic capacitance of the upper plate, maintaining the voltage as follows: ; As can be seen from the comparative example, this method of connecting the upper and lower plates of the calibration capacitor results in the parasitic capacitance of the lower plate being connected in parallel with that of the upper plate. This causes the parasitic capacitance of the lower plate, which has no effect during the sampling phase, to affect the value of the holding voltage after sampling, significantly impacting the sampling accuracy. Furthermore, since the upper plate of the DAC is extremely sensitive to charge, the additional switching caused by connecting the upper and lower plates of the calibration capacitor introduces charge injection and clock feedthrough effects, severely damaging the sampling accuracy. Moreover, when the sampled offset voltage is 0, the impact of the parasitic capacitance of the lower plate of the calibration capacitor array becomes even more severe.

[0040] like Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, the first embodiment of the present invention provides a comparator offset voltage calibration method for an analog-to-digital converter (ADC). The ADC includes a comparator, a logic control unit, a quantization capacitor array, and a calibration capacitor array. The quantization capacitor array includes M symmetrically distributed capacitors and M symmetrically distributed capacitors. The calibration capacitor array includes N symmetrically distributed capacitors and N symmetrically distributed capacitors. M and N are both positive integers greater than 1. Each capacitor includes a lower plate and an upper plate. The comparator has a positive input terminal and a negative input terminal. The upper plates of the M capacitors in the quantization capacitor array and the upper plates of the N capacitors in the calibration capacitor array are connected to the positive input terminal. The upper plates of the M capacitors in the quantization capacitor array and the upper plates of the N capacitors in the calibration capacitor array are connected to the negative input terminal. The lower plate is connected to the logic control unit, which is used to switch the circuit connected to the lower plate to apply the voltage of the corresponding circuit to the lower plate. The method includes the following steps S1-S3: S1, entering the sampling phase of calibration mode, applying common-mode voltage to the lower plate of the quantization capacitor array and the lower plate of the calibration capacitor array, so that both the positive and negative input terminals of the comparator are common-mode voltages, and obtaining the output result of the comparator.

[0041] S2. Enter the quantization stage of the calibration mode. According to the output result, the logic control unit controls the voltage applied to the lower plates of the calibration capacitor array to perform a successive approximation operation and generate an offset code. The offset code is used to characterize the input offset voltage of the comparator.

[0042] S3. When entering the normal working mode, the logic control unit controls the voltage applied to the lower plates of the calibration capacitor array according to the offset code to compensate for the input offset voltage of the comparator.

[0043] In some specific embodiments, the analog-to-digital conversion device is a successive approximation analog-to-digital converter. The comparator is a dynamic comparator. Among them, the quantization capacitor array is composed of 2M unit capacitors, symmetrically divided into the first M and the second M, which are respectively connected to the positive input terminal and the negative input terminal of the dynamic comparator. The calibration capacitor array is composed of 2N smaller unit capacitors (N < M), also symmetrically distributed, the first N are connected to the positive input terminal, the second N are connected to the negative input terminal, and its total capacitance is much smaller than the total capacitance of the quantization capacitor array to ensure that the calibration accuracy does not affect the main conversion range. 第

[0044] In the calibration mode, the lower plates of all capacitors are switched to the common-mode voltage V cm , making the two ends of the comparator at equal potential. At this time, the comparator output only reflects the polarity of its inherent input offset voltage. Based on this, the logic control unit starts the successive approximation algorithm: starting from the highest-order calibration capacitor, sequentially switch the corresponding lower plates to the positive or negative reference voltage (such as V refp or V refn ), and judge whether to retain the bit compensation according to the comparator output feedback, and gradually generate an N-bit "offset code". This offset code essentially encodes the compensation charge amount required to offset the offset.

[0045] After entering the normal working mode, in each sampling-holding period, the logic control unit connects the lower plates of the calibration capacitor array to V refp , V refn or V cm respectively according to the pre-stored offset code, so as to inject a compensation voltage equal in amplitude and opposite in phase to the original offset voltage at the input end of the comparator. Since this calibration is completed in real time in the analog domain and is implemented using the original SAR logic, no additional hardware or extended conversion cycle is required, effectively improving the accuracy of the dynamic comparator and the overall linear performance of the SAR ADC, while taking into account the characteristics of high speed and low power consumption.

[0046] It is worth noting that by eliminating the influence of the comparator offset voltage in the output quantization code obtained from the successive approximation analog-to-digital converter, a series of problems caused by the comparator offset voltage that narrow the input signal window can be eliminated. This embodiment is simple in logic and easy to implement, requiring only a small portion of logic circuitry to satisfy the switching and a calibration capacitor array that meets the comparator offset voltage range.

[0047] In some embodiments, the total capacitance of the calibration capacitor array is less than the total capacitance of the quantization capacitor array.

[0048] In some examples, the total capacitance of the calibration capacitor array is 0.5 times the total capacitance of the quantization capacitor array.

[0049] In other examples, the total capacitance of the calibration capacitor array is 0.3 times the total capacitance of the quantization capacitor array.

[0050] In some other examples, the total capacitance of the calibration capacitor array is 0.7 times the total capacitance of the quantization capacitor array.

[0051] Please refer to Figure 1 In one embodiment, the first N capacitors and the last N capacitors include four minimum calibration capacitors with a capacitance of 1 unit and two capacitors with a capacitance of 2 units. N-2 The maximum calibration capacitance is 1 unit. The first M capacitors and the last M capacitors include 4 minimum quantization capacitors with a capacitance of 1 unit and 2 capacitors with a capacitance of 2 units. M-2 The maximum quantization capacitance is [number] units. The logic control unit includes 2M+2N-4 plate switches, each of which is connected to the lower plate of one of the 2M+2N-4 capacitors. For example... Figure 5 and Figure 6 As shown, after entering the normal working mode, the method includes: entering the sampling stage of the normal working mode, and inputting the differential signal V in and V ip A common-mode voltage V is applied to the upper plates of the quantization capacitor array and the calibration capacitor array, corresponding to the lower plates of the first M capacitors and the last M capacitors of the quantization capacitor array. cm When the sampling phase of the normal operating mode is completed, the application of the common-mode voltage V to the upper plates of the quantization capacitor array and the calibration capacitor array is stopped. cm This keeps the upper plate in a floating state to maintain the charge stored during the sampling phase. During the holding phase, based on the offset code obtained in the calibration mode, the switches of each plate in the calibration capacitor array are controlled to reverse the potential applied to the lower plate corresponding to the valid bit of the offset code, causing the voltage applied to the lower plate of the capacitor corresponding to the offset code in the calibration capacitor array to change from the common-mode voltage Vo.cm Switching to the reference voltage introduces a compensation voltage at the comparator input node that has the opposite polarity to the comparator input offset voltage; the magnitude of the compensation voltage is determined by the capacitance of the capacitor where the lower plate of the reverse switching is located and the difference between the reference voltage and the common-mode voltage.

[0052] In some specific embodiments, N=4 and M=5, meaning each side of the calibration capacitor array contains 4 capacitors (8 in total), and each side of the quantization capacitor array contains 5 capacitors (10 in total). Specifically, the calibration capacitor array adopts a symmetrical distribution structure: the first 4 capacitors (connected to the positive input terminal of the comparator) and the last 4 capacitors (connected to the negative input terminal) each contain 2 minimum calibration capacitors with a capacitance of 1C, 1 intermediate calibration capacitor with a capacitance of 2C, and 1 maximum calibration capacitor with a capacitance of 4C, so that the total capacitance of the calibration capacitors on one side is 8C, and the total capacitance of the entire calibration capacitor array is 16C. The quantization capacitor array also adopts a symmetrical structure: the first 5 capacitors and the last 5 capacitors each contain 2 minimum quantization capacitors of 1C, 1 intermediate quantization capacitor of 2C, 1 larger quantization capacitor of 4C, and 1 maximum quantization capacitor of 8C, so that the total capacitance of the quantization capacitors on one side is 16C, and the total capacitance of the entire quantization capacitor array is 32C, which meets the design requirement that "the total capacitance of the calibration capacitor array is less than the total capacitance of the quantization capacitor array".

[0053] The logic control unit contains 14 plate switches, each connected to one of the lower plates of 14 capacitors. The lower plates of the two largest capacitors in the quantization capacitor array are fixedly connected to the common-mode voltage V. cm The lower plates of the two largest capacitors in the calibration capacitor array are also fixedly connected to V. cm The lower plates of the remaining 14 capacitors can be switched controllably via switches.

[0054] In normal operating mode, the differential input signal V is sampled during the sampling phase. ip and V in The voltage is applied to the lower plates of the first five and last five capacitors of the quantization capacitor array, respectively, while a common-mode voltage V is applied to the upper plates of all capacitors. cm After sampling is complete, the upper electrode is disconnected from V. cm And float to maintain the sampling charge. After entering the hold phase, the logic control unit, based on the 4-bit offset code obtained from the calibration mode, controls the lower plate of the corresponding valid bit in the calibration capacitor array to move from V... cm Switch to reference voltage (V) refp or V refn This allows for the injection of a compensation voltage at the comparator input node. This voltage has the opposite polarity to the input offset voltage and its amplitude is a multiple of the minimum effective bit determined by the corresponding calibration capacitor weights (1C, 2C, or 4C). This enables direct offset cancellation in the analog domain, significantly improving the accuracy of analog-to-digital conversion.

[0055] In one embodiment, after the holding phase, the method includes: entering a quantization phase, whereby the comparator compares the voltages at the positive and negative input terminals to obtain a comparison result. Based on the comparison result, the logic control unit sequentially switches the potential connected to the lower plate of the quantization capacitor array, performing a successive approximation operation. When the voltage on the lower plate of the least significant capacitor in the quantization capacitor array has been switched, all quantization codes are output, completing the analog-to-digital conversion. The quantization codes are the conversion result after eliminating the influence of the comparator input offset voltage.

[0056] In some specific embodiments, the dynamic comparator performs an initial comparison of the voltages at the positive and negative input terminals and outputs the comparison result. Based on this comparison result, the logic control unit, starting from the highest-order capacitor (8C) of the quantization capacitor array, sequentially lowers the corresponding lower plate from the common-mode voltage V. cm Switch to positive reference voltage V refp Or negative reference voltage V refn Each bit switch is followed by a comparison, forming a successive approximation process. When the voltage of the lower plate of the least significant capacitor (1C) has switched, the logic control unit outputs a complete 5-bit quantization code, completing the analog-to-digital conversion. Since the calibration mode has injected precise compensation voltage through the calibration capacitor array, this quantization code is a high-precision conversion result that has completely eliminated the influence of the comparator input offset voltage, significantly improving the overall linearity and effective number of bits of the SAR ADC.

[0057] In one embodiment, the analog-to-digital converter employs a single-ended sampling structure, wherein one input of the comparator is connected to the quantization capacitor array and the calibration capacitor array, and the other input is connected to a positive reference voltage. During the sampling phase of the calibration mode, a common-mode voltage V is applied to the lower plates of all capacitors in the quantization capacitor array and all capacitors in the calibration capacitor array. cm Simultaneously, the corresponding plate switches are closed, and a common-mode voltage V is applied to the upper plates of the quantization capacitor array and the calibration capacitor array. cm .

[0058] In some specific embodiments, N=4 and M=5, and the analog-to-digital converter adopts a single-ended sampling structure. In this structure, the positive input terminal of the dynamic comparator is connected to the upper plate node of the quantization capacitor array and the calibration capacitor array, and the negative input terminal is fixedly connected to the positive reference voltage V. refp It can also be configured to other reference potentials to achieve differential comparison of single-ended input signals.

[0059] During the sampling phase of calibration mode, the logic control unit applies a common-mode voltage V to the lower plates of all 10 capacitors in the quantization capacitor array and all 8 capacitors in the calibration capacitor array. cmSimultaneously, all corresponding plate switches are closed, so that the upper plates of the quantization capacitor array and calibration capacitor array are also connected to the common-mode voltage V. cm This completes the initial charge reset of the capacitor array. After sampling, the upper plate is disconnected from V. cm The device connects and enters a floating state to maintain the initial charge distribution established during the sampling phase, laying the foundation for subsequent offset voltage detection and compensation operations.

[0060] Compared to traditional differential structures, this single-ended sampling structure has the advantages of simple circuit implementation and small area overhead, making it suitable for low-power applications that are sensitive to chip area. At the same time, through the precise compensation mechanism of the calibration capacitor array, it can still effectively eliminate the impact of comparator input offset voltage on conversion accuracy.

[0061] In one embodiment, the analog-to-digital converter employs a dual-ended sampling structure, wherein the positive and negative input terminals of the comparator are respectively connected to a symmetrically arranged quantization capacitor array and a calibration capacitor array. During the sampling phase of the calibration mode, a common-mode voltage V is applied to the lower plates of all capacitors in the quantization capacitor array and the calibration capacitor array. cm Simultaneously, the corresponding plate switches are closed, and a common-mode voltage V is applied to the upper plates of the quantization capacitor array and the calibration capacitor array. cm .

[0062] In some specific embodiments, during the sampling sub-stage of the calibration mode, the logic control unit applies a common-mode voltage V to the lower plates of all capacitors in the quantization capacitor array and the calibration capacitor array. cm Simultaneously, the corresponding upper plate switch is closed, so that the upper plates of all capacitors are also connected to the common-mode voltage V. cm The initial charge reset is completed. Then, the upper plate switch is disconnected, entering a holding state. At this time, the offset voltage at the comparator input is sampled and stored in the capacitor array. Next, a successive approximation operation is performed. The comparator compares the input voltage, and the logic control unit switches the lower plate potential of the capacitor based on the comparison result, ultimately obtaining the digital code representing the comparator offset voltage, i.e., the offset code. After calibration, the device enters the normal analog-to-digital conversion process. Depending on the sampling structure, the specific operation is as follows: If a single-ended sampling structure is used, one input terminal of the comparator (e.g., the positive terminal) is connected to the quantization capacitor array and the calibration capacitor array, and the other input terminal (e.g., the negative terminal) is connected to the positive reference voltage V. refp At this point, the quantization range is... V cm +V cm During the sampling phase, the upper plates of all capacitors are connected to a common-mode voltage V. cmAfter entering the hold and quantization phase, based on the offset code obtained from the calibration mode, the logic control unit reverses the connection of the lower plate of the capacitor array, which was originally connected to V. cm The potential switches to a high level V refp or low level V refn This generates a compensation voltage to counteract the offset, thereby achieving high-precision single-ended signal quantization.

[0063] If a dual-ended sampling structure is used, the positive and negative input terminals of the comparator are connected to a symmetrically arranged quantization capacitor array and a calibration capacitor array, respectively. When the differential input signal is V... ip V in At that time, the sampling voltages on the positive and negative sides are V respectively. cm V ip and V cm V in Similarly, during the hold phase after sampling, the logic control unit, based on the offset code obtained from calibration, controls the potential of the lower plate of the capacitor array on both sides from V... cm Switch to the corresponding reference level to cancel common-mode interference and comparator input offset through differential method.

[0064] It is worth noting that in this embodiment, the connection between the upper plate of the capacitor array and the common-mode voltage is disconnected first, and the charge is locked in the upper plate. This can eliminate the nonlinearity problem of quantization in the analog-to-digital converter. The connection between the upper plate of the capacitor array and the common-mode voltage is disconnected first, and then the lower plate of the quantization capacitor array is connected to the common-mode voltage.

[0065] In one implementation, taking a dual-ended sampling 5-bit SAR ADC as an example, in the calibration mode, the sampling charge amounts in the quantization capacitor array and the calibration capacitor array satisfy the following: (1).

[0066] in, This refers to the amount of sampling charge carried by the upper plates of the quantization capacitor array and calibration capacitor array connected to the positive input terminal of the comparator. This refers to the amount of sampling charge carried by the upper plates of the quantization capacitor array and calibration capacitor array connected to the negative input terminal of the comparator. Common-mode voltage, and These are the input voltages applied to the negative input terminal and the positive input terminal, respectively. It is the sum of the total capacitance of the calibration capacitor array and the quantization capacitor array.

[0067] At this time, due to the sampling common-mode voltage V cm Therefore, at this moment Vin =V ip =Vcm, therefore Q at this time p =Q n =0. When quantization begins in calibration mode, the input voltage switch is disconnected. At this time, the lower plate of the capacitor array is connected to Vcm, and the voltage across the comparator is V. cm Due to the comparator offset voltage V offset The quantization result will not be 10000 or 01111, but will contain the comparator offset voltage, such as 10011, 01100, etc. Thus, the equivalent offset code obtained by the comparator offset voltage in CDAC is 00011.

[0068] In one embodiment, the potential loaded on the lower plate corresponding to the effective bit of the offset code is reversed, causing the lower plate of the capacitor corresponding to the offset code in the capacitor calibration array to switch from the common-mode voltage V. cm Switching to the reference voltage introduces a compensation voltage at the comparator input node with the opposite polarity to the comparator input offset voltage. At this point, the sampled charge of the capacitor array satisfies: (2).

[0069] in, This refers to the amount of sampling charge carried by the upper plates of the quantization capacitor array and calibration capacitor array connected to the positive input terminal of the comparator. This refers to the amount of sampling charge carried by the upper plates of the quantization capacitor array and calibration capacitor array connected to the negative input terminal of the comparator. Let be the capacitance value of the i-th capacitor in the capacitor array, sorted from largest to smallest. Let be the potential connected to the lower plate of the i-th capacitor, and let be the positive reference voltage of this potential. or negative reference voltage , for The reverse potential.

[0070] This embodiment introduces a certain amount of charge to counteract the influence of the dynamic comparator offset voltage by switching the potential connected to the lower plate of the capacitor, so that the calibration accuracy can reach within 1 LSB.

[0071] In one implementation, after the sampling phase of the normal operating mode ends, a holding phase begins, at which time the lower plates of all capacitors in the capacitor array are connected. The input voltage of the comparator satisfy: (3).

[0072] Among them, V pV is the node analog potential connected to the upper plate of the comparator's positive input terminal. n The node simulation potential is connected to the upper plate of the comparator's negative input terminal. and These are the input voltages applied to the negative input terminal and the positive input terminal, respectively. This refers to the amount of sampling charge carried by the upper plates of the quantization capacitor array and calibration capacitor array connected to the positive input terminal of the comparator. V represents the amount of sampling charge carried by the upper plates of the quantization capacitor array and calibration capacitor array connected to the negative input terminal of the comparator. offset The offset voltage of the comparator. Let be the capacitance value of the i-th capacitor in the capacitor array, sorted from largest to smallest. Let be the potential connected to the lower plate of the i-th capacitor, and let be the positive reference voltage of this potential. or negative reference voltage , for The reverse potential.

[0073] According to a second embodiment of the present invention, a comparator offset voltage calibration system for an analog-to-digital converter is provided, for use with the method described in any one of the above embodiments, comprising: a comparator having a positive input terminal and a negative input terminal, for comparing input voltages and outputting a comparison result; a quantization capacitor array including symmetrically distributed first M capacitors and last M capacitors, the upper plates of the first M capacitors being connected to the positive input terminal of the comparator, and the upper plates of the last M capacitors being connected to the negative input terminal of the comparator; a calibration capacitor array including symmetrically distributed first N capacitors and last N capacitors, the upper plates of the first N capacitors being connected to the positive input terminal of the comparator, and the upper plates of the last N capacitors being connected to the negative input terminal of the comparator, the total capacitance of the calibration capacitor array being less than the total capacitance of the quantization capacitor array; and an editing control unit connected to the lower plates of all capacitors in the quantization capacitor array and the calibration capacitor array, for controlling the voltage source connected to each lower plate, generating an offset code based on the output result of the comparator, and controlling the voltage of the lower plates of the calibration capacitor array according to the offset code in normal operating mode to compensate for the input offset voltage of the comparator. A voltage source module is used to provide a common-mode voltage applied to the lower plate of the quantization capacitor array and the lower plate of the calibration capacitor array.

[0074] In one embodiment, the first N capacitors and the last N capacitors include four minimum calibration capacitors with a capacitance of 1 unit and two capacitors with a capacitance of 2 units. N-2 The maximum calibration capacitance is 1 unit. The first M capacitors and the last M capacitors include 4 minimum quantization capacitors with a capacitance of 1 unit and 2 capacitors with a capacitance of 2 units.M-2 The maximum quantization capacitance is 1 unit. The logic control unit includes 2M+2N-4 plate switches, and each of the 2M+2N-4 plate switches is connected to the lower plate of one of the 2M+2N-4 capacitors. After entering the normal operating mode, the system is configured to: enter the sampling phase of the normal operating mode, and input differential signal V in and V ip A common-mode voltage V is applied to the upper plates of the quantization capacitor array and the calibration capacitor array, corresponding to the lower plates of the first M capacitors and the last M capacitors of the quantization capacitor array. cm Upon completion of the sampling phase, the application of the common-mode voltage V to the upper plates of the quantization capacitor array and the calibration capacitor array is stopped. cm This keeps the upper plate in a floating state to maintain the charge stored during the sampling phase. During the holding phase of the normal operating mode, based on the offset code obtained in the calibration mode, the switches of each plate in the calibration capacitor array are controlled to reverse the potential loaded on the lower plate corresponding to the valid bit of the offset code, causing the voltage loaded on the lower plate of the capacitor corresponding to the offset code in the calibration capacitor array to change from the common-mode voltage Vo. cm Switching to the reference voltage introduces a compensation voltage at the comparator input node that has the opposite polarity to the comparator input offset voltage; the magnitude of the compensation voltage is determined by the capacitance of the capacitor where the lower plate of the reverse switching is located and the difference between the reference voltage and the common-mode voltage.

[0075] In this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0076] The above description of the embodiments is intended to enable those skilled in the art to understand and apply the present invention. It will be apparent to those skilled in the art that various modifications can be made to these embodiments, and the general principles described herein can be applied to other embodiments without creative effort. Therefore, the present invention is not limited to the embodiments described herein, and any improvements and modifications made by those skilled in the art based on the disclosure of the present invention without departing from the scope and spirit of the invention are within the scope of the present invention.

Claims

1. A method for calibrating the comparator offset voltage of an analog-to-digital converter, characterized in that, The analog-to-digital converter includes a comparator, a logic control unit, a quantization capacitor array, and a calibration capacitor array; the quantization capacitor array includes a symmetrically distributed first M capacitors and a symmetrically distributed last M capacitors; the calibration capacitor array includes a symmetrically distributed first N capacitors and a symmetrically distributed last N capacitors; M and N are both positive integers greater than 1; each capacitor includes a lower electrode and an upper electrode. The comparator has a positive input terminal and a negative input terminal; the upper plates of the first M capacitors in the quantization capacitor array and the upper plates of the first N capacitors in the calibration capacitor array are connected to the positive input terminal; the upper plates of the last M capacitors in the quantization capacitor array and the upper plates of the last N capacitors in the calibration capacitor array are connected to the negative input terminal. The lower electrode plate is connected to the logic control unit, which is used to switch the circuit connected to the lower electrode plate so as to apply the voltage on the corresponding circuit to the lower electrode plate. The method includes: During the sampling phase of entering calibration mode, a common-mode voltage is applied to the lower plate of the quantization capacitor array and the lower plate of the calibration capacitor array, so that both the positive and negative input terminals of the comparator are common-mode voltages, and the output result of the comparator is obtained. During the quantization phase of entering calibration mode, based on the output result, the logic control unit controls the voltage applied to the lower plate of the calibration capacitor array to perform a successive approximation operation and generate an offset code; the offset code is used to characterize the input offset voltage of the comparator; when entering normal operation mode, the logic control unit controls the voltage applied to the lower plate of the calibration capacitor array according to the offset code to compensate for the input offset voltage of the comparator.

2. The method according to claim 1, characterized in that, The total capacitance of the calibration capacitor array is less than the total capacitance of the quantization capacitor array.

3. The method according to claim 1, characterized in that, The first N capacitors and the last N capacitors include four minimum calibration capacitors with a capacitance of 1 unit and two capacitors with a capacitance of 2 units. N-2 The maximum calibration capacitance is 1 unit; the first M capacitors and the last M capacitors include 4 minimum quantization capacitors with a capacitance value of 1 unit and 2 capacitors with a capacitance value of 2 units. M-2 Maximum quantization capacitance per unit; The logic control unit includes 2M+2N-4 plate switches, and the 2M+2N-4 plate switches are connected one-to-one with the lower plates of the 2M+2N-4 capacitors. After entering the normal working mode, the method includes: During the sampling phase of entering the normal operating mode, the input differential signal V is... in and V ip A common-mode voltage V is applied to the upper plates of the quantization capacitor array and the calibration capacitor array, corresponding to the lower plates of the first M capacitors and the last M capacitors of the quantization capacitor array. cm When the sampling phase of the normal operating mode is completed, the application of the common-mode voltage V to the upper plates of the quantization capacitor array and the calibration capacitor array is stopped. cm This keeps the upper electrode plate in a floating state to maintain the charge stored during the sampling phase; During the holding phase of the normal operating mode, based on the offset code obtained in the calibration mode, the switches of each plate in the calibration capacitor array are controlled to reverse the potential applied to the lower plate corresponding to the valid bit of the offset code, so that the voltage applied to the lower plate of the capacitor corresponding to the offset code in the calibration capacitor array changes from the common-mode voltage V. cm Switching to the reference voltage introduces a compensation voltage at the comparator input node that has the opposite polarity to the comparator input offset voltage; the magnitude of the compensation voltage is determined by the capacitance of the capacitor where the lower plate of the reverse switching is located and the difference between the reference voltage and the common-mode voltage.

4. The method according to claim 3, characterized in that, After the holding phase, the method includes: During the quantization phase, the comparator compares the voltages at the positive and negative input terminals to obtain a comparison result. Based on the comparison result, the logic control unit sequentially switches the potential connected to the lower plate of the quantization capacitor array to perform successive approximation operations. When the voltage on the lower plate of the least significant capacitor in the quantization capacitor array has switched completely, all quantization codes are output, and the analog-to-digital conversion is completed. The quantization code is the conversion result after eliminating the influence of the comparator input offset voltage.

5. The method according to claim 3, characterized in that, The analog-to-digital converter employs a single-ended sampling structure, wherein one input of the comparator is connected to the quantization capacitor array and the calibration capacitor array, and the other input is connected to a positive reference voltage; during the sampling phase of the calibration mode, a common-mode voltage V is applied to the lower plates of all capacitors in the quantization capacitor array and all capacitors in the calibration capacitor array. cm Simultaneously, the corresponding plate switches are closed, and a common-mode voltage V is applied to the upper plates of the quantization capacitor array and the calibration capacitor array. cm .

6. The method according to claim 3, characterized in that, The analog-to-digital converter employs a dual-ended sampling structure, wherein the positive and negative input terminals of the comparator are respectively connected to a symmetrically arranged quantization capacitor array and a calibration capacitor array; during the sampling phase of the calibration mode, a common-mode voltage V is applied to the lower plates of all capacitors in the quantization capacitor array and the calibration capacitor array. cm Simultaneously, the corresponding plate switches are closed, and a common-mode voltage V is applied to the upper plates of the quantization capacitor array and the calibration capacitor array. cm .

7. The method according to claim 1, characterized in that, In the calibration mode, the sampling charge amounts in the quantization capacitor array and the calibration capacitor array satisfy the following: （1）； in, This refers to the amount of sampling charge carried by the upper plates of the quantization capacitor array and calibration capacitor array connected to the positive input terminal of the comparator. This refers to the amount of sampling charge carried by the upper plates of the quantization capacitor array and calibration capacitor array connected to the negative input terminal of the comparator. Common-mode voltage, and These are the input voltages applied to the negative input terminal and the positive input terminal, respectively. It is the sum of the total capacitance of the calibration capacitor array and the quantization capacitor array.

8. The method according to claim 3, characterized in that, The potential applied to the lower plate corresponding to the effective bit of the offset code is reversed, causing the lower plate of the capacitor corresponding to the offset code in the capacitor calibration array to switch from the common-mode voltage V. cm Switching to the reference voltage introduces a compensation voltage at the comparator input node with the opposite polarity to the comparator input offset voltage. At this point, the sampled charge of the capacitor array satisfies: （2）； in, This refers to the amount of sampling charge carried by the upper plates of the quantization capacitor array and calibration capacitor array connected to the positive input terminal of the comparator. This refers to the amount of sampling charge carried by the upper plates of the quantization capacitor array and calibration capacitor array connected to the negative input terminal of the comparator. Let be the capacitance value of the i-th capacitor in the capacitor array, sorted from largest to smallest. Let be the potential connected to the lower plate of the i-th capacitor, and let be the positive reference voltage of this potential. or negative reference voltage , for The reverse potential.

9. The method according to claim 3, characterized in that, After the sampling phase of the normal operating mode ends, the holding phase begins, at which point the lower plates of all capacitors in the capacitor array are connected. The input voltage of the comparator satisfy: （3）； Among them, V p V is the node analog potential connected to the upper plate of the comparator's positive input terminal. n The node simulation potential is connected to the upper plate of the comparator's negative input terminal. and These are the input voltages applied to the negative input terminal and the positive input terminal, respectively. This refers to the amount of sampling charge carried by the upper plates of the quantization capacitor array and calibration capacitor array connected to the positive input terminal of the comparator. V represents the amount of sampling charge carried by the upper plates of the quantization capacitor array and calibration capacitor array connected to the negative input terminal of the comparator. offset The offset voltage of the comparator. Let be the capacitance value of the i-th capacitor in the capacitor array, sorted from largest to smallest. Let be the potential connected to the lower plate of the i-th capacitor, and let be the positive reference voltage of this potential. or negative reference voltage , for The reverse potential.

10. A comparator offset voltage calibration system for an analog-to-digital converter, used in the method of any one of claims 1 to 9, characterized in that, include: A comparator has a positive input terminal and a negative input terminal, and is used to compare input voltages and output the comparison result; A quantization capacitor array includes M symmetrically distributed capacitors in the first M capacitors and M capacitors in the last M capacitors. The upper plates of the first M capacitors are connected to the positive input terminal of the comparator, and the upper plates of the last M capacitors are connected to the negative input terminal of the comparator. The calibration capacitor array includes N symmetrically distributed capacitors in the first N capacitors and N capacitors in the last N capacitors. The upper plates of the first N capacitors are connected to the positive input terminal of the comparator, and the upper plates of the last N capacitors are connected to the negative input terminal of the comparator. The total capacitance of the calibration capacitor array is less than the total capacitance of the quantization capacitor array. A logic control unit is connected to the lower plate of all capacitors in the quantization capacitor array and the calibration capacitor array. It is used to control the voltage source connected to each lower plate, generate an offset code according to the output result of the comparator, and control the voltage of the lower plate of the calibration capacitor array according to the offset code in normal operation mode to compensate the input offset voltage of the comparator. A voltage source module is used to provide a common-mode voltage applied to the lower plate of the quantization capacitor array and the lower plate of the calibration capacitor array.

11. The system according to claim 10, characterized in that, The first N capacitors and the last N capacitors include four minimum calibration capacitors with a capacitance of 1 unit and two capacitors with a capacitance of 2 units. N-2 The maximum calibration capacitance is 1 unit; the first M capacitors and the last M capacitors include 4 minimum quantization capacitors with a capacitance value of 1 unit and 2 capacitors with a capacitance value of 2 units. M-2 Maximum quantization capacitance per unit; The logic control unit includes 2M+2N-4 plate switches, and the 2M+2N-4 plate switches are connected one-to-one with the lower plates of the 2M+2N-4 capacitors. After entering the normal operating mode, the system is configured as follows: During the sampling phase of entering the normal operating mode, the input differential signal V is... in and V ip A common-mode voltage V is applied to the upper plates of the quantization capacitor array and the calibration capacitor array, corresponding to the lower plates of the first M capacitors and the last M capacitors of the quantization capacitor array. cm When the sampling phase is completed, the application of the common-mode voltage V to the upper plates of the quantization capacitor array and the calibration capacitor array is stopped. cm This keeps the upper electrode plate in a floating state to maintain the charge stored during the sampling phase; During the holding phase of the normal operating mode, based on the offset code obtained in the calibration mode, the switches of each plate in the calibration capacitor array are controlled to reverse the potential applied to the lower plate corresponding to the valid bit of the offset code, so that the voltage applied to the lower plate of the capacitor corresponding to the offset code in the calibration capacitor array changes from the common-mode voltage V. cm Switching to the reference voltage introduces a compensation voltage at the comparator input node that has the opposite polarity to the comparator input offset voltage; the magnitude of the compensation voltage is determined by the capacitance of the capacitor where the lower plate of the reverse switching is located and the difference between the reference voltage and the common-mode voltage.

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