A digital-to-analog conversion circuit, method and analog-to-digital converter

Abstract

The embodiment of the application discloses a digital-to-analog conversion circuit, a method and an analog-to-digital converter, relates to the technical field of integrated circuits, and is convenient for improving the performance of the analog-to-digital converter. The circuit comprises: a capacitor array unit comprising at least one differential capacitor array group, each differential capacitor array group comprising a positive capacitor array and a negative capacitor array, and each comprising a plurality of capacitor units and a sampling electrode plate and a control electrode plate oppositely arranged above and below each capacitor unit; a switching control unit connected with the control electrode plate of the capacitor unit and configured to control the connection state of the control electrode plate of at least one capacitor unit before the first comparison of the differential analog voltage signal output by the capacitor array unit, so that the capacitor array unit outputs a plurality of groups of differential analog voltage signals with a predetermined voltage amplitude offset relationship; and the predetermined voltage amplitude offset relationship is used to make the result of the first comparison of the differential analog voltage signal at least 2-bit data. The application is suitable for the analog-to-digital conversion scene.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a digital-to-analog conversion circuit, method, and analog-to-digital converter. Background Technology

[0002] In wireless communication systems, the analog-to-digital converter (ADC) is the core module for converting analog signals to digital signals. With the rapid development of communication technologies, taking Wi-Fi 7 as an example, its signal bandwidth and data rate have significantly increased, often requiring ADC sampling rates of around 1.28 GS / s while simultaneously meeting strict low-power design constraints. Traditional successive-approximation register (SAR) ADCs, limited by their serial operation mechanism of successive comparisons, struggle to achieve both high accuracy and low power consumption at such high sampling rates.

[0003] To improve conversion speed, existing technologies often employ multi-bit-per-cycle architectures. A typical implementation uses a capacitor-based digital-to-analog converter (CDAC). Specifically, it employs two differential capacitor arrays and three comparators. The input signal is first sampled, then a 1-bit comparison is performed to generate the Most Significant Bit (MSB). Based on the comparison result, the CDAC's capacitor array is switched, generating 2 bits in each subsequent conversion cycle. Typically, four comparisons are required to complete a 7-bit conversion. However, this scheme only outputs 1 bit in the first comparison, resulting in insufficient conversion efficiency. This is especially true when applied to sub-ADCs of pipelined successive approximation ADCs. If 4 or 6 bits need to be output, multiple comparisons are still required, consuming significant conversion time and limiting performance in high-speed systems. Summary of the Invention

[0004] In view of this, embodiments of this application provide a digital-to-analog conversion circuit, method, and analog-to-digital converter to facilitate improvement of the performance of the analog-to-digital converter.

[0005] In a first aspect, embodiments of this application provide a digital-to-analog converter circuit, comprising: a capacitor array unit, the capacitor array unit including at least one differential capacitor array group, each differential capacitor array group including: a positive capacitor array and a negative capacitor array, the positive capacitor array and the negative capacitor array respectively including: a plurality of capacitor units and sampling plates and control plates disposed above and below each capacitor unit; a switching control unit, connected to the control plates of the capacitor units in each differential capacitor array group, configured to control and adjust the connection state of the control plates of at least one capacitor unit in the positive capacitor array and the negative capacitor array in at least one differential capacitor array group before performing a first comparison of the differential analog voltage signal output by the capacitor array unit, so that the capacitor array unit outputs multiple sets of differential analog voltage signals with a predetermined voltage amplitude offset relationship; wherein, the predetermined voltage amplitude offset relationship is used to ensure that the result of the first comparison of the differential analog voltage signal output by the capacitor array unit is at least 2 bits of data.

[0006] In some embodiments, the capacitor array unit includes: two differential capacitor array groups for outputting four sets of differential analog voltage signals with predetermined voltage amplitude offset relationships; wherein the four sets of differential analog voltage signals are used to form at least three sets of differential comparison signals, at least the first set of differential comparison signals is configured as a reference differential voltage, at least the second set of differential comparison signals has a positive voltage amplitude offset relative to the reference differential voltage, and at least the third set of differential comparison signals has a negative voltage amplitude offset relative to the reference differential voltage.

[0007] In some embodiments, each of the positive capacitor arrays or negative capacitor arrays includes: at least one capacitor cell with a capacitance value of 4 times the unit capacitance, and at least two capacitor cell groups; the sampling plate of the capacitor cell with a capacitance value of 4 times the unit capacitance is connected to the common sampling terminal of the capacitor array; each capacitor cell group includes: at least one capacitor cell with a capacitance value of 3 times the unit capacitance and one capacitor cell with a capacitance value of 1 time the unit capacitance, and the sampling plates of the capacitor cell with a capacitance value of 3 times the unit capacitance and the capacitor cell with a capacitance value of 1 time the unit capacitance are shared by the common sampling terminal, and the control plate of each capacitor cell is connected to the switching control unit.

[0008] In some embodiments, the connection state of the control plate of the at least one capacitor unit that controls the adjustment is specifically: the connection state of the control plate of the capacitor unit that controls the adjustment of the capacitance value of 4 times the unit capacitance is flipped.

[0009] In some embodiments, the difference between the differential analog voltage signals output by the positive capacitor array of the second differential capacitor array group and the negative capacitor array of the first differential capacitor array group forms the first set of differential comparison signals; the difference between the differential analog voltage signals output by the positive capacitor array of the first differential capacitor array group and the negative capacitor array of the first differential capacitor array group forms the second set of differential comparison signals; and the difference between the differential analog voltage signals output by the positive capacitor array of the second differential capacitor array group and the negative capacitor array of the second differential capacitor array group forms the third set of differential comparison signals.

[0010] In some embodiments, the sampling plate is an upper plate or a lower plate, and the switching control unit is a switch array corresponding to each pair of capacitor array control loops. The switch array includes multiple MOS transistor switching units, each of which corresponds to the control plate of a capacitor unit. The signal input terminal of the MOS transistor switching unit is electrically connected to the control plate of the corresponding capacitor unit, the first selection terminal of the MOS transistor switching unit is electrically connected to the ground terminal, and the second selection terminal of the MOS transistor switching unit is configured to be connected to a dynamic register. The MOS transistor switching unit is also configured to control the signal input terminal to conduct with the first selection terminal or the second selection terminal based on the digital control signal output by the dynamic register, so as to switch the conduction state between the control plate and the ground terminal or the dynamic register.

[0011] Secondly, embodiments of this application provide a digital-to-analog conversion method, comprising: controlling and adjusting the control plate connection state of at least one capacitor unit in the positive capacitor array and the negative capacitor array in at least one differential capacitor array group, so that the capacitor array unit outputs multiple sets of differential analog voltage signals with predetermined voltage amplitude offset relationships; wherein, the capacitor array unit includes at least one differential capacitor array group; performing parallel comparison of the differential analog voltage signals, and outputting a comparison result of at least 2 bits of digital code.

[0012] In some embodiments, after simultaneously comparing the differential analog voltage signals and outputting a comparison result of at least 2 bits, the method includes: generating a switching control signal based on the comparison result; controlling the connection state of the control plates of at least one capacitor unit in the positive capacitor array and at least one capacitor unit in the negative capacitor array of at least one differential capacitor array group according to the switching control signal; and outputting a differential analog voltage signal; performing a parallel comparison on the differential analog voltage signals again and outputting a comparison result of at least 2 bits.

[0013] In some embodiments, before performing parallel comparison of the differential analog voltage signal, the method includes: connecting the output terminals of the capacitor array units to three comparators in a predetermined combination; the predetermined combination includes: connecting the negative capacitor array output terminal of the first differential capacitor array group and the positive capacitor array output terminal of the second differential capacitor array group to the differential input terminal of the first comparator; connecting the positive capacitor array output terminal and the negative capacitor array output terminal of the first differential capacitor array group to the differential input terminal of the second comparator; and connecting the positive capacitor array output terminal and the negative capacitor array output terminal of the second differential capacitor array group to the differential input terminal of the third comparator.

[0014] In some embodiments, at least the differential output signal of the first comparator is configured as a reference differential voltage, at least the differential comparison signal of the second comparator has a positive offset relative to the voltage amplitude of the reference differential voltage, and at least the differential comparison signal of the third comparator has a negative offset relative to the voltage amplitude of the reference differential voltage.

[0015] Thirdly, embodiments of this application provide an analog-to-digital converter (ADC), including: a digital-to-analog conversion circuit, a comparison unit, and a dynamic register; the signal output terminal of the digital-to-analog conversion circuit is electrically connected to the signal input terminal of the comparison unit, the signal output terminal of the comparison unit is electrically connected to the signal input terminal of the dynamic register, and the signal output terminal of the dynamic register is electrically connected to a switching control unit of the digital-to-analog conversion circuit; the digital-to-analog conversion circuit, as described in any of the first aspects, is configured to receive an analog input signal, and after adjustment by the switching control unit, output multiple sets of differential analog voltage signals with a predetermined voltage amplitude offset relationship; the comparison unit is connected to the output terminal of a capacitor array unit of the digital-to-analog conversion circuit, and is configured to compare the multiple sets of differential analog voltage signals output by the capacitor array unit, and output a comparison result corresponding to a 2-bit digital code; the signal input terminal of the dynamic register is connected to the signal output terminal of the comparison unit, and the signal output terminal is connected to the switching control terminal of the capacitor array unit, and is configured to receive the comparison result and generate a switching control signal based on the comparison result for controlling the digital-to-analog conversion circuit to perform the next voltage adjustment.

[0016] The analog-to-digital converter (ADC) circuit, method, and ADC provided in this application utilize a capacitor array unit comprising at least one differential capacitor array group. Each differential capacitor array group includes a positive capacitor array and a negative capacitor array. The positive and negative capacitor arrays each include multiple capacitor units and sampling and control plates positioned above and below each capacitor unit, respectively. This improves the symmetry and matching accuracy of signal sampling, laying a stable analog foundation for high-precision conversion. Secondly, the switching control unit actively adjusts the connection state of the capacitor unit control plates before the first comparison, achieving a pre-offset of the output voltage before the comparator starts. This directly enables at least 2 bits of data to be output during the first comparison, significantly shortening the first conversion cycle and improving overall conversion efficiency. Simultaneously, by pre-setting the voltage amplitude offset relationship between the capacitor array outputs, multiple accurate and stable quantization thresholds are provided for multiple parallel comparators, ensuring the reliability and linearity of parallel comparison. This overcomes the bottleneck of low first-conversion efficiency in traditional successive approximation ADCs, improving the performance of the ADC. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the digital-to-analog converter circuit architecture provided in an embodiment of this application; Figure 2 This is a schematic diagram of a basic structure of a capacitor array unit provided in an embodiment of this application; Figure 3 A schematic diagram of the capacitor cell state during sampling and initial conversion provided in an embodiment of this application; Figure 4 This application provides a schematic diagram illustrating the calculation of output voltage at each stage during the analog-to-digital conversion process. Figure 5 This is a schematic diagram of the quantization threshold distribution during parallel comparison provided in an embodiment of this application; Figure 6 This is a schematic diagram of the digital-to-analog conversion method provided in the embodiments of this application. Detailed Implementation

[0019] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0020] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0021] In cutting-edge applications such as wireless communication and high-speed data acquisition, successive approximation analog-to-digital converters (ADCs) are widely used due to their advantages of low power consumption and high energy efficiency. As system requirements for data throughput continue to increase, traditional SAR ADCs that convert 1 bit per cycle are no longer sufficient to meet high-speed demands. To address this, existing technologies have proposed architectures that convert multiple bits per cycle, typically using multiple capacitor arrays in conjunction with multiple comparators. However, in actual circuit operation, after analog signal sampling is completed and the first voltage comparison is initiated, the capacitor array often remains in its initial state from the end of sampling. This limited voltage swing in the initial state means that the first comparison can usually only distinguish 1 bit of information, failing to fully utilize the conversion potential of the first comparison cycle, thus restricting further improvements in overall conversion speed.

[0022] Therefore, embodiments of this application provide a digital-to-analog conversion circuit to facilitate the improvement of the performance of the analog-to-digital converter.

[0023] like Figure 1 As shown, the digital-to-analog converter circuit provided in the embodiments of this application includes: a capacitor array unit 1, the capacitor array unit 1 including at least one differential capacitor array group 10, each differential capacitor array group 10 including: a positive capacitor array 101 and a negative capacitor array 102, the positive capacitor array 101 and the negative capacitor array 102 respectively including: a plurality of capacitor units 1001 and sampling plates 1002 and control plates 1003 disposed above and below each capacitor unit 1001; a switching control unit 2, which is connected to the control plates 1002 of the capacitor units 1001 in each differential capacitor array group 10. The 003 connection is configured to control and adjust the connection state of the control plates 1003 of at least one capacitor unit 1001 in the positive capacitor array 101 and negative capacitor array 102 in at least one differential capacitor array group 10 before performing the first comparison of the differential analog voltage signal output by the capacitor array unit 1, so that the capacitor array unit 1 outputs multiple sets of differential analog voltage signals with a predetermined voltage amplitude offset relationship; wherein, the predetermined voltage amplitude offset relationship is used to ensure that the result of the first comparison of the differential analog voltage signal output by the capacitor array unit 1 is at least 2 bits of data.

[0024] This application provides a digital-to-analog converter circuit, which includes a capacitor array unit 1 and a switching control unit 2 working in conjunction with it. In some examples, the capacitor array unit 1 includes at least one differential capacitor array group 10. Each differential capacitor array group 10 includes a positive capacitor array 101 and a negative capacitor array 102. Each capacitor array is integrated from multiple capacitor units 1001 distributed according to binary weights. Each capacitor unit 1001 adopts a parallel plate capacitor structure and has a sampling plate 1002 located above and a control plate 1003 located below. The sampling plate 1002 is usually connected to the comparator input terminal, and the control plate 1003 is used to receive control signals to switch to different reference voltages.

[0025] In one specific embodiment Figure 2 This is a schematic diagram of a basic structure of a capacitor array unit provided in an embodiment of this application. See also... Figure 2 The capacitor array unit 1 includes an array of multiple binary weighted capacitors with capacitance values ​​of 1x unit capacitance (1C), 2x unit capacitance (2C), and 4x unit capacitance (4C), etc. The upper plate of each capacitor, i.e. the sampling plate, is connected to the common output terminal, while the lower plate, i.e. the control plate, is connected to different reference voltages Vref or ground GND through a switching network.

[0026] To achieve high-efficiency conversion, this application introduces a circuit module in the circuit design, namely the switching control unit 2. Specifically, the switching control unit 2 does not act only after receiving feedback from the comparator, but intervenes at an earlier critical time point, that is, after the analog input signal is sampled and before the first comparison operation is triggered. Within this time window, the switching control unit 2 actively controls the connection state of the control plate 1003 of at least one designated capacitor unit 1001 in at least one differential capacitor array group 10 according to the preset timing logic, so that it undergoes a predetermined voltage flip, for example, switching a capacitor control plate that was originally connected to the positive reference voltage Vref to the ground level.

[0027] For example, Figure 3 For a schematic diagram of the capacitor cell state during sampling and initial conversion provided in an embodiment of this application, see [link to relevant documentation]. Figure 3Assuming 1 represents the reference voltage VREF and 0 represents ground, the diagram visually illustrates the states of the four differential capacitor arrays DAC1P, DAC1N, DAC2P, and DAC2N at two key timing points. The first row, the sampling phase, shows the connection state of the lower plate of each capacitor in each array during the sampling phase. At this time, all comparators are in a reset state, i.e., QN or QP is 0. The second row, the conversion phase, shows the voltage flipping operation after sampling and before the first comparison begins. The lower plate of the leftmost 4-cell capacitor (4C) in the first differential capacitor array DAC1P flips from "1" to "0". This active switching operation is completed while the comparators are still in a reset state. This allows a voltage with a fixed offset to be established at the output of each array before the comparators operate. The fixed offset is such as ±Vref / 4, thus creating conditions for generating a 2-bit output for the first parallel comparison.

[0028] By switching, the charge distribution on the capacitor array is altered before the comparators even begin operating. This allows the output of capacitor array unit 1 to pre-establish a set of differential analog voltage signals with a fixed and precise amplitude offset before the first comparison begins. This pre-set offset creates the conditions for the three subsequent parallel comparators to simultaneously perform multi-threshold determinations. Therefore, the result of the first comparison can directly correspond to and decode at least 2 bits of valid digital data, thereby improving the efficiency of the first conversion cycle of the SAR ADC.

[0029] The analog-to-digital converter circuit provided in this application includes at least one differential capacitor array group in the capacitor array unit. Each differential capacitor array group includes a positive capacitor array and a negative capacitor array. The positive and negative capacitor arrays respectively include multiple capacitor units and sampling plates and control plates arranged above and below each capacitor unit. This improves the symmetry and matching accuracy of signal sampling, laying a stable analog foundation for high-precision conversion. Secondly, the switching control unit actively adjusts the connection state of the capacitor unit control plates before the first comparison, realizing the pre-offset of the output voltage before the comparator starts. This directly enables at least 2 bits of data to be output in the first comparison, significantly shortening the first conversion cycle and improving the overall conversion efficiency. At the same time, by pre-setting the voltage amplitude offset relationship between the outputs of the capacitor arrays, multiple accurate and stable quantization thresholds are provided for multiple parallel comparators simultaneously, ensuring the reliability and linearity of parallel comparison. This overcomes the bottleneck of low first conversion efficiency in traditional successive approximation ADCs and improves the performance of the analog-to-digital converter.

[0030] In some embodiments, the capacitor array unit 1 includes: two differential capacitor array groups 10, for outputting four sets of differential analog voltage signals with predetermined voltage amplitude offset relationships; wherein, the four sets of differential analog voltage signals are used to form at least three sets of differential comparison signals, at least the first set of differential comparison signals is configured as a reference differential voltage, at least the second set of differential comparison signals has a positive voltage amplitude offset relative to the reference differential voltage, and at least the third set of differential comparison signals has a negative voltage amplitude offset relative to the reference differential voltage.

[0031] In designing a SAR ADC that outputs multiple bits per cycle, a set of reference signals with accurate and stable voltage relationships is needed to simultaneously provide multiple parallel comparators in order to distinguish multiple bits in a single comparison. However, existing solutions typically rely on complex capacitor network switching or additional calibration circuitry to generate these reference signals, increasing design complexity and power consumption.

[0032] To overcome the above problems, the capacitor array unit of this application is implemented through two differential capacitor array groups, which can stably output four sets of differential analog voltage signals DAC1P, DAC1N, DAC2P, and DAC2N with predetermined voltage amplitude offset relationships. In some examples, these four sets of signals are combined to form at least three sets of differential comparison signals required for subsequent comparison. At least the first set of differential comparison signals is configured as a reference differential voltage and used as a comparison reference. At least the second set of differential comparison signals is formed by combining the outputs of a specific positive capacitor array and a negative capacitor array, and has a positive offset relative to the reference differential voltage. At least the third set of differential comparison signals is implemented by combining another specific positive capacitor array and a negative capacitor array, and has a negative offset relative to the reference differential voltage.

[0033] In this embodiment, by using a capacitor array connection design, multiple differential signals with fixed offsets are directly generated from the output signals. This eliminates the need for additional operational amplifiers or complex switching networks, and provides multiple accurate and stable comparison thresholds for subsequent parallel comparators. This is the key to achieving efficient and stable multi-bit per-cycle conversion.

[0034] In some embodiments, each of the positive capacitor array 101 or negative capacitor array 102 includes: at least one capacitor unit 1001 with a capacitance value of 4 times the unit capacitance, and at least two capacitor unit groups; the sampling plate of the capacitor unit 1001 with a capacitance value of 4 times the unit capacitance is connected to the common sampling terminal of the capacitor array; each capacitor unit group includes: at least one capacitor unit with a capacitance value of 3 times the unit capacitance and one capacitor unit with a capacitance value of 1 time the unit capacitance, and the sampling plates of the capacitor unit with a capacitance value of 3 times the unit capacitance and the capacitor unit with a capacitance value of 1 time the unit capacitance are shared by the common sampling terminal, and the control plate of each capacitor unit is connected to the switching control unit 2.

[0035] In a capacitor array design that achieves a 2-bit high-efficiency conversion per cycle, the capacitance configuration and connection method of the capacitor cells determine the accuracy of voltage generation and switching efficiency. In some embodiments, each positive capacitor array 101 or negative capacitor array 102 of this application includes at least one capacitor cell 1001 with a capacitance value of 4 times the unit capacitance, and at least two capacitor cell groups. Specifically, the sampling plate of at least one capacitor cell 1001 with a capacitance value of 4 times the unit capacitance is directly connected to the common sampling terminal of the capacitor array, ensuring that the sampling plate can participate in the effective sampling of the input signal. The capacitor cell group includes at least one capacitor cell with a capacitance value of 3 times the unit capacitance and one capacitor cell with a capacitance value of 1 time. The sampling plates of the capacitor cells with a capacitance value of 3 times the unit capacitance and the capacitor cells with a capacitance value of 1 time are shared and connected to the same common sampling terminal. Whether it is an independent 4-times-unit capacitor cell or each 3-times-unit capacitor cell and 1-times-unit capacitor cell in a group, their control plates are independently connected to the switching control unit 2.

[0036] In this embodiment, through this control connection, the switching control unit 2 can perform precise and flexible programmable switching of the lower plate voltage of each capacitor unit in the array, thereby efficiently and accurately outputting multiple sets of differential analog voltage signals with predetermined offset relationships. This allows the circuit to pre-establish multiple quantization thresholds before the first comparison begins, thus ensuring stable output of 2-bit data in the first comparison, solving the problem of low efficiency in the first cycle conversion in the prior art.

[0037] In some embodiments, the control plate connection state of the at least one capacitor unit 1001 that controls the adjustment is specifically: the control plate connection state of the capacitor unit that controls the adjustment of 4 times the unit capacitance value is flipped.

[0038] When performing the operation of actively injecting voltage offset before the first comparison, the switching control unit 2 needs to precisely select and control a specific capacitor unit, for example, control the connection state of the control plate of capacitor unit 1001 that adjusts the capacitance value by 4 times to perform a voltage flip.

[0039] Specifically, after the sampling phase ends, the switching control unit 2 sends a control signal to a capacitor cell with a capacitance value of 4 times the unit capacitance, causing the connection state of its control plate to be flipped. For example, the capacitor cell with a capacitance value of 4 times the unit capacitance is switched from being connected to the positive reference voltage Vref to being connected to ground potential GND. Since the capacitance value of a 4-times-unit capacitor is relatively large, for example, it usually corresponds to a higher bit weight in a binary weighted array, so a single flip can generate a precise and significant voltage change at the common sampling terminal.

[0040] In one specific embodiment, after the sampling operation is completed, while the three comparators are still in the reset state, the switching control unit 2 controls the capacitor unit located on the far left with a capacitance value of 4 times that of the unit capacitor, causing it to respond and perform a control plate voltage flipping operation. Since this is an active switch before the first comparison begins, it directly changes the charge distribution stored in the four capacitor arrays, thereby establishing a voltage with a precise offset relationship at the output terminals of the four capacitor arrays before the first comparison starts. For example, if the input analog signals VINP and VINN have an offset of 1 / 4Vref, then the differential analog voltage signal DAC1P output by the first positive capacitor array is VINP - 1 / 4 * Vref, the differential analog voltage signal DAC1N output by the first negative capacitor array is VINN + 1 / 4 * Vref, the differential analog voltage signal DAC2P output by the second positive capacitor array is VINP + 1 / 4 * Vref, and the differential analog voltage signal DAC2N output by the second negative capacitor array is VINN - 1 / 4 * Vref.

[0041] In some embodiments, the difference between the differential analog voltage signals output by the positive capacitor array of the second differential capacitor array group and the negative capacitor array of the first differential capacitor array group forms the first set of differential comparison signals; the difference between the differential analog voltage signals output by the positive capacitor array of the first differential capacitor array group and the negative capacitor array of the first differential capacitor array group forms the second set of differential comparison signals; and the difference between the differential analog voltage signals output by the positive capacitor array of the second differential capacitor array group and the negative capacitor array of the second differential capacitor array group forms the third set of differential comparison signals.

[0042] To achieve parallel comparison of multiple thresholds, this application designs the signal routing for the output signals of the two differential capacitor array groups, so that they can form three sets of comparison signals with precise offset relationships through direct differential connection.

[0043] Specifically, the positive capacitor array output of the second differential capacitor array group is differentially connected to the negative capacitor array output of the first differential capacitor array group. The difference between them forms the first set of differential comparison signals, which serves as the reference voltage for subsequent comparisons, and its value directly reflects the original input differential voltage. The positive capacitor array output of the first differential capacitor array group is differentially connected to the negative capacitor array output of the same group, and the difference between them forms the second set of differential comparison signals. The positive capacitor array output of the second differential capacitor array group is differentially connected to the negative capacitor array output of the same group, and the difference between them forms the third set of differential comparison signals. Based on the differential connection described above, three different comparison pairs are obtained. For example, suppose four sets of differential analog voltage signals DAC1P, DAC1N, DAC2P, and DAC2N with predetermined voltage amplitude offset relationships are output, and DAC1P = VINP - 1 / 4 * Vref, DAC1N = VINN + 1 / 4 * Vref, DAC2P = VINP + 1 / 4 * Vref, DAC2N = VINN - 1 / 4 * Vref; then the first set of differential comparison signals is DAC2P - DAC1N = (VINP - VINN), the second set of differential comparison signals is DAC1P - DAC1N = (VINP - VINN) - 1 / 2 * Vref, and the third set of differential comparison signals is DAC2P - DAC2N = (VINP - VINN) + 1 / 2 * Vref.

[0044] In this embodiment, by directly connecting wires and configuring them as differential analog voltage signals with a predetermined voltage amplitude offset relationship, the generation of three different threshold comparison signals is realized without the need for additional operational amplifiers or complex switching networks, which ensures accuracy while minimizing circuit complexity and power consumption.

[0045] In some embodiments, the sampling plate is an upper plate or a lower plate, and the switching control unit is a switch array corresponding to each pair of capacitor array control loops. The switch array includes multiple MOS transistor switching units, each of which corresponds to the control plate of a capacitor unit. The signal input terminal of the MOS transistor switching unit is electrically connected to the control plate of the corresponding capacitor unit, the first selection terminal of the MOS transistor switching unit is electrically connected to the ground terminal, and the second selection terminal of the MOS transistor switching unit is configured to be connected to a dynamic register. The MOS transistor switching unit is also configured to control the signal input terminal to conduct with the first selection terminal or the second selection terminal based on the digital control signal output by the dynamic register, so as to switch the conduction state between the control plate and the ground terminal or the dynamic register.

[0046] To achieve precise, independent, and high-speed voltage switching of the control plate of each capacitor unit in the capacitor array, the embodiments of this application use a switching control unit to optimize the hardware. In some examples, the switching control unit is a switch array connected to each pair of capacitor array control loops, and the switch array is composed of multiple MOS transistor switching units with the same function. Each switching unit precisely corresponds to and controls the control plate of a capacitor unit.

[0047] Specifically, each MOSFET switching unit has three key ports: a signal input terminal, a first strobe terminal, and a second strobe terminal. The signal input terminal is directly electrically connected to the control plate of the corresponding capacitor unit to form a control path. The first strobe terminal is fixedly connected to the ground terminal of the circuit to provide a definite low-level reference. The second strobe terminal is configured to be connected to the corresponding output node of the dynamic register to receive a high-precision control voltage generated by digital logic that varies with each comparison result.

[0048] Each MOSFET switching unit acts as a controlled single-pole double-throw switch, determined by the digital control signal output from the dynamic register. Specifically, the first, second, and third sets of differential comparison signals generated earlier directly output a 3-bit thermometer code. This thermometer code, after decoding, becomes the 2-bit digital code generated by the first comparison. This 2-bit comparison result is sent to the dynamic register in real time and directly fed back to the control plate of the capacitor array-based digital-to-analog converter. Based on the different digital results generated by this comparison, the dynamic register generates corresponding control signals to switch the base plate voltage of the capacitor array, thereby setting a new reference voltage threshold corresponding to the current quantization range for the next comparison. When a specific control signal is received, the switching unit connects the signal input terminal to the first gating terminal, connecting the corresponding capacitor control plate to the ground terminal, thus pulling its potential low. Conversely, when another set of control signals is received, the switching unit switches the path, connecting the signal input terminal to the second gating terminal, thereby controlling the potential of the control plate to the high-level signal output by the dynamic register.

[0049] Based on the different digital results generated in the first comparison, the dynamic register will generate corresponding control signals to switch the base plate voltage of the capacitor array and obtain the 2-bit digital code generated in the second comparison. The corresponding first set of differential comparison signals is DAC1P-DAC1N=VINP-VINN-6 / 8*Vref, the second set of differential comparison signals is DAC2P-DAC1N=VINP-VINN-7 / 8*Vref, and the third set of differential comparison signals is DAC2P-DAC2N=VINP-VINN+5 / 8*Vref.

[0050] Figure 4For a schematic diagram illustrating the calculation of output voltage at each stage during the analog-to-digital conversion process provided in this application embodiment, please refer to [link / reference]. Figure 4 The paper presents the output voltage calculation formulas for four capacitor arrays (DAC1P, DAC1N, DAC2P, and DAC2N) at different time points: after sampling, before the first comparison, and after feedback switching based on specific comparison results. It clearly reveals how the output of each array is preset with a voltage offset of ±Vref / 4 under the key operation of actively flipping the capacitor before the first comparison. The subsequent part lists the updated calculation formulas for the output voltage of each array after feedback switching when different codes are output during the first comparison, such as 01, 10, 11, and 00. It fully describes the voltage quantization relationship of the signal in the complete link from sampling, preset offset, to feedback subdivision.

[0051] Figure 5 This is a schematic diagram of the quantization threshold distribution during parallel comparison provided in an embodiment of this application. See also... Figure 5 Taking the dynamic setting of comparator thresholds during the second conversion in 2-bit mode of an analog-to-digital converter as an example, after completing the first comparison and obtaining a 2-bit digital code output, the input voltage range is locked within the corresponding quarter-interval based on the comparison result. Subsequently, the dynamic register sets a new set of differential input thresholds for the three parallel comparators according to a preset mapping relationship, which further subdivides the sub-interval. Each set of fractions, such as 7 / 8, 6 / 8, 5 / 8, etc., represents the specific normalized threshold voltage set for the three comparators under a certain first output result. For example, when the first output is 11, the comparator threshold is set between +5 / 8 Vref and +7 / 8 Vref, thereby further dividing the high-end sub-interval into four finer levels so that the next 2-bit digital code can be output through the second parallel comparison. This mechanism is the core of achieving efficient, step-by-step subdivision quantization, ensuring that 2-bit data can be stably produced in each conversion cycle.

[0052] After obtaining the 2-bit digital code generated by the second comparison, this code is immediately fed to the dynamic register. Based on the result of the second 2-bit digital code, the dynamic register decodes and generates the corresponding third set of switching control signals. This drives the switching control unit to perform a third switching operation on the lower plate voltage of all relevant capacitor units in the four capacitor arrays, further adjusting the residual voltage on each capacitor array and setting a new quantization range for the next comparison. Then, the third comparison begins. Each cycle of digital code output, dynamic register feedback, capacitor array switching, and parallel comparison generates a new 2-bit digital code until the accumulated number of bits reaches the ADC's preset total conversion accuracy. For example, it completes an 8-bit code conversion after four cycles, thus achieving efficient, multi-cycle, and stable 2-bit digital code output per cycle successive approximation analog-to-digital conversion.

[0053] Secondly, embodiments of this application provide a digital-to-analog conversion method that facilitates improving the performance of analog-to-digital converters.

[0054] like Figure 6 As shown in the figure, an embodiment of this application provides a digital-to-analog conversion method, including: S11. Control and adjust the connection state of the control plates of at least one capacitor unit in the positive capacitor array and the negative capacitor array in at least one differential capacitor array group, so that the capacitor array unit outputs multiple sets of differential analog voltage signals with a predetermined voltage amplitude offset relationship; wherein, the capacitor array unit includes at least one differential capacitor array group. In successive approximation analog-to-digital conversion, one of the challenges in improving conversion speed lies in making full use of the first comparison cycle. Traditional methods often only output 1 bit of data during the first comparison, resulting in an inherent bottleneck in conversion efficiency. To overcome this limitation, this application provides a digital-to-analog conversion method that introduces an active voltage offset injection step after sampling and before the first comparison, thereby achieving the output of at least 2 bits of digital code during the first comparison.

[0055] First, during the sampling phase, at least one differential capacitor array group is sampled, and a charge proportional to the input analog signals VINP and VINN is established on the upper plate of the capacitor array.

[0056] After the sampling phase ends, the comparator is still in a reset and not started state. According to the preset timing, it actively controls the voltage of the lower plate of at least one specified capacitor unit to perform a flip operation. For example, it switches the lower plate of a specific capacitor in the positive terminal array from the state of being connected to the positive reference voltage Vref to the state of being connected to the ground potential.

[0057] Because the switching of capacitors changes the charge distribution of the capacitor array and affects the output voltage of all associated capacitor arrays through capacitive coupling, a set of differential analog voltage signals DAC1P, DAC1N, DAC2P, and DAC2N with precise offset relationships are formed at the output of all capacitor arrays before comparison. Assuming the preset offset is 1 / 4Vref, then DAC1P = VINP - 1 / 4 * Vref, DAC1N = VINN + 1 / 4 * Vref, DAC2P = VINP + 1 / 4 * Vref, and DAC2N = VINN - 1 / 4 * Vref.

[0058] S12. Perform parallel comparison on the differential analog voltage signal and output the comparison result as a 2-bit digital code.

[0059] After obtaining multiple sets of differential analog voltage signals with precise offsets through preset capacitor switching, the circuit enters the efficient parallel quantization stage.

[0060] Specifically, differential analog voltage signals are simultaneously and in parallel fed into multiple comparators. Each comparator receives a pair of differential signals composed of different capacitor array output combinations. These signal pairs have a fixed voltage offset, and all comparators synchronously compare their respective input pairs under the same clock control. For example, assuming four sets of differential analog voltage signals DAC1P, DAC1N, DAC2P, and DAC2N with predetermined voltage amplitude offset relationships are output, and DAC1P=VINP-1 / 4*Vref, DAC1N=VINN+1 / 4*Vref, DAC2P=VINP+1 / 4*Vref, and DAC2N=VINN-1 / 4*Vref, then the input of the comparator is DAC2P-DAC1N=(VINP-VINN), the input of the second comparator is DAC1P-DAC1N=(VINP-VINN)-1 / 2*Vref, and the input of the third comparator is DAC2P-DAC2N=(VINP-VINN)+1 / 2*Vref.

[0061] The parallel output of the comparator is typically a thermometer code, also known as a thermometer code, which uses a continuous string of "1"s to represent numerical values. This encoding method is widely used in analog-to-digital converters (ADCs). The parallel output of the comparator is then fed into a decoding logic unit. This unit directly maps and generates a valid digital code of at least 2 bits based on the combined states of the multiple comparator outputs, serving as the final result of the first comparison. This process is completed within one comparison cycle, thus achieving high-speed and efficient conversion from analog signals to multi-bit digital codes.

[0062] The analog-to-digital conversion method provided in this application improves the symmetry and matching accuracy of signal sampling by controlling and adjusting the connection state of the control plates of at least one capacitor unit in the positive and negative capacitor arrays of at least one differential capacitor array group, thus laying a stable analog foundation for high-precision conversion. Secondly, by actively adjusting the connection state of the control plates of the capacitor units before the first comparison, a pre-offset of the output voltage is achieved before the comparator starts. This directly enables the output of at least 2 bits of digital code during the first comparison, significantly shortening the first conversion cycle and improving the overall conversion efficiency. Simultaneously, by pre-setting the voltage amplitude offset relationship between the capacitor array outputs, multiple accurate and stable quantization thresholds are provided for multiple parallel comparators, ensuring the reliability and linearity of parallel comparison. This overcomes the bottleneck of low first-conversion efficiency in traditional successive approximation ADCs and improves the performance of the analog-to-digital converter.

[0063] In some embodiments, after simultaneously comparing the differential analog voltage signals and outputting a comparison result of at least 2 bits, the method includes: generating a switching control signal based on the comparison result; controlling the connection state of the control plates of at least one capacitor unit in the positive capacitor array and at least one capacitor unit in the negative capacitor array of at least one differential capacitor array group according to the switching control signal; and outputting a differential analog voltage signal; performing a parallel comparison on the differential analog voltage signals again and outputting a comparison result of at least 2 bits.

[0064] After successfully completing the first parallel comparison and outputting the first 2-bit digital code, it is still necessary to perform iterative approximation in a loop to gradually improve the conversion accuracy.

[0065] Specifically, firstly, a set of precise switching control signals is generated based on the 2-bit digital code output from the first comparison. These signals define which capacitor cells need to be switched and in what state. Then, according to these switching control signals, the control plate connection states of relevant capacitor cells in at least one differential capacitor array group are adjusted. For example, depending on the digital code, the lower plate of a specific capacitor may be switched from ground potential to the reference voltage, or vice versa. After the switching is complete, the charge distribution on the capacitor array changes again, generating an updated set of differential analog voltage signals at its output. These updated signals represent another precise division of the remaining voltage range after the previous comparison. Next, similar to the first comparison, this updated differential analog voltage signal is simultaneously input to multiple comparators operating in parallel. The comparators again synchronously compare these voltage pairs with the new offset relationship. Finally, the output of this parallel comparison is decoded to generate and output the next 2-bit digital code. This newly generated digital code, together with the previous results, constitutes a higher-precision digital output.

[0066] In this embodiment, the process of digital result feedback, generating control signals, switching capacitor states, updating output voltage signals, and parallel comparison constitutes a complete conversion cycle. This cycle can be repeated. Each cycle further subdivides the voltage range based on the previous result and outputs a new 2-bit code until the predetermined total conversion accuracy is reached. For example, executing 4 cycles outputs 8 bits, thereby realizing an efficient successive approximation digital-to-analog conversion method that stably produces multiple bits per cycle.

[0067] In some embodiments, before performing parallel comparison of the differential analog voltage signal, the method includes: connecting the output terminals of the capacitor array units to three comparators in a predetermined combination; the predetermined combination includes: connecting the negative capacitor array output terminal of the first differential capacitor array group and the positive capacitor array output terminal of the second differential capacitor array group to the differential input terminal of the first comparator; connecting the positive capacitor array output terminal and the negative capacitor array output terminal of the first differential capacitor array group to the differential input terminal of the second comparator; and connecting the positive capacitor array output terminal and the negative capacitor array output terminal of the second differential capacitor array group to the differential input terminal of the third comparator.

[0068] Before initiating parallel comparison operations on differential analog voltage signals, a correct signal path needs to be established from the capacitor array output to the comparator input. In some cases, the outputs of the capacitor array units can be connected to the differential inputs of the three comparators in a specific predetermined combination, thereby creating comparison pairs with different offsets for each comparator.

[0069] Specifically, firstly, signals are drawn from the negative capacitor array output of the first differential capacitor array group and simultaneously from the positive capacitor array output of the second differential capacitor array group. These two signals are connected together to the positive and negative differential inputs of the first comparator, forming a first comparison pair. Next, signals are drawn from the positive capacitor array output of the first differential capacitor array group and the negative capacitor array output of the same group, respectively. These two signals, originating from the same group but with opposite polarities, are connected together to the positive and negative differential inputs of the second comparator, forming a second comparison pair. Finally, signals are drawn from the positive capacitor array output of the second differential capacitor array group and the negative capacitor array output of the same group, respectively. These two signals are connected together to the positive and negative differential inputs of the third comparator, forming a third comparison pair.

[0070] In some embodiments, at least the differential output signal of the first comparator is configured as a reference differential voltage, at least the differential comparison signal of the second comparator has a positive offset relative to the voltage amplitude of the reference differential voltage, and at least the differential comparison signal of the third comparator has a negative offset relative to the voltage amplitude of the reference differential voltage.

[0071] In some examples, the signals processed by the comparators also have a precise hierarchical relationship. Specifically, at least the differential input signal processed by the first comparator, for example, the signal consisting of the difference between the voltage of the second positive terminal array and the voltage of the first negative terminal array, is set as the reference differential voltage, which can directly reflect the original difference VINP-VINN of the input signal and serve as the central reference for the entire quantization range.

[0072] At the same time, at least the differential input signal processed by the second comparator has a positive offset in amplitude relative to the reference differential voltage. The second comparator will flip when the input signal is greater than the positive offset threshold.

[0073] Correspondingly, at least the differential input signal processed by the third comparator has a negative offset relative to the reference differential voltage, and the third comparator will flip when the input signal is below the negative offset threshold.

[0074] Through a single parallel comparison operation, the output states of the three comparators form a thermometer code, uniquely determining which of the four different voltage ranges the input signal falls into. Specifically, the combination of the three comparator outputs directly corresponds to whether the input signal is below the negative offset threshold, between the negative offset and the reference, between the reference and the positive offset, or above the positive offset threshold. Decoding this output state directly outputs a 2-bit digital code.

[0075] Therefore, by constructing a multi-threshold parallel comparison with a preset offset, a 2-bit conversion can be completed in a single comparison cycle, which improves the efficiency of the traditional serial successive approximation process and provides core methodological support for achieving high-speed analog-to-digital conversion.

[0076] Thirdly, embodiments of this application also provide an analog-to-digital converter (ADC) to facilitate improvements in the performance of the ADC.

[0077] The analog-to-digital converter (ADC) includes: a digital-to-analog conversion circuit, a comparison unit, and a dynamic register; the signal output terminal of the digital-to-analog conversion circuit is electrically connected to the signal input terminal of the comparison unit, the signal output terminal of the comparison unit is electrically connected to the signal input terminal of the dynamic register, and the signal output terminal of the dynamic register is electrically connected to the switching control unit of the digital-to-analog conversion circuit; the digital-to-analog conversion circuit is any of the digital-to-analog conversion circuits described in the preceding embodiments, configured to receive an analog input signal, and output multiple sets of differential analog voltage signals with predetermined voltage amplitude offset relationships after adjustment by the switching control unit; the comparison unit is connected to the output terminal of the capacitor array unit of the digital-to-analog conversion circuit, configured to compare the multiple sets of differential analog voltage signals output by the capacitor array unit, and output a comparison result corresponding to a 2-bit digital code; the signal input terminal of the dynamic register is connected to the signal output terminal of the comparison unit, and the signal output terminal is connected to the switching control terminal of the capacitor array unit, configured to receive the comparison result and generate a switching control signal for controlling the digital-to-analog conversion circuit to perform the next voltage adjustment based on the comparison result.

[0078] This application achieves a stable 2-bit digital code output for each comparison, which can be efficiently applied to the sub-analog-to-digital converter in a pipelined successive approximation analog-to-digital converter. For example, 4-bit quantization can be completed in just two conversions, or 6-bit quantization can be completed in three conversions. This significantly improved conversion efficiency enables the SAR architecture to support single-channel sampling rates of 1GHz or even higher, thus effectively solving the problem of insufficient conversion speed of traditional SAR ADCs in high-speed application scenarios such as Wi-Fi 7 and 5G.

[0079] Secondly, the proposed solution is also of great value to multi-channel time-interleaved analog-to-digital converters. Since the conversion speed of the single-channel ADC is greatly improved, the number of parallel time-interleaved channels can be significantly reduced while keeping the total system sampling rate unchanged. This reduces the overall system complexity and chip area, and greatly alleviates the pressure and complexity of the background calibration circuit in calibrating the mismatch between multiple channels, thereby improving the system's reliability and energy efficiency.

[0080] This application employs a novel capacitor array structure, providing a physical basis for parallel comparison. Furthermore, a preset capacitor switching operation is introduced before the first conversion, which is crucial for achieving a 2-bit output in the first cycle. It should be noted that although this application's embodiments demonstrate the specific operation of capacitor switching using the upper plate sampling method, those skilled in the art will understand that, based on the same inventive concept, the lower plate sampling method, through equivalent timing and switching control, can also achieve the effect of injecting an offset voltage before the first comparison and achieving a 2-bit conversion per cycle. Therefore, the scope of protection of this invention should explicitly cover all specific embodiments based on the same principle of upper plate sampling and lower plate sampling.

[0081] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also any other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0082] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from the other embodiments.

[0083] In particular, the device embodiments are basically similar to the method embodiments, so they are described in a simpler way. For relevant details, please refer to the description of the method embodiments.

[0084] For ease of description, the above apparatus is described by dividing it into functional units / modules. Of course, in implementing this application, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0085] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0086] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A digital-to-analog converter circuit, characterized in that, include: A capacitor array unit, the capacitor array unit including at least one differential capacitor array group, each differential capacitor array group including: a positive capacitor array and a negative capacitor array, the positive capacitor array and the negative capacitor array respectively including: multiple capacitor units and sampling plates and control plates disposed on the upper and lower sides relative to each capacitor unit; A switching control unit, connected to the control plate of the capacitor unit in each of the differential capacitor array groups, is configured to control and adjust the connection state of the control plates of at least one capacitor unit in the positive and negative capacitor arrays of at least one differential capacitor array group before the first comparison of the differential analog voltage signal output by the capacitor array unit, so that the capacitor array unit outputs multiple sets of differential analog voltage signals with a predetermined voltage amplitude offset relationship; wherein the predetermined voltage amplitude offset relationship is used to ensure that the result of the first comparison of the differential analog voltage signal output by the capacitor array unit is at least 2 bits of data.

2. The digital-to-analog converter circuit according to claim 1, characterized in that, The capacitor array unit includes two differential capacitor array groups for outputting four sets of differential analog voltage signals with predetermined voltage amplitude offset relationships; wherein the four sets of differential analog voltage signals are used to form at least three sets of differential comparison signals, at least the first set of differential comparison signals is configured as a reference differential voltage, at least the second set of differential comparison signals has a positive voltage amplitude offset relative to the reference differential voltage, and at least the third set of differential comparison signals has a negative voltage amplitude offset relative to the reference differential voltage.

3. The digital-to-analog converter circuit according to claim 1, characterized in that, Each of the positive capacitor arrays or negative capacitor arrays includes: at least one capacitor cell with a capacitance value of 4 times the unit capacitance, and at least two groups of capacitor cells; The sampling plate of the capacitor unit with a capacitance value of 4 times that of the unit capacitor is connected to the common sampling terminal of the capacitor array. Each capacitor unit group includes: at least one capacitor unit with a capacitance value of 3 times the unit capacitance value and one capacitor unit with a capacitance value of 1 time the unit capacitance value. The sampling plates of the capacitor unit with a capacitance value of 3 times the unit capacitance value and the capacitor unit with a capacitance value of 1 time the unit capacitance value in each capacitor unit group are connected to the common sampling terminal. The control plate of each capacitor unit is connected to the switching control unit.

4. The digital-to-analog converter circuit according to claim 1, characterized in that, The connection state of the control plate of at least one capacitor unit that controls the adjustment is specifically: the connection state of the control plate of the capacitor unit that controls the adjustment of 4 times the capacitance value of the unit is flipped.

5. The digital-to-analog converter circuit according to claim 2, characterized in that, The difference between the differential analog voltage signals output by the positive capacitor array of the second differential capacitor array group and the negative capacitor array of the first differential capacitor array group forms the first group of differential comparison signals. The difference between the differential analog voltage signals output by the positive capacitor array and the negative capacitor array of the first differential capacitor array group forms the second group of differential comparison signals. The difference between the differential analog voltage signals output by the positive capacitor array and the negative capacitor array of the second differential capacitor array group forms the third set of differential comparison signals.

6. The digital-to-analog converter circuit according to claim 3, characterized in that, The sampling plate is either an upper plate or a lower plate. The switching control unit is a switch array connected to each pair of capacitor array control loops. The switch array includes multiple MOS transistor switching units, each of which corresponds to the control plate of a capacitor unit. The signal input terminal of the MOS transistor switching unit is electrically connected to the control plate of the corresponding capacitor unit. The first selection terminal of the MOS transistor switching unit is electrically connected to the ground terminal. The second selection terminal of the MOS transistor switching unit is configured to be connected to a dynamic register. The MOS transistor switching unit is further configured to control the signal input terminal to be connected to the first strobe terminal or the second strobe terminal based on the digital control signal output by the dynamic register, so as to switch the conduction state between the control plate and the ground terminal or the dynamic register.

7. A digital-to-analog conversion method, characterized in that, include: The connection state of the control plates of at least one capacitor unit in the positive capacitor array and at least one capacitor unit in the negative capacitor array of at least one differential capacitor array group is controlled and adjusted so that the capacitor array unit outputs multiple sets of differential analog voltage signals with predetermined voltage amplitude offset relationships; wherein, the capacitor array unit includes at least one differential capacitor array group. The differential analog voltage signals are compared in parallel, and the comparison result is output as a digital code of at least 2 bits.

8. The digital-to-analog conversion method according to claim 7, characterized in that, After simultaneously comparing the differential analog voltage signals and outputting a comparison result of at least 2 bits, the method further includes: A switching control signal is generated based on the comparison results; According to the switching control signal, the connection state of the control plates of at least one capacitor unit in the positive capacitor array and the negative capacitor array in at least one differential capacitor array group is controlled, and a differential analog voltage signal is output. The differential analog voltage signal is compared in parallel again, and the comparison result is output as a digital code of at least 2 bits.

9. The digital-to-analog conversion method according to claim 7, characterized in that, Before performing parallel comparison of the differential analog voltage signal, the method includes: connecting the output terminals of the capacitor array units to three comparators in a predetermined combination; the predetermined combination includes: connecting the negative capacitor array output terminal of the first differential capacitor array group and the positive capacitor array output terminal of the second differential capacitor array group to the differential input terminal of the first comparator; connecting the positive capacitor array output terminal and the negative capacitor array output terminal of the first differential capacitor array group to the differential input terminal of the second comparator; and connecting the positive capacitor array output terminal and the negative capacitor array output terminal of the second differential capacitor array group to the differential input terminal of the third comparator.

10. The digital-to-analog conversion method according to claim 9, characterized in that, At least the differential output signal and differential comparison signal of the first comparator are configured as a reference differential voltage, at least the differential comparison signal of the second comparator has a positive offset relative to the voltage amplitude of the reference differential voltage, and at least the differential comparison signal of the third comparator has a negative offset relative to the voltage amplitude of the reference differential voltage.

11. An analog-to-digital converter, characterized in that, include: Digital-to-analog converter circuit, comparator unit, and dynamic register; The signal output terminal of the digital-to-analog converter is electrically connected to the signal input terminal of the comparison unit, the signal output terminal of the comparison unit is electrically connected to the signal input terminal of the dynamic register, and the signal output terminal of the dynamic register is electrically connected to the switching control unit of the digital-to-analog converter. The digital-to-analog conversion circuit is the digital-to-analog conversion circuit according to any one of claims 1-6, configured to receive analog input signals and output multiple sets of differential analog voltage signals with predetermined voltage amplitude offset relationships after adjustment by the switching control unit; The comparison unit is connected to the output terminal of the capacitor array unit of the digital-to-analog converter circuit, and is configured to compare multiple sets of differential analog voltage signals output by the capacitor array unit and output a comparison result corresponding to a 2-bit digital code. The signal input terminal of the dynamic register is connected to the signal output terminal of the comparison unit, and the signal output terminal is connected to the switching control terminal of the capacitor array unit. It is configured to receive the comparison result and generate a switching control signal based on the comparison result to control the digital-to-analog converter circuit to perform the next voltage adjustment.

Images