A multi-channel signal processing system based on parallel accumulation and hierarchical multiplication

Abstract

The application discloses a kind of multi-channel signal processing systems based on parallel accumulation and hierarchical multiplication, belong to high-precision data acquisition technical field.The system includes signal modulation module, clock adjustment module, pulse distribution module, accumulation module, hierarchical multiplication module and control module.Signal modulation module converts multiple analog signals into 1-bit digital signal;Pulse distribution module distributes each channel digital signal to accumulation module according to preset distribution strategy for accumulation;Hierarchical multiplication module is graded and multiplied when accumulation module reaches the upper limit, to improve effective precision;Clock adjustment module adjusts the clock frequency of each signal through frequency divider, to realize the synchronization or asynchronous grading of accumulation module under non-uniform distribution.The application significantly improves the flexibility, resource utilization efficiency and effective precision of multi-channel signal processing through flexible hardware resource allocation and hierarchical multiplication processing flow.

Description

Technical Field

[0001] This application relates to the field of signal processing, and more particularly to a multi-channel signal processing system based on parallel accumulation and hierarchical multiplication. Background Technology

[0002] Sigma-Delta ADCs (analog-to-digital converters) are widely used in audio processing, sensor interfaces, and precision measurement due to their high resolution and excellent noise shaping capabilities. In multi-channel data acquisition systems, such as multiphase current detection and multi-parameter biosignal monitoring, it is often necessary to process multiple analog signals simultaneously.

[0003] Traditional multi-channel Sigma-Delta ADCs typically employ an architecture where each channel has its own independently configured digital filter. Each channel's analog signal is converted to a 1-bit digital stream by an independent Sigma-Delta modulator, then downsampled and filtered by its corresponding digital filter to output a high-resolution digital result. While this architecture is simple to design, it has significant drawbacks: First, the hardware resource consumption is directly proportional to the number of channels, resulting in a larger chip area and higher power consumption, which is detrimental to highly integrated applications. Second, its resource allocation is fixed, making it impossible to differentiate configurations based on the actual importance or dynamic range requirements of each channel's signal. For example, for critical high-precision channels, a longer filtering window or a higher oversampling rate might be desired, but a fixed architecture struggles to achieve this optimization, leading to resource waste or performance bottlenecks.

[0004] Therefore, there is an urgent need for a multi-channel signal processing system with dynamically configurable hardware resources that can flexibly adapt to the characteristics of different channels. Summary of the Invention

[0005] To address the shortcomings of existing technologies and problems in current multi-channel signal processing, this application provides a multi-channel signal processing system based on parallel accumulation and hierarchical multiplication, comprising: a signal modulation module, including at least one Sigma-Delta modulator, for modulating at least one analog input signal into a 1-bit digital signal; a clock adjustment module, including at least one frequency divider connected to the clock terminal of the Sigma-Delta modulator, for configuring the clock frequency of at least one Sigma-Delta modulator; a pulse distribution module, connected to the output terminal of at least one Sigma-Delta modulator, for receiving at least one 1-bit digital signal and continuously distributing the 1-bit digital signal of each channel as pulse signals to the accumulation module according to a preset distribution strategy; and an accumulation module, including at least one first accumulation register with a configurable bit width, for... The allocated pulse signals are accumulated and counted according to the allocation strategy. A hierarchical multiplication module, connected to the accumulation module, includes at least one second accumulation register and a multiplier, used to perform a hierarchical multiplication operation in response to the accumulation module reaching its accumulation limit. After the first accumulation register reaches its accumulation limit, it is hierarchically divided into at least one second accumulation register according to the hierarchical strategy, and the first accumulation register is reset to continue accumulating. The hierarchically divided second accumulation registers are multiplied with the hierarchically divided second accumulation registers from the previous time step using the multiplier, and the second accumulation registers are updated. The hierarchical multiplication steps are repeated. The bit widths of the first and second accumulation registers are equal. A control module is used to configure the allocation strategy of the pulse allocation module, the clock frequency of the frequency divider, and the hierarchical parameters of the second accumulation register through software.

[0006] Optionally, the allocation strategy includes uniform allocation and non-uniform allocation, wherein the sum of the bit widths of the pulse signals of each channel under the uniform allocation strategy does not exceed the total bit width of the first accumulator register.

[0007] Optionally, under the non-uniform distribution strategy, the first accumulator register is configured with different bit widths for pulse signals of different channels, and the maximum configured bit width of the pulse signal of any channel does not exceed half of the total bit width of the first accumulator register.

[0008] Optionally, in the non-uniform distribution mode, the control module configures the division coefficient of the frequency divider so that the clock frequency of the Sigma-Delta modulator in all channels matches the configured bit width of the first accumulator register, thereby causing the pulse signals allocated to the first accumulator register in all channels to synchronously reach the accumulation limit, thereby triggering the hierarchical multiplication module to perform a synchronous hierarchical operation.

[0009] Optionally, in the non-uniform distribution mode, the hierarchical multiplication module supports an asynchronous hierarchical mode, the frequency divider configures the clock frequencies of the Sigma-Delta modulators of all channels to be consistent, and the hierarchical multiplication module responds when any channel independently reaches the accumulation limit in the first accumulation register, and then hierarchically assigns the current channel to the second accumulation register for multiplication processing.

[0010] The beneficial effects of this application are:

[0011] 1. Through configurable pulse allocation strategies and bit-width-independent accumulator modules, the system can flexibly switch between uniform and non-uniform allocation modes according to actual application requirements. Users can allocate more accumulator bit width (higher precision) to critical signal channels and less resources to other channels, thereby achieving optimal allocation of overall performance without changing or even reducing the total chip area and power consumption, greatly improving the utilization efficiency of hardware resources and application flexibility.

[0012] 2. To address the challenge of multi-channel data synchronization caused by uneven data distribution, this invention proposes two configurable solutions. First, by adjusting the modulator's clock frequency using a frequency divider, the accumulators of all channels are intelligently and synchronously filled, achieving simple hierarchical synchronization and ensuring strict time alignment of data across channels. This is suitable for scenarios with stringent synchronization requirements, such as multiphase measurements. Second, it supports an asynchronous hierarchical mode, where each channel is processed independently, maximizing the data throughput and accuracy of each channel. This is suitable for applications where channels are relatively independent. This flexibility greatly expands the system's applicability.

[0013] 3. Under non-uniform allocation, the accumulator bit width allocated to any channel must not exceed half of the total bit width of the accumulator register. This key design constraint prevents the risk of data overflow in subsequent multiplication operations from the source, ensuring the stability and reliability of the entire signal processing system. Attached Figure Description

[0014] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0015] Figure 1 This is a structural diagram of a multi-channel signal processing system based on parallel accumulation and hierarchical multiplication.

[0016] Figure 2 This is a schematic diagram of the processing operation based on the uniform distribution strategy in the embodiments of this application;

[0017] Figure 3 This is a schematic diagram of a non-uniform distribution strategy based on an embodiment of this application.

[0018] The above figures include the following reference numerals:

[0019] 1-Frequency divider, 2-Sigma-Delta modulator, 3-Pulse distributor, 4-First accumulator register, 5-Second accumulator register, 6-Multiplier, 7-MCU (Micro-Controller Unit). Detailed Implementation

[0020] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] like Figure 1 As shown in the diagram, this embodiment provides a structural diagram of a multi-channel signal processing system based on parallel accumulation and hierarchical multiplication. The system mainly consists of a signal modulation module, a clock adjustment module, a pulse distribution module, an accumulation module, a hierarchical multiplication module, and a control module.

[0023] The signal modulation module includes multiple Sigma-Delta modulators 2. Each Sigma-Delta modulator receives one analog input signal Vin and converts it into a high-speed 1-bit digital signal through its internal high-order noise shaping and oversampling techniques. In this embodiment, the number of modulators can be flexibly configured according to the number of channels required by the system. Figure 1 The input consists of 4 channels of analog input signals and 4 modulators. In practical applications, at least one modulator can be used in any number of modulators depending on the requirements. This application does not impose any specific restrictions.

[0024] The clock adjustment module is specifically a frequency divider 1. Each frequency divider is connected to the clock input of one Sigma-Delta modulator. Alternatively, a single frequency divider can be connected to the clock inputs of all Sigma-Delta modulators. This allows for software configuration of the division ratios of the frequency dividers, thereby independently adjusting the clock frequency of each Sigma-Delta modulator. The underlying principle is to divide the system's master clock to generate the sampling clock required by each modulator. By adjusting the division ratios, different clock frequencies can be achieved for each channel, providing a basis for subsequent synchronous or asynchronous hierarchical processing.

[0025] The pulse distribution module is specifically pulse distributor 3. The input of the pulse distributor is connected to the output of all Sigma-Delta modulators. It is used to map and distribute the 1-bit digital signal from each channel to the back-end accumulation module according to a preset distribution strategy and actual needs. The distribution strategy is configured via software and supports two modes: uniform distribution and non-uniform distribution. In uniform distribution mode, each channel receives the same bit width; in non-uniform distribution mode, each channel receives accumulation resources of different bit widths to match the different dynamic range requirements of the signal.

[0026] The accumulation module specifically includes multiple independently configurable first accumulation registers 4. In the embodiments of this application, it is specifically a 32-bit accumulation register. Through the logical configuration of the pulse distributor, its internal 32-bit width is divided into multiple logically independent regions, each region corresponding to a channel. According to the allocation strategy, the bit width range occupied by each channel in the 32-bit register is defined by software.

[0027] In one embodiment, in uniform distribution mode, the 32-bit register is divided into four 8-bit regions, with each 8-bit region allocating the pulse signal for each channel.

[0028] In another embodiment, under the non-uniform distribution mode, each channel occupies a different bit width according to the actual needs of each channel. Specifically, the first channel occupies a 4-bit bit width, the second channel occupies a 4-bit bit width, the third channel occupies an 8-bit bit width, and the fourth channel occupies a 16-bit bit width.

[0029] After the 1-bit digital signal from each channel enters the pulse distribution module, it is allocated to the corresponding logic area in the 32-bit first accumulator register for that channel. Within this area, the count value is accumulated with the previous pulse signal for each signal acquisition. Multiple channels can acquire signals simultaneously and perform parallel accumulation processing.

[0030] When the accumulation region of any channel reaches the current region's register limit, a hierarchical accumulation operation is performed through the hierarchical accumulation module. At the same time, the current first accumulation register is reset and cleared to start a new round of accumulation, while other regions that have not reached their full capacity continue to accumulate normally without interference.

[0031] The hierarchical multiplication module specifically includes multiple second accumulator registers 5 and a multiplier 6. The number of hierarchical steps can be configured via software, thus determining the required number of second accumulator registers. When the logical region of any first accumulator register in the accumulation module reaches its accumulation limit, the hierarchical multiplication module transfers the current count value of that region to the corresponding second accumulator register. The total bit width of the second accumulator register is equal to that of the first accumulator register, also a 32-bit accumulator register. Internally, it contains the effective bit width data after hierarchical steps in the first accumulator register, as well as other high-order padded data.

[0032] At this point, the multiplier multiplies the second accumulator register of any channel data after the first accumulator register has been graded, with the second accumulator register after the previous grading. The content of the second accumulator register is then updated based on the multiplication result. When the second accumulator register reaches its storage limit after multiple multiplications, the next grading operation can be executed. By executing the current loop logic, the efficiency and accuracy of the data acquisition and processing are improved.

[0033] In the pulse allocation process, the bit width of any channel configured according to actual needs shall not exceed half of the total bit width of the first accumulator register. In this embodiment, the maximum bit width allocated to any channel in the first accumulator register is 16 bits, in order to prevent data overflow when multiplying in the second accumulator register after grading.

[0034] The control module is specifically an MCU7, which can dynamically configure the following parameters in the module through software during operation: the division coefficient of each frequency divider in the clock adjustment module; the allocation bit width of each channel in the pulse distribution module under uniform or non-uniform distribution; and the accumulation count and hierarchical configuration of the second accumulator register.

[0035] Based on the multi-channel signal processing system mentioned in the above embodiments, in one embodiment, combined with... Figure 2 The diagram illustrating the uniform distribution process details the specific operation of the system in uniform distribution mode:

[0036] like Figure 2 As shown, the MCU configures the system to uniform distribution mode, acquiring and modulating the input signals of 4 channels. The total bit width of the first accumulator register is 32 bits, so each channel is allocated an 8-bit bit width. At this time, the MCU configures the clock frequency of the 4 Sigma-Delta modulators to be the same through the frequency divider. The 1 bit stream of each channel enters its respective region at the same time. Specifically, all pulse signals acquired in parallel by all channels each time are usually represented as "0" or "1". Each time a signal is acquired, the count value of each region is accumulated with the previous pulse signal.

[0037] Since the bit width and clock are the same, the counting progress of the four regions is completely consistent. After the acquisition time t1, the first accumulator register of all channels reaches the accumulation limit. At this time, the MCU controls the four channels to perform a graded operation, clearing all four regions of the first accumulator register to zero and starting a new round of accumulation. The number of grades is set to 2, that is, graded into 2 second accumulator registers, specifically the second accumulator registers of channels 1 and 2, and channels 3 and 4. When the 16-bit width data of channels 1 and 2, and channels 3 and 4 are graded to the 16 low bits of the second accumulator register, the remaining high bits are padded with zeros, and multiplied with the second accumulator registers of channels 1 and 2, and channels 3 and 4 of the previous time t0 through a multiplier. After one multiplication, the upper limit of the second accumulator register is reached, and at this time, the grading can continue to be graded into the second accumulator registers of channels 1, 2, 3, and 4 for multiplication. Under the current allocation strategy, when the first accumulator register reaches the accumulation limit, it can also be directly divided into four second accumulator registers by the MCU, namely the second accumulator registers of channels 1, 2, 3, and 4. Specifically, the low-order bits of the second accumulator register are filled with zeros, and the remaining high-order bits are padded with zeros. At this time, four accumulation multiplications can be performed, that is, the second accumulator registers after being divided at four different times are multiplied together until the accumulation limit is reached.

[0038] The uniform distribution strategy ensures the synchronization of all channels and the consistent data processing rhythm, making it suitable for applications involving multi-channel synchronous acquisition.

[0039] In another embodiment, combined Figure 3 The diagram below illustrates the specific working process of the system under the non-uniform distribution mode in detail:

[0040] like Figure 3 As shown, the MCU configures the system in a non-uniform distribution mode to adapt to the dynamic range differences of different channel signals, and acquires and modulates the input signals of four channels. The total bit width of the first accumulator register is 32 bits. According to actual needs, the bit width of the first channel is allocated to 4 bits, the bit width of the second channel is allocated to 4 bits, the bit width of the third channel is allocated to 8 bits, and the bit width of the fourth channel is allocated to 16 bits. The 1 bit stream of each channel enters its respective area of ​​the first accumulator register for accumulation at the same time.

[0041] The system supports two hierarchical modes. The first is the asynchronous hierarchical mode, which involves hierarchically classifying the current channel when the accumulation limit of any single channel in the first accumulation register region overflows. The specific working process includes:

[0042] At time t1, when the 4-bit region of channel 1 reaches its accumulation limit first, a tiering operation is triggered. At this time, the MCU controls the current 4 valid count values ​​of that region to be tiered and transferred to the corresponding second accumulator register, stored in the lower 4 bits [0:3] of the second accumulator register, with the remaining higher bits padded with zeros. Subsequently, the first accumulator register region of channel 1 is reset and cleared to zero, and accumulation begins again.

[0043] When the system reaches the next sampling time t2, the 4-bit region of channel 1 is accumulated to its upper limit again. At this time, the 4-bit data [0:3] stored in the second accumulator register at the previous time t1 is logically shifted upwards by 4 bits to the [4:7] position of the register. This step is to make room for the lower bits of the new data. The 4-bit new data from channel 1 at the current time t2 is written into the lower 4 bits [0:3] of the second accumulator register.

[0044] Once all data from all channels has been allocated to the second accumulator register, the multiplier performs a cumulative multiplication operation and updates the result to the second accumulator register. Since the bit width allocated to any channel does not exceed half of the first accumulator register, overflow of the second accumulator register can be prevented, and the tiering operation can continue.

[0045] The second type is a synchronization hierarchical mode based on global clock triggering. Although the bit width of each channel is different, synchronization hierarchical can be achieved through the intervention of the clock adjustment module. The MCU controls the clock frequency of the Sigma-Delta modulator of the 1st, 2nd and 3rd channels by adjusting the division coefficient of the frequency divider, or suppresses oversampling of the high-frequency channels, thereby precisely controlling the accumulation speed of each channel.

[0046] Through the above adjustments, the previously asynchronous channels simultaneously reach their respective accumulation limits at the same global moment. At this point, the system triggers a synchronization hierarchical operation, performing hierarchical multiplication on the hierarchical data of the four channels. Now, the data from all channels are strictly aligned on the time axis, facilitating subsequent unified mathematical operations or filtering.

[0047] In summary, the allocation strategy, number of stages, and working mode can be flexibly switched through software configuration, taking into account hardware resource utilization, processing accuracy, and system flexibility, and can be widely used in the fields of multi-channel high-precision data acquisition and signal processing.

[0048] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0049] In the above embodiments of this application, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0050] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0051] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0052] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A multi-channel signal processing system based on parallel accumulation and hierarchical multiplication, characterized in that, include: The signal modulation module includes at least one Sigma-Delta modulator for modulating at least one analog input signal into a 1-bit digital signal; A clock adjustment module includes at least one frequency divider connected to the clock terminal of the Sigma-Delta modulator, used to configure the clock frequency of at least one of the Sigma-Delta modulators; The pulse distribution module is connected to at least one output terminal of the Sigma-Delta modulation, and is used to receive at least one 1-bit digital signal and continuously distribute the 1-bit digital signal of each channel as a pulse signal to the accumulation module according to a preset distribution strategy. An accumulation module includes at least one first accumulation register with a configurable bit width, used to accumulate and count the allocated pulse signal according to the allocation strategy; A hierarchical multiplication module, connected to the accumulation module, includes at least one second accumulation register and a multiplier. It is used to perform a hierarchical multiplication operation in response to the accumulation module reaching its accumulation limit. After the first accumulation register reaches its accumulation limit, it is hierarchically divided into at least one second accumulation register according to a hierarchical strategy. The first accumulation register is then reset and accumulation continues. The hierarchically divided second accumulation registers are multiplied by the previous hierarchically divided second accumulation register using the multiplier, and the second accumulation registers are updated. This hierarchical multiplication process is repeated. The first accumulator register and the second accumulator register have the same bit width; The control module is used to configure the allocation strategy of the pulse allocation module, the clock frequency of the frequency divider, and the hierarchical parameters of the second accumulator register through software.

2. The multi-channel signal processing system based on parallel accumulation and hierarchical multiplication according to claim 1, characterized in that, The allocation strategy includes uniform allocation and non-uniform allocation. Under the uniform allocation strategy, the sum of the bit widths of the pulse signals of each channel does not exceed the total bit width of the first accumulator register.

3. A multi-channel signal processing system based on parallel accumulation and hierarchical multiplication according to claim 2, characterized in that, Under the non-uniform distribution strategy, the first accumulator register is configured with different bit widths for pulse signals of different channels, and the maximum configured bit width of the pulse signal of any channel does not exceed half of the total bit width of the first accumulator register.

4. A multi-channel signal processing system based on parallel accumulation and hierarchical multiplication according to claim 2, characterized in that, In the non-uniform distribution mode, the control module configures the division coefficient of the frequency divider so that the clock frequency of the Sigma-Delta modulator in all channels matches the configured bit width of the first accumulator register, thereby causing the pulse signals allocated to the first accumulator register in all channels to synchronously reach the accumulation limit, thereby triggering the hierarchical multiplication module to perform a synchronous hierarchical operation.

5. A multi-channel signal processing system based on parallel accumulation and hierarchical multiplication according to claim 2, characterized in that, In the non-uniform distribution mode, the hierarchical multiplication module supports asynchronous hierarchical mode. The frequency divider configures the clock frequency of the Sigma-Delta modulator of all channels to be consistent. In response to any channel independently reaching the accumulation limit in the first accumulation register, the hierarchical multiplication module then divides the current channel into the second accumulation register for multiplication processing.

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