Communication method and communication apparatus based on LDPC code

Abstract

A communication method and a communication device based on LDPC code, in which a device encodes or decodes based on an LDPC matrix, the LDPC matrix is determined based on a base matrix, the base matrix includes an extended check region, an incremental redundancy region and a core region, the extended check region is a lower triangular matrix with diagonal elements being 1, the extended check region includes at least one 1 element except the diagonal elements, the column where the at least one 1 element is located is a first column, the row where the diagonal element in the first column is located is a first row, the row same as the row where the first value maximum in a first region is located, the first value is related to the row weight of the corresponding row, the first region is composed of consecutive rows in a second region, the second region is a region composed of part columns in the incremental redundancy region, and the part columns are the same as the columns with a column weight of 2 in the core region. The method can flexibly construct the LDPC code and improve the performance of the LDPC code.

Description

Technical Field

[0001] This application relates to the field of coding, and more specifically, to a communication method and communication device based on LDPC codes. Background Technology

[0002] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used channel coding schemes. Quasi-cyclic low-density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of their parity check matrix, they can be encoded using simple feedback shift registers, reducing the coding complexity of LDPC codes.

[0003] Currently, in the LDPC basemap design of 5th generation (5G) systems, the extended parity region adopts a raptor-like structure, where the extended parity region is an identity matrix, and the row weight of each row and the column weight of each column are both equal to 1. The disadvantage of the raptor-like structure is that the column weight is only 1 within this extended parity region, thus preventing density evolution. Summary of the Invention

[0004] The embodiments of this application provide a communication method and communication device based on LDPC codes, which can flexibly construct LDPC codes and improve the performance of the constructed LDPC codes.

[0005] In the first aspect, a communication method based on LDPC code is provided. This method can be executed by a transmitting device. Unless otherwise specified, the term "transmitting device" in this application can refer to the transmitting device itself (e.g., a network device, a terminal device), a component in the transmitting device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the transmitting device.

[0006] The method includes: acquiring an information bit sequence; encoding the information bit sequence according to an LDPC matrix to obtain a codeword sequence, wherein the LDPC matrix is ​​determined based on an LDPC code base matrix, the base matrix includes an extended parity check region, an incremental redundancy region, and a core region, the extended parity check region is a lower triangular square matrix with all diagonal elements being 1, the extended parity check region includes at least one 1 element in addition to the diagonal elements, the column containing at least one 1 element is the first column, the row containing the diagonal elements in the first column is the first row, the first row is the same row as the row with the largest first value in the first region, the first value of each row in the first region is correlated with the row weight of each row, the first region is composed of multiple consecutive rows in the second region, the second region is a region composed of some columns in the incremental redundancy region, at least one column in the partial columns is the same column with a first feature in the core region, the column with the first feature is the column with a column weight of 2 in the core region.

[0007] Specifically, the technical solution of this application proposes a structured basis matrix design method. The position of the 1 element (excluding diagonal elements) in the extended check region of the basis matrix is ​​related to the first value of a row in a sub-region (i.e., the first region) of the incremental redundancy region. The position of this sub-region is further related to the double columns in the core region. This method, by associating the first region with the double columns in the core region, strengthens the check weakness of the double columns in the core region within the extended check region. Furthermore, the first value of a row in the first region is correlated with the row's row weight; a larger first value allows the double columns to obtain more check information. Therefore, the method proposed in this application can effectively improve the performance of LDPC codes.

[0008] In some implementations of the first aspect, the first value of each row in the first region is the row weight of each row, or the first value of each row in the first region is determined based on the value of the element in each row and the coefficient (or weight) corresponding to the column where the element is located.

[0009] The above technical solution describes the characteristics that the first value may satisfy. Satisfying the first characteristic can improve performance over a wider range of bitrates in the base matrix, while satisfying the second characteristic can achieve a greater performance improvement at the same bitrate.

[0010] In some implementations of the first aspect, the column containing the incremental redundancy region is the same column as the column containing the core region, and the row containing the incremental redundancy region is the same row as the row containing the extended verification region.

[0011] In some implementations of the first aspect, at least one 1 element is located in the first lower triangular matrix of the extended verification region, wherein the diagonal elements of the first lower triangular matrix are all located on the diagonal of the extended verification region, and the row of the first lower triangular matrix is ​​the same row as the row of the first region.

[0012] In some implementations of the first aspect, the extended verification region contains an additional 1 element in addition to the diagonal elements and at least one 1 element. The additional 1 element is located in the first lower triangular matrix. The at least one 1 element and the additional 1 element are located in N columns of the first lower triangular matrix. The N diagonal elements in the N columns are located in N rows of the first lower triangular matrix, where N is a positive integer. The N rows are the same rows as the rows corresponding to the first N values ​​in the first value of the first region.

[0013] The above technical solution describes the characteristics of the 1 element present in the first lower triangular matrix included in the extended check region. The advantage of this method is that placing a 1 element in the column containing the diagonal elements of the row corresponding to the first value in the sorting sequence significantly improves the performance of the LDPC code.

[0014] In some implementations of the first aspect, if the first value of the i1th row in the first region is equal to the first value of the i2th row, and the i1th row is before the i2th row, then the order of the first value of the i1th row is before the first value of the i2th row; or, if the i1th row is contained in the i3th row of the base matrix, and the i2th row is contained in the i4th row of the base matrix, and the row weight of the i3th row is greater than the row weight of the i4th row, then the order of the first value of the i1th row is before the first value of the i2th row.

[0015] In the above technical solution, when the first values ​​corresponding to rows i1 and i2 in the first region are the same, since row i1 precedes row i2, the earlier a row is, the earlier it is selected when the bitrate decreases. Therefore, in the first sorting method, the first value of row i1 can be placed before the first value of row i2. Furthermore, the row weight of row i3 is greater than that of row i4, and a higher row weight has a greater impact on performance improvement. Therefore, in the second sorting method, the first value of row i1 corresponding to row i3 can be placed before the first value of row i2 corresponding to row i4.

[0016] In some implementations of the first aspect, each of the N columns contains only one 1 element, excluding the diagonal elements.

[0017] It is understandable that the performance of having only one 1 element in each column (excluding the diagonal) is equivalent to having multiple 1 elements. Therefore, having only one 1 element in each column (excluding the diagonal) can reduce the storage resources required for the base matrix.

[0018] In some implementations of the first aspect, there is a row in each column that contains a 1 element that is the same row as the second row of the first region, the second row is the row with the smallest row weight among all rows after the third row in the first region, and the third row is the same row as the row containing the diagonal elements in each column.

[0019] The above technical solution describes the characteristics of the row containing the element with a 1 in the column containing the 1 in the first lower triangular matrix. It can be understood that the column containing the 1 is related to the first value of the first region. The larger the first value, the more verification information the double column in the core region can obtain. The advantage of this method is that after determining the column containing the 1, selecting the row with the smaller row weight in the first region as the row containing the 1 allows obtaining the verification information of the non-double column in the core region, instead of reverting to the double column.

[0020] In some implementations of the first aspect, the extended verification region contains an additional 1 element in addition to the diagonal elements and at least one 1 element. The additional 1 element is located in the second lower triangular matrix of the extended verification region. The diagonal elements of the second lower triangular matrix are all located on the diagonal of the extended verification region. The positions of the diagonal elements of the first lower triangular matrix and the diagonal elements of the second lower triangular matrix do not overlap. The additional 1 element is located in the M columns of the second lower triangular matrix. The M diagonal elements in the M columns are located in the M rows of the second lower triangular matrix. The M rows are the same as the rows corresponding to the first M values ​​in all rows of the third region. M is a positive integer. The third region is a region composed of multiple consecutive rows in the second region. The rows in the second lower triangular matrix are the same as the rows in the third region.

[0021] In some implementations of the first aspect, the first column of the first lower triangular matrix or the second lower triangular matrix is ​​the same column as the corresponding column of a redundant version RV of the base matrix in the base matrix, or the first column of the first lower triangular matrix is ​​the same column as the first column of the extended check region.

[0022] Based on the above technical methods, in one possible implementation, the Raptor-like structure of the extended parity region can be modified into a structure of multiple cascaded lower triangular matrices based on the RV. The starting column of one RV corresponds to the starting column of one lower triangular matrix, thus enabling compatibility with the incremental redundancy hybrid automatic repeat request (IR-HARQ) scheme of 5G LDPC codes. This supports retransmission in certain specific columns, where the specified column is the starting column of the RV. It can be understood that when IR-HARQ is supported, all elements in the extended parity region except for the diagonal 1 elements and the 1 elements contained in the multiple lower triangular matrices are 0 elements.

[0023] Secondly, a communication method based on LDPC code is provided. This method can be executed by a receiving device. Unless otherwise specified, the term "receiving device" in this application can refer to the receiving device itself (e.g., a network device, a terminal device), a component in the receiving device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the receiving device.

[0024] The method includes: acquiring a symbol sequence; decoding the symbol sequence according to the LDPC matrix to obtain an information bit sequence, wherein the LDPC matrix is ​​determined based on the LDPC code base matrix, the base matrix includes an extended parity check region, an incremental redundancy region, and a core region, the extended parity check region is a lower triangular square matrix with all diagonal elements being 1, the extended parity check region includes at least one 1 element in addition to the diagonal elements, the column containing at least one 1 element is the first column, the row containing the diagonal elements in the first column is the first row, the first row is the same row as the row with the largest first value in the first region, the first value of each row in the first region is correlated with the row weight of each row, the first region is composed of multiple consecutive rows in the second region, the second region is a region composed of some columns in the incremental redundancy region, at least one column in some columns is the same column with a first feature in the core region, the column with the first feature is the column with a column weight of 2 in the core region.

[0025] For the beneficial effects of the second aspect and some implementations of the second aspect, please refer to the description of the first aspect, which will not be repeated here.

[0026] In some implementations of the second aspect, the first value of each row is the row weight of each row, or the first value of each row is determined based on the values ​​of the elements in each row and the coefficients corresponding to the columns in which the elements are located.

[0027] In some implementations of the second aspect, the column containing the incremental redundancy region is the same column as the column containing the core region, and the row containing the incremental redundancy region is the same row as the row containing the extended verification region.

[0028] In some implementations of the second aspect, at least one 1 element is located in the first lower triangular matrix of the extended verification region, wherein the diagonal elements of the first lower triangular matrix are all located on the diagonal of the extended verification region, and the row of the first lower triangular matrix is ​​the same row as the row of the first region.

[0029] In some implementations of the second aspect, the extended verification region contains an additional 1 element in addition to the diagonal elements and at least one 1 element. The additional 1 element is located in the first lower triangular matrix, wherein at least one 1 element and the additional 1 element are located in N columns of the first lower triangular matrix, and the N diagonal elements in the N columns are located in N rows of the first lower triangular matrix, where N is a positive integer. The N rows are the same rows as the rows corresponding to the first N values ​​sorted in the first value of the first region.

[0030] In some implementations of the second aspect, if the first value of the i1th row in the first region is equal to the first value of the i2th row, and the i1th row is before the i2th row, then the order of the first value of the i1th row is before the first value of the i2th row. Alternatively, if the i1th row is contained in the i3th row of the base matrix, and the i2th row is contained in the i4th row of the base matrix, and the row weight of the i3th row is greater than the row weight of the i4th row, then the order of the first value of the i1th row is before the first value of the i2th row.

[0031] In some implementations of the second aspect, each of the N columns contains only one 1 element, excluding the diagonal elements.

[0032] In some implementations of the second aspect, there is a row in each column that contains a 1 element that is the same row as the second row of the first region, the second row is the row with the smallest row weight among all rows after the third row in the first region, and the third row is the same row as the row containing the diagonal elements in each column.

[0033] In some implementations of the second aspect, the first column of the first lower triangular matrix is ​​the same column as the column corresponding to a redundant version RV of the base matrix in the base matrix, or the first column of the first lower triangular matrix is ​​the same column as the first column of the extended check region.

[0034] In some implementations of the second aspect, in addition to the diagonal elements and at least one 1 element, there is an extra 1 element in the extended verification region. The extra 1 element is located in the second lower triangular matrix of the extended verification region. The diagonal elements of the second lower triangular matrix are all located on the diagonal of the extended verification region. The positions of the diagonal elements of the first lower triangular matrix and the diagonal elements of the second lower triangular matrix do not overlap. The extra 1 element is located in the M columns of the second lower triangular matrix. The M diagonal elements in the M columns are located in the M rows of the second lower triangular matrix. M is a positive integer. The M rows are the same as the rows corresponding to the first M values ​​in the first value of all rows in the third region. The third region is a region composed of multiple consecutive rows in the second region. The rows in the second lower triangular matrix are the same as the rows in the third region.

[0035] In some implementations of the second aspect, the first column of the second lower triangular matrix is ​​the same column as the corresponding column of a redundant version RV of the base matrix in the base matrix, or the first column of the second lower triangular matrix is ​​the same column as the first column of the extended check region.

[0036] Thirdly, a communication apparatus is provided for performing the method provided by any of the above aspects or their implementations. Specifically, the apparatus may include units and / or modules for performing the method provided by any of the above aspects or their implementations, such as processing units and / or transceiver units.

[0037] In one implementation, the device is either a transmitting device or a receiving device. When the device is a transmitting device or a receiving device, the transceiver unit can be a transceiver, an input / output interface, or a communication interface; the processing unit can be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0038] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device. When the device is a chip, chip system, or circuit used in a transmitting or receiving device, the transceiver unit can be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; the processing unit can be at least one processor, processing circuit, or logic circuit.

[0039] Fourthly, a communication device is provided, comprising: a memory for storing a program; and at least one processor for executing the computer program or instructions stored in the memory to perform the method provided in any of the foregoing aspects or their implementations.

[0040] In one implementation, the device is either a transmitting device or a receiving device.

[0041] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device.

[0042] Fifthly, a communication device is provided, comprising: at least one processor and a communication interface, wherein the at least one processor is configured to obtain a computer program or instructions stored in a memory via the communication interface to execute the method provided in any of the foregoing aspects or their implementations. The communication interface may be implemented in hardware or software.

[0043] In one implementation, the device further includes the memory.

[0044] Sixthly, a processor is provided for executing the methods provided in the above aspects.

[0045] Unless otherwise specified, or if it does not contradict its actual function or internal logic in the relevant description, the transmission and acquisition / reception operations involved in the processor can be understood as processor output and reception, input and other operations, or as transmission and reception operations performed by radio frequency circuits and antennas. This application does not limit them in this regard.

[0046] In a seventh aspect, a computer-readable storage medium is provided that stores program code for execution by a device, the program code including methods for performing any of the foregoing aspects or their implementations.

[0047] Eighthly, a computer program product containing instructions is provided, which, when run on a computer, causes the computer to perform the method provided in any of the foregoing aspects or their implementations.

[0048] Ninthly, a chip is provided, comprising a processor and a communication interface. The processor reads instructions stored in a memory through the communication interface and executes the methods provided in any of the above aspects or their implementations. The communication interface can be implemented in hardware or software.

[0049] Optionally, as one implementation, the chip also includes a memory that stores computer programs or instructions. The processor is used to execute the computer programs or instructions stored in the memory. When the computer programs or instructions are executed, the processor is used to perform the methods provided by any of the above aspects or their implementations.

[0050] When the method provided in this application is executed by a chip, this application does not limit the specific number of chips implementing the method. For example, it can be executed by one chip, or by two or more chips. Furthermore, when the number of chips implementing the method is two or more, the chip manufacturers are not limited; they can be from the same manufacturer or different manufacturers.

[0051] In a tenth aspect, a computer program is provided that, when run on a computer, causes the methods provided by any of the foregoing aspects or their implementations to be executed.

[0052] Eleventhly, a communication system is provided, including at least one of the transmitting end device or receiving end device described above. Attached Figure Description

[0053] Figure 1 This is a schematic diagram of a network architecture that can be applied to embodiments of this application.

[0054] Figure 2 This is a schematic diagram of the parity check matrix H of an LDPC.

[0055] Figure 3 This is a Tanner plot of the parity-check matrix H of an LDPC.

[0056] Figure 4 This is a schematic diagram of the structure of the parity check matrix.

[0057] Figure 5 This is a schematic diagram of the information transmission process.

[0058] Figure 6 This is a schematic flowchart of a communication method 600 based on LDPC code provided in this application.

[0059] Figure 7 This is a schematic diagram of a basis matrix proposed in this application.

[0060] Figure 8 This is a schematic diagram of another basis matrix proposed in this application.

[0061] Figure 9 This is an example diagram of a lower triangular matrix obtained by partitioning the RV based on the basis matrix in the extended parity region.

[0062] Figure 10 This is a schematic diagram of a specific example of the basis matrix proposed in this application.

[0063] Figure 11 This is a schematic block diagram of the communication device 1000 provided in the embodiments of this application.

[0064] Figure 12 A schematic block diagram of a communication device 1100 provided in an embodiment of this application. Detailed Implementation

[0065] To facilitate understanding of the embodiments of this application, the following points will be explained before introducing the embodiments of this application.

[0066] The terms "for indicating" or "instruction" can include both direct and indirect indication, or they can be explicit and / or implicit. The various numerical designations such as "first," "second," etc., are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application, such as distinguishing different messages or different information. "Predefined" can be implemented by pre-storing corresponding codes, tables, or other methods that can be used to indicate relevant information in the device; this application does not limit the specific implementation method. The "protocol" involved can refer to standard protocols in the field of communication, such as the Long Term Evolution (LTE) protocol, the New Radio (NR) protocol, and related protocols applied to future communication systems; this application does not limit this. The words "exemplary," "for example," "exemplary," "as another example," etc., are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. "At least one" means one or more, while "more" means two or more. "At most one" means one or zero. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Here, a, b, and c can be single or multiple. Descriptions relating to network element A sending messages, information, or data to network element B, and network element B receiving messages, information, or data from network element A, aim to specify which network element the message, information, or data is intended for, without specifying whether the transmission is direct or indirect via other network elements. Descriptions such as "when…", "in the case of…", "if", and "if" indicate that the device will take corresponding action under certain objective circumstances, not a time limit, nor requiring the device to perform a judgment action during implementation, nor implying any other limitations. Phrases such as "corresponding to…", "correspondingly", and equivalent expressions indicate a correspondence between the preceding and following elements, which may include indirect correspondence. For example, corresponding to a certain objective situation, the device will directly or indirectly take corresponding action, without requiring the corresponding action to immediately follow that objective situation.

[0067] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0068] The following describes a communication system to which embodiments of this application can be applied.

[0069] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems, LTE systems, long term evolution-advanced (LTE-A) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, etc. They can also be applied to future communication systems, such as 6th generation mobile communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. Furthermore, it can be extended to similar wireless communication systems, such as Wireless-Fidelity (WiFi), Worldwide Interoperability for Microwave Access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0070] The communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices.

[0071] Figure 1 This is a schematic diagram of a network architecture applicable to embodiments of this application. For example... Figure 1 As shown, the embodiments of this application can be applied to both uplink and downlink data transmission. Figure 1 This document uses only uplink or downlink data transmission between one network device and two terminal devices (such as terminal device 1 and terminal device 2) as examples. In uplink data transmission, the sending device is the terminal device and the receiving device is the network device; conversely, in downlink data transmission, the sending device is the network device and the receiving device is the terminal device. Furthermore, the applicability of the embodiments of this application to other communication scenarios is not limited; for example, they can also be applied to sidelink communication.

[0072] The terminal equipment in this application can also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication equipment, user agent, or user device, etc. The terminal equipment in the embodiments of this application can be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as handheld devices with wireless connectivity, vehicle-mounted devices, etc. The terminal devices in the embodiments of this application may be mobile phones, tablets, laptops, handheld computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0073] The network equipment in this application can be a device with wireless transceiver capabilities, which can be a device that provides wireless communication services. It is usually located on the network side, including but not limited to next-generation base stations (gNodeB, gNB) in 5G systems, base stations in sixth-generation mobile communication systems, base stations in future mobile communication systems, or access nodes in wireless fidelity (WiFi) systems, evolved node B (eNB), radio network controller (RNC), node B (NB), base station controller (BSC), home base station (e.g., home-evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellites, drones, etc. in long term evolution (LTE) systems. In a network architecture, network equipment may include centralized unit (CU) nodes, distributed unit (DU) nodes, or RAN equipment including CU and DU nodes, or RAN equipment including control plane CU nodes, user plane CU nodes, and DU nodes. Alternatively, network equipment may also be a radio controller, relay station, vehicle-mounted equipment, or wearable device in a cloud radio access network (CRAN) scenario. Furthermore, a base station may be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station may also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station may also be a mobile switching center and equipment performing base station functions in D2D, V2X, and M2M communications, network-side equipment in future communication networks, or equipment performing base station functions in future communication systems. A base station may support networks with the same or different access technologies, without limitation.

[0074] Unless otherwise specified, the means for implementing the functions of a terminal device or network device in this application can refer to the terminal device or network device itself, or it can refer to a means that enables the terminal device or network device to implement the functions, such as a chip system or chip, specifically a system-on-a-chip (SoC) or a modem. This means can be installed in the terminal device or network device. In the embodiments of this application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0075] It should also be noted that some embodiments in this article use a 5G system as an example to introduce specific solution details. It is understood that when this solution is used in other communication systems, such as LTE systems, or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0076] Furthermore, the embodiments of this application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability low-latency scenarios, or low-power scenarios. Among them, high-throughput scenarios can be, for example, enhanced mobile broadband (eMBB) scenarios, high-reliability low-latency scenarios can be, for example, URLLC (ultrareliable low-latency communication) scenarios, and low-power scenarios can be, for example, M2M scenarios, MTC scenarios, or IoT scenarios.

[0077] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0078] 1. LDPC code

[0079] LDPC codes are a type of linear block code. Linear block codes divide the information sequence to be encoded into groups of q bits each. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits are then combined with the m parity bits to obtain a codeword of length n = q + m. The mapping from q information bits to an n-bit codeword is typically represented by a parity check matrix H. Based on the parity check matrix H, a codeword sequence can be generated to complete the encoding process. After the codeword sequence is transmitted through the channel, the receiving equipment decodes the received signal to determine the original information bits.

[0080] The parity-check matrix H of an LDPC is a sparse matrix. The number of zero elements in the parity-check matrix H is far greater than the number of non-zero elements; in other words, the row weight (or column weight) of the parity-check matrix is ​​far less than the number of elements in each row (or column) of the LDPC matrix. Specifically, an LDPC code with an information bit sequence length of q and a code length of n can be uniquely determined by its parity-check matrix H.

[0081] Tanner represented the parity-check matrix H graphically in 1981; this type of graph is now called a Tanner graph. There is a one-to-one correspondence between Tanner graphs and parity-check matrices. A Tanner graph consists of two types of vertices: one type represents codeword bits and is called variable nodes; the other type consists of parity nodes, representing parity constraints. Each parity node represents a parity constraint. The following section will discuss this in conjunction with... Figure 2 and Figure 3 Please provide an explanation.

[0082] Figure 2 This is a schematic diagram of the parity check matrix H of an LDPC.

[0083] Figure 2 In the middle, {V i} represents the set of variable nodes (VN), {C i} represents the set of check nodes (CN). Each row of the check matrix H represents a check equation, and each check equation corresponds to a check node. Each column represents a codeword bit, and each codeword bit corresponds to a variable node. Figure 2 In the diagram, there are 8 variable nodes and 4 check nodes. If a codeword bit is included in the corresponding check equation, a line is used to connect the involved variable nodes and check nodes to obtain the Tanner diagram.

[0084] Figure 3 The Tanner plot of the parity-check matrix H of an LDPC.

[0085] like Figure 3As shown, the Tanner graph represents the parity check matrix of the LDPC. For example, for a parity check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m parity nodes. The n variable nodes correspond to the n columns of the parity check matrix H, and the m parity nodes correspond to the m rows of the parity check matrix H. Cycles in the Tanner graph are composed of interconnected vertices. A cycle starts and ends at one vertex in this group of vertices and passes through each node only once. More specifically, a cycle is a closed loop consisting of variable nodes, parity nodes, and connecting edges. The length of a cycle is defined as the number of edges it contains, while the perimeter of the graph, also known as the circumference, is defined as the length of the smallest cycle in the graph, such as... Figure 3 In the middle, the circumference is 4, such as Figure 3 The diagram shows the black lines connecting the variable nodes in the Tanner graph. Variable nodes in the Tanner graph correspond to each column of the parity-check matrix H, which is equivalent to each codeword bit in the LDPC. Parity nodes in the Tanner graph correspond to each row of the parity-check matrix H, which is equivalent to the parity bits in the LDPC. The connection between two types of nodes corresponds to the value of an element in the H matrix. If there is a connection between the i-th parity node and the j-th variable node, the element (i, j) in the H matrix has a value of 1; otherwise, the corresponding element is 0. The connection between a variable node and a parity node can also be called an edge. A connection between a parity node and a variable node can also be described as: there is a connection or an edge between the parity node and the variable node. The edge relationship between a parity node and a variable node can include either the presence of an edge or the absence of an edge.

[0086] 2. QC-LDPC code

[0087] QC-LDPC codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be implemented using a simple feedback shift register, reducing the encoding complexity of LDPC codes. In practice, QC-LDPC codes are represented using a base graph (BG), where elements are either 0 or 1. Expanding the 1s and 0s in the BG yields a parity-check matrix H, which can be used for encoding or decoding. In the embodiments of this application, the BG can be written in matrix form, which can be referred to as the base matrix H in this application. BG Basis matrix H BGAn element of 0 indicates that there are no edges in the base graph, while a value of 1 indicates that there are edges in the base graph (or that the corresponding check is associated with the corresponding variable). NR LDPC codes involve multiple base graph selection; currently, the standard stores two base graphs, BG1 and BG2. BG2 is used when the information length is less than or equal to 292, or when the information length is less than or equal to 3824 and the code rate is less than or equal to 2 / 3, or when the code rate is less than or equal to 0.25; otherwise, BG1 is used. The expansion process of the base matrix is ​​described below.

[0088] Based on the base matrix and the lifting size Zc, the base matrix can be expanded into a complete parity-check matrix for encoding or decoding. In this application, Zc can also be referred to as the expansion factor, lifting factor, expansion value, expansion coefficient, lifting size, etc. The expansion process involves lifting all elements of the base matrix into a Zc*Zc square matrix, where 0 is lifted to a Zc*Zc 0 matrix, and 1 is lifted to an identity matrix. This identity matrix is ​​then cyclically shifted based on the shifting value (SV) corresponding to 1. This cyclic shift can be left or right, and this application does not limit this. It can be understood that each 1 in the base matrix corresponds to a shifting value. Taking a 4*4 identity matrix as an example, if the shifting values ​​are 0, 1, and 3, the cyclically shifted matrix after a rightward cyclic shift is shown below:

[0089] (1) When the translation value is 0 (i.e., remains unchanged), the corresponding cyclically shifted matrix is:

[0090] (2) When the translation value is 1, the corresponding cyclically shifted matrix is:

[0091] (3) When the translation value is 3, the corresponding cyclically shifted matrix is:

[0092] Alternatively, it can be understood that the complete parity check matrix H can be derived from an exponential matrix H. b H indicates b Each element in the matrix corresponds to a Zc*Zc submatrix. Each element indicates the number of times the corresponding submatrix is ​​cyclically shifted from the Zc*Zc identity matrix. Therefore, the storage space required for the complete parity check matrix H is greatly reduced. (Exponential matrix H) b The elements in it can also be called QC blocks.

[0093] For example, the exponent matrix H of the QC-LDPC code b As shown below:

[0094]

[0095] It can be seen that the exponent matrix H bThe size is 4 rows and 24 columns, and the exponent matrix H b Each element i in the matrix represents a square matrix of order Zc. Let represent a cyclic shift matrix, where i represents the cyclic shift value of the cyclic shift matrix, and i is an integer. Additionally, the exponent matrix H... b In this context, "-1" represents a zero matrix and "0" represents the identity matrix.

[0096] For example, As shown below:

[0097]

[0098] Optional, exponent matrix H b In addition to "-1", zero elements in the matrix can also be represented in other ways, such as using "-" or null values ​​to represent a matrix of all zeros.

[0099] It is understandable that the above exponent matrix H... b The matrix corresponding to the positions greater than or equal to 0 that are changed to 1 and the positions of -1 that are changed to 0 is the basis matrix. The 1s in the basis matrix are expanded into a Zc-order cyclic shift matrix based on the corresponding elements of the exponent matrix, and the 0s are expanded into a Zc-order all-zero matrix. After the expansion, the parity check matrix H is obtained.

[0100] 3. Lifting Size (Zc) and Shifting Value

[0101] The storage content of the 5G LDPC code regarding the translation values ​​includes: (1) a list of lifting values; and (2) a list of translation values ​​that corresponds one-to-one with the rows of the Lifting Size list.

[0102] For example, the list of promotion values ​​is shown in Table 1.

[0103] Table 1

[0104] Promotion Index Promotion value set 0 {2,4,8,16,32,64,128,256} 1 {3,6,12,24,48,96,192,384} 2 {5,10,20,40,80,160,320} 3 {7,14,28,56,112,224} 4 {9,18,36,72,144,288} 5 {11,22,44,88,176,352} 6 {13,26,52,104,208} 7 {15,30,60,120,240}

[0105] The j-th row of the boost value list includes Where a j ∈{2,3,5,7,9,11,13,15}, max(k j )∈{7,7,6,5,5,5,4,4}; the index of the lifted value corresponds one-to-one with the column index of the shift value, that is, the index of the lifted value in each row of the lifted value list corresponds to a set of shift values.

[0106] For example, the list of translation values ​​is shown in Table 2.

[0107] Table 2

[0108]

[0109]

[0110] For a fixed lift index, a non-zero position in the base matrix corresponds to one translation value. For example, H... BG The shift value corresponding to row 0, column 0 when the promotion index is 0 is 211, H BG The shift value corresponding to the 6th column of the 1st row in the middle when the lifting index = 3 is 66, H BG The shift value corresponding to the second row and ninth column of the middle column when the promotion index is 7 is 206.

[0111] It's understandable that LDPC encoding requires first determining the lift value, and then constructing a parity check matrix based on the corresponding shift value. For example, if the determined lift value is 40, and the lift value index corresponding to 40 in Table 1 is 2, then the parity check matrix can be constructed based on the shift value in the column corresponding to lift value index = 2 in Table 2.

[0112] 4. Structure of the parity-check matrix and the basis matrix

[0113] Figure 4 This is a schematic diagram of the structure of the parity check matrix.

[0114] like Figure 4 As shown in (a), the parity-check matrix can include a high-rate region (also known as the core region), an all-zero region, an incremental redundancy region, and an extended parity-check region. The high-rate region can include... Figure 4 Parts A and B are shown in (b) above. Part A corresponds to information bits (or information digits, system bits, etc.), and part B is a square matrix corresponding to core parity bits (or core parity digits). The core parity can be the parity corresponding to the highest bit rate, or a parity where all degrees are greater than or equal to 2, or a parity node corresponding to the set of rows with the highest row weight (row weight significantly higher than other rows). A region of all zeros can correspond to... Figure 4 In (b) of the matrix, part C is an all-zero matrix. The incremental redundancy region can correspond to... Figure 4 Part D of (b) in the diagram. The extended check area can correspond to... Figure 4In (b), part E can be an identity matrix corresponding to the parity bits of the low-rate extension. Parts B and E are both parity parts. Part B is defined as the core parity region, and its features can be either a non-lower triangular encoded part (i.e., values ​​above the diagonal are not all 0) or an encoded part with column weights greater than 1. Part E is defined as the extended parity region, and its features can be either a lower triangular encoded part (i.e., values ​​above the diagonal are all 0) or a diagonal matrix.

[0115] For example, the extended check region of the NR LDPC code adopts a "raptor-like" structure, which can be gradually extended from high-rate regions to low-rate regions. In practical use, such as... Figure 4 As shown in (a), X rows and X columns can be added to the high bitrate region. As the bitrate decreases, X gradually increases, and the matrix region used also gradually expands.

[0116] It should be noted that the parity check matrix can be represented by the LDPC basis matrix. Therefore, the structure of the LDPC basis matrix is ​​similar to that of the parity check matrix, and will not be described in detail here.

[0117] 5. Column weight and row weight

[0118] For a column of a matrix, column weight can refer to the number of non-zero elements contained in that column.

[0119] For a given row of a matrix, row weight can refer to the number of non-zero elements contained in that row.

[0120] 6. Core rows and core columns

[0121] Core rows: The core rows of the LDPC base matrix correspond to the core parity bits. In other words, the core rows are the rows corresponding to high bitrate regions, or the rows corresponding to parts A, B, or C.

[0122] Core columns: These can include all information columns and all core check columns. In other words, core columns are the columns corresponding to high bitrate areas, or the columns corresponding to parts A and B.

[0123] Core matrix:

[0124] 7. Message length, code length, and code rate

[0125] The information length is the length of the bit sequence of information to be sent (i.e., the number of bits contained therein). This length can be the length of the payload information bits, or the length of the payload information bits after adding cyclic redundancy check (CRC) bits. This application does not impose any specific restrictions.

[0126] Code length refers to the length of the bit sequence to be transmitted, which can be the transmitted bit sequence corresponding to the modulated symbol.

[0127] Code rate refers to the ratio of the length of the bit sequence of information to be transmitted to the code length.

[0128] Optionally, the above three values ​​can be pre-configured by higher-layer signaling, media access control (MAC) layer, or downlink physical layer signals, or they can be directly obtained and calculated by the transceiver. For example, the code length can be determined by the frame structure, number of layers, and modulation scheme of the encoded and transmitted information bit sequence; the code rate can be indicated in the above manner or given in the modulation and coding scheme (MCS).

[0129] 8. Information Transmission Process

[0130] Figure 5 This is a schematic diagram illustrating the information transmission process applicable to this application. For example... Figure 5 As shown, information is sent from the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, and source recovery before reaching the destination, completing the transmission of information from the source to the destination. Among these processes, Figure 5 The upper-layer processing (including source coding, channel coding, and modulation) is performed at the transmitting end device, while the lower-layer processing (including demodulation, channel decoding, and source recovery) is performed at the receiving end device. The embodiments of this application mainly relate to... Figure 5 The diagram shows source coding, channel coding, channel decoding, and source recovery.

[0131] Based on the description in the background section, this application proposes a communication method based on LDPC codes, which can effectively solve the aforementioned technical problems. The method proposed in this application is described in detail below.

[0132] Figure 6 This is a schematic flowchart of a communication method 600 based on LDPC codes provided in this application. The method includes the following steps.

[0133] It is understood that method 600 can be executed by both the sending device and the receiving device. Unless otherwise specified, "sending device" or "receiving device" can refer to the sending device or receiving device itself, or it can refer to a device that enables the sending device or receiving device to implement this function. For ease of description, the following text will use "sending device" and "receiving device" to describe it. Among them, the sending device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0134] S610, the transmitting device obtains the information bit sequence.

[0135] It is understandable that if the sending device needs to communicate with the receiving device, that is, if the sending device needs to send a signal to the receiving device, then the sending device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0136] The process of the transmitting device acquiring the information bit sequence can refer to: the transmitting device performing source encoding on the source symbols to generate the information bit sequence; or, the transmitting device acquiring the information bit sequence can also refer to: the transmitting device receiving the information bit sequence from other communication devices. This application does not limit the method of acquiring the information bit sequence.

[0137] S620, the transmitting device encodes the information bit sequence according to the LDPC matrix to obtain the codeword sequence, wherein the LDPC matrix is ​​determined based on the LDPC code base matrix.

[0138] The LDPC code base matrix (hereinafter referred to as the base matrix) proposed in this application will be introduced below.

[0139] (1) The base matrix includes the core region, the extended check region, and the incremental redundancy region.

[0140] In one possible implementation, the column containing the incremental redundancy region and the column containing the core region are the same columns in the base matrix; secondly, the row containing the incremental redundancy region and the row containing the extended verification region are the same rows in the base matrix.

[0141] In this application, row A and row B are the same row, which can be understood as row A and row B being contained in the same row of the basis matrix; similarly, column A and column B are the same column, which can be understood as column A and column B being contained in the same column of the basis matrix.

[0142] Based on the above implementation method, the structure of the basis matrix can be as follows: Figure 4 As shown, specifically, the core region of the basis matrix is Figure 4 In region A of (b), the incremental redundancy region is Figure 4 In region D of (b), the extended verification region is Figure 4 Region E in (b). The core region is formed by the core rows and core columns of the base matrix; the extended check region is formed by all rows of the base matrix excluding the core rows and all columns of the base matrix excluding the core columns; the incremental redundancy region is formed by all rows of the base matrix excluding the core rows and all core columns of the base matrix.

[0143] It is understood that the core area, extended verification area, and incremental redundancy area are only for the convenience of distinguishing different areas, and this application does not make specific restrictions on the names of each area.

[0144] (2) The extended verification region is a lower triangular matrix with all diagonal elements being 1, and includes at least one 1 element in addition to the diagonal elements. For ease of distinction, this at least one 1 element is denoted as at least one first element, the column containing this at least one first element is denoted as the first column, and the row containing the diagonal elements in the first column is denoted as the first row. Among them, the first row is the same row as the row with the largest first value in the first region, the first value of each row in the first region is related to the row weight of each row, the first region is composed of multiple consecutive rows in the second region, the second region is a region composed of a portion of the columns in the incremental redundancy region of the base matrix, at least one of the columns in this portion is the same column as the column with the first characteristic in the core region of the base matrix, and the column with the first characteristic is the column with a column weight of 2 in the core region of the base matrix.

[0145] It is understood that the lower triangular matrix described in this application refers to a matrix that is both a lower triangular matrix and a square matrix (i.e., a matrix with the number of rows equal to the number of columns).

[0146] The following examples illustrate the components that make up the second region.

[0147] Example 1: Some columns in the incremental redundant region of the base matrix share the same first characteristic as all columns in the same column. If there are x columns with the first characteristic in the core region of the base matrix, and the column indices of these x columns are c1, c2, ..., c... X Then the column indices of the second region, which is the incremental redundant region of the basis matrix, are c1, c2, ..., c. X The area formed by column x.

[0148] based on Figure 7 The base matrix shown illustrates the second region. The core region, extended check region, and incremental redundancy region are as follows: Figure 7 As shown, there are 6 columns with the first characteristic in the core area, and the column indices of these 6 columns are 2, 5, 7, 11, 12, and 13. Therefore, the second area is the area formed by the columns with column indices 2, 5, 7, 11, 12, and 13 in the incremental redundancy area (i.e., the second area is...). Figure 7 (The dashed area in the incremental redundancy region).

[0149] Example 2: This part of the column includes at least one column with a first characteristic in the incremental redundancy region of the base matrix, and at least one column with a second characteristic in the incremental redundancy region of the base matrix, wherein the column with the second characteristic is a column with a column weight not equal to 2 in the core region of the base matrix.

[0150] For example, this part consists of all columns with a first characteristic and at least one column with a second characteristic in the incremental redundant region of the base matrix.

[0151] For example, this part of the column replaces some columns in all columns with the first characteristic in the incremental redundant region of the base matrix with columns corresponding to the second characteristic.

[0152] For example, columns with the second characteristic are those with a column weight of 3 in the core region of the base matrix.

[0153] In one possible implementation, the first region is the region consisting of all rows of the second region; that is, the first region is the second region. All 1 elements remaining in the extended validation region (excluding diagonal elements) are located in the N columns of the extended validation region. The N diagonal elements in these N columns are located in the N rows of the extended validation region. These N rows are the same rows as the N rows corresponding to the first N values ​​in the first region. An example of these N rows in the extended validation region is given below.

[0154] For example, the rows corresponding to the N rows in the extended verification region and the N rows corresponding to the first values ​​in the sorted order of all rows in the second region are the same. In this application, the larger the first value, the earlier it appears in the sorted order; this will not be elaborated further in subsequent sections.

[0155] For example, the rows corresponding to the N rows of the extended verification region and the N rows corresponding to the P first values ​​sorted from the first value of all rows in the second region are the same, where P is an integer greater than N.

[0156] It is understood that this application does not limit the number of 1 elements in the N columns of the extended verification area, excluding the diagonal elements.

[0157] The possible ways to determine the first value in each row of the first region will continue to be explained.

[0158] Method 1: The first value of each row in the first region is the row weight of each row.

[0159] Continue to combine Figure 7 Let's take an example to illustrate method one. Figure 7 The second region is the area comprised of columns with column indices 2, 5, 7, 11, 12, and 13 in the incremental redundancy region. For example, the first region could be the area comprised of rows with row indices 5 to 16 in the second region. Based on this method, the first value of row 5 in the first region would be 3, the first value of row 7 would be 3, the first value of row 8 would be 4, and the first value of row 9 would be 1, and so on. It can be understood that the above row indices are the row indices of the base matrix.

[0160] Method 2: The first value of each row in the first region is determined based on the value of the element in each row and the coefficient (or weight) of each element.

[0161] For example, the first region consists of 4 columns, and the element in the k-th row of the first region is {a k1 a k2 a k3 a k4}, the coefficient corresponding to each element is {t} k1 t k2 t k3 t k4 Let T be the first value in the k-th row. k Then T k =a k1 *t k1 +a k2 *t k2 +a k3 *t k3 +a k4 *t k4 .

[0162] Method 3: The first value of each row in the first region is determined based on the value of the element in each row and the coefficient (or weight) of the column in which the element is located.

[0163] For example, the first region consists of 4 columns, and the coefficients corresponding to these 4 columns are {t1 t2 t3 t4}. The element in the k-th row of the first region is {a}. k1 a k2 a k3 a k4 Let T be the first value in the k-th row. k Then T k =a k1 *t k1 +a k2 *t k2 +a k3 *t k3 +a k4 *t k4 Similarly, the element in row s of the first region is {a}. s1 a s2 a s3 a s4 Let T be the first value in the i-th row. i Then T1 = a i1 *t i1 +a i2 *t i2 +a i3 *t i3 +a i4 *t i4.

[0164] Optionally, at least one first element is located in the first lower triangular matrix of the extended verification region, wherein the diagonal elements of the first lower triangular matrix are all located on the diagonal of the extended verification region, and the row of the first lower triangular matrix is ​​the same row as the row of the first region.

[0165] It is understood that the extended verification region may contain other 1 elements besides its diagonal elements and at least one first element, and these other 1 elements may be all or partly located in the first lower triangular matrix. Optionally, the extended verification region may contain some additional 1 elements besides its diagonal elements and at least one first element, and these additional 1 elements are located in the first lower triangular matrix. Specifically, at least one 1 element and the additional 1 elements are located in the N columns of the first lower triangular matrix (i.e., each of the N columns of the first lower triangular matrix contains one element besides its diagonal elements, and the N columns include the first column), where N is a positive integer. The N diagonal elements of the N columns of the first lower triangular matrix are located in the N rows of the first lower triangular matrix, and these N rows are the same rows as the rows corresponding to the first N values ​​sorted in the first region. The following is an example illustrating the N rows of the first lower triangular matrix.

[0166] For example, the N rows of the first lower triangular matrix are the same rows as the rows corresponding to the N most frequently ranked first values ​​among all rows in the first region. For instance, in this application, the larger the first value, the earlier it ranks in the sorting; this will not be elaborated further in subsequent sections.

[0167] For example, the N rows of the first lower triangular matrix are the same rows as the rows corresponding to the N values ​​among the first P values ​​in the sorted order of all rows in the first region, where P is an integer greater than N. For instance, if the first lower triangular matrix has 10 columns, P = 5, and N = 3, then 3 columns in the first lower triangular matrix satisfy the characteristic that these 3 columns correspond to 3 values ​​among the first 5 values ​​in the sorted order of the first value. For example, the choice of P can be adjusted according to the needs of decoding complexity and achieving a specified bit error rate.

[0168] It is understandable that since at least one first element is located in the first lower triangular matrix, the column containing at least one first element (i.e., the first column mentioned above) is contained in the N columns of the first lower triangular matrix. The N rows of the first lower triangular matrix include the row containing the diagonal elements in the first column (i.e., the first row mentioned above). The first row is the same row as the row with the largest first value in the first region.

[0169] It is understandable that the N columns of the first lower triangular matrix can be all columns of the first lower triangular matrix, or only some columns of the first lower triangular matrix, without limitation.

[0170] It can also be understood that this application does not limit the number of elements containing 1 (excluding diagonal elements) in each of the N columns of the first lower triangular matrix. The number of elements containing 1 (excluding diagonal elements) in different columns can be the same or different.

[0171] This is understandable, because of the characteristics of the first lower triangular matrix, in each of the N columns of the first lower triangular matrix, all elements with a value of 1 except for the diagonal elements are located below the diagonal elements of the corresponding column.

[0172] In one possible implementation, each of the N columns of the first lower triangular matrix contains only one 1 element, excluding the diagonal elements. For example, the row containing one 1 element in each column is the same row as the i1th row of the first region, the i1th row is the row with the smallest row weight among all rows after the i2th row in the first region, and the i2th row is the same row as the row containing the diagonal elements in each column.

[0173] In addition, in the above description, the larger the first value, the earlier it is sorted. In one possible scenario, if the first value of row #1 in the first region is equal to the first value of row #2 in the first region, the sorting of the first values ​​of row #1 and row #2 can be determined in the following two ways.

[0174] Example 1: If row #1 is before row #2, then the first value of row #1 is ordered before the first value of row #2.

[0175] Example 2: If row #1 is contained in row #3 of the base matrix, and row #2 is contained in row #4 of the base matrix, and the row weight of row #3 is greater than the row weight of row #4, then the first value of row #1 is ordered before the first value of row #2. It can be understood that rows #3 and #4 here represent entire rows of the base matrix.

[0176] Combination Figure 7 An example is given for the first lower triangular matrix corresponding to the first region. For example... Figure 7 As shown, the second region is the region corresponding to the dashed part of the incremental redundancy region, and the first region is the region consisting of rows with row indices of 5 to 16 in the incremental redundancy region. The first lower triangular matrix is ​​the lower triangular matrix shown in the thick box in the extended verification region. It can be seen that the row index corresponding to the row where the first lower triangular matrix is ​​located is also 5 to 16 (the row where the first lower triangular matrix is ​​located is the same row as the row where the first region is located), and all diagonal elements of the first lower triangular matrix are located on the diagonal of the extended verification region.

[0177] Continue to combine Figure 7 This describes the position of at least one first element in the first lower triangular matrix. As described above, the column containing at least one first element is the first column, the row containing the diagonal elements of the first column is the first row, and the first row is the same row as the row with the largest first value in the first region.

[0178] like Figure 7 As shown, the first region is the area consisting of rows with row indices 5 to 16 in the incremental redundancy region. The first lower triangular matrix is ​​the lower triangular matrix shown in the thick box in the extended verification region. Taking the first value of each row as the row weight as an example, the row with the largest first value in the first region is the row with row index 7 (i.e., the first row). The column containing the diagonal element of the first lower triangular matrix (i.e., the 1 element in the dashed box in the first lower triangular matrix) is the column with column index 17 (i.e., the first column). Therefore, at least one first element is located in the column with column index 17, and at least one first element is located after the diagonal element of the first column. For example, at least one 1 element is one first element, and the row containing this one first element can be the second row. The second row is the same row as the row with the smallest row weight among the rows with row indices 8 to 16 in the first region, i.e., as shown in the example. Figure 7 As shown, the first element is the element within the solid-line box in the first lower triangular matrix (i.e., the element in the 9th row and 17th column of the base matrix).

[0179] Understandable. Figure 7 This example illustrates the concept of having at least one first element. For instance, at least one first element can be two, three, or even more first elements. For example, if at least one first element is two first elements, then... Figure 8 exist Figure 7 Based on this, the two first elements are two 1 elements in the column with column index 17, excluding its diagonal elements.

[0180] Example, Figure 7 In the first lower triangular matrix, except for the column with column index 17, all other columns can contain at least one element. For example, Figure 8 exist Figure 7 Based on this, there is one 1 element in column index 15 excluding its diagonal element, and at least two 1 elements in column index 17 excluding its diagonal element. For example, the method for determining where to place a 1 element in column index 15 can be as follows: The rows with the second largest first value in the first region are the rows with row indices 5 and 6. For example, the row with index 5 is earlier, so a 1 element can be placed in the column containing the diagonal element of the row with index 5 in the base matrix (i.e., the column with column index 15).

[0181] Optionally, in addition to the first lower triangular matrix mentioned above, the extended verification region also includes a second lower triangular matrix. The diagonal elements of the second lower triangular matrix are all located on the diagonal of the extended verification region, and the positions of the diagonal elements of the second lower triangular matrix and the diagonal elements of the first lower triangular matrix do not overlap (i.e., the first lower triangular matrix and the second lower triangular matrix do not overlap).

[0182] It is understandable that the extended verification region may contain other 1-element elements besides its diagonal elements and the 1-element elements in the first lower triangular matrix. These other 1-element elements may be all or partly located in the second lower triangular matrix. Optionally, the extended verification region may contain additional 1-element elements besides its diagonal elements and the 1-element elements in the first lower triangular matrix. These additional 1-element elements are located in the M columns of the second lower triangular matrix (i.e., each column of the M columns of the second lower triangular matrix contains 1-element elements besides the diagonal elements), where M is a positive integer. The M diagonal elements in these M columns are located in the M rows of the second lower triangular matrix. The M rows are the same rows as the rows corresponding to the first M values ​​in the first value of the third region. An example of the M rows in the second lower triangular matrix is ​​given below.

[0183] For example, the M rows in the second lower triangular matrix are the same rows as the M rows that correspond to the first M values ​​in the sorted order of all rows in the third region.

[0184] For example, the M rows in the second lower triangular matrix correspond to the M rows of the first P values ​​sorted from the first value in all rows of the third region, where P is an integer greater than M.

[0185] It is understandable that column M of the second lower triangular matrix can be all columns of the second lower triangular matrix or only some columns of the second lower triangular matrix, without limitation.

[0186] It can also be understood that this application does not limit the number of elements containing 1 (excluding diagonal elements) in each of the N columns of the second lower triangular matrix. The number of elements containing 1 (excluding diagonal elements) in different columns can be the same or different.

[0187] In one possible implementation, each of the M columns of the second lower triangular matrix contains only one 1 element, excluding the diagonal elements. For example, the row containing one 1 element in each column is the same row as the i1th row of the third region, the i1th row is the row with the smallest row weight among all rows after the i2th row in the third region, and the i2th row is the same row as the row containing the diagonal elements in each column.

[0188] Optionally, in addition to the first and second lower triangular matrices, other lower triangular matrices may exist in the extended verification region. The diagonal elements of each of these multiple lower triangular matrices are located on the diagonal of the extended verification region, and the positions of the diagonal elements of the multiple lower triangular matrices do not overlap. It can be understood that the characteristics of columns containing 1 element in other lower triangular matrices are similar to those of columns containing 1 element in the second lower triangular matrices, and will not be elaborated further here.

[0189] Optionally, all elements in the extended check area except for the 1 element on the diagonal of the extended check area and the 1 element in the included lower triangular matrix are 0 elements.

[0190] In one possible implementation, one or more lower triangular matrices can be partitioned in the extended parity region based on the redundant version (RV) of the base matrix.

[0191] For example, the RV of the basis matrix can divide the extended parity region into X parts. The first part is the region consisting of columns 0 (i.e., the first column of the extended parity region) to e1, the second part is the region consisting of columns e1 to e2, and so on. The Xth part is the region consisting of columns e1 to e2. X-1 The area formed by columns e1, e2, ..., e3. X-1 The columns that correspond to RV in the base matrix (i.e., the starting columns of RV) are the same. Specifically, columns 0 to e1 of the extended check region, and rows 0 (i.e., the first column of the extended check region) to e1 are a lower triangular matrix within the extended check region; columns e1 to e2 of the extended check region, and rows e1 to e2 are another lower triangular matrix within the extended check region, and so on. X-1 List up to the last column, and, the eth column X-1 The last row represents another lower triangular matrix within the expanded verification region. The following section combines... Figure 9 For example.

[0192] like Figure 9 As shown, lower triangular matrices #1, #2, and #3 can be obtained by dividing the extended verification region based on the base matrices RV1 and RV2. The first column of lower triangular matrix #2 is the same as the starting column of RV1, the first column of lower triangular matrix #3 is the same as the starting column of RV2, and the first column of lower triangular matrix #1 is the same as the first column of the extended verification region.

[0193] In one specific embodiment, the basis matrix in this application can be viewed as a matrix obtained by redefining the extended parity region (i.e., the E region) of BG2. Specifically, the Raptor-like structure of the extended parity region can be modified into a structure of multiple cascaded lower triangular matrices based on RV, with the starting column of one RV corresponding to the starting column of one lower triangular matrix. Currently, the standard sets four RVs for 5G BG2, and the basis matrix H corresponding to BG2 is... BG2The matrix comprises 52 columns. For example, these 52 columns have column indices from 0 to 51. RV0 starts at column 2 in BG2, RV1 at column 15, RV2 at column 27, and RV3 at column 45. Based on RV1 to RV3 in BG2, the extended parity region of the base matrix can be divided into three lower triangular matrices. Examples of 1 elements in each lower triangular matrix are shown below. Figure 10 The description in the text will not be elaborated here.

[0194] It is understandable that, after determining the lower triangular matrices contained in the extended check region, the characteristics of the positions of the elements with 1s (excluding the diagonal elements) in each lower triangular matrices are as described above, and will not be repeated here. Optionally, all elements in the extended check region other than the diagonal 1-element and the 1-element elements in the contained lower triangular matrices are 0 elements.

[0195] Figure 10 This is a schematic diagram of a specific example of the basis matrix proposed in this application. Figure 10 This can be viewed as a matrix obtained by redefining the extended parity region (i.e., the E region) of BG2 based on the method proposed in this application. The following is an example illustrating how to determine the presence of a 1 element in the extended parity region of this base matrix.

[0196] 1) The incremental redundancy region is divided according to the column weights in the core region, resulting in the extended verification region located below all columns with a weight of 2 in the core region. This is referred to as region D1 (an example of the second region; see details of region D1). Figure 10 (The dashed area in the incremental redundancy region).

[0197] 2) Based on BG2, RV1, RV2, and RV3 will be used to extend the verification region and determine the positions of the three lower triangular matrices (see details). Figure 10 The three lower triangular matrices are shown in the solid-lined frame of the extended verification region. For ease of description, the three lower triangular matrices will be referred to as E1, E2, and E3 below.

[0198] 3) Determine the region D1 corresponding to E1. 11 Region D corresponding to E2 12 And, the region D corresponding to E3 13 It's understandable that region D... 11 For region D1, which is located in the same row as E1, region D... 12 For region D1, which is in the same row as E2, region D... 13 This refers to the region in region D1 that is in the same row as E3.

[0199] 4) For region D 11Sort the first value corresponding to all rows in region D. 12 Sort the first value corresponding to all rows in region D. 13 Sort the first value corresponding to all rows in the table.

[0200] As can be seen, there are 6 columns with a weight of 2 in the core area. In this example, the first value T corresponds to row k in area D1. k As shown below:

[0201] T k =t1*a k,1 +t2*a k,2 +t3*a k,3 +t4*a k,4 +t5*a k,5 +t6*a k,6

[0202] Among them, {a k,1 a k,2 a k,3 a k,4 a k,5 a k,6} represents the values ​​of the 6 elements in the 6 columns with a weight of 2 in row k, and {t1t2t3t4t5t6} represents the coefficient (or weight) of each of the 6 columns with a weight of 2.

[0203] In this example, we can take the values ​​t1=1, t2=6, t3=6, t4=1, t5=1, and t6=1. Using region D... 11 For example, region D 11 It consists of 12 rows, and the first values ​​corresponding to the first row from the first row to the twelfth row are {13,13,14,1,1,6,7,1,1,2,1,2}.

[0204] 5) In this example, E1 needs to have two 1 elements other than the diagonal elements, E2 needs to have three 1 elements other than the diagonal elements, and E3 needs to have one 1 element other than the diagonal elements, and each column of any lower triangular matrix needs to have at most one 1 element other than the diagonal elements.

[0205] For example, the positions of the two 1 elements in E1 other than the diagonal elements are determined based on the following method. As can be seen from the sorting in (4), region D 11 The first value (14) in the third row of E1 is the largest, so a 1 element can be placed anywhere after the diagonal element in the third row of E1. In addition, region D 11The first value (13) in the first and second rows of E1 is the second largest. Since the first row is before the second row, another 1 element can be placed anywhere after the diagonal element in the first row of E1. It can be understood that the placement of the two 1 elements in E1 other than the diagonal element in the above-determined column is not limited. In addition, the existence of three 1 elements in E2 other than the diagonal element, and one 1 element in E3 other than the diagonal element are determined based on the same criteria, which will not be repeated here. For example, the placement of the two 1 elements in E1 other than the diagonal element, the three 1 elements in E2 other than the diagonal element, and the one 1 element in E3 other than the diagonal element in the corresponding column can be as follows. Figure 10 As shown.

[0206] For example, the basis matrix proposed in this application can be a matrix defined in the protocol, or it can be determined by the device based on its own needs, without any specific limitation.

[0207] The LDPC matrix in this application can also be called the LDPC encoding matrix. For example, the LDPC matrix can be an LDPC parity-check matrix or an LDPC generator matrix. The LDPC parity-check matrix or the LDPC generator matrix is ​​obtained by lifting and shifting the elements of the LDPC base matrix described in this step, and there is a one-to-one correspondence between the LDPC generator matrix and the LDPC parity-check matrix.

[0208] For example, the translation value S of the off-diagonal 1-element (denoted as element #1) in the extended parity region of the base matrix of this application. i,j The translation value S of any other 1 element (denoted as element #2) in the same row as element #1. i,j′ Satisfy: S i,j ≠S i,j′ , where i is the row number of the row containing element #1 and element #2, and j and j′ represent the column numbers of the column containing element #1 and element #2, respectively.

[0209] For example, for the maximum lift Z within any of multiple lift sets. max Satisfy S i,i ≠mod(S i,j′ Z max ).

[0210] S630, the transmitting device determines the symbol sequence based on the codeword sequence.

[0211] It is understandable that a symbol sequence can be a rate-matched sequence or a modulated sequence. For example, the transmitting device performs rate matching on the codeword sequence, then modulates the rate-matched sequence to obtain a symbol sequence, and then maps the modulated symbol sequence onto physical resources for transmission.

[0212] S640, the transmitting device sends a symbol sequence to the receiving device. Correspondingly, the receiving device receives the symbol sequence from the transmitting device.

[0213] It is understandable that the symbol sequence #1 sent by the transmitting device and the symbol sequence #2 received by the receiving device may be different because channel noise signals may be introduced during the transmission of the symbol sequence.

[0214] In S650, the receiving device decodes the symbol sequence according to the LDPC matrix to obtain the information bit sequence.

[0215] The LDCP matrix used for decoding by the receiving device is the same as the LDPC matrix used for encoding by the transmitting device. The specific method by which the receiving device determines the LDPC matrix can be found in the description on the transmitting device side, and will not be detailed here.

[0216] It is understood that the steps in the above figures are merely illustrative and are not intended to be strictly limited. Furthermore, the sequence numbers of the processes described above do not imply a specific order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0217] It is also understood that some optional features in the various embodiments of this application may not depend on other features in some scenarios, or may be combined with other features in some scenarios, without limitation.

[0218] It is also understood that, in the above-described method embodiments, the methods and operations implemented by the device (transmitting device or receiving device) can also be implemented by components of the device (such as chips or circuits), without limitation.

[0219] The above text combined Figures 1 to 10 The present application provides a detailed description of the method embodiments, which will be discussed below in conjunction with... Figure 11 and Figure 12 This describes an embodiment of the apparatus described in this application. It is understood that, in order to achieve the functions described in the above embodiments, Figure 11 and Figure 12 The apparatus includes hardware structures and / or software modules corresponding to perform various functions. Those skilled in the art will readily recognize that, based on the units and method steps described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. It is understood that the technical features described in the above method embodiments are also applicable to the following apparatus embodiments.

[0220] Figure 11 and Figure 12The diagram illustrates the possible structures of apparatuses provided for embodiments of this application. These apparatuses can be used to implement the functions of the transmitting or receiving devices in the above method embodiments, and thus also achieve the beneficial effects of the above method embodiments.

[0221] Figure 11 This is a schematic block diagram of the communication device 1000 provided in an embodiment of this application. Figure 11 As shown, the device 1000 may include a communication unit 1010 and a processing unit 1020. The communication unit 1010 can communicate with the outside world, and the processing unit 1020 is used for data processing. The communication unit 1010 may also be referred to as a communication interface or a transceiver unit.

[0222] In one possible design, the device 1000 can implement the steps or processes corresponding to those performed by the transmitting device in the above method embodiments, wherein the processing unit 1020 is used to perform processing-related operations of the transmitting device in the above method embodiments, and the communication unit 1010 is used to perform transmission-related operations of the transmitting device in the above method embodiments.

[0223] In another possible design, the device 1000 can implement the steps or processes corresponding to those performed by the receiving device in the above method embodiments, wherein the communication unit 1010 is used to perform the receiving-related operations of the receiving device in the above method embodiments, and the processing unit 1020 is used to perform the processing-related operations of the receiving device in the above method embodiments.

[0224] It is understood that the device 1000 here is embodied in the form of a functional unit. The term "unit" here can refer to an application-specific integrated circuit (ASIC), electronic circuitry, a processor (e.g., a shared processor, a proprietary processor, or a group processor, etc.) and memory for executing one or more software or firmware programs, integrated logic circuitry, and / or other suitable components supporting the described functions. In an alternative example, those skilled in the art will understand that the device 1000 may specifically be the transmitting end device in the above embodiments, used to execute the various processes and / or steps corresponding to the transmitting end device in the above method embodiments; or, the device 1000 may specifically be the receiving end device in the above embodiments, used to execute the various processes and / or steps corresponding to the receiving end device in the above method embodiments. To avoid repetition, further details are omitted here.

[0225] The apparatus 1000 of each of the above-described schemes has the function of implementing the corresponding steps performed by the transmitting device in the above-described method, or the apparatus 1000 of each of the above-described schemes has the function of implementing the corresponding steps performed by the receiving device in the above-described method. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions; for example, the communication unit can be replaced by a transceiver (e.g., the transmitting unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as processing units, can be replaced by a processor, respectively executing the transmission and reception operations and related processing operations in each method embodiment.

[0226] Furthermore, the aforementioned communication unit can also be a transceiver circuit (e.g., it may include a receiving circuit and a transmitting circuit), and the processing unit can be a processing circuit. In embodiments of this application, Figure 11 The device mentioned can be the receiving or transmitting device in the foregoing embodiments, or it can be a chip or a chip system, such as a system on a chip (SoC). The communication unit can be an input / output circuit or a communication interface; the processing unit is a processor, microprocessor, or integrated circuit integrated on the chip. No limitations are imposed here.

[0227] Figure 12 This is a schematic block diagram of a communication device 1100 provided in an embodiment of this application. The device 1100 includes a processor 1110 and a transceiver 1120. The processor 1110 and the transceiver 1120 communicate with each other through an internal connection path. The processor 1110 is used to execute instructions to control the transceiver 1120 to transmit and / or receive signals.

[0228] Optionally, the device 1100 may further include a memory 1130, which communicates with the processor 1110 and the transceiver 1120 via an internal connection path. The memory 1130 stores instructions, and the processor 1110 can execute the instructions stored in the memory 1130. In one possible implementation, the device 1100 is used to implement the various processes and steps corresponding to the transmitting device in the above method embodiments. In another possible implementation, the device 1100 is used to implement the various processes and steps corresponding to the receiving device in the above method embodiments.

[0229] Optionally, the memory 1130 may be integrated into the processor 1110.

[0230] In one possible scenario, device 1100 includes at least one processor with integrated memory, and other memory besides the memory integrated on the processor.

[0231] It is understood that the device 1100 can specifically be the transmitting or receiving device in the above embodiments, or it can be a chip or a chip system. Correspondingly, the transceiver 1120 can be the transceiver circuit of the chip, which is not limited here. Specifically, the device 1100 can be used to execute the various steps and / or processes corresponding to the transmitting or receiving device in the above method embodiments.

[0232] Optionally, the memory 1130 may include read-only memory and random access memory, and provide instructions and data to the processor. The memory may include non-volatile random access memory. For example, the memory may also store device type information. The processor 1110 may be used to execute instructions stored in the memory, and when the processor 1110 executes instructions stored in the memory, the processor 1110 is used to perform the various steps and / or processes of the method embodiments corresponding to the transmitting or receiving devices described above.

[0233] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0234] It should be noted that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuitry in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, digital signal processing (DSP), ASIC, field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor in the embodiments of this application can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0235] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0236] Optionally, the memory (e.g., 1130) in this embodiment may be integrated into the processor (e.g., 1110).

[0237] In addition, this application also provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause the operations and / or processes performed by the sending or receiving device in the various method embodiments of this application to be executed.

[0238] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending end device or the receiving end device in the various method embodiments of this application are executed.

[0239] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, such that operations and / or processes performed by a transmitting or receiving device in any method embodiment are performed.

[0240] Furthermore, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Furthermore, the chip may also include a memory.

[0241] In addition, this application also provides a communication system, including the transmitting end device and the receiving end device in the embodiments of this application.

[0242] It should also be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0243] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, the functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0244] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0245] It is understood that the term "embodiment" used throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, various embodiments throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0246] It can also be understood that in this application, "when," "if," and "if" all refer to the network element making corresponding processing under certain objective circumstances, and are not time-limited, nor do they require the network element to make a judgment when it is implemented, nor do they mean that there are other limitations.

[0247] It can also be understood that in the various embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it can also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

Claims

1. A communication method based on a low-density parity-check (LDPC) code, characterized by, The method includes: Obtain the information bit sequence; The information bit sequence is encoded according to the LDPC matrix to obtain a codeword sequence, wherein... The LDPC matrix is ​​determined based on the LDPC code base matrix. The base matrix includes an extended parity check region, an incremental redundancy region, and a core region. The extended parity check region is a lower triangular matrix with all diagonal elements being 1. The extended parity check region includes at least one 1 element in addition to the diagonal elements. The column containing the at least one 1 element is the first column. The row containing the diagonal element in the first column is the first row. The first row is the same row as the row with the largest first value in the first region. The first value of each row in the first region is correlated with the row weight of each row. The first region is composed of multiple consecutive rows in the second region. The second region is a region composed of some columns in the incremental redundancy region. At least one column in the partial columns is the same column with a first characteristic in the core region. The column with the first characteristic is the column with a column weight of 2 in the core region.

2. The method according to claim 1, characterized in that, The first value of each row is the row weight of each row. or, The first value of each row is determined based on the value of the element in each row and the coefficient corresponding to the column in which the element is located.

3. The method according to claim 1 or 2, characterized in that, The at least one 1 element is located in the first lower triangular matrix of the extended verification region, wherein the diagonal elements of the first lower triangular matrix are all located on the diagonal of the extended verification region, and the row of the first lower triangular matrix is ​​the same row as the row of the first region.

4. The method according to claim 3, characterized in that, In addition to the diagonal elements and at least one 1 element, the extended verification region also contains an additional 1 element, which is located in the first lower triangular matrix. The at least one 1 element and the additional 1 element are located in N columns of the first lower triangular matrix, and the N diagonal elements of the N columns are located in N rows of the first lower triangular matrix, where N is a positive integer. The N rows are the same rows as the N rows corresponding to the first N values ​​in the first value of the first region.

5. The method of claim 4, wherein, The first value in the i1th row of the first region is equal to the first value in the i2th row. If the i1th row is before the i2th row, then the first value of the i1th row is ordered before the first value of the i2th row. or, The i1th row is contained in the i3th row of the base matrix, the i2th row is contained in the i4th row of the base matrix, and the row weight of the i3th row is greater than the row weight of the i4th row. Therefore, the first value of the i1th row is ordered before the first value of the i2th row.

6. The method according to claim 4 or 5, characterized in that, Each of the N columns contains only one 1 element, excluding the diagonal elements.

7. The method according to claim 6, characterized in that, The row in each column that contains one element is the same as the second row in the first region. The second row is the row with the smallest row weight among all rows after the third row in the first region. The third row is the same as the row containing the diagonal element in each column.

8. The method according to any one of claims 3 to 7, characterized in that, The column containing the incremental redundancy region is the same column as the column containing the core region, and the row containing the incremental redundancy region is the same row as the row containing the extended verification region.

9. The method according to any one of claims 3 to 8, characterized in that, The first column of the first lower triangular matrix is ​​the same column as the corresponding column of a redundant version RV of the basis matrix in the basis matrix. or, The first column of the first lower triangular matrix is ​​the same as the first column of the extended verification region.

10. The method according to any one of claims 3 to 9, characterized in that, In addition to the diagonal elements and at least one 1 element, the extended verification region contains an additional 1 element located in the second lower triangular matrix of the extended verification region. The diagonal elements of the second lower triangular matrix are all located on the diagonal of the extended verification region, and the positions of the diagonal elements of the first and second lower triangular matrices do not overlap. The additional 1 element is located in column M of the second lower triangular matrix, and the M diagonal elements of the M columns are located in row M of the second lower triangular matrix, where M is a positive integer. The rows M are the same as the rows corresponding to the first M values ​​in the first value of the third region. The third region is a region composed of multiple consecutive rows in the second region. The rows in which the second lower triangular matrix is ​​located are the same as the rows in which the third region is located.

11. The method according to claim 10, characterized in that, The first column of the second lower triangular matrix is ​​the same column as the corresponding column of a redundant version RV of the basis matrix in the basis matrix. or, The first column of the second lower triangular matrix is ​​the same as the first column of the extended verification region.

12. A communication method based on low-density parity-check (LDPC) codes, characterized in that, Obtain the symbol sequence; Based on the LDPC matrix, the symbol sequence is decoded to obtain the information bit sequence, wherein... The LDPC matrix is ​​determined based on the LDPC code base matrix. The base matrix includes an extended parity check region, an incremental redundancy region, and a core region. The extended parity check region is a lower triangular matrix with all diagonal elements being 1. The extended parity check region includes at least one 1 element in addition to the diagonal elements. The column containing the at least one 1 element is the first column. The row containing the diagonal element in the first column is the first row. The first row is the same row as the row with the largest first value in the first region. The first value of each row in the first region is correlated with the row weight of each row. The first region is composed of multiple consecutive rows in the second region. The second region is a region composed of some columns in the incremental redundancy region. At least one column in the partial columns is the same column with a first characteristic in the core region. The column with the first characteristic is the column with a column weight of 2 in the core region.

13. The method according to claim 12, characterized in that, The first value of each row is the row weight of each row. or, The first value of each row is determined based on the value of the element in each row and the coefficient corresponding to the column in which the element is located.

14. The method according to claim 12 or 13, characterized in that, The at least one 1 element is located in the first lower triangular matrix of the extended verification region, wherein the diagonal elements of the first lower triangular matrix are all located on the diagonal of the extended verification region, and the row of the first lower triangular matrix is ​​the same row as the row of the first region.

15. The method according to claim 14, characterized in that, In addition to the diagonal elements and the at least one 1 element, the extended verification region also contains an additional 1 element. This additional 1 element is located in the first lower triangular matrix. The at least one 1 element and the additional 1 element are located in N columns of the first lower triangular matrix. The N diagonal elements in the N columns are located in N rows of the first lower triangular matrix, where N is a positive integer. The N rows are the same rows as the N rows corresponding to the first N values ​​in the first value of the first region.

16. The method according to claim 15, characterized in that, The first value in the i1th row of the first region is equal to the first value in the i2th row. If the i1th row is before the i2th row, then the first value of the i1th row is ordered before the first value of the i2th row. or, The i1th row is contained in the i3th row of the base matrix, the i2th row is contained in the i4th row of the base matrix, and the row weight of the i3th row is greater than the row weight of the i4th row. Therefore, the first value of the i1th row is ordered before the first value of the i2th row.

17. The method according to claim 15 or 16, characterized in that, Each of the N columns contains only one 1 element, excluding the diagonal elements.

18. The method according to claim 17, characterized in that, The row in each column that contains one element is the same as the second row in the first region. The second row is the row with the smallest row weight among all rows after the third row in the first region. The third row is the same as the row containing the diagonal element in each column.

19. The method according to any one of claims 14 to 18, characterized in that, The column containing the incremental redundancy region is the same column as the column containing the core region, and the row containing the incremental redundancy region is the same row as the row containing the extended verification region.

20. The method according to any one of claims 14 to 19, characterized in that, The first column of the first lower triangular matrix is ​​the same column as the corresponding column of a redundant version RV of the basis matrix in the basis matrix. or, The first column of the first lower triangular matrix is ​​the same as the first column of the extended verification region.

21. The method according to any one of claims 14 to 20, characterized in that, In addition to the diagonal elements and at least one 1 element, the extended verification region contains an additional 1 element located in the second lower triangular matrix of the extended verification region. The diagonal elements of the second lower triangular matrix are all located on the diagonal of the extended verification region, and the positions of the diagonal elements of the first and second lower triangular matrices do not overlap. The additional 1 element is located in column M of the second lower triangular matrix, and the M diagonal elements of the M columns are located in row M of the second lower triangular matrix, where M is a positive integer. The rows M are the same as the rows corresponding to the first M values ​​in the first value of the third region. The third region is a region composed of multiple consecutive rows in the second region. The rows in which the second lower triangular matrix is ​​located are the same as the rows in which the third region is located.

22. The method according to claim 21, characterized in that, The first column of the second lower triangular matrix is ​​the same column as the corresponding column of a redundant version RV of the basis matrix in the basis matrix. or, The first column of the second lower triangular matrix is ​​the same as the first column of the extended verification region.

23. A communication device, characterized in that, The device includes at least one processor and an interface circuit, the interface circuit being configured to receive signals from other communication devices besides the communication device and transmit them to the processor, or to send signals from the processor to other communication devices besides the communication device, the processor causing the method as described in any one of claims 1 to 11 to be implemented, or causing the method as described in any one of claims 12 to 22 to be implemented, through logic circuits or by executing code instructions.

24. The communication device according to claim 23, characterized in that, The communication device is a chip or chip system.

25. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions that, when executed, cause the method as described in any one of claims 1 to 11 to be implemented, or cause the method as described in any one of claims 12 to 22 to be implemented.

26. A computer program product, characterized in that, Includes a computer program that, when run, causes the method as described in any one of claims 1 to 11 to be implemented, or causes the method as described in any one of claims 12 to 22 to be implemented.

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