A multi-core decoding order scheduling method and system based on DDR identification cache

Abstract

The application relates to the technical field of digital communication, and discloses a multi-core decoding ordered scheduling method and system based on DDR identification caching, which comprises the following steps: through a multi-core decoding input scheduling module arranged at the input end of a decoder, a to-be-decoded data block is distributed to an idle decoder, and a unique identification ID of the to-be-decoded data block is added; each decoder carries out parallel decoding processing on the to-be-decoded data block based on the unique identification ID; through a caching reordering module arranged at the output end of the decoder, a DDR block storage area is divided, and the decoding results corresponding to each decoder are written into the corresponding sub-blocks of the DDR block storage area in disorder; and the empty-full state signals of the DDR block storage area and the output states of each decoder are used to carry out caching scheduling operation of the DDR block storage area. The application can realize efficient, stable and extensible operation of a multi-core decoding system in a high-bandwidth application scenario.

Description

Technical Field

[0001] This invention relates to a multi-core decoding ordered scheduling method and system based on DDR identifier cache, belonging to the field of digital communication technology. Background Technology

[0002] In modern communication systems, the channel decoder is a key module for physical layer data recovery. Its throughput directly determines the overall system's data transmission rate and latency performance. With the continuous increase in the bandwidth and high-speed data link requirements of communication systems, the system places higher demands on the real-time processing capabilities of the decoder.

[0003] However, in existing parallel decoding architectures, a fixed sequential scheduling method is usually adopted, that is, the LLR soft information of multiple code blocks is distributed to multiple decoders in the order of input, and the decoding results are expected to be output in the same order. Although this method can improve the overall throughput through multi-core parallelism, the decoding iteration number and convergence time corresponding to different codewords are different, which leads to the time when each decoder completes its task is inconsistent, thus causing the problem of out-of-order decoding output results. Summary of the Invention

[0004] This invention provides a multi-core decoding ordered scheduling method and system based on DDR identifier cache. Its main purpose is to achieve efficient, stable and scalable operation of the multi-core decoding system in high-bandwidth application scenarios.

[0005] To achieve the above objectives, this invention provides a multi-core decoding ordered scheduling method based on DDR identifier cache, comprising:

[0006] By deploying a multi-core decoding input scheduling module at the decoder input end, the data block to be decoded is allocated to an idle decoder, and a unique identifier ID is added to the data block to be decoded. Each decoder performs parallel decoding processing on the data block to be decoded based on the unique identifier ID to generate a decoding result corresponding to the unique identifier ID.

[0007] The DDR block storage area is divided by a cache reordering module deployed at the output of the decoder, and the decoding results corresponding to each decoder are written out of order into the sub-blocks corresponding to the DDR block storage area. The DDR block storage area consists of multiple large blocks and multiple sub-blocks within each large block.

[0008] Identify the read-write pointer relationship within the cache reordering module. When all sub-blocks within any large block of the DDR block storage area have been written with decoding results, generate an empty / full status signal for the DDR block storage area based on the read-write pointer relationship.

[0009] Based on the empty / full status signal and the output status of each decoder, the cache scheduling operation of the DDR block storage area is executed. The cache scheduling operation includes at least one of out-of-order write operation and sequential read operation.

[0010] Optionally, a unique identifier ID for the data block to be decoded is added by a multi-core decoder input scheduling module deployed at the decoder input, including:

[0011] After the data block to be decoded is sent to the input of the decoder through the corresponding interface, the current busy / idle status of each decoder is polled to obtain the polling detection result;

[0012] Based on the polling detection results, the target channel number of the decoder to be assigned is determined;

[0013] According to the pre-configured identifier mapping rules, the target channel number is bound to the logical sequence number of the data block to be decoded to generate a unique identifier ID for the data block to be decoded.

[0014] Optionally, the current busy / idle status of each decoder is polled to obtain the polling results, including:

[0015] Continuously loop through the busy / idle status registers corresponding to all decoders;

[0016] Read the status signal of each decoder in sequence. A high level indicates that the decoder is in a busy state, and a low level indicates that the decoder is in an idle state.

[0017] The state signals are combined in decoder number order to generate state vectors corresponding to all current decoders.

[0018] Based on the state vector, the decoder number corresponding to the low level in the state signal is identified, and the decoder number corresponding to the low level is used as the polling detection result.

[0019] Optionally, the DDR block storage area is divided by a cache reordering module deployed at the decoder output, including:

[0020] The contiguous physical address space in the external DDR memory is divided into multiple logical blocks according to preset rules;

[0021] Each logical block is further subdivided into multiple sub-blocks, the number of which is equal to the number of decoders.

[0022] A unique starting address is pre-assigned to each sub-block, and a mapping relationship is established between the unique starting address and the decoding result ID of each decoder to complete the division of the DDR block storage area.

[0023] Optionally, identifying the read-write pointer relationship within the cache reordering module includes:

[0024] Read the first and second values ​​of the write pointer and read pointer in the cache reordering module at the current position;

[0025] When the first value is equal to the second value, the read / write pointer relationship is null.

[0026] When the first value is not equal to the second value and the difference between the values ​​is less than the total number of large blocks, the read / write pointer relationship is full.

[0027] When the first value is greater than the second value and the difference between the values ​​is greater than the total number of blocks, the read / write pointer relationship is a non-empty and non-full relationship.

[0028] Optionally, based on the empty / full status signal and the output status of each decoder, the cache scheduling operation of the DDR block memory area is performed, including:

[0029] When the full signal in the empty / full state signal is invalid and the output state of at least one decoder is valid, the out-of-order write operation of the DDR block memory area is performed.

[0030] When the empty signal in the empty / full state signal is invalid and the current decoder output state is valid, the sequential read operation of the DDR block storage area is performed.

[0031] Optionally, when the empty signal in the empty / full state signal is invalid and the current decoder output state is valid, the sequential read operation of the DDR block memory area is performed, including:

[0032] Determine the starting address of the large block to be read from the DDR block storage area;

[0033] According to the sub-block numbering order in the DDR block storage area, the decoding result data corresponding to the starting address of the large block is read sequentially, and the decoding result data is output in the original input order.

[0034] Optionally, the multi-core decoder input scheduling module is a dedicated hardware unit set between the system data input interface and the input end of the multi-core decoder array. It is used to dynamically allocate input data according to the busy / idle status of the decoder and to attach an identifier to the data to maintain sequential traceability. The module integrates a decoder status register group, a polling control state machine, an identifier generation and binding unit, and a multi-channel data distributor.

[0035] Optionally, the cache reordering module is a dedicated hardware unit located between the output of the multi-core decoder array and the system data output interface. It is used to cache, sort, and output the out-of-order results generated by parallel decoding. The module integrates block address management logic, polling and control state machine, identifier matching and address translation unit, read / write pointer controller, and high-speed data path interface.

[0036] To address the aforementioned problems, this invention also provides a multi-core decoding ordered scheduling system based on a DDR identifier cache, the system comprising:

[0037] The input scheduling module is used to allocate the data block to be decoded to the idle decoder through the multi-core decoding input scheduling module deployed at the decoder input end, and add a unique identifier ID to the data block to be decoded. Each decoder performs parallel decoding processing on the data block to be decoded based on the unique identifier ID to generate a decoding result corresponding to the unique identifier ID.

[0038] The storage management module is used to divide the DDR block storage area by a cache reordering module deployed at the output of the decoder, and to write the decoding results corresponding to each decoder into the sub-blocks corresponding to the DDR block storage area in random order. The DDR block storage area consists of multiple large blocks and multiple sub-blocks within each large block.

[0039] The status control module is used to identify the read-write pointer relationship within the cache reordering module. When all sub-blocks within any large block of the DDR block storage area have been written with the decoding result, the module generates an empty / full status signal for the DDR block storage area based on the read-write pointer relationship.

[0040] The scheduling execution module is used to perform cache scheduling operations on the DDR block storage area according to the empty / full status signal and the output status of each decoder. The cache scheduling operation includes at least one of out-of-order write operation and sequential read operation.

[0041] Compared to the problems described in the background art, the embodiments of the present invention, through a multi-core decoding input scheduling module deployed at the decoder input end, allocate the data blocks to be decoded to idle decoders and add a unique identifier ID to the data blocks to be decoded, which can restore the original data order at the decoding result output end, thereby ensuring a one-to-one correspondence between the decoding result and the input data and avoiding out-of-order output problems. Furthermore, the embodiments of the present invention, through a cache reordering module deployed at the decoder output end, divide the DDR block storage area, and through structured address space management, realize out-of-order writing and sequential reading of decoding results, thereby ensuring the orderliness of the output data. The embodiments of the present invention, through a cache reordering module deployed at the decoder output end, write the decoding results corresponding to each decoder into the corresponding sub-blocks of the DDR block storage area out of order, which can decouple the decoding completion time from the output order, allowing each decoding core to independently complete the operation at the maximum rate and output immediately, thereby avoiding the problem of blocking the overall processing flow due to waiting for slow decoding blocks. By identifying the read / write pointer relationship within the cache reordering module, the data occupancy status of the DDR block storage area can be monitored in real time, accurately determining whether the cache space is empty or full. Furthermore, in this embodiment of the invention, when all sub-blocks within any large block of the DDR block storage area have been written with decoding results, an empty / full status signal for the DDR block storage area is generated based on the read / write pointer relationship. This enables real-time feedback on the cache space usage status, thereby dynamically controlling the start and stop of data writing and reading. This ensures that during parallel out-of-order writing, unread data is not overwritten, and invalid reads are not performed when there is no data. Finally, this embodiment of the invention, by executing the cache scheduling operation of the DDR block storage area according to the empty / full status signal and the output status of each decoder, can intelligently coordinate resource contention and timing conflicts between data writing and reading. While ensuring data integrity and correct order, it maximizes the utilization efficiency of the parallel data path, thereby achieving high throughput, low latency, and stable and orderly multi-core decoding output. Therefore, this invention can achieve efficient, stable, and scalable operation of a multi-core decoding system in high-bandwidth application scenarios. Attached Figure Description

[0042] Figure 1 This is a flowchart illustrating a multi-core decoding ordered scheduling method based on DDR identifier cache, provided in an embodiment of the present invention.

[0043] Figure 2 The overall data path diagram for implementing the multi-core decoding ordered scheduling method based on DDR identifier cache is provided in one embodiment of the present invention;

[0044] Figure 3 A flowchart of a multi-core decoding input scheduling method based on DDR identifier cache, provided as an embodiment of the present invention;

[0045] Figure 4 This is a schematic diagram of the DDR block logic for implementing a multi-core decoding ordered scheduling method based on DDR identifier cache, as provided in an embodiment of the present invention.

[0046] Figure 5 The flowchart of DDR-based decoding result caching and reordering is provided as an embodiment of the present invention for a multi-core decoding ordered scheduling method based on DDR identifier caching.

[0047] Figure 6 A system flowchart of a multi-core decoding ordered scheduling method based on DDR identifier cache provided in an embodiment of the present invention;

[0048] Figure 7 This is a functional block diagram of a multi-core decoding ordered scheduling system based on DDR identifier cache, provided in an embodiment of the present invention.

[0049] Figure 8 A schematic diagram of a computer device for a multi-core decoding ordered scheduling method based on DDR identifier cache provided in an embodiment of the present invention;

[0050] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0051] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0052] This application provides a multi-core decoding ordered scheduling method based on DDR identifier caching. The executing entity of this multi-core decoding ordered scheduling method based on DDR identifier caching includes, but is not limited to, at least one of the following electronic devices that can be configured to execute the method provided in this application: a server, a terminal, etc. In other words, the multi-core decoding ordered scheduling method based on DDR identifier caching can be executed by software or hardware installed on a terminal device or a server device. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0053] Reference Figure 1 The diagram shown is a flowchart illustrating a multi-core decoding ordered scheduling method based on a DDR identifier cache according to an embodiment of the present invention. In this embodiment, the multi-core decoding ordered scheduling method based on a DDR identifier cache includes:

[0054] To address the issues of unbalanced task scheduling and out-of-order output in multi-core parallel decoding, this invention provides a multi-core decoding scheduling architecture based on a DDR caching strategy. (See attached document.) Figure 2The diagram shown is an overall data path diagram of a multi-core decoding ordered scheduling method based on DDR identifier caching provided in an embodiment of the present invention. The diagram clearly shows the main components of the multi-core decoding scheduling architecture and their connection relationships, specifically including: a multi-core decoding input scheduling module (DEMUX), a parallel decoder array, a DDR-based decoding result caching and reordering module (MUX), and an external DDR storage unit. The key signals of interaction between the modules (such as Finish, identifier ID, etc.) are also marked. This block diagram intuitively presents the flow of data from input to output and the cooperative relationship between modules from an architectural perspective, providing a clear topological view for understanding the overall hardware implementation of the present invention.

[0055] S1. The multi-core decoding input scheduling module deployed at the decoder input end allocates the data block to be decoded to the idle decoder and adds a unique identifier ID to the data block to be decoded. Each decoder performs parallel decoding processing on the data block to be decoded based on the unique identifier ID to generate a decoding result corresponding to the unique identifier ID.

[0056] This invention, through a multi-core decoding input scheduling module deployed at the decoder input, allocates data blocks to be decoded to idle decoders. It achieves intelligent scheduling and data allocation of decoder resources by dynamically polling the idle status of each decoder. The decoder input refers to the entry point where decoding task data enters the decoder for processing. For example, in a system architecture, the decoder input is typically connected to an input scheduling module (DEMUX) to receive the scheduled code block data, including an ID identifier in the first segment for subsequent result matching and reordering. The data block to be decoded refers to the original information or signal that needs decoding processing, typically soft-decision information received after channel transmission, such as the log-likelihood ratio (LLR). An idle decoder is a decoder core that is currently not executing a decoding task and is in an available state. For example, if a decoder has completed the decoding of the previous code block and written the result to the DDR cache, its state will be updated to idle, waiting for the input scheduling module to allocate a new data block to be decoded.

[0057] It should be noted that the multi-core decoder input scheduling module is a dedicated hardware unit set between the system data input interface and the input end of the multi-core decoder array. Its core function is to dynamically allocate input data according to the busy / idle status of the decoder and attach an identifier to the data to maintain the order traceability. The module integrates a decoder status register group, a polling control state machine, an identifier generation and binding unit, and a multi-channel data distributor.

[0058] Specifically, the process of allocating the data block to be decoded to an idle decoder through the multi-core decoder input scheduling module deployed at the decoder input end is as follows: the state machine of the multi-core decoder input scheduling module continuously and cyclically detects the busy / idle status signals of each decoder core; when a decoder is detected to be in an idle state, the decoder is immediately locked as the target channel, and the code block data to be scheduled is sent to the input end of the decoder through the corresponding interface. When data transmission starts, the state machine control identifier generation unit assigns a unique ID to the current code block and inserts the ID into the header of the data stream or sends it along with the control signaling. Once data transmission begins, the state machine synchronously updates the status of the decoder to "busy" to prevent the same decoder from being repeatedly assigned tasks, until the "idle" signal returned by the decoder after it has completed decoding and written to the buffer is received.

[0059] To clearly demonstrate the specific workflow of the multi-core decoding input scheduling module, please refer to [link / reference]. Figure 3 The diagram shows a multi-core decoding input scheduling flowchart for an embodiment of the multi-core decoding ordered scheduling method based on DDR identifier caching provided by the present invention. The flowchart first updates the busy / idle status of each decoder based on status feedback from the backend cache module. Then, a polling mechanism is used to sequentially check whether each decoder is idle. When an idle decoder is identified, it is selected as the target channel, and the data to be decoded is allocated to that decoder. Simultaneously, a unique identifier ID is inserted into the data header. Through this process, the present invention achieves dynamic load balancing and task order binding among multiple decoders, thereby laying the foundation for the ordered output of subsequent decoding results.

[0060] Furthermore, in this embodiment of the invention, by deploying a multi-core decoding input scheduling module at the decoder input end, a unique identifier ID is added to the data block to be decoded. This allows the original data order to be restored at the decoding result output end, thereby ensuring a one-to-one correspondence between the decoding result and the input data and avoiding out-of-order output problems. The unique identifier ID refers to a unique numerical identifier assigned to each group of input data blocks to be decoded, used to uniquely identify the data block to be decoded during parallel decoding.

[0061] As an embodiment of the present invention, a multi-core decoding input scheduling module deployed at the decoder input end adds a unique identifier ID to the data block to be decoded, including: after the data block to be decoded is sent to the decoder input end through the corresponding interface, polling the current busy / idle status of each decoder to obtain the polling detection result; based on the polling detection result, determining the target channel number of the decoder to be assigned; and binding the target channel number with the logical sequence number of the data block to be decoded according to the pre-configured identifier mapping rule to generate a unique identifier ID for the data block to be decoded.

[0062] The current busy / idle state refers to whether each decoder core is in a state where it can receive new decoding tasks at a certain moment. This is usually determined by the "busy" signal in the status register or the "finish" signal from the output buffer module. For example, "busy=0" indicates idle, and "busy=1" indicates busy. The polling detection result refers to a set of states obtained by sequentially querying the busy / idle states of each decoder. This result is used to identify the decoder number currently in an idle state. The target channel number refers to the physical channel identifier of the decoder ultimately selected to receive the current data block to be decoded based on the polling detection result. For example, in a six-core system, the channel number can be 1 to 6. The identifier mapping rule refers to a predefined encoding rule used to combine the target channel number and logical sequence number to generate a unique identifier ID. For example, a composite encoding method can be used: ID = (logical sequence number × 10) + channel number; the logical sequence number refers to the sequential number of the data block to be decoded in its original input data stream, used to restore the original order at the output.

[0063] It should be noted that the unique identifier ID is generated by combining the logical sequence number and the channel number bit by bit, and the structure satisfies: ID = (logical sequence number << N) | channel number, where N is the bit width of the channel number.

[0064] Optionally, a segmented encoding rule can be used to bind the target channel number with the logical sequence number of the data block to be decoded, such as assigning the high bit of the ID to the logical sequence number and the low bit to the channel number, in order to support subsequent address mapping and sequence recovery.

[0065] As an optional embodiment of the present invention, the current busy / idle state of each decoder is polled to obtain the polling detection result, including: continuously looping through the busy / idle state registers corresponding to all decoders; sequentially reading the state signal of each decoder, wherein a high level indicates that the decoder is in a busy state, and a low level indicates that the decoder is in an idle state; combining the state signals in the order of decoder numbers to generate a state vector corresponding to all current decoders; identifying the decoder number corresponding to the low level in the state signal according to the state vector, and using the decoder number corresponding to the low level as the polling detection result.

[0066] The busy / idle status register refers to a 1-bit register set up for each decoder core within the multi-core decoder input scheduling module, used to store and update the occupancy status of the decoder in real time; the status signal refers to the current value of the decoder core read from the busy / idle status register, represented in the form of a level signal, which typically corresponds to logic "1" (high level) or logic "0" (low level) in digital circuits; the decoder numbering order refers to the fixed physical identifier order assigned to each decoder core, for example, in a 6-core system, the numbering order can be channel 0 to channel 5; the status direction A quantity refers to a multi-bit binary data formed by combining all the status signals read in the order of the decoder number, such as a 6-bit vector [1,0,1,0,0,1], where each bit corresponds to the busy / idle state of a decoder, where 1 indicates that the corresponding decoder is busy and 0 indicates that the corresponding decoder is idle; the low level refers to the level signal that represents logic "0" in digital logic, and in this embodiment, it indicates that the corresponding decoder is in an "idle" state; the high level refers to the level signal that represents logic "1" in digital logic, and in this embodiment, it indicates that the corresponding decoder is in a "busy" state.

[0067] In detail, the specific process of combining the status signals according to the decoder number order to generate the status vector corresponding to all current decoders is as follows: after reading the status signals of each decoder in the order of the decoder number, the level value of the status signal is directly mapped to a logic value, wherein a high level is mapped to logic 1 and a low level is mapped to logic 0, and the corresponding logic values ​​are written into the corresponding binary bits of the vector register in the same order to obtain the status vector corresponding to all current decoders.

[0068] In this embodiment of the invention, each decoder performs parallel decoding on the data block to be decoded based on the unique identifier ID to generate a decoding result corresponding to the unique identifier ID. This provides the necessary basis for subsequent correct caching and order restoration of data under out-of-order output conditions. The decoding result refers to the data output by each decoder core after completing the decoding operation on the data block to be decoded with the unique identifier ID. Its content is the original information bit sequence after error correction and restoration, and the output still carries the same identifier ID corresponding to the input data, which is used for data matching and order reassembly in the subsequent caching and output stages.

[0069] Specifically, the process by which each decoder performs parallel decoding on the data block to be decoded based on the unique identifier ID to generate a decoding result corresponding to the unique identifier ID is as follows: after receiving the data block to be decoded with the unique identifier ID attached, each decoder performs independent calculations according to the built-in decoding algorithm, such as the LDPC algorithm, and maintains the binding relationship between the unique identifier ID and the data block during the decoding process. After the decoding is completed, the decoded result with the same identifier ID is output.

[0070] S2. The DDR block storage area is divided by the cache reordering module deployed at the output of the decoder, and the decoding results corresponding to each decoder are written out of order into the sub-blocks corresponding to the DDR block storage area.

[0071] This invention, through a cache reordering module deployed at the decoder output, divides the DDR block storage area. This enables structured address space management, allowing for out-of-order writing and sequential reading of decoding results, thus ensuring the orderliness of the output data. The decoder output refers to the data interface or bus through which each decoder core outputs the decoding result after completing the decoding operation. This output is directly connected to the subsequent cache reordering module, used to send the decoding result with an identifier ID to the cache system. The DDR block storage area refers to a contiguous address space pre-divided and logically organized in external DDR memory. This space is hierarchically divided into multiple large blocks, each further divided into multiple sub-blocks. Each sub-block stores the decoding result output by one decoder. For example, the storage area can be divided into 4 large blocks, each containing 6 sub-blocks, for a total of 24 sub-blocks, corresponding to 24 possible decoding result IDs, thereby achieving address-based management and orderly reorganization of the decoding results.

[0072] Specifically, the cache reordering module is a dedicated hardware unit located between the output of the multi-core decoder array and the system data output interface. Its core function is to cache, sort, and output the out-of-order results generated by parallel decoding. The module integrates block address management logic, polling and control state machine, identifier matching and address translation unit, read / write pointer controller, and high-speed data path interface.

[0073] It should be noted that the specific operation of the cache reordering module includes: First, during the system initialization phase, DDR block storage areas are partitioned in the external DDR memory; during system operation, the module continuously monitors the output status of each decoder through a polling mechanism; when a decoder is detected to have completed decoding and output a result with a unique identifier ID, the module maps the result data to the corresponding DDR sub-block address based on the identifier ID and writes the result data to that address, supporting out-of-order parallel writing of multiple data streams; on the read side, the module accesses the sub-blocks within each major block sequentially according to the read pointer, reads the data sequentially according to the original logical order, and sends it to the system output; the module maintains independent read and write pointers and compares their positional relationships to generate a real-time empty / full status signal for the storage area, which is used for feedback control and process scheduling, thereby ensuring that the decoding results are ultimately output in the correct order while avoiding data overwriting, achieving a balance between high throughput and output order in the multi-core decoding system.

[0074] As an embodiment of the present invention, the DDR block storage area is divided by a cache reordering module deployed at the output of the decoder, including: dividing the continuous physical address space in the external DDR memory into multiple logical blocks according to preset rules; further subdividing each logical block into multiple sub-blocks equal to the number of decoders; pre-allocating a unique starting address for each sub-block, and establishing a mapping relationship between the unique starting address and the decoding result ID of each decoder, so as to complete the division of the DDR block storage area.

[0075] The external DDR memory is a dynamic random access memory located outside the programmable logic chip (PL) and accessed through a memory controller, used to provide high-speed cache space for large-capacity decoding results. The continuous physical address space refers to a contiguous storage area within the external DDR memory that can be directly addressed by the system. The preset rules include determining the number of blocks and the number of sub-blocks within each block based on the number of batches of parallel decoding and the total number of decoder cores. The logical block refers to a logical storage unit partitioned within the aforementioned continuous address space, used to store all decoder outputs within a complete parallel decoding cycle; each block can independently accommodate a batch of decoding results. The sub-block refers to the smallest storage unit within each logical block, further partitioned and corresponding one-to-one with a single decoder output, used to store a single decoding result. The unique starting address refers to a unique starting access address allocated to each sub-block within the DDR physical address space, used to locate the storage location of the sub-block. The mapping relationship refers to a deterministic address correspondence rule established based on the decoding result ID and the hierarchical structure of the DDR block storage area. Specifically, the mapping relationship directly calculates the corresponding unique starting address by parsing the decoded result ID into two parts: a block index and a sub-block index. For example, in a storage area divided into 4 blocks, each block containing 6 sub-blocks, if the block size is Bsize and the sub-block size is Ssize, the starting address corresponding to the decoded result ID can be determined by the following formula: starting address = base address + (block index × Bsize) + (sub-block index × Ssize), where the block index and sub-block index can be directly extracted from the encoding of the decoded result ID.

[0076] Optionally, each logical block can be further subdivided into multiple sub-blocks equal to the number of decoders by calculating address offsets; a unique starting address can be pre-assigned to each sub-block using arithmetic operations based on base address and index; the mapping relationship between the unique starting address and the decoding result ID of each decoder can be established by hash function conversion.

[0077] See Figure 4The diagram shown is a schematic diagram of the DDR block logic for implementing the multi-core decoding ordered scheduling method based on DDR identifier cache according to an embodiment of the present invention. The diagram illustrates the logical layout of the storage area division in DDR according to the present invention. The diagram clearly shows that the DDR storage space is organized into a two-level structure of "large block - sub-block": the entire cache area is divided into multiple consecutive large blocks, and each large block is divided into several sub-blocks equal to the number of decoders. Each sub-block is pre-allocated with a unique starting address. This block design is the key to realizing "out-of-order writing and sequential reading" of the decoding results: for example, during writing, each decoder can directly locate the corresponding sub-block for independent writing based on the identifier ID carried by the result; during reading, the system reads sequentially according to the numbering order of the large blocks and sub-blocks, thereby naturally restoring the original order of the data.

[0078] Furthermore, in this embodiment of the invention, by deploying a cache reordering module at the output end of the decoder, the decoding results corresponding to each decoder are written out of order into the sub-blocks corresponding to the DDR block storage area. This can decouple the decoding completion time from the output order, allowing each decoding core to complete the operation independently at the maximum rate and output it in real time, thereby avoiding the problem of blocking the overall processing flow due to waiting for slow decoding blocks.

[0079] Optionally, the decoding results corresponding to each decoder can be written out of order to the sub-blocks corresponding to the DDR block storage area based on the addressing and writing mechanism of the identifier ID. Specifically, the cache reordering module directly maps the unique identifier ID carried by the decoding result to the pre-allocated starting address of the corresponding sub-block in the DDR block storage area, thereby allowing the output of each decoder to be written independently and without synchronization to its corresponding storage location according to the order of its completion time.

[0080] To visually demonstrate the internal processing flow of the cache reordering module, please refer to... Figure 5The diagram illustrates a DDR-based decoding result caching and reordering flowchart of a multi-core decoding ordered scheduling method based on DDR identifier caching, provided by an embodiment of the present invention. The diagram clearly describes how the cache reordering module detects the output status of each decoder through a polling mechanism and dynamically decides read / write operations based on empty / full flags: When a valid decoder output is detected and the cache is not full, the system writes the decoder result to the corresponding DDR sub-block according to the identifier ID carried by the decoder result, and updates the write pointer after completing the entire block write; when there is no decoder output and the cache is not empty, the system reads all sub-block data within the current block sequentially according to the read pointer, and updates the read pointer after reading, thereby completing the complete data reassembly process from out-of-order reception to sequential output. Furthermore, the diagram also illustrates how the system dynamically coordinates read / write conflicts, prevents data overwriting, and maintains consistent output order under high throughput through the closed-loop logic of state judgment and pointer management. For example, the diagram clearly shows that in the "state judgment" stage, the system synchronously monitors the full and empty signals: if the full signal is valid, writing is prohibited to avoid overwriting unread data; if the empty signal is valid, reading is paused to prevent outputting invalid data.

[0081] S3. Identify the read-write pointer relationship within the cache reordering module. When all sub-blocks within any large block of the DDR block storage area are written with decoding results, generate an empty / full status signal for the DDR block storage area based on the read-write pointer relationship.

[0082] This invention, by identifying the read-write pointer relationship within the cache reordering module, can monitor the data occupancy status of the DDR block storage area in real time and accurately determine whether the cache space is empty or full. The read-write pointer relationship refers to the relative position and logical comparison relationship between the write pointer (wr_ptr) and the read pointer (rd_ptr) maintained inside the cache reordering module.

[0083] In detail, identifying the read-write pointer relationship within the cache reordering module includes: reading the first and second values ​​corresponding to the write pointer and read pointer in the cache reordering module at the current time; when the first value is equal to the second value, the read-write pointer relationship is empty; when the first value is not equal to the second value and the value difference is less than the total number of large blocks, the read-write pointer relationship is full; when the first value is greater than the second value and the value difference is greater than the total number of large blocks, the read-write pointer relationship is neither empty nor full.

[0084] The "empty" relationship indicates that all written decoding results in the DDR block storage area have been read sequentially, and there is currently no valid data available for output, so the cache is empty. The "full" relationship indicates that the cache space in the DDR block storage area is completely occupied and cannot accept new decoding results, so the cache is full. The "neither empty nor full" relationship indicates that there are both written but unread data blocks and free large blocks available for writing in the DDR block storage area, and the system can perform out-of-order write and sequential read operations simultaneously, so the cache is in normal working condition. The total number of large blocks refers to the total number of logical large blocks that have been pre-divided in the DDR block storage area.

[0085] Furthermore, in this embodiment of the invention, when all sub-blocks within any large block of the DDR block storage area have been written with decoding results, an empty / full status signal of the DDR block storage area is generated based on the read / write pointer relationship. This enables real-time feedback on the cache space usage status, thereby dynamically controlling the start and stop of data writing and reading. It ensures that during parallel out-of-order writing, neither unread data is overwritten nor invalid reads are performed when there is no data. The empty / full status signal refers to a set of control signals generated and output in real time by the cache reordering module based on the read / write pointer relationship, used to indicate the current space occupancy status of the DDR block storage area. The empty / full status signal includes an empty signal, a full signal, and a non-empty / non-full signal.

[0086] Optionally, the empty / full status signals of the DDR block storage area can be generated by a finite state machine, such as by embedding pointer comparison logic in the state transition conditions to generate corresponding status signals in different states, including empty, full, and normal working states.

[0087] S4. Based on the empty / full status signal and the output status of each decoder, perform the cache scheduling operation of the DDR block storage area.

[0088] This invention, by performing cache scheduling operations on the DDR block storage area based on the empty / full status signal and the output status of each decoder, can intelligently coordinate resource contention and timing conflicts between data writing and reading. Under the premise of ensuring data integrity and correct sequence, it maximizes the utilization efficiency of parallel data paths, thereby achieving high throughput, low latency, and stable and orderly multi-core decoding output.

[0089] The output status refers to the real-time working status of each decoder's output port after completing the decoding of the current data block; the cache scheduling operation includes out-of-order write operation, sequential read operation, and wait / arbitration operation. For example, when the cache is full, all write operations are paused; when the cache is empty, all read operations are paused; when multiple decoders output valid values ​​simultaneously, write arbitration is performed according to a preset priority or round-robin strategy.

[0090] As an embodiment of the present invention, the cache scheduling operation of the DDR block storage area is performed according to the empty / full status signal and the output status of each decoder, including: when the full signal in the empty / full status signal is invalid and the output status of at least one decoder is valid, performing an out-of-order write operation of the DDR block storage area; when the empty signal in the empty / full status signal is invalid and the current output status of no decoder is valid, performing a sequential read operation of the DDR block storage area.

[0091] It should be noted that, in order to prevent reading invalid data and ensure the reliability of cache operations, all write operations are suspended when the full signal in the empty / full status signal is valid; and all read operations are suspended when the empty signal in the empty / full status signal is valid.

[0092] Furthermore, when the empty signal in the empty / full state signal is invalid and the current no decoder output state is valid, the sequential read operation of the DDR block storage area is performed, including: determining the starting address of the block to be read in the DDR block storage area; sequentially reading the decoding result data corresponding to the starting address of the block according to the sub-block numbering order in the DDR block storage area, and outputting the decoding result data in the original input order.

[0093] Accordingly, after completing the reading of all sub-blocks of the current block, the control logic inside the cache reordering module automatically increments the read pointer to point to the starting address of the next logical block in the DDR block storage area, so as to continue the sequential output of subsequent data.

[0094] See Figure 6 The diagram shown is a system flowchart of a multi-core decoding ordered scheduling method based on DDR identifier cache provided in an embodiment of the present invention. The diagram summarizes the entire process from the input of data to be decoded, through multi-core scheduling and parallel decoding, to the decoding results being reordered through the DDR cache and finally output in an ordered manner. Similarly, the diagram also comprehensively presents the data flow and control relationship between the input scheduling module (DEMUX), the parallel decoder array, the cache reordering module (MUX), and the DDR storage unit, which helps to understand the overall collaborative operation mechanism and implementation architecture of each link of the present invention.

[0095] like Figure 7 The diagram shown is a functional block diagram of a multi-core decoding ordered scheduling system based on DDR identifier cache according to the present invention.

[0096] The multi-core decoding ordered scheduling system 400 based on DDR identifier cache described in this invention can be installed in an electronic device. Depending on the functions implemented, the multi-core decoding ordered scheduling system based on DDR identifier cache includes an input scheduling module 401, a storage management module 402, a state control module 403, and a scheduling execution module 404. The module described in this invention can also be called a unit, which refers to a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, and are stored in the memory of the electronic device.

[0097] In this embodiment of the invention, the functions of each module / unit are as follows:

[0098] The input scheduling module 401 is used to allocate the data block to be decoded to the idle decoder through the multi-core decoding input scheduling module deployed at the decoder input end, and add a unique identifier ID to the data block to be decoded. Each decoder performs parallel decoding processing on the data block to be decoded based on the unique identifier ID to generate a decoding result corresponding to the unique identifier ID.

[0099] The storage management module 402 is used to divide the DDR block storage area by a cache reordering module deployed at the decoder output end, and to write the decoding results corresponding to each decoder into the sub-blocks corresponding to the DDR block storage area in random order. The DDR block storage area consists of multiple large blocks and multiple sub-blocks within each large block.

[0100] The state control module 403 is used to identify the read-write pointer relationship within the cache reordering module. When all sub-blocks within any large block of the DDR block storage area are written with decoding results, the empty / full status signal of the DDR block storage area is generated based on the read-write pointer relationship.

[0101] The scheduling execution module 404 is used to execute the cache scheduling operation of the DDR block storage area according to the empty / full status signal and the output status of each decoder. The cache scheduling operation includes at least one of out-of-order write operation and sequential read operation.

[0102] In detail, the modules in the multi-core decoding ordered scheduling system 400 based on DDR identifier cache described in this embodiment of the invention employ the same methods as described above. Figure 1 This method employs the same technical means as the multi-core decoding ordered scheduling method based on DDR identifier cache described in the previous section, and can produce the same technical effect, so it will not be elaborated here.

[0103] In one embodiment, a computer device is provided, which may be a server or a client, and its internal structure diagram may be as follows: Figure 8As shown, the computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile and / or volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used to communicate with external clients via a network connection. When the computer program is executed by the processor, it implements the functions or steps of a multi-core decoding ordered scheduling method based on DDR identifier cache on the server or client side.

[0104] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0105] The input scheduling module is used to allocate the data block to be decoded to the idle decoder through the multi-core decoding input scheduling module deployed at the decoder input end, and add a unique identifier ID to the data block to be decoded. Each decoder performs parallel decoding processing on the data block to be decoded based on the unique identifier ID to generate a decoding result corresponding to the unique identifier ID.

[0106] The storage management module is used to divide the DDR block storage area by a cache reordering module deployed at the output of the decoder, and to write the decoding results corresponding to each decoder into the sub-blocks corresponding to the DDR block storage area in random order. The DDR block storage area consists of multiple large blocks and multiple sub-blocks within each large block.

[0107] The status control module is used to identify the read-write pointer relationship within the cache reordering module. When all sub-blocks within any large block of the DDR block storage area have been written with the decoding result, the module generates an empty / full status signal for the DDR block storage area based on the read-write pointer relationship.

[0108] The scheduling execution module is used to perform cache scheduling operations on the DDR block storage area according to the empty / full status signal and the output status of each decoder. The cache scheduling operation includes at least one of out-of-order write operation and sequential read operation.

[0109] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0110] The input scheduling module is used to allocate the data block to be decoded to the idle decoder through the multi-core decoding input scheduling module deployed at the decoder input end, and add a unique identifier ID to the data block to be decoded. Each decoder performs parallel decoding processing on the data block to be decoded based on the unique identifier ID to generate a decoding result corresponding to the unique identifier ID.

[0111] The storage management module is used to divide the DDR block storage area by a cache reordering module deployed at the output of the decoder, and to write the decoding results corresponding to each decoder into the sub-blocks corresponding to the DDR block storage area in random order. The DDR block storage area consists of multiple large blocks and multiple sub-blocks within each large block.

[0112] The status control module is used to identify the read-write pointer relationship within the cache reordering module. When all sub-blocks within any large block of the DDR block storage area have been written with the decoding result, the module generates an empty / full status signal for the DDR block storage area based on the read-write pointer relationship.

[0113] The scheduling execution module is used to perform cache scheduling operations on the DDR block storage area according to the empty / full status signal and the output status of each decoder. The cache scheduling operation includes at least one of out-of-order write operation and sequential read operation.

[0114] It should be noted that the functions or steps that can be implemented by the computer-readable storage medium or computer device described above can be referred to the relevant descriptions on the server side and client side in the foregoing method embodiments. To avoid repetition, they will not be described one by one here.

[0115] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0116] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0117] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0118] Finally, it should be noted that in the above embodiments, each embodiment can be combined with each other or independent. Deleting any one of them will not affect the technical implementation of other embodiments. The above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A multi-core decoding ordered scheduling method based on DDR identifier cache, characterized in that, The method includes: By deploying a multi-core decoding input scheduling module at the decoder input end, the data block to be decoded is allocated to an idle decoder, and a unique identifier ID is added to the data block to be decoded. Each decoder performs parallel decoding processing on the data block to be decoded based on the unique identifier ID to generate a decoding result corresponding to the unique identifier ID. The DDR block storage area is divided by a cache reordering module deployed at the output of the decoder, and the decoding results corresponding to each decoder are written out of order into the sub-blocks corresponding to the DDR block storage area. The DDR block storage area consists of multiple large blocks and multiple sub-blocks within each large block. Identify the read-write pointer relationship within the cache reordering module. When all sub-blocks within any large block of the DDR block storage area have been written with decoding results, generate an empty / full status signal for the DDR block storage area based on the read-write pointer relationship. Based on the empty / full status signal and the output status of each decoder, the cache scheduling operation of the DDR block storage area is executed. The cache scheduling operation includes at least one of out-of-order write operation and sequential read operation.

2. The multi-core decoding ordered scheduling method based on DDR identifier cache as described in claim 1, characterized in that, By using a multi-core decoding input scheduling module deployed at the decoder input, a unique identifier ID is added to the data block to be decoded, including: After the data block to be decoded is sent to the input of the decoder through the corresponding interface, the current busy / idle status of each decoder is polled to obtain the polling detection result; Based on the polling detection results, the target channel number of the decoder to be assigned is determined; According to the pre-configured identifier mapping rules, the target channel number is bound to the logical sequence number of the data block to be decoded to generate a unique identifier ID for the data block to be decoded.

3. The multi-core decoding ordered scheduling method based on DDR identifier cache as described in claim 2, characterized in that, The current busy / idle status of each decoder is polled to obtain the polling results, including: Continuously loop through the busy / idle status registers corresponding to all decoders; Read the status signal of each decoder in sequence. A high level indicates that the decoder is in a busy state, and a low level indicates that the decoder is in an idle state. The state signals are combined in decoder number order to generate state vectors corresponding to all current decoders. Based on the state vector, the decoder number corresponding to the low level in the state signal is identified, and the decoder number corresponding to the low level is used as the polling detection result.

4. The multi-core decoding ordered scheduling method based on DDR identifier cache as described in claim 1, characterized in that, The DDR block storage area is divided by a cache reordering module deployed at the decoder output, including: The contiguous physical address space in the external DDR memory is divided into multiple logical blocks according to preset rules; Each logical block is further subdivided into multiple sub-blocks, the number of which is equal to the number of decoders. A unique starting address is pre-assigned to each sub-block, and a mapping relationship is established between the unique starting address and the decoding result ID of each decoder to complete the division of the DDR block storage area.

5. The multi-core decoding ordered scheduling method based on DDR identifier cache as described in claim 1, characterized in that, Identifying the read-write pointer relationship within the cache reordering module includes: Read the first and second values ​​of the write pointer and read pointer in the cache reordering module at the current position; When the first value is equal to the second value, the read / write pointer relationship is null. When the first value is not equal to the second value and the difference between the values ​​is less than the total number of large blocks, the read / write pointer relationship is full. When the first value is greater than the second value and the difference between the values ​​is greater than the total number of blocks, the read / write pointer relationship is a non-empty and non-full relationship.

6. The multi-core decoding ordered scheduling method based on DDR identifier cache as described in claim 1, characterized in that, Based on the empty / full status signal and the output status of each decoder, the cache scheduling operation of the DDR block memory area is performed, including: When the full signal in the empty / full state signal is invalid and the output state of at least one decoder is valid, the out-of-order write operation of the DDR block memory area is performed. When the empty signal in the empty / full state signal is invalid and the current decoder output state is valid, the sequential read operation of the DDR block storage area is performed.

7. The multi-core decoding ordered scheduling method based on DDR identifier cache as described in claim 6, characterized in that, When the empty signal in the empty / full state signal is invalid and the current decoder output state is valid, the sequential read operation of the DDR block memory area is performed, including: Determine the starting address of the large block to be read from the DDR block storage area; According to the sub-block numbering order in the DDR block storage area, the decoding result data corresponding to the starting address of the large block is read sequentially, and the decoding result data is output in the original input order.

8. The multi-core decoding ordered scheduling method based on DDR identifier cache as described in claim 1, characterized in that, The multi-core decoder input scheduling module is a dedicated hardware unit located between the system data input interface and the input end of the multi-core decoder array. It is used to dynamically allocate input data according to the busy / idle status of the decoder and to attach an identifier to the data to maintain sequential traceability. The module integrates a decoder status register group, a polling control state machine, an identifier generation and binding unit, and a multi-channel data distributor.

9. The multi-core decoding ordered scheduling method based on DDR identifier cache as described in claim 1, characterized in that, The cache reordering module is a dedicated hardware unit located between the output of the multi-core decoder array and the system data output interface. It is used to cache, sort, and output the out-of-order results generated by parallel decoding. The module integrates block address management logic, polling and control state machine, identifier matching and address translation unit, read and write pointer controller, and high-speed data path interface.

10. A multi-core decoding ordered scheduling system based on DDR identifier cache, characterized in that, The system is used to execute a multi-core decoding ordered scheduling method based on a DDR identifier cache as described in any one of claims 1-9, the system comprising: The input scheduling module is used to allocate the data block to be decoded to the idle decoder through the multi-core decoding input scheduling module deployed at the decoder input end, and add a unique identifier ID to the data block to be decoded. Each decoder performs parallel decoding processing on the data block to be decoded based on the unique identifier ID to generate a decoding result corresponding to the unique identifier ID. The storage management module is used to divide the DDR block storage area by a cache reordering module deployed at the output of the decoder, and to write the decoding results corresponding to each decoder into the sub-blocks corresponding to the DDR block storage area in random order. The DDR block storage area consists of multiple large blocks and multiple sub-blocks within each large block. The status control module is used to identify the read-write pointer relationship within the cache reordering module. When all sub-blocks within any large block of the DDR block storage area have been written with the decoding result, the module generates an empty / full status signal for the DDR block storage area based on the read-write pointer relationship. The scheduling execution module is used to perform cache scheduling operations on the DDR block storage area according to the empty / full status signal and the output status of each decoder. The cache scheduling operation includes at least one of out-of-order write operation and sequential read operation.

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