Turbo code rate matching method, device, equipment and medium

Abstract

The application relates to the technical field of wireless communication, and discloses a Turbo code rate matching method, device, equipment and medium, the method comprising the following steps: performing encoding processing on information bits, and respectively outputting a first check bit group and a second check bit group; respectively removing a first tail bit sequence and a second tail bit sequence from the first check bit group and the second check bit group, and obtaining a first check bit sequence and a second check bit sequence; performing staggered arrangement on the first check bit sequence and the second check bit sequence, and generating a check merging sequence; and performing puncturing on the check merging sequence according to a preset puncturing position, and outputting a check sequence after rate matching. The application improves decoding performance.

Description

Technical Field

[0001] This application relates to the field of wireless communication technology, and in particular to a Turbo code rate matching method, apparatus, device, and medium. Background Technology

[0002] The Turbo coding module specified in the low-Earth orbit satellite protocol flexibly adapts to different rate services. The puncturing position for rate matching calculation is related to the input bitstream length L1 and the puncturing length L2. When both are fixed, the puncturing position is the same for different data, and the tail bit position is always punctured. For high-rate burst signals, there are more punctured bits, resulting in relatively less check information obtained during decoding. Under ideal puncturing distribution, the error correction capability of iterative decoding is limited, leading to poor decoding performance. Summary of the Invention

[0003] Based on this, this application provides a Turbo code rate matching method, apparatus, device, and medium.

[0004] This application discloses a Turbo code rate matching method, which includes: The information bits are encoded to output a first parity bit group and a second parity bit group respectively. The first parity bit group includes a first parity bit sequence and a first tail bit sequence, and the second parity bit group includes a second parity bit sequence and a second tail bit sequence. The first tail bit sequence and the second tail bit sequence are removed from the first parity bit group and the second parity bit group, respectively, to obtain the first parity bit sequence and the second parity bit sequence; The first check bit sequence and the second check bit sequence are interleaved to generate a check merge sequence; The verification merge sequence is punched according to the preset punching position, and the rate-matched verification sequence is output.

[0005] Further, the step of interleaving the first check bit sequence and the second check bit sequence to generate a check merge sequence includes: The first and second parity bit sequences are interleaved at the bit level to generate a parity merge sequence, so that all bits in the first and second parity bit sequences form a staggered punch distribution at the same punch position.

[0006] Further, the step of interleaving the first parity bit sequence and the second parity bit sequence at the bit level to generate a parity merge sequence includes: The bits in the first check bit sequence and the bits in the second check bit sequence are interleaved according to their bit position correspondence to generate a check merge sequence.

[0007] Further, the step of interleaving the bits in the first check bit sequence with the bits in the second check bit sequence according to their bit position correspondence to generate a check merge sequence includes: The nth bit in the first check bit sequence and the nth bit in the second check bit sequence are arranged alternately in order to generate a check merge sequence; where n is a positive integer.

[0008] Furthermore, the check merge sequence is formed by cyclically alternating the nth bit of the first check bit sequence and the nth bit of the second check bit sequence.

[0009] Further, the encoding process of the information bits to output the first parity bit group and the second parity bit group respectively includes: The information bits are encoded in parallel, and the first and second parity bit groups are output respectively.

[0010] Furthermore, the parallel encoding process includes: The information bits are divided into two paths. One path is directly input to the first component encoder and outputs the first set of check bits. The other path is bit interleaved and then input to the second component encoder, outputting the second set of check bits.

[0011] Furthermore, the first component encoder is a first recursive system convolutional encoder, and the second component encoder is a second recursive system convolutional encoder.

[0012] Furthermore, the preset punching position is obtained in the following way: The punch index is calculated based on the burst length, and the punch position is determined based on the punch index.

[0013] Further, the step of calculating the punch index based on the burst length and determining the punch position based on the punch index includes: According to the punch index calculation method specified in the low-Earth orbit satellite protocol system, the punch index is calculated based on the burst length, and the punch position is determined based on the punch index.

[0014] Furthermore, the information bits are directly output as system bits.

[0015] This application also discloses a Turbo code rate matching device, which includes: The information encoding module is used to encode information bits and output a first parity bit group and a second parity bit group respectively. The first parity bit group includes a first parity bit sequence and a first tail bit sequence, and the second parity bit group includes a second parity bit sequence and a second tail bit sequence. The tail bit removal module is used to remove the first tail bit sequence and the second tail bit sequence from the first check bit group and the second check bit group respectively, to obtain the first check bit sequence and the second check bit sequence; The interleaving module is used to interleave the first parity bit sequence and the second parity bit sequence to generate a parity merge sequence; The rate matching module is used to punch holes in the verification merged sequence according to the preset punching position and output the rate-matched verification sequence.

[0016] This application also discloses an electronic device, including a memory and a processor, wherein the memory stores a computer program that, when executed by the processor, implements the method described above.

[0017] This application also discloses a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described above.

[0018] Due to the adoption of the above technical solution, this application has the following advantages: by optimizing the distribution of punch holes, the decoding performance is improved. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0020] Figure 1 This is a flowchart illustrating a Turbo code rate matching method according to an embodiment of this application. Figure 2 This is a schematic diagram of the Turbo encoding process according to an embodiment of this application; Figure 3 A schematic diagram of punching holes to match the existing rate; Figure 4 This is a schematic diagram of the optimized rate matching punching method according to an embodiment of this application; Figure 5 This is a schematic diagram of rate matching simulation comparison according to an embodiment of this application; Figure 6 This is a block diagram of a Turbo code rate matching device according to an embodiment of this application; Figure 7 This is a block diagram of an electronic device according to an embodiment of this application. Detailed Implementation

[0021] The present application will be further described in conjunction with the accompanying drawings and embodiments. The described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of the present application.

[0022] See Figure 1 This application provides an embodiment of a Turbo code rate matching method, which includes: Step 101: Encode the information bits and output the first parity bit group and the second parity bit group respectively.

[0023] The first parity bit group includes a first parity bit sequence and a first tail bit sequence, and the second parity bit group includes a second parity bit sequence and a second tail bit sequence.

[0024] In one embodiment of this application, the information bits are encoded to output a first check bit group and a second check bit group, respectively, including: The information bits are encoded in parallel, and the first and second parity bit groups are output respectively.

[0025] In one embodiment of this application, the parallel encoding process includes: The information bits are divided into two paths. One path is directly input to the first component encoder and outputs the first set of check bits. The other path is bit interleaved and then input to the second component encoder, outputting the second set of check bits.

[0026] In one embodiment of this application, the first component encoder is a first recursive system convolutional encoder, and the second component encoder is a second recursive system convolutional encoder.

[0027] In one embodiment of this application, the information bits are directly output as system bits.

[0028] In one possible implementation of the embodiments of this application, see [link to relevant documentation]. Figure 2 , Figure 3 and Figure 4 Information bits The output is split into two paths. One path is output directly to the multiplexer without any processing. The other path requires interleaving via line permutation before output. Both paths are encoded by two RSC (Recursive Systematic Convolutional Encoders) encoders (a first RSC encoder and a second RSC encoder), outputting two sets of parity bits (a first parity bit set and a second parity bit set). For example... This is the first parity bit group. This is the first parity bit sequence. This is the second tail bit sequence. This is the second parity bit group. This is the second parity bit sequence. This is the second tail bit sequence, where, This is the k-th parity bit in the first parity bit sequence. It is the 6th tail bit in the first tail bit sequence. For the second parity bit sequence One check bit, It is the 6th tail bit in the second tail bit sequence.

[0029] Step 102: Remove the first tail bit sequence and the second tail bit sequence from the first parity bit group and the second parity bit group respectively to obtain the first parity bit sequence and the second parity bit sequence.

[0030] Based on the aforementioned possible implementations, starting from the first parity bit group... Remove the first and last bit sequences Then, the first parity bit sequence is obtained. From the second parity bit group Remove the second tail bit sequence Then, the second parity bit sequence is obtained. .

[0031] Step 103: Interleave the first parity bit sequence and the second parity bit sequence to generate a parity merge sequence.

[0032] In one embodiment of this application, the first check bit sequence and the second check bit sequence are interleaved to generate a check merge sequence, including: The first and second parity bit sequences are interleaved at the bit level to generate a parity merge sequence, so that all bits in the first and second parity bit sequences form a staggered punch distribution at the same punch position.

[0033] In one embodiment of this application, the first check bit sequence and the second check bit sequence are interleaved at the bit level to generate a check merge sequence, including: The bits in the first parity bit sequence and the bits in the second parity bit sequence are interleaved according to their bit position correspondence to generate a parity merge sequence.

[0034] In one embodiment of this application, the bits in the first check bit sequence and the bits in the second check bit sequence are interleaved according to their bit position correspondence to generate a check merge sequence, including: The nth bit in the first parity bit sequence and the nth bit in the second parity bit sequence are arranged alternately in order to generate a parity merge sequence; where n is a positive integer.

[0035] In one embodiment of this application, the check merge sequence is formed by cyclically alternating the nth bit of the first check bit sequence and the nth bit of the second check bit sequence.

[0036] Based on the aforementioned possible implementation methods, see Figure 4 The two sets of parity bit sequences (the first parity bit sequence and the second parity bit sequence) are interleaved to obtain the parity merged sequence. This interleaving ensures that the subsequent puncture positions of the bits in the two parity bit sequences do not overlap. The expression for the parity merged sequence is:

[0037] in, To verify the merged sequence.

[0038] Step 104: Punch holes in the verification merge sequence according to the preset punching positions, and output the verification sequence after rate matching.

[0039] In one embodiment of this application, the preset drilling position is obtained in the following way: The punch index is calculated based on the burst length, and the punch position is determined based on the punch index.

[0040] In one embodiment of this application, calculating the punch index based on the burst length and determining the punch position based on the punch index includes: According to the punch index calculation method stipulated in the low-Earth orbit satellite protocol system, the punch index is calculated based on the burst length, and the punch position is determined based on the punch index.

[0041] To ensure compatibility with different burst channels, this application proposes an optimized Turbo rate-matched puncturing method without altering the Turbo coding mode. The calculation method for the puncturing index position remains unchanged, still determined by the input bitstream length L1 and the puncturing length L2. However, the bitstream arrangement is modified so that the puncturing positions of the parity bits output by the two encoders are staggered, providing a degree of complementarity and ensuring that at least one valid parity observation exists at any given time. This increases the reliability information during decoding. Furthermore, the tail bit does not need to participate in rate matching during transmission, essentially performing direct puncturing, which further increases the reliability information during decoding, solves the fixed-bit decoding error problem, and improves decoding performance.

[0042] This application optimizes and processes the puncture distribution of Turbo codes. While maintaining the puncture index calculation method, it redesigns the puncture positions and changes the rules. By altering the order of the rate-matching input bits, the puncture positions of the two sets of parity bits are no longer identical, such as... Figure 4 As shown, the punched bits of the two sets of parity bits are staggered, which indirectly realizes the change of punch position, so that more parity information can be obtained during decoding. Compared with the output of the existing rate matching module, the effective parity observations are greatly increased, avoiding local parity holes. This optimization method has little change to the protocol system and improves the decoding performance of high code rate bursts without increasing complexity.

[0043] Compared to existing Turbo rate matching methods, this application retains more verification information, achieving superior performance without increasing complexity. It effectively improves the anti-interference capability of burst channels, has strong applicability, and enhances the decoding performance of high-rate bursts. It can be used in communication scenarios employing Turbo encoding and decoding. For the same high-rate burst signal, under the same simulation conditions, when the packet error rate reaches 1 / 10,000, the performance can be improved by 3.6dB. Figure 5 As shown. According to Figure 5 The simulation results shown demonstrate that this application can effectively improve the demodulation performance of specific high-bit-rate burst signals from low-Earth orbit satellites. Figure 5 In this context, Eb / N0 represents the signal-to-noise ratio, Eb is the average power per bit of signal, and N0 is the average power of noise.

[0044] Based on the above embodiments, the check sequence after rate matching is added after the information bits, and the resulting sequence is the output of the Turbo encoding module.

[0045] See Figure 6 This application also provides a Turbo code rate matching device, which includes: The information encoding module is used to encode information bits and output a first parity bit group and a second parity bit group respectively. The first parity bit group includes a first parity bit sequence and a first tail bit sequence, and the second parity bit group includes a second parity bit sequence and a second tail bit sequence. The tail bit removal module is used to remove the first tail bit sequence and the second tail bit sequence from the first parity bit group and the second parity bit group respectively to obtain the first parity bit sequence and the second parity bit sequence. The interleaving module is used to interleave the first parity bit sequence and the second parity bit sequence to generate a parity merge sequence; The rate matching module is used to punch holes in the verification merge sequence according to the preset punching position and output the rate-matched verification sequence.

[0046] See Figure 7 This application also provides an electronic device including a memory and a processor. The memory stores a computer program, which, when executed by the processor, implements the methods described in the above embodiments. As an example, the electronic device may include multiple processors. A processor may refer to one or more devices, circuits, and / or computing units for processing data (e.g., computer programs). The processor can invoke the computer program stored in the memory to implement the methods described in the above embodiments. Figure 7 Taking an electronic device consisting of one processor and one memory as an example, the processor and memory are used to indicate a type of device or equipment, and the quantity of each type of device or equipment can be determined according to business needs.

[0047] This application also provides a computer-readable storage medium storing a computer program or instructions that, when executed on a computer, cause the computer to perform the methods described in the above-described method embodiments.

[0048] It should be noted that, in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0049] Those skilled in the art should clearly understand that, for the sake of convenience and brevity, the specific working processes of the Turbo code rate matching system, electronic device, and computer-readable storage medium described in the above embodiments can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0050] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware, or by a program instructing the relevant hardware to implement them. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0051] The above are merely optional embodiments of this application, used only to illustrate the technical solution of this application and not to limit it. Any modifications, equivalent substitutions, improvements, etc., to the specific implementation of this application without departing from the spirit and scope of this application should be covered within the protection scope of this application.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and not to limit them. Although this application has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of this application. Any modifications or equivalent substitutions that do not depart from the spirit and scope of this application should be covered within the protection scope of the claims of this application.

Claims

1. A Turbo code rate matching method, characterized in that, include: The information bits are encoded to output a first parity bit group and a second parity bit group respectively. The first parity bit group includes a first parity bit sequence and a first tail bit sequence, and the second parity bit group includes a second parity bit sequence and a second tail bit sequence. The first tail bit sequence and the second tail bit sequence are removed from the first parity bit group and the second parity bit group, respectively, to obtain the first parity bit sequence and the second parity bit sequence; The first check bit sequence and the second check bit sequence are interleaved to generate a check merge sequence; The verification merge sequence is punched according to the preset punching position, and the rate-matched verification sequence is output.

2. The method according to claim 1, characterized in that, The step of interleaving the first check bit sequence and the second check bit sequence to generate a check merge sequence includes: The first and second parity bit sequences are interleaved at the bit level to generate a parity merge sequence, so that all bits in the first and second parity bit sequences form a staggered punch distribution at the same punch position.

3. The method according to claim 2, characterized in that, The step of interleaving the first check bit sequence and the second check bit sequence at the bit level to generate a check merge sequence includes: The bits in the first check bit sequence and the bits in the second check bit sequence are interleaved according to their bit position correspondence to generate a check merge sequence.

4. The method according to claim 3, characterized in that, The step of interleaving the bits in the first check bit sequence with the bits in the second check bit sequence according to their bit position correspondence to generate a check merge sequence includes: The nth bit in the first check bit sequence and the nth bit in the second check bit sequence are arranged alternately in order to generate a check merge sequence; where n is a positive integer.

5. The method according to claim 4, characterized in that, The check merge sequence is formed by cyclically alternating the nth bit of the first check bit sequence and the nth bit of the second check bit sequence.

6. The method according to claim 1, characterized in that, The encoding process of the information bits, which outputs the first parity bit group and the second parity bit group respectively, includes: The information bits are encoded in parallel, and the first and second parity bit groups are output respectively.

7. The method according to claim 6, characterized in that, The parallel encoding process includes: The information bits are divided into two paths. One path is directly input to the first component encoder and outputs the first set of check bits. The other path is bit interleaved and then input to the second component encoder, outputting the second set of check bits.

8. The method according to claim 7, characterized in that, The first component encoder is a first recursive system convolutional encoder, and the second component encoder is a second recursive system convolutional encoder.

9. The method according to any one of claims 1-8, characterized in that, The preset drilling position is obtained in the following way: The punch index is calculated based on the burst length, and the punch position is determined based on the punch index.

10. The method according to claim 9, characterized in that, The step of calculating the punch index based on the burst length and determining the punch position based on the punch index includes: According to the punch index calculation method specified in the low-Earth orbit satellite protocol system, the punch index is calculated based on the burst length, and the punch position is determined based on the punch index.

11. The method according to any one of claims 1-8, characterized in that, The information bits are directly output as system bits.

12. A Turbo code rate matching device, characterized in that, include: The information encoding module is used to encode information bits and output a first parity bit group and a second parity bit group respectively. The first parity bit group includes a first parity bit sequence and a first tail bit sequence, and the second parity bit group includes a second parity bit sequence and a second tail bit sequence. The tail bit removal module is used to remove the first tail bit sequence and the second tail bit sequence from the first parity bit group and the second parity bit group respectively, to obtain the first parity bit sequence and the second parity bit sequence; The interleaving module is used to interleave the first parity bit sequence and the second parity bit sequence to generate a parity merge sequence; The rate matching module is used to punch holes in the verification merged sequence according to the preset punching position and output the rate-matched verification sequence.

13. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1-11.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1-11.

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