Frequency hopping control circuit, chip and electronic device

Abstract

The present disclosure relates to a frequency hopping control circuit, a chip and an electronic device. The frequency hopping control circuit comprises: a phase calibration circuit, which is electrically connected with a phase-locked loop circuit; and a logic control circuit, which is electrically connected with the phase calibration circuit and the phase-locked loop circuit. The logic control circuit is configured to control the phase calibration circuit to control an initial phase difference between a first clock signal output by the phase-locked loop circuit and a reference clock signal in a base station switching process, the first clock signal being obtained by frequency division of a second clock signal whose frequency is calibrated by the phase-locked loop circuit, and the reference clock signal being generated by a crystal oscillator circuit. In the present disclosure, the time for the initial phase difference to reach a target phase difference is avoided from being too long, the frequency hopping time is shortened, the noise performance of the phase-locked loop circuit is avoided from being degraded, and the power consumption of the frequency hopping control process is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and in particular to a frequency hopping control circuit, chip, and electronic device. Background Technology

[0002] Frequency hopping is required when electronic devices switch base stations. With the development of cellular communication technology, higher demands are placed on the speed of frequency hopping. Current methods for shortening frequency hopping time result in a significant deterioration in the noise performance of the phase-locked loop circuit and an increase in power consumption during the frequency hopping control process. Summary of the Invention

[0003] To overcome the problems existing in related technologies, this disclosure provides a frequency hopping control circuit, chip, and electronic device.

[0004] According to a first aspect of the present disclosure, a frequency hopping control circuit is provided, the frequency hopping control circuit comprising: A phase calibration circuit, wherein the phase calibration circuit is electrically connected to a phase-locked loop circuit; A logic control circuit is electrically connected to the phase calibration circuit and is also electrically connected to the phase-locked loop circuit. The logic control circuit is used to control the phase calibration circuit during base station handover so that the phase calibration circuit controls the initial phase difference between the first clock signal output by the phase-locked loop circuit and the reference clock signal. The first clock signal is obtained by dividing the frequency of the second clock signal output by the phase-locked loop circuit after frequency calibration. The reference clock signal is generated by a crystal oscillator circuit.

[0005] In this embodiment, the initial phase difference is controllable, which avoids the random generation of an excessively large initial phase difference, resulting in an excessively long time to calibrate the phase difference between the first clock signal and the reference clock signal to the target phase difference. This shortens the frequency hopping time, and at the same time, it does not require reducing the calibration accuracy or using analog circuits, thus avoiding the degradation of the noise performance of the phase-locked loop circuit and the increase in power consumption during the frequency hopping control process.

[0006] In some exemplary embodiments of this disclosure, the phase calibration circuit includes: A phase difference control circuit, wherein the input terminal of the phase difference control circuit is electrically connected to the logic control circuit, and the output terminal of the phase difference control circuit is used to be electrically connected to the phase-locked loop circuit; The logic control circuit controls the phase difference control circuit through a first control signal to control the initial phase difference.

[0007] In this embodiment, the phase difference control circuit can control the initial phase difference according to the first control signal, and can even control the initial phase difference to the target phase difference, which greatly shortens the frequency hopping time and improves the user's communication experience.

[0008] In some exemplary embodiments of this disclosure, the first control signal includes an input synchronization signal, an input clock signal, and a first enable signal, wherein the input clock signal and the reference clock signal are differential signals to each other; The phase difference control circuit includes: An enable signal generation circuit is provided, wherein the input terminal of the enable signal generation circuit is electrically connected to the logic control circuit, and the output terminal of the enable signal generation circuit is electrically connected to the phase-locked loop (PLL) circuit. When the first enable signal is enabled, the enable signal generation circuit generates a second enable signal and a third enable signal based on the input synchronization signal and the input clock signal, and outputs the second enable signal and the third enable signal to the PLL circuit. The second enable signal enables the frequency and phase detector of the PLL circuit, and the third enable signal enables the frequency divider of the PLL circuit. The frequency divider divides the second clock signal to obtain the first clock signal.

[0009] In this embodiment, based on the input synchronization signal, input clock signal and first enable signal output by the logic control circuit, the enable signal generation circuit can generate a corresponding enable signal to control the timing sequence of the frequency divider enable and the frequency and phase detector enable, thereby controlling the initial phase difference. This shortens the frequency hopping time while avoiding the degradation of noise performance of the phase-locked loop circuit and the increase in power consumption during the frequency hopping control process.

[0010] In some exemplary embodiments of this disclosure, when the frequency divider is enabled, the frequency divider outputs the first clock signal; When the frequency and phase detector is enabled, the frequency and phase detector receives the first clock signal and the reference clock signal; The logic control circuit is used to control the time from when the frequency divider is enabled until the first trigger edge of the first clock signal reaches the frequency detector and phase detector, and to control the timing sequence of the frequency divider enabling and the frequency detector enabling through the enable signal generation circuit, so as to control the initial phase difference.

[0011] In this embodiment, the logic control circuit and the enable signal generation circuit together realize the control of the initial phase difference. By controlling the initial phase difference to the target phase difference, the frequency hopping time can be greatly shortened.

[0012] In some exemplary embodiments of this disclosure, the enable signal generation circuit includes: A steady-state control circuit, wherein the input terminal of the steady-state control circuit is electrically connected to the logic control circuit, and the steady-state control circuit is used to delay the input synchronization signal when the first enable signal enables it and is triggered by the input clock signal. A first signal generation circuit has a first input terminal electrically connected to the output terminal of the steady-state control circuit, a second input terminal of the first signal generation circuit receiving the input clock signal, a control terminal of the first signal generation circuit receiving the first enable signal, and an output terminal of the first signal generation circuit electrically connected to the first input terminal of the phase-locked loop circuit. The first signal generation circuit is used to generate a second enable signal based on the input clock signal and the delayed input synchronization signal when the first enable signal is enabled. The second signal generation circuit has a first input terminal electrically connected to the output terminal of the steady-state control circuit, a second input terminal receiving the input clock signal, a control terminal receiving the first enable signal, and an output terminal electrically connected to the second input terminal of the phase-locked loop circuit. The second signal generation circuit is used to generate the third enable signal based on the input clock signal and the delayed input synchronization signal when the first enable signal is enabled.

[0013] In this embodiment, the quality of the second and third enable signals is improved by the steady-state control circuit, thereby improving the stability of the circuit. The second and third enable signals are generated by the first and second signal generation circuits, respectively, which can conveniently control the relative timing of the two enable signals and improve the flexibility of control.

[0014] In some exemplary embodiments of this disclosure, the steady-state control circuit includes: Multiple first flip-flops are connected in series, with their data input and data output terminals connected together. The data input terminal of the first first flip-flop receives the input synchronization signal. The data output terminal of the last first flip-flop is electrically connected to both the first input terminal of the first signal generation circuit and the first input terminal of the second signal generation circuit. The clock input terminal of each first flip-flop receives the input clock signal, and the enable terminal of each first flip-flop receives the first enable signal.

[0015] In this embodiment, a steady-state control circuit is composed of multiple first flip-flops, which can remove unstable parts in the input synchronization signal and improve the stability of the signals entering the first input terminal of the first signal generation circuit and the first input terminal of the second signal generation circuit.

[0016] In some exemplary embodiments of this disclosure, the number of the first triggers is greater than or equal to 3.

[0017] In this embodiment, the unstable part of the input synchronization signal can be removed to prevent the steady-state control circuit from becoming metastable.

[0018] In some exemplary embodiments of this disclosure, the first signal generating circuit includes: Multiple second flip-flops are connected in series, with their data input and data output terminals connected together. The data input terminal of the first second flip-flop is electrically connected to the output terminal of the steady-state control circuit, and the data output terminal of the last second flip-flop is electrically connected to the first input terminal of the phase-locked loop circuit. The clock input terminal of each second flip-flop receives the input clock signal, and the enable terminal of each second flip-flop receives the first enable signal.

[0019] In this embodiment, a first signal generation circuit is composed of multiple second flip-flops, which improves the stability of the generated second enable signal.

[0020] In some exemplary embodiments of this disclosure, the second signal generating circuit includes: An inverter, the input of which receives the input clock signal; Multiple third flip-flops are connected in series, with their data input and data output terminals connected together. The data input terminal of the first third flip-flop is electrically connected to the output terminal of the steady-state control circuit, and the data output terminal of the last third flip-flop is electrically connected to the second input terminal of the phase-locked loop circuit. The clock input terminal of each third flip-flop is electrically connected to the output terminal of the inverter, and the enable terminal of each third flip-flop receives the first enable signal.

[0021] In this embodiment, the stability of the third enable signal is improved, and a third enable signal that is half a clock cycle earlier than the second enable signal can be generated. This allows control over the timing sequence and time interval between the frequency divider enable and the frequency and phase detector enable, thereby controlling the initial phase difference.

[0022] In some exemplary embodiments of this disclosure, the logic control circuit is further configured to control the phase calibration circuit after the initial phase difference reaches the target phase difference, so that the phase calibration circuit switches the charging current of the capacitor of the loop filter in the phase-locked loop circuit to the target current.

[0023] In this embodiment, the charging time of the capacitor in the loop filter after the initial phase difference reaches the target phase difference can be shortened by controlling the charging current of the capacitor in the loop filter, thereby shortening the frequency hopping time.

[0024] In some exemplary embodiments of this disclosure, the phase calibration circuit includes: A current switching circuit is provided, wherein a first terminal of the current switching circuit is electrically connected to the first terminals of multiple pull-up current sources of the charge pump of the phase-locked loop circuit, a second terminal of the current switching circuit is electrically connected to the first terminal of the pull-down current source of the charge pump, and a third terminal of the current switching circuit is electrically connected to the capacitor of the loop filter. The current switching circuit is used to connect at least one of the multiple pull-up current sources and the pull-down current sources to the capacitor of the loop filter to charge or discharge the capacitor of the loop filter. The second end of each of the pull-up current sources is electrically connected to the power supply, and the second end of each pull-down current source is electrically connected to the ground.

[0025] In this embodiment, the charging current of the capacitor in the loop filter can be switched to the target current by changing the current source of the capacitor electrically connected to the loop filter, resulting in a simple circuit structure.

[0026] In some exemplary embodiments of this disclosure, the plurality of pull-up current sources include a first current source, a second current source, and a third current source, and the pull-down current source includes a fourth current source; The current switching circuit includes: A first switching unit, wherein a first terminal of the first switching unit is electrically connected to a first terminal of the first current source, and a control terminal of the first switching unit is electrically connected to the logic control circuit; The second switching unit has a first terminal for electrical connection to the first terminal of the second current source, and a control terminal for electrical connection to the logic control circuit. The third switching unit has a first terminal for electrical connection to the first terminal of the third current source, and a control terminal for electrical connection to the logic control circuit. The fourth switching unit has a first terminal electrically connected to the second terminals of the first switching unit, the second switching unit, and the third switching unit, and is used to be electrically connected to the capacitor of the loop filter. The second terminal of the fourth switching unit is used to be electrically connected to the first terminal of the fourth current source. The control terminal of the fourth switching unit is electrically connected to the logic control circuit. The second end of the first current source, the second end of the second current source, and the second end of the third current source are all electrically connected to the power supply, and the second end of the fourth current source is electrically connected to the grounding terminal. The logic control circuit is used to switch the charging current to the target current by controlling the first switching unit, the third switching unit and the fourth switching unit to be disconnected, and controlling the second switching unit to be turned on.

[0027] In this embodiment, the current source of the capacitor electrically connected to the loop filter is changed by the switching unit, resulting in low device cost and low power consumption.

[0028] In some exemplary embodiments of this disclosure, the logic control circuit is further configured to calibrate the frequency of the second clock signal according to the target frequency in the handover command generated during the base station handover process.

[0029] In this embodiment, the frequency-calibrated second clock signal can meet the communication requirements of electronic devices when switching to a base station.

[0030] In some exemplary embodiments of this disclosure, the logic control circuit calibrates the frequency of the second clock signal by executing a successive approximation algorithm.

[0031] In this embodiment, the time for calibrating the frequency of the second clock signal according to the target frequency is a component of the frequency hopping time. The frequency of the second clock signal is calibrated by the successive approximation algorithm. Compared with the calibration by the binary method, the counting period time is shorter, thus shortening the frequency hopping time.

[0032] In some exemplary embodiments of this disclosure, the logic control circuit is further configured to look up the bandwidth parameter of the phase-locked loop circuit and the amplitude parameter of the voltage-controlled oscillator of the phase-locked loop circuit corresponding to the target frequency in a pre-stored parameter table, and use the found bandwidth parameter and amplitude parameter to set the phase-locked loop circuit.

[0033] In this embodiment, the bandwidth and amplitude parameters are determined by looking up a table, which saves the time of calibrating the bandwidth and amplitude parameters to the values ​​corresponding to the target frequency, thereby shortening the frequency hopping time.

[0034] According to a second aspect of the present disclosure, a frequency hopping control chip is provided, the frequency hopping control chip including the frequency hopping control circuit as described in the first aspect of the present disclosure.

[0035] According to a third aspect of the present disclosure, a phase-locked loop (PLL) chip is provided, the PLL chip including a PLL circuit and a frequency hopping control circuit as described in the first aspect of the present disclosure.

[0036] According to a fourth aspect of the present disclosure, a baseband chip is provided, the baseband chip including a frequency hopping control chip as described in the second aspect of the present disclosure, or a phase-locked loop chip as described in the third aspect of the present disclosure.

[0037] According to a fifth aspect of the present disclosure, a system-on-a-chip (SoC) is provided, the SoC including a baseband chip as described in the fourth aspect of the present disclosure.

[0038] According to a sixth aspect of the present disclosure, an electronic device is provided, the electronic device including a baseband chip as described in the fourth aspect of the present disclosure, or a system-on-a-chip as described in the fifth aspect of the present disclosure.

[0039] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects: This disclosure avoids the time required for the initial phase difference to reach the target phase difference to be too long, shortens the frequency hopping time, avoids the degradation of the noise performance of the phase-locked loop circuit, and reduces the power consumption of the frequency hopping control process.

[0040] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0041] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0042] Figure 1 This is a schematic diagram of a frequency hopping control circuit according to an exemplary embodiment.

[0043] Figure 2 This is a schematic diagram of a frequency hopping control circuit according to another exemplary embodiment.

[0044] Figure 3 This is a schematic diagram of a frequency hopping control circuit according to another exemplary embodiment.

[0045] Figure 4 This is a schematic diagram of a frequency hopping control circuit according to another exemplary embodiment.

[0046] Figure 5 This is a schematic diagram of a frequency hopping control circuit according to another exemplary embodiment.

[0047] Figure 6 This is a schematic diagram of a frequency hopping control circuit according to another exemplary embodiment.

[0048] Figure 7 This is a schematic diagram of a frequency hopping control circuit according to another exemplary embodiment.

[0049] Figure 8This is a schematic diagram of a frequency hopping control circuit according to another exemplary embodiment.

[0050] Figure 9 This is a schematic diagram of a frequency hopping control circuit according to another exemplary embodiment.

[0051] Figure 10 This is a schematic diagram of a frequency hopping control circuit according to another exemplary embodiment.

[0052] Figure 11 This is a timing diagram illustrating the operation of an enable signal generation circuit according to an exemplary embodiment.

[0053] Figure 12 This is a diagram illustrating the radio frequency communication link architecture of an electronic device according to an exemplary embodiment.

[0054] Figure 13 This is a block diagram of an electronic device according to an exemplary embodiment.

[0055] In the picture: 1-Phase calibration circuit; 2-Logic control circuit; 3-Phase-locked loop circuit; 4-Crystal oscillator circuit; 11-Phase difference control circuit; 12-Enable signal generation circuit; 13-Steady-state control circuit; 14-First signal generation circuit; 15-Second signal generation circuit; 16-Current switching circuit; 31-Charge pump; 32-Loop filter; 33-Frequency and phase detector; 34-Frequency divider; 35-Voltage-controlled oscillator; C-Loop filter capacitor; CLK1-Input clock signal; CLK2-Reference clock signal; CLK3-First clock signal; CTRL1-First control signal; CS1-First current source; CS2-Second current source; CS3-Third current source; CS4-Fourth current source; DFF1-First flip-flop; DFF2-Second flip-flop DFF3 - Third trigger; EN1 - First enable signal; EN2 - Second enable signal; EN3 - Third enable signal; GND - Ground; INV - Inverter; PUCS - Pull-up current source; PDCS - Pull-down current source; R - Resistor of loop filter; SW1 - First switching unit; SW2 - Second switching unit; SW3 - Third switching unit; SW4 - Fourth switching unit; SYNC - Input synchronization signal; VDD - Power supply; 1300 - Electronic equipment; 1302 - Processing component; 1304 - Memory; 1306 - Power supply component; 1308 - Multimedia component; 1310 - Audio component; 1312 - Input / output interface; 1314 - Sensor component; 1316 - Communication component; 1320 - Processor. Detailed Implementation

[0056] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0057] During the switching of electronic devices to a new base station, the frequency of the clock signal output by its phase-locked loop (PLL) circuit needs to be changed to match the center frequency of the new base station. This process of changing the clock signal frequency is called frequency hopping. With the development of cellular communication technology, higher demands are placed on the speed of frequency hopping to maintain continuous and effective data transmission and improve communication stability during base station switching. Currently, methods using analog circuits to shorten the frequency hopping time by reducing calibration accuracy or increasing the bandwidth of the PLL circuit require a large gain in the voltage-controlled oscillator (VCO) within the PLL circuit to compensate for the frequency error caused by reduced calibration accuracy. This leads to a significant deterioration in the noise performance of the PLL circuit, increased power consumption during the frequency hopping control process, and increasing the bandwidth of the PLL circuit only slightly shortens the frequency hopping time.

[0058] To address the aforementioned issues, this disclosure provides a frequency hopping control circuit that uses a logic control circuit to control the phase calibration circuit. This controls the initial phase difference between the first clock signal output by the phase-locked loop circuit and the reference clock signal, avoiding the generation of an excessively large initial phase difference, which would cause the time required to calibrate the phase difference between the first clock signal and the reference clock signal to the target phase difference to be too long. This shortens the frequency hopping time, while also eliminating the need to reduce calibration accuracy or use analog circuits. This avoids the degradation of the noise performance of the phase-locked loop circuit and the increase in power consumption during the frequency hopping control process.

[0059] In some exemplary embodiments, a frequency hopping control circuit is provided. For example... Figure 1 As shown, the frequency hopping control circuit includes a phase calibration circuit 1 and a logic control circuit 2. The phase calibration circuit 1 is electrically connected to the phase-locked loop (PLL) circuit 3. The logic control circuit 2 is electrically connected to the phase calibration circuit 1 and also to the PLL circuit 3. During base station handover, the logic control circuit 2 controls the phase calibration circuit 1 to control the initial phase difference between the first clock signal output by the PLL circuit 3 and the reference clock signal. The first clock signal is obtained by dividing the frequency-calibrated second clock signal output by the PLL circuit 3. The reference clock signal is generated by a crystal oscillator circuit.

[0060] The crystal oscillator circuit utilizes the piezoelectric effect of quartz crystals to generate a stable and highly accurate clock signal, which serves as a reference clock signal for the phase-locked loop (PLL) circuit 3. The PLL circuit 3, based on the frequency and phase of the reference clock signal, generates a second clock signal of the required frequency through negative feedback control, used in the transmission and reception of radio frequency signals in cellular communication. During the handover process between the electronic device and the base station, the frequency of the second clock signal needs to be changed to a target frequency corresponding to the center frequency of the new base station, so that the electronic device can communicate under the new base station. For example, the target frequency may be the same as the center frequency of the new base station.

[0061] In some examples, the logic control circuit 2 can be composed of digital circuit units, capable of generating output control signals according to preset rules based on the input signals. During base station handover, the logic control circuit 2 can receive handover commands, which may include a target frequency. The logic control circuit 2 can control the capacitors in the capacitor array of the voltage-controlled oscillator in the phase-locked loop circuit 3 to turn on or off according to the target frequency, thereby changing the total capacitance value of the capacitor array and calibrating the frequency of the second clock signal output by the voltage-controlled oscillator to the target frequency.

[0062] After obtaining the frequency-calibrated second clock signal, the phase-locked loop (PLL) circuit 3 needs to calibrate the phase relationship between the second clock signal and the reference clock signal to meet the phase-locking condition before locking the state. The frequency of the second clock signal is usually much higher than the frequency of the reference clock signal. The PLL circuit 3 first uses its frequency divider to divide the second clock signal to obtain a first clock signal with a frequency matching the reference clock signal. Then, it uses its frequency and phase detector to compare the phase difference between the first clock signal and the reference clock signal, and then uses a negative feedback mechanism to calibrate the phase difference to the target phase difference so that the phase relationship between the second clock signal and the reference clock signal meets the phase-locking condition. The time required to calibrate the phase difference to the target phase difference is a component of the frequency hopping time. If the frequency of the second clock signal is an integer multiple of the frequency of the reference clock signal, the target phase difference can be 0. If the frequency of the second clock signal is not an integer multiple of the frequency of the reference clock signal, the target phase difference can be 8° to 10°, such as 8°, 9°, 10°, etc.

[0063] Phase-locked loop circuit 3 uses its phase-frequency detector to compare the initial moment of the phase difference between the first clock signal and the reference clock signal. This initial phase difference is the phase difference between the first clock signal and the reference clock signal. If the magnitude of the initial phase difference is not controlled, it will be a random value. If this random value is large, for example, close to one clock cycle, it will take a long time to calibrate the phase difference between the first clock signal and the reference clock signal to the target phase difference, resulting in an excessively long frequency hopping time. To shorten the frequency hopping time, logic control circuit 2 can control phase calibration circuit 1 to control the initial phase difference. For example, it can directly control the initial phase difference to the target phase difference, thereby reducing the time to calibrate the phase difference between the first clock signal and the reference clock signal to the target phase difference to 0, greatly shortening the frequency hopping time.

[0064] Phase calibration circuit 1 can be a circuit composed of digital circuit units. Through the control of logic control circuit 2, phase calibration circuit 1 can control the timing sequence of enabling the frequency divider and the phase-frequency detector. Logic control circuit 2 can also control the time from the frequency divider's enable to the arrival of the first trigger edge of the first clock signal at the phase-frequency detector, thereby achieving control of the initial phase difference. The trigger edge can be, for example, a rising edge.

[0065] In this embodiment, the initial phase difference is controllable, which avoids the random generation of an excessively large initial phase difference, resulting in an excessively long time to calibrate the phase difference between the first clock signal and the reference clock signal to the target phase difference. This shortens the frequency hopping time, and at the same time, it does not require reducing the calibration accuracy or using analog circuits, thus avoiding the degradation of the noise performance of the phase-locked loop circuit and the increase in power consumption during the frequency hopping control process.

[0066] In some embodiments, such as Figure 2 As shown, the phase calibration circuit 1 includes a phase difference control circuit 11. The input terminal of the phase difference control circuit 11 is electrically connected to the logic control circuit 2, and the output terminal of the phase difference control circuit 11 is electrically connected to the phase-locked loop circuit 3. The logic control circuit 2 controls the phase difference control circuit 11 through a first control signal CTRL1 to control the initial phase difference.

[0067] In some examples, the phase difference control circuit 11 can be a circuit composed of digital circuit units. The input terminal of the phase difference control circuit 11 receives the first control signal CTRL1, and can generate a corresponding control signal based on the first control signal CTRL1. The control signal controls the timing sequence of enabling the frequency divider and enabling the frequency and phase detector. The logic control circuit 2 can also control the time from the frequency divider being enabled to the arrival of the first trigger edge of the first clock signal at the frequency and phase detector, thereby realizing the control of the initial phase difference.

[0068] In this embodiment, the phase difference control circuit can control the initial phase difference according to the first control signal, and can even control the initial phase difference to the target phase difference, which greatly shortens the frequency hopping time and improves the user's communication experience.

[0069] In some embodiments, such as Figure 3 As shown, the first control signal CTRL1 includes an input synchronization signal SYNC, an input clock signal CLK1, and a first enable signal EN1. The input clock signal CLK1 and the reference clock signal are differential signals. The phase difference control circuit 11 includes an enable signal generation circuit 12. The input terminal of the enable signal generation circuit 12 is electrically connected to the logic control circuit 2, and the output terminal of the enable signal generation circuit 12 is electrically connected to the phase-locked loop circuit 3. When the first enable signal EN1 is enabled, the enable signal generation circuit 12 generates a second enable signal EN2 and a third enable signal EN3 based on the input synchronization signal SYNC and the input clock signal CLK1, and outputs the second enable signal EN2 and the third enable signal EN3 to the phase-locked loop circuit 3. The second enable signal EN2 enables the frequency and phase detector of the phase-locked loop circuit 3, and the third enable signal EN3 enables the frequency divider of the phase-locked loop circuit 3. The frequency divider is used to divide the second clock signal to obtain the first clock signal.

[0070] In some examples, the enable signal generation circuit 12 can be enabled when the first enable signal EN1 is at a first level. After the enable signal generation circuit 12 is enabled, the first enable signal EN2 can change to a second level. The first level can be higher than the second level.

[0071] In some examples, when the enable signal generation circuit 12 is enabled, the input synchronization signal SYNC can change from a third level to a fourth level. The enable signal generation circuit 12 generates a second enable signal EN2 and a third enable signal EN3 based on the input synchronization signal SYNC at the fourth level. The fourth level can be higher than the third level.

[0072] In some examples, both the input clock signal CLK1 and the reference clock signal are generated by a crystal oscillator circuit and are differential signals. The input clock signal CLK1 is input to the enable signal generation circuit 12 via the logic control circuit 2, and the reference clock signal is input to the frequency and phase detector of the phase-locked loop circuit 3. The frequency and phase detector compares the phase difference between the first clock signal and the reference clock signal. In other examples, the signal generated by the crystal oscillator circuit is a differential signal, which can be provided to the logic control circuit 2. The logic control circuit 2 leaves the non-inverting input of the differential signal floating and inputs the inverting input to the enable signal generation circuit 12 as the input clock signal CLK1. The crystal oscillator circuit can input both the non-inverting and inverting inputs of the differential signal to the frequency and phase detector. The frequency and phase detector processes the differential signal to generate a single-ended reference clock signal, and then compares the phase difference between the first clock signal and the reference clock signal.

[0073] In some examples, the enable signal generation circuit 12 can be a circuit composed of digital circuit units. The enable signal generation circuit 12 controls the timing sequence of enabling the frequency divider and the frequency and phase detector through the second enable signal EN2 and the third enable signal EN3. The logic control circuit 2 can also control the time from the frequency divider being enabled to the arrival of the first trigger edge of the first clock signal at the frequency and phase detector, thereby realizing the control of the initial phase difference.

[0074] In this embodiment, based on the input synchronization signal, input clock signal and first enable signal output by the logic control circuit, the enable signal generation circuit can generate a corresponding enable signal to control the timing sequence of the frequency divider enable and the frequency and phase detector enable, thereby controlling the initial phase difference. This shortens the frequency hopping time while avoiding the degradation of noise performance of the phase-locked loop circuit and the increase in power consumption during the frequency hopping control process.

[0075] In some embodiments, when the frequency divider is enabled, the frequency divider outputs a first clock signal. When the frequency and phase detector is enabled, the frequency and phase detector receives the first clock signal and a reference clock signal. The logic control circuit 2 is used to control the time from when the frequency divider is enabled until the first trigger edge of the first clock signal reaches the frequency and phase detector, and controls the timing sequence of the frequency divider enabling and the frequency and phase detector enabling through the enable signal generation circuit 12 to control the initial phase difference.

[0076] In some examples, the enable signal generation circuit 12 can control the timing order of the trigger edge of the third enable signal EN3 and the trigger edge of the second enable signal EN2, thereby controlling the timing order of the frequency divider enable and the frequency detector enable. For example, the enable signal generation circuit 12 can control the trigger edge of the third enable signal EN3 to be half a clock cycle earlier than the trigger edge of the second enable signal EN2, thereby controlling the frequency divider to enable half a clock cycle earlier than the frequency detector. This clock cycle can be the clock cycle of the input clock signal CLK1, and both the trigger edges of the second enable signal EN2 and the third enable signal EN3 can be rising edges. The second enable signal EN2 is generated based on the input clock signal CLK1. The reference clock signal and the input clock signal CLK1 are differential signals, and the circuit can control that the first trigger edge of the reference clock signal reaches the frequency detector half a clock cycle after the trigger edge of the second enable signal EN2. By controlling the time from the trigger edge of the third enable signal EN3 to the first trigger edge of the first clock signal reaching the frequency and phase detector, the time difference between the first trigger edge of the first clock signal received after the frequency and phase detector is enabled and the first trigger edge of the reference clock signal can be controlled. This time difference, together with the clock period of the input clock signal CLK1, determines the initial phase difference.

[0077] In this embodiment, the logic control circuit and the enable signal generation circuit together realize the control of the initial phase difference. By controlling the initial phase difference to the target phase difference, the frequency hopping time can be greatly shortened.

[0078] In some embodiments, such as Figure 4As shown, the enable signal generation circuit 12 includes a steady-state control circuit 13, a first signal generation circuit 14, and a second signal generation circuit 15. The input terminal of the steady-state control circuit 13 is electrically connected to the logic control circuit 2. When the first enable signal EN1 is enabled, the steady-state control circuit 13, triggered by the input clock signal CLK1, delays the input synchronization signal SYNC. The first input terminal of the first signal generation circuit 14 is electrically connected to the output terminal of the steady-state control circuit 13. The second input terminal of the first signal generation circuit 14 receives the input clock signal CLK1. The control terminal of the first signal generation circuit 14 receives the first enable signal EN1. The output terminal of the first signal generation circuit 14 is electrically connected to the first input terminal of the phase-locked loop circuit 3. When the first enable signal EN1 is enabled, the first signal generation circuit 14 generates a second enable signal EN2 based on the input clock signal CLK1 and the delayed input synchronization signal SYNC. The first input terminal of the second signal generation circuit 15 is electrically connected to the output terminal of the steady-state control circuit 13. The second input terminal of the second signal generation circuit 15 receives the input clock signal CLK1. The control terminal of the second signal generation circuit 15 receives the first enable signal EN1. The output terminal of the second signal generation circuit 15 is electrically connected to the second input terminal of the phase-locked loop circuit 3. The second signal generation circuit 15 is used to generate a third enable signal EN3 based on the input clock signal CLK1 and the delayed input synchronization signal SYNC when the first enable signal EN1 is enabled.

[0079] In some examples, the steady-state control circuit 13, the first signal generation circuit 14, and the second signal generation circuit 15 can all be circuits composed of digital circuit units.

[0080] In some examples, the steady-state control circuit 13, when enabled and triggered by the input clock signal CLK1, can delay the input synchronization signal SYNC for multiple clock cycles, which can be the clock cycle of the input clock signal CLK1, to prevent unstable parts (e.g., brief, unwanted glitches) in the input synchronization signal SYNC from being transmitted to the downstream first signal generation circuit 14 and second signal generation circuit 15, thereby improving signal quality.

[0081] In some examples, the first signal generation circuit 14, when enabled, can be triggered by the input clock signal CLK1 to sample the delayed input synchronization signal SYNC to generate a second enable signal EN2. The second signal generation circuit 15 can invert the input clock signal CLK1, and then, when enabled, be triggered by the inverted input clock signal CLK1 to sample the delayed input synchronization signal SYNC to generate a third enable signal EN3. This allows for control over the timing of the trigger edges of the third enable signal EN3 and the second enable signal EN2, and further enables control over the difference between their trigger edges by half a clock cycle.

[0082] In this embodiment, the quality of the second and third enable signals is improved by the steady-state control circuit, thereby improving the stability of the circuit. The second and third enable signals are generated by the first and second signal generation circuits, respectively, which can conveniently control the relative timing of the two enable signals and improve the flexibility of control.

[0083] In some embodiments, such as Figure 5 As shown, the steady-state control circuit 13 includes multiple first flip-flops DFF1. The data input terminals D and data output terminals Q of the multiple first flip-flops DFF1 are connected in series. The data input terminal D of the first first flip-flop DFF1 receives the input synchronization signal SYNC. The data output terminal Q of the last first flip-flop DFF1 is electrically connected to the first input terminal of the first signal generation circuit 14 and the first input terminal of the second signal generation circuit 15. The clock input terminal CLK of each first flip-flop DFF1 receives the input clock signal CLK1, and the enable terminal SET of each first flip-flop DFF1 receives the first enable signal EN1.

[0084] Figure 5 Four first flip-flops DFF1 are shown. It is understood that the number of first flip-flops DFF1 can also be other numbers, such as greater than or equal to 3, as long as the unstable part of the input synchronization signal SYNC can be removed after delaying the input synchronization signal SYNC.

[0085] In some examples, when the first enable signal EN1 is at the first level, each first flip-flop DFF1 is enabled, and its output can be 0.

[0086] In some examples, the first flip-flop DFF1 can be a D flip-flop. Using a D flip-flop as the first flip-flop DFF1 allows the steady-state control circuit 13 to delay the input synchronization signal SYNC by the same number of clock cycles as the number of first flip-flops DFF1, for example... Figure 5The steady-state control circuit 13 can delay the input synchronization signal SYNC by 4 clock cycles, which can be the clock cycle of the input clock signal CLK1. The D flip-flop can sample the input synchronization signal SYNC only at the rising or falling edge of the input clock signal CLK1. As long as the unstable part of the input synchronization signal SYNC does not appear within the time window of the sampling edge, the D flip-flop will not sample this unstable part. After passing through multiple D flip-flops, the unstable part of the input synchronization signal SYNC is removed.

[0087] In this embodiment, a steady-state control circuit is composed of multiple first flip-flops, which can remove unstable parts in the input synchronization signal and improve the stability of the signals entering the first input terminal of the first signal generation circuit and the first input terminal of the second signal generation circuit.

[0088] In some embodiments, the number of first triggers is greater than or equal to 3. For example, it can be 3, 4, 5, etc.

[0089] In this embodiment, the number of first flip-flops is greater than or equal to 3, which can ensure that the unstable part in the input synchronization signal is removed and prevent the steady-state control circuit from becoming metastable.

[0090] In some embodiments, such as Figure 6 As shown, the first signal generation circuit 14 includes multiple second flip-flops DFF2. The data input terminals D and data output terminals Q of the multiple second flip-flops DFF2 are connected in series. The data input terminal D of the first second flip-flop DFF2 is electrically connected to the output terminal of the steady-state control circuit 13, and the data output terminal Q of the last second flip-flop DFF2 is electrically connected to the first input terminal of the phase-locked loop circuit 3. The clock input terminal CLK of each second flip-flop DFF2 receives the input clock signal CLK1, and the enable terminal SET of each second flip-flop DFF2 receives the first enable signal EN1.

[0091] Figure 6 Two second triggers DFF2 are shown. It is understood that the number of second triggers DFF2 can also be other numbers, such as 3, 4, etc.

[0092] In some examples, when the first enable signal EN1 is at the first level, each of the second flip-flops DFF2 is enabled, and its output can be 0.

[0093] In some examples, the second flip-flop DFF2 can be a D flip-flop. The D flip-flop can generate the second enable signal EN2 by sampling the delayed input synchronization signal SYNC only at the rising or falling edge of the input clock signal CLK1, further improving the stability of the second enable signal EN2.

[0094] In this embodiment, a first signal generation circuit is composed of multiple second flip-flops, which improves the stability of the generated second enable signal.

[0095] In some embodiments, such as Figure 7 As shown, the second signal generation circuit 15 includes an inverter INV and multiple third flip-flops DFF3. The input terminal of the inverter INV receives the input clock signal CLK1. The data input terminals D and data output terminals Q of the multiple third flip-flops DFF3 are connected in series. The data input terminal D of the first third flip-flop DFF3 is electrically connected to the output terminal of the steady-state control circuit 13, and the data output terminal Q of the last third flip-flop DFF3 is electrically connected to the second input terminal of the phase-locked loop circuit 3. The clock input terminal CLK of each third flip-flop DFF3 is electrically connected to the output terminal of the inverter INV, and the enable terminal SET of each third flip-flop DFF3 receives the first enable signal EN1.

[0096] Figure 7 Two third flip-flops DFF3 are shown. It can be understood that the number of third flip-flops DFF3 can also be other numbers, such as 3 or 4, as long as it is the same as the number of second flip-flops DFF2 in the first signal generation circuit 14. Because the input clock signal CLK1 is inverted by the inverter INV and then input to the clock input CLK of each third flip-flop DFF3, the sampling time of the first third flip-flop DFF3 for the delayed input synchronization signal SYNC is half a clock cycle earlier than the sampling time of the first second flip-flop DFF2 for the delayed input synchronization signal SYNC. This clock cycle can be the clock cycle of the input clock signal CLK1. Since the number of third flip-flops DFF3 is the same as the number of second flip-flops DFF2, the third enable signal EN3 can also be half a clock cycle earlier than the second clock signal EN2.

[0097] In some examples, when the first enable signal EN1 is at the first level, each third flip-flop DFF3 is enabled, and its output can be 0.

[0098] In some examples, the third flip-flop DFF3 can be a D flip-flop. The D flip-flop can sample the delayed input synchronization signal SYNC only at the rising or falling edge of the input clock signal CLK1 after it has been inverted by the inverter INV to generate the third enable signal EN3, further improving the stability of the third enable signal EN3.

[0099] In this embodiment, the stability of the third enable signal is improved, and a third enable signal that is half a clock cycle earlier than the second enable signal can be generated. This allows control over the timing sequence and time interval between the frequency divider enable and the frequency and phase detector enable, thereby controlling the initial phase difference.

[0100] In some embodiments, the logic control circuit 2 is further configured to control the phase calibration circuit 1 after the initial phase difference reaches the target phase difference, so that the phase calibration circuit 1 switches the charging current of the capacitor of the loop filter in the phase-locked loop circuit 3 to the target current.

[0101] In some examples, the initial phase difference equals the target phase difference, meaning the initial phase difference directly reaches the target phase difference. In other examples, the initial phase difference does not equal the target phase difference, requiring the phase detector of the phase-locked loop circuit 3 to compare the phase difference between the first clock signal and the reference clock signal. Then, through a negative feedback mechanism, the phase difference is calibrated to the target phase difference, thereby enabling the initial phase difference to reach the target phase difference.

[0102] After the initial phase difference reaches the target phase difference, the capacitor in the loop filter of the phase-locked loop circuit 3 needs to be charged to the required control voltage to lock the frequency and phase state of the second clock signal, providing a stable second clock signal that meets communication requirements for the transmission and reception of radio frequency signals in cellular communication. The time to charge the capacitor of the loop filter to the required control voltage is a component of the frequency hopping time. If the charging current is too small during the charging process of the loop filter capacitor, the time required to charge to the control voltage will be too long, resulting in an excessively long frequency hopping time and affecting the stability of communication. In some examples, the phase calibration circuit 1 can switch the charging current output by the charge pump circuit of the phase-locked loop circuit 3 under the control of the logic control circuit 2. After the initial phase difference reaches the target phase difference, the phase calibration circuit 1 can switch the charging current to a larger target current to shorten the charging time of the loop filter capacitor, thereby shortening the frequency hopping time.

[0103] In this embodiment, the charging time of the capacitor in the loop filter after the initial phase difference reaches the target phase difference can be shortened by controlling the charging current of the capacitor in the loop filter, thereby shortening the frequency hopping time.

[0104] In some embodiments, such as Figure 8As shown, the phase calibration circuit 1 includes a current switching circuit 16. The first terminal of the current switching circuit 16 is electrically connected to the first terminals of multiple pull-up current sources (PUCS) of the charge pump 31 in the phase-locked loop circuit 3. The second terminal of the current switching circuit 16 is electrically connected to the first terminal of the pull-down current source (PDCS) of the charge pump 31. The third terminal of the current switching circuit 16 is electrically connected to the capacitor C of the loop filter 32. The current switching circuit 16 is used to connect at least one of the multiple pull-up current sources (PUCS) and pull-down current sources (PDCS) to the capacitor C of the loop filter 32, thereby charging or discharging the capacitor C of the loop filter 32. The second terminal of each pull-up current source (PUCS) is electrically connected to the power supply VDD, and the second terminal of each pull-down current source (PDCS) is electrically connected to the ground terminal GND.

[0105] The pull-up current source PUCS can charge capacitor C when electrically connected to capacitor C of loop filter 32, increasing the voltage of capacitor C. The pull-down current source PDCS can discharge capacitor C when electrically connected to capacitor C of loop filter 32, decreasing the voltage of capacitor C. This voltage of capacitor C can be adjusted to ensure that the frequency and phase of the second clock signal meet communication requirements under the control of the voltage of capacitor C.

[0106] In some examples, the magnitudes of the currents output by multiple pull-up current sources (PUCS) can be different. After the initial phase difference reaches the target phase difference, when it is necessary to charge the capacitor C in the loop filter 32 of the phase-locked loop circuit 3 to the required control voltage, the logic control circuit 2 can control the current switching circuit 16 to electrically connect at least one pull-up current source (PUCS) to the capacitor C of the loop filter 32. The current output by the at least one pull-up current source (PUCS) electrically connected to the capacitor C is the target current, so as to use the target current to charge the capacitor C, shorten the charging time, and thus shorten the frequency hopping time.

[0107] In this embodiment, the charging current of the capacitor in the loop filter can be switched to the target current by changing the current source of the capacitor electrically connected to the loop filter, resulting in a simple circuit structure.

[0108] In some embodiments, such as Figure 9As shown, the multiple pull-up current sources PUCS include a first current source CS1, a second current source CS2, and a third current source CS3. The pull-down current source PDCS includes a fourth current source CS4. The current switching circuit 16 includes a first switching unit SW1, a second switching unit SW2, a third switching unit SW3, and a fourth switching unit SW4. The first terminal of the first switching unit SW1 is electrically connected to the first terminal of the first current source CS1, and the control terminal of the first switching unit SW1 is electrically connected to the logic control circuit 2. The first terminal of the second switching unit SW2 is electrically connected to the first terminal of the second current source CS2, and the control terminal of the second switching unit SW2 is electrically connected to the logic control circuit 2. The first terminal of the third switching unit SW3 is electrically connected to the first terminal of the third current source CS3, and the control terminal of the third switching unit SW3 is electrically connected to the logic control circuit 2. The first terminal of the fourth switching unit SW4 is electrically connected to the second terminals of the first switching unit SW1, the second switching unit SW2, and the third switching unit SW3, and is also used to electrically connect to the capacitor C of the loop filter 32. The second terminal of the fourth switching unit SW4 is electrically connected to the first terminal of the fourth current source CS4, and the control terminal of the fourth switching unit SW4 is electrically connected to the logic control circuit 2. The second terminals of the first current source CS1, the second current source CS2, and the third current source CS3 are all electrically connected to the power supply VDD, and the second terminal of the fourth current source CS4 is electrically connected to the ground terminal GND. The logic control circuit 2 is used to switch the charging current to the target current by controlling the first switching unit SW1, the third switching unit SW3, and the fourth switching unit SW4 to be disconnected and controlling the second switching unit SW2 to be turned on.

[0109] In some examples, the first switching unit SW1, the second switching unit SW2, the third switching unit SW3, and the fourth switching unit SW4 can all be transistors.

[0110] In some examples, the current supplied to capacitor C by the first current source CS1 can be the same as the current drawn from capacitor C by the fourth current source CS4. The second current source CS2 can supply the target current to capacitor C, which is greater than the current supplied to capacitor C by the third current source CS3. After the initial phase difference reaches the target phase difference, capacitor C is charged to the required control voltage using the second current source CS2. The larger charging current shortens the charging time.

[0111] In some examples, after the capacitor C is charged to the required control voltage, the logic control circuit 2 is also used to control the first switching unit SW1, the third switching unit SW3 and the fourth switching unit SW4 to be turned on, and to control the second switching unit SW2 to be turned off, so as to charge or discharge the capacitor C through the first current source CS1, the third current source CS3 and the fourth current source CS4. This can prevent the phase-locked loop circuit 3 from having a dead zone problem, and at the same time make the charge pump 31 work in a range with better linearity.

[0112] In this embodiment, the current source of the capacitor electrically connected to the loop filter is changed by the switching unit, resulting in low device cost and low power consumption.

[0113] In some embodiments, the logic control circuit 2 is further configured to calibrate the frequency of the second clock signal according to the target frequency in the handover command generated during the base station handover process.

[0114] In some examples, the logic control circuit 2 can control the capacitors in the capacitor array of the voltage-controlled oscillator of the phase-locked loop circuit 3 to turn on or off according to the target frequency, thereby changing the total capacitance value of the capacitor array and calibrating the frequency of the second clock signal output by the voltage-controlled oscillator to the target frequency.

[0115] In this embodiment, the frequency-calibrated second clock signal can meet the communication requirements of electronic devices when switching to a base station.

[0116] In some embodiments, the logic control circuit 2 calibrates the frequency of the second clock signal by executing a successive approximation algorithm.

[0117] In some examples, a digital control word can be used to control the capacitors in the capacitor array of a voltage-controlled oscillator to turn on or off, thereby changing the frequency of the second clock signal. When calibrating the frequency of the second clock signal using a successive approximation algorithm, the logic control circuit 2 can first set the value of the digital control word to the middle value of the possible range, compare the frequency of the second clock signal with the target frequency, and determine the range to be narrowed down based on the comparison result. Then, the value of the digital control word is set to the middle value of the narrowed range, and further comparisons and narrowing of the possible range are performed until the final value of the digital control word that makes the frequency of the second clock signal equal to the target frequency is obtained. This value is then used to control the capacitors in the capacitor array of the voltage-controlled oscillator to turn on or off, thus completing the frequency calibration of the second clock signal. When comparing the frequency of the second clock signal with the target frequency, the later part of the second clock signal needs to be counted within a fixed counting period. The count value is then divided by the time of the counting period to obtain the frequency of the second clock signal, which is then compared with the target frequency.

[0118] In this embodiment, the time for calibrating the frequency of the second clock signal according to the target frequency is a component of the frequency hopping time. The frequency of the second clock signal is calibrated by the successive approximation algorithm. Compared with the calibration by the binary method, the counting period time is shorter, thus shortening the frequency hopping time.

[0119] In some embodiments, the logic control circuit 2 is further configured to look up the bandwidth parameter of the phase-locked loop circuit 3 corresponding to the target frequency and the amplitude parameter of the voltage-controlled oscillator of the phase-locked loop circuit 3 in a pre-stored parameter table, and to set the phase-locked loop circuit 3 using the found bandwidth parameter and amplitude parameter.

[0120] During base station handover, the bandwidth parameters and amplitude parameters of the phase-locked loop circuit 3 (PLL 3) and its voltage-controlled oscillator (VCO) need to be calibrated to values ​​corresponding to the target frequency. This calibration time is a component of the frequency hopping time, resulting in a long hopping time. In some examples, a pre-stored parameter table may include the correspondence between the target frequency and the bandwidth and amplitude parameters. The logic control circuit 2 searches the pre-stored parameter table to determine the bandwidth and amplitude parameters corresponding to the target frequency, saving calibration time.

[0121] In some examples, the loop filter 32 also includes a resistor R, and the bandwidth parameters include the gain parameters of the voltage-controlled oscillator of the phase-locked loop circuit 3 and the time constant of the circuit composed of the capacitor C and the resistor R of the loop filter 32.

[0122] In this embodiment, the bandwidth and amplitude parameters are determined by looking up a table, which saves the time of calibrating the bandwidth and amplitude parameters to the values ​​corresponding to the target frequency, thereby shortening the frequency hopping time.

[0123] In some exemplary embodiments, a frequency hopping control circuit is provided, such as... Figure 10As shown, the frequency hopping control circuit includes multiple first flip-flops DFF1, multiple second flip-flops DFF2, an inverter INV, multiple third flip-flops DFF3, a first switching unit SW1, a second switching unit SW2, a third switching unit SW3, a fourth switching unit SW4, and a logic control circuit 2. The data input terminals D and Q of the multiple first flip-flops DFF1 are connected in series. The data input terminal D of the first first flip-flop DFF1 is electrically connected to the logic control circuit 2 to receive the input synchronization signal SYNC. The clock input terminal CLK of each first flip-flop DFF1 is electrically connected to the logic control circuit 2 to receive the input clock signal CLK1. The enable terminal SET of each first flip-flop DFF1 is electrically connected to the logic control circuit 2 to receive the first enable signal EN1. Multiple second flip-flops (DFF2) have their data input terminals D and data output terminals Q connected in series. The data input terminal D of the first second flip-flop (DFF2) is electrically connected to the data output terminal Q of the last first flip-flop (DFF1). The data output terminal Q of the last second flip-flop (DFF2) is electrically connected to the frequency and phase detector 33 of the phase-locked loop circuit 3, providing a second enable signal EN2 to the frequency and phase detector 33. The clock input terminal CLK of each second flip-flop (DFF2) is electrically connected to the logic control circuit 2 to receive the input clock signal CLK1. The enable terminal SET of each second flip-flop (DFF2) is also electrically connected to the logic control circuit 2 to receive the first enable signal EN1. The input terminal of the inverter INV is electrically connected to the logic control circuit 2 to receive the input clock signal CLK1. Multiple third flip-flops (DFF3) have their data input terminals D and data output terminals Q connected in series. The data input terminal D of the first third flip-flop (DFF3) is electrically connected to the data output terminal Q of the last first flip-flop (DFF1). The data output terminal Q of the last third flip-flop (DFF3) is electrically connected to the frequency divider 34 of the phase-locked loop (PLL) circuit 3, providing a third enable signal EN3 to the frequency divider 34. The clock input terminal CLK of each third flip-flop (DFF3) is electrically connected to the output terminal INV of the inverter. The enable terminal SET of each third flip-flop (DFF3) is electrically connected to the logic control circuit 2, receiving a first enable signal EN1. The first terminal of the first switching unit SW1 is electrically connected to the first terminal of the first current source CS1 of the charge pump 31 of the PLL circuit 3. The first terminal of the second switching unit SW2 is electrically connected to the first terminal of the second current source CS2 of the charge pump 31 of the PLL circuit 3. The first terminal of the third switching unit SW3 is electrically connected to the first terminal of the third current source CS3 of the charge pump 31 of the PLL circuit 3.The first terminal of the fourth switching unit SW4 is electrically connected to the second terminals of the first switching unit SW1, the second switching unit SW2, and the third switching unit SW3, and is also electrically connected to the first terminal of the capacitor C of the loop filter 32. The second terminal of the fourth switching unit SW4 is electrically connected to the first terminal of the fourth current source CS4 of the charge pump 31 of the phase-locked loop circuit 3. The control terminals of the first switching unit SW1, the second switching unit SW2, the third switching unit SW3, and the fourth switching unit SW4 are all electrically connected to the logic control circuit 2. The logic control circuit 2 is electrically connected to the loop filter 32, the frequency divider 34, and the voltage-controlled oscillator 35 of the phase-locked loop circuit 3, and is also electrically connected to the crystal oscillator circuit 4. The crystal oscillator circuit 4 generates the input clock signal CLK1 and the reference clock signal CLK2. After obtaining the input clock signal CLK1 from the crystal oscillator circuit 4, the logic control circuit 2 outputs it to each flip-flop.

[0124] In some examples, such as Figure 10 As shown, in the phase-locked loop circuit 3, the first input terminal of the frequency and phase detector 33 is electrically connected to the output terminal of the frequency divider 34. The second input terminal of the frequency and phase detector 33 is used to connect electrically to the crystal oscillator circuit 4 to receive the reference clock signal CLK2 from the crystal oscillator circuit 4. The output terminal of the frequency and phase detector 33 is electrically connected to the input terminal of the charge pump 31. The second terminal of the capacitor C is electrically connected to the first terminal of the resistor R of the loop filter 32, and the second terminal of the resistor R is electrically connected to the ground terminal GND. The input terminal of the voltage-controlled oscillator 35 is electrically connected to the first terminal of the capacitor C. The input terminal of the frequency divider 34 is electrically connected to the output terminal of the voltage-controlled oscillator 35, and the output terminal of the frequency divider 34 outputs the first clock signal CLK3. The second terminals of the first current source CS1, the second current source CS2, and the third current source CS3 of the charge pump 31 are all electrically connected to the power supply VDD, and the second terminal of the fourth current source CS4 is electrically connected to the ground terminal GND.

[0125] In some examples, the timing diagram for logic control circuit 2 controlling multiple first flip-flops DFF1, multiple second flip-flops DFF2, inverter INV, and multiple third flip-flops DFF3 is as follows: Figure 11 As shown. It can be seen that, under the control of logic control circuit 2, the enable time of frequency divider 34 is half a clock cycle earlier than the enable time of frequency and phase detector 33. This clock cycle is the clock cycle of the input clock signal CLK1. Logic control circuit 2 also controls frequency divider 34 from its enable time until the first trigger edge of the first clock signal CLK3. Figure 11 The time it takes for the rising edge of the frequency to reach the phase detector 33 is used to control the initial phase difference and shorten the frequency hopping time.

[0126] In some exemplary embodiments, a frequency hopping control chip is provided, which includes any of the frequency hopping control circuits in the above embodiments. In this embodiment, because the frequency hopping control chip includes the frequency hopping control circuits in the above embodiments, the initial phase difference is controllable, the frequency hopping time is shortened, and the noise performance degradation of the phase-locked loop circuit and the power consumption increase in the frequency hopping control process are avoided.

[0127] In some exemplary embodiments, a phase-locked loop (PLL) chip is provided, which includes a PLL circuit 3 and any of the frequency hopping control circuits described in the above embodiments. In this embodiment, the integration density is improved because the PLL circuit and the frequency hopping control circuit are integrated on a single chip.

[0128] In some exemplary embodiments, a baseband chip is provided, which includes the frequency hopping control chip or the phase-locked loop chip described in the above embodiments. In this embodiment, because the baseband chip includes the frequency hopping control chip or the phase-locked loop chip described in the above embodiments, the initial phase difference is controllable, the frequency hopping time is shortened, and the noise performance degradation of the phase-locked loop circuit and the power consumption increase during the frequency hopping control process are avoided.

[0129] In some exemplary embodiments, a system-on-a-chip (SoC) is provided, which includes the baseband chip described in the above embodiments. In this embodiment, because the SoC includes the baseband chip described in the above embodiments, the initial phase difference is controllable, the frequency hopping time is shortened, and the noise performance degradation of the phase-locked loop circuit and the power consumption increase during the frequency hopping control process are avoided.

[0130] In some exemplary embodiments, an electronic device is provided, which includes the baseband chip or the system-on-a-chip in the above embodiments.

[0131] In some examples, the radio frequency communication link architecture of electronic devices is as follows: Figure 12 As shown. During base station handover, Figure 12 The radio frequency phase-locked loop (RFPL) in this invention requires frequency hopping, and the frequency hopping control circuit in this disclosure is used to control the frequency hopping of the RFPL.

[0132] In this embodiment, because the electronic device includes the baseband chip or the system-on-a-chip in the above embodiments, the initial phase difference is controllable, which shortens the frequency hopping time and avoids the degradation of noise performance of the phase-locked loop circuit and the increase in power consumption during the frequency hopping control process.

[0133] In some exemplary embodiments, such as Figure 13As shown, an electronic device 1300 is provided, which may include one or more of the following components: a processing component 1302, a memory 1304, a power supply component 1306, a multimedia component 1308, an audio component 1310, an input / output (I / O) interface 1312, a sensor component 1314, and a communication component 1316.

[0134] Processing component 1302 typically controls the overall operation of electronic device 1300, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 1302 may include one or more processors 1320 to execute instructions. Furthermore, processing component 1302 may include one or more modules to facilitate interaction between processing component 1302 and other components. For example, processing component 1302 may include a multimedia module to facilitate interaction between multimedia component 1308 and processing component 1302.

[0135] Memory 1304 is configured to store various types of data to support the operation of electronic device 1300. Examples of such data include instructions for any application or method operating on electronic device 1300, contact data, phonebook data, messages, pictures, videos, etc. Memory 1304 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0136] Power supply component 1306 provides power to various components of electronic device 1300. Power supply component 1306 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 1300.

[0137] Multimedia component 1308 includes a screen that provides an output interface between electronic device 1300 and a user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 1308 includes a front-facing camera and / or a rear-facing camera. When electronic device 1300 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0138] Audio component 1310 is configured to output and / or input audio signals. For example, audio component 1310 includes a microphone (MIC) configured to receive external audio signals when electronic device 1300 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 1304 or transmitted via communication component 1316. In some embodiments, audio component 1310 also includes a speaker for outputting audio signals.

[0139] I / O interface 1312 provides an interface between processing component 1302 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0140] Sensor assembly 1314 includes one or more sensors for providing state assessments of various aspects of electronic device 1300. For example, sensor assembly 1314 may detect the on / off state of electronic device 1300, the relative positioning of components such as the display and keypad of electronic device 1300, changes in position of electronic device 1300 or a component of electronic device 1300, the presence or absence of user contact with electronic device 1300, the orientation or acceleration / deceleration of electronic device 1300, and temperature changes of electronic device 1300. Sensor assembly 1314 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 1314 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 1314 may also include an accelerometer, a gyroscope, a magnetometer, a pressure sensor, or a temperature sensor.

[0141] Communication component 1316 is configured to facilitate wired or wireless communication between electronic device 1300 and other devices. Electronic device 1300 can access wireless networks based on communication standards, such as WiFi, 2G, or 3G, or combinations thereof. In one exemplary embodiment, communication component 1316 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 1316 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0142] In an exemplary embodiment, the electronic device 1300 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0143] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 1304 including instructions that can be executed by a processor 1320 of an electronic device 1300. For example, the non-transitory computer-readable storage medium may be a ROM, CD-ROM, magnetic tape, floppy disk, or optical data storage device.

[0144] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

[0145] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

[0146] The examples in this document may involve user data, data acquisition, and / or use. All of these aspects comply with relevant laws, regulations, and rules. In the examples, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, when implementing each example, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained through appropriate means, in accordance with relevant laws and regulations. The specific methods of notification and / or authorization can vary depending on the actual situation and application scenario; the scope of the solution is not limited in this regard.

[0147] In this manual and the sample solutions, any processing of personal information will be conducted only under legal grounds (such as obtaining the consent of the data subject or being necessary for the performance of a contract) and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information beyond what is necessary for basic functions will not affect the user's use of basic functions.

Claims

1. A frequency hopping control circuit, characterized by comprising: The frequency hopping control circuit includes: A phase calibration circuit, wherein the phase calibration circuit is electrically connected to a phase-locked loop circuit; A logic control circuit is electrically connected to the phase calibration circuit and is also electrically connected to the phase-locked loop circuit. The logic control circuit is used to control the phase calibration circuit during base station handover so that the phase calibration circuit controls the initial phase difference between the first clock signal output by the phase-locked loop circuit and the reference clock signal. The first clock signal is obtained by dividing the frequency of the second clock signal output by the phase-locked loop circuit after frequency calibration. The reference clock signal is generated by a crystal oscillator circuit.

2. The frequency hopping control circuit of claim 1, wherein, The phase calibration circuit includes: A phase difference control circuit, wherein the input terminal of the phase difference control circuit is electrically connected to the logic control circuit, and the output terminal of the phase difference control circuit is used to be electrically connected to the phase-locked loop circuit; The logic control circuit controls the phase difference control circuit through a first control signal to control the initial phase difference.

3. The frequency hopping control circuit of claim 2, wherein, The first control signal includes an input synchronization signal, an input clock signal, and a first enable signal, wherein the input clock signal and the reference clock signal are differential signals. The phase difference control circuit includes: An enable signal generation circuit is provided, wherein the input terminal of the enable signal generation circuit is electrically connected to the logic control circuit, and the output terminal of the enable signal generation circuit is electrically connected to the phase-locked loop (PLL) circuit. When the first enable signal is enabled, the enable signal generation circuit generates a second enable signal and a third enable signal based on the input synchronization signal and the input clock signal, and outputs the second enable signal and the third enable signal to the PLL circuit. The second enable signal enables the frequency and phase detector of the PLL circuit, and the third enable signal enables the frequency divider of the PLL circuit. The frequency divider divides the second clock signal to obtain the first clock signal.

4. The frequency hopping control circuit according to claim 3, characterized in that, When the frequency divider is enabled, the frequency divider outputs the first clock signal; When the frequency and phase detector is enabled, the frequency and phase detector receives the first clock signal and the reference clock signal; The logic control circuit is used to control the time from when the frequency divider is enabled until the first trigger edge of the first clock signal reaches the frequency detector and phase detector, and to control the timing sequence of the frequency divider enabling and the frequency detector enabling through the enable signal generation circuit, so as to control the initial phase difference.

5. The frequency hopping control circuit of claim 3, wherein, The enable signal generation circuit includes: A steady-state control circuit, wherein the input terminal of the steady-state control circuit is electrically connected to the logic control circuit, and the steady-state control circuit is used to delay the input synchronization signal when the first enable signal enables it and is triggered by the input clock signal. A first signal generation circuit has a first input terminal electrically connected to the output terminal of the steady-state control circuit, a second input terminal of the first signal generation circuit receiving the input clock signal, a control terminal of the first signal generation circuit receiving the first enable signal, and an output terminal of the first signal generation circuit electrically connected to the first input terminal of the phase-locked loop circuit. The first signal generation circuit is used to generate a second enable signal based on the input clock signal and the delayed input synchronization signal when the first enable signal is enabled. The second signal generation circuit has a first input terminal electrically connected to the output terminal of the steady-state control circuit, a second input terminal receiving the input clock signal, a control terminal receiving the first enable signal, and an output terminal electrically connected to the second input terminal of the phase-locked loop circuit. The second signal generation circuit is used to generate the third enable signal based on the input clock signal and the delayed input synchronization signal when the first enable signal is enabled.

6. The frequency hopping control circuit according to claim 5, characterized in that, The steady-state control circuit includes: Multiple first flip-flops are connected in series, with their data input and data output terminals connected together. The data input terminal of the first first flip-flop receives the input synchronization signal. The data output terminal of the last first flip-flop is electrically connected to both the first input terminal of the first signal generation circuit and the first input terminal of the second signal generation circuit. The clock input terminal of each first flip-flop receives the input clock signal, and the enable terminal of each first flip-flop receives the first enable signal.

7. The frequency hopping control circuit according to claim 6, characterized in that, The number of the first triggers is greater than or equal to 3.

8. The frequency hopping control circuit according to claim 5, characterized in that, The first signal generation circuit includes: Multiple second flip-flops are connected in series, with their data input and data output terminals connected together. The data input terminal of the first second flip-flop is electrically connected to the output terminal of the steady-state control circuit, and the data output terminal of the last second flip-flop is electrically connected to the first input terminal of the phase-locked loop circuit. The clock input terminal of each second flip-flop receives the input clock signal, and the enable terminal of each second flip-flop receives the first enable signal.

9. The frequency hopping control circuit according to claim 5, characterized in that, The second signal generation circuit includes: An inverter, the input of which receives the input clock signal; Multiple third flip-flops are connected in series, with their data input and data output terminals connected together. The data input terminal of the first third flip-flop is electrically connected to the output terminal of the steady-state control circuit, and the data output terminal of the last third flip-flop is electrically connected to the second input terminal of the phase-locked loop circuit. The clock input terminal of each third flip-flop is electrically connected to the output terminal of the inverter, and the enable terminal of each third flip-flop receives the first enable signal.

10. The frequency hopping control circuit according to any one of claims 1 to 9, characterized in that, The logic control circuit is also used to control the phase calibration circuit after the initial phase difference reaches the target phase difference, so that the phase calibration circuit switches the charging current of the capacitor of the loop filter in the phase-locked loop circuit to the target current.

11. The frequency hopping control circuit according to claim 10, characterized in that, The phase calibration circuit includes: A current switching circuit is provided, wherein a first terminal of the current switching circuit is electrically connected to the first terminals of multiple pull-up current sources of the charge pump of the phase-locked loop circuit, a second terminal of the current switching circuit is electrically connected to the first terminal of the pull-down current source of the charge pump, and a third terminal of the current switching circuit is electrically connected to the capacitor of the loop filter. The current switching circuit is used to connect at least one of the multiple pull-up current sources and the pull-down current sources to the capacitor of the loop filter to charge or discharge the capacitor of the loop filter. The second end of each of the pull-up current sources is electrically connected to the power supply, and the second end of each pull-down current source is electrically connected to the ground.

12. The frequency hopping control circuit according to claim 11, characterized in that, The plurality of pull-up current sources include a first current source, a second current source and a third current source, and the pull-down current source includes a fourth current source; The current switching circuit includes: A first switching unit, wherein a first terminal of the first switching unit is electrically connected to a first terminal of the first current source, and a control terminal of the first switching unit is electrically connected to the logic control circuit; The second switching unit has a first terminal for electrical connection to the first terminal of the second current source, and a control terminal for electrical connection to the logic control circuit. The third switching unit has a first terminal for electrical connection to the first terminal of the third current source, and a control terminal for electrical connection to the logic control circuit. The fourth switching unit has a first terminal electrically connected to the second terminals of the first switching unit, the second switching unit, and the third switching unit, and is used to be electrically connected to the capacitor of the loop filter. The second terminal of the fourth switching unit is used to be electrically connected to the first terminal of the fourth current source. The control terminal of the fourth switching unit is electrically connected to the logic control circuit. The second end of the first current source, the second end of the second current source, and the second end of the third current source are all electrically connected to the power supply, and the second end of the fourth current source is electrically connected to the grounding terminal. The logic control circuit is used to switch the charging current to the target current by controlling the first switching unit, the third switching unit and the fourth switching unit to be disconnected, and controlling the second switching unit to be turned on.

13. The frequency hopping control circuit according to any one of claims 1 to 9, characterized in that, The logic control circuit is also used to calibrate the frequency of the second clock signal according to the target frequency in the handover command generated during the base station handover process.

14. The frequency hopping control circuit according to claim 13, characterized in that, The logic control circuit calibrates the frequency of the second clock signal by executing a successive approximation algorithm.

15. The frequency hopping control circuit according to claim 13, characterized in that, The logic control circuit is also used to look up the bandwidth parameter of the phase-locked loop circuit and the amplitude parameter of the voltage-controlled oscillator of the phase-locked loop circuit corresponding to the target frequency in a pre-stored parameter table, and to set the phase-locked loop circuit using the found bandwidth parameter and amplitude parameter.

16. A frequency hopping control chip, characterized in that, The frequency hopping control chip includes the frequency hopping control circuit as described in any one of claims 1 to 15.

17. A phase-locked loop chip, characterized in that, The phase-locked loop chip includes a phase-locked loop circuit and a frequency hopping control circuit as described in any one of claims 1 to 15.

18. A baseband chip, characterized in that, The baseband chip includes the frequency hopping control chip as described in claim 16, or the phase-locked loop chip as described in claim 17.

19. A system-on-a-chip, characterized in that, The system-on-a-chip includes the baseband chip as described in claim 18.

20. An electronic device, characterized in that, The electronic device includes the baseband chip as described in claim 18, or the system-on-a-chip as described in claim 19.

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