Method and system for identifying and demodulating variable rate satellite signals based on FPGA

Abstract

The application discloses a kind of based on FPGA variable rate satellite signal identification demodulation method and system, method includes: obtaining the satellite signal to be identified and demodulated, according to the symbol rate of the satellite signal to be identified and demodulated, wideband sampling rate, output FPGA preset parameter;According to the FPGA preset parameter, digital down conversion processing is carried out, and the narrowband data of preset multiple oversampling is output;Based on the narrowband data and the preset parameter, identification demodulation is carried out, and the result whether signal is detected and identified and the demodulation result of signal identified are output.The application realizes the accurate adaptation of arbitrary symbol rate by three-stage cascade extraction architecture, overcomes the defects that traditional FPGA demodulation only supports fixed or limited preset rate, avoids high delay and resource waste caused by frequent reloading configuration, improves the continuity of satellite communication link and data reception success rate, and reduces the complexity of FPGA implementation.

Description

Technical Field

[0001] This invention relates to the fields of satellite communication and digital signal processing technology, and in particular to a method and system for identifying and demodulating FPGA-based variable rate satellite signals. Background Technology

[0002] In satellite communication systems, to meet users' needs for data communication with varying bandwidths, satellite signals often employ a variable symbol rate transmission scheme. For example, in deep space exploration communications, tactical data links, or certain broadband satellite communication systems, the symbol rate can be dynamically adjusted according to link budget and service requirements.

[0003] However, most existing FPGA-based satellite signal demodulation technologies are designed for fixed symbol rates or only support a limited number of preset rates, lacking designs that support continuous and arbitrary changes in symbol rates. When the signal rate exceeds the preset range or changes continuously within the range, such systems either fail to function or require frequent reload configurations consuming significant resources. Summary of the Invention

[0004] To address the aforementioned issues, this invention provides a method and system for identifying and demodulating FPGA-based variable-rate satellite signals, enabling real-time identification and demodulation of any variable symbol rate satellite signal.

[0005] This invention provides a method for identifying and demodulating variable-rate satellite signals based on FPGA, the specific technical solution of which is as follows: Acquire the satellite signal to be identified and demodulated, and output FPGA preset parameters based on the symbol rate and broadband sampling rate of the satellite signal to be identified and demodulated; Digital downconversion processing is performed based on the preset parameters of the FPGA to output narrowband data with 4 times oversampling. Based on the narrowband data and the preset parameters, identification and demodulation are performed, and the result of whether the signal was detected and the demodulation result of the detected signal are output.

[0006] Furthermore, the FPGA preset parameters include the integral comb filter (CIC) decimation factor, fractional decimation parameters, number of decimation stages for multi-stage half-band filters, synchronization sequence waveform, and signal burst length.

[0007] Furthermore, the digital down-conversion processing based on the preset parameters of the FPGA to output narrowband data with 4x oversampling is as follows: Based on the decimation factor of the integral comb filter (CIC), a 6-stage CIC filter is used in the FPGA to decimate the data and output the decimated data. Based on the number of multi-level half-band filtering extraction stages, the extracted data is subjected to multi-level half-band filtering extraction in the FPGA, and the filtered data is output. Based on the fractional extraction parameters, the filtered data is subjected to Farrow filtering to output the fractionally extracted data, which is the narrowband data with 4x oversampling.

[0008] Furthermore, it also includes: performing low-pass filtering on the output data after fractional extraction, and outputting filtered data; wherein the coefficients of the low-pass filtering are pre-simulated, generated, and stored in the FPGA.

[0009] Furthermore, the filtered data is subjected to Farrow filtering, as follows: Acquire the digital signal input to the Farrow filter and the output signal after fractional decimation, and determine the relationship between the sampling interval of the output signal and the sampling interval of the input signal; The integer multiple of the output signal sampling interval is used as the initial sampling point index, and the fractional part of the ratio of the output signal sampling interval to the input signal sampling interval is used as the distance between the interpolation point and the nearest original data point, i.e., the fractional delay parameter. Set the filter length, construct a polynomial filter, and obtain the output signal by weighting the polynomial with the fractional delay parameter as a variable and the neighboring input data points.

[0010] The coefficients of the polynomial are fixed values, and the interpolation position can be changed by changing the fractional delay parameter, without the need to recalculate the filter coefficients in real time.

[0011] Furthermore, the polynomial coefficients of the polynomial filter are obtained as follows: The interpolation result is obtained by using the Lagrange interpolation method, based on the sum of the products of the function values ​​of each interpolation node and the corresponding Lagrange basis functions. The Lagrange basis function is expanded with the interpolation position as the variable, and the polynomial coefficients are extracted as the fixed coefficients of the Farrow filter. The interpolation position is used as the fractional delay parameter.

[0012] Furthermore, the identification and demodulation are specifically as follows: In the FPGA, the output fractionally decimated data is subjected to matched filtering, and the filtered data is output. The matched filter coefficients are pre-simulated, generated, and stored in the FPGA. Based on the synchronization sequence waveform, differential correlation processing is performed on the filtered data in the FPGA to detect whether the correlation result is greater than the set correlation peak threshold. Based on the comparison result, it is identified whether it is the current satellite signal. The position of the maximum peak value is detected through the correlation result to determine the accurate start position of the signal. Based on the signal burst length and the maximum peak position, the filtered data is processed by taking one point every four points, starting from the maximum peak position, as the symbol synchronization output data; Carrier synchronization calculation is performed on the output data, and demodulated constellation point data is output. Perform constellation mapping calculations on the demodulated constellation point data and output demodulated symbol data.

[0013] Furthermore, the differential correlation processing is calculated as follows:

[0014]

[0015] in, The received signal after matched filtering. Given the waveform of the synchronization sequence, For the differential correlation length, For the difference interval, The value is different from 0 and , This is the final normalized output value of the differential correlation.

[0016] Furthermore, the symbol synchronization employs the Gardner algorithm, and the timing error estimation is as follows:

[0017] in, This is a value representing the timing error. For timing error, It is the moment of judgment. and Sample values ​​of each symbol I / Q channel. Indicates the first and The intermediate sample value of each symbol.

[0018] This invention also provides an identification and demodulation system for FPGA-based variable rate satellite signals, comprising: The parameter calculation module performs FPGA parameter calculations on the satellite signal to be identified and demodulated. Based on the symbol rate and broadband sampling rate of the signal, it outputs preset FPGA parameters, which include the integral comb filter decimation factor, fractional decimation parameters, number of multi-level half-band decimation stages, synchronization sequence waveform, and signal burst length. The digital downconversion module performs digital downconversion calculations based on the preset parameters of the FPGA and outputs narrowband data with 4x oversampling. The identification and demodulation module performs identification and demodulation based on the narrowband data and the preset parameters, and outputs the result of whether the signal was detected and the demodulation result of the detected signal.

[0019] The beneficial effects of this invention are as follows: This invention designs a digital down-conversion processing architecture that supports arbitrary down-conversion rates. By performing digital down-conversion processing on the obtained FPGA preset parameters, it realizes the identification and demodulation of satellite signals with continuously or discretely varying symbol rates. This effectively overcomes the shortcomings of traditional FPGA demodulation, which can only handle fixed or limited preset rates. It avoids demodulation failures caused by rate mismatch, eliminates the high latency and resource waste caused by frequent reload hardware configuration, and significantly improves the continuity of satellite communication links and the data reception success rate. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the method flow of the present invention.

[0021] Figure 2 This is a schematic diagram of the CIC filtering extraction architecture of the present invention.

[0022] Figure 3 This is a schematic diagram of the Farrow filter structure of the present invention.

[0023] Figure 4 This is a schematic diagram of the Gardner algorithm when the timing error of the present invention is 0.

[0024] Figure 5 This is a schematic diagram of the Gardner algorithm when the timing error of the present invention is less than 0.

[0025] Figure 6 This is a schematic diagram of the Gardner algorithm when the timing error is greater than 0.

[0026] Figure 7 This is a schematic diagram of the Costas ring architecture based on the symbolic multiplier of the present invention.

[0027] Figure 8 This is a schematic diagram of the loop filter architecture of the present invention. Detailed Implementation

[0028] The technical solutions in the embodiments of the present invention are clearly and completely described in the following description. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0029] In the description of the embodiments of the present invention, it should be noted that the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the invention is conventionally placed during use, or the orientation or positional relationship in which those skilled in the art conventionally understand it during use. This is only for the convenience of describing the present invention and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of the present invention. Furthermore, the terms "first" and "second" are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0030] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0031] Example 1 Embodiment 1 of the present invention discloses a method for identifying and demodulating variable rate satellite signals based on FPGA, such as... Figure 1 As shown, the details are as follows: Acquire the satellite signal to be identified and demodulated, and output FPGA preset parameters based on the symbol rate and broadband sampling rate of the satellite signal to be identified and demodulated; The preset parameters of the FPGA include the decimation factor of the integral comb filter (CIC), the fractional decimation parameter, the number of decimation stages of the multi-stage half-band filter, the synchronization sequence waveform, and the signal burst length.

[0032] The CIC extraction multiplier is calculated as follows:

[0033] in, Indicates the CIC extraction multiple. Indicates the broadband sampling rate. The symbol rate of the satellite signal. This indicates rounding down to the nearest integer.

[0034] The number of half-band filter decimation levels is calculated as follows:

[0035] in, This is the number of decimation stages for a half-band filter. 4* .

[0036] The fractional extraction parameter is calculated as follows:

[0037]

[0038] in, The input sampling rate is a fractional multiple of the original sampling rate. The output sampling rate is a fractional multiple of the original sampling rate.

[0039] Based on the preset parameters of the FPGA, digital down-conversion processing is performed to output narrowband data with 4x oversampling, as detailed below: like Figure 2 As shown, based on the CIC decimation factor, a 6-stage CIC filter is used in the FPGA to decimate the data, outputting the decimated data. The data transmission rate of the decimated signal is reduced to that of the original signal. ; Based on the number of decimation stages in the multi-stage half-band filter, the decimated data undergoes multi-stage half-band filtering in the FPGA, outputting filtered and decimated data. The data transmission rate of the decimated signal is reduced to the data rate output after decimation by a 6-stage CIC filter. ; Specifically, the half-band filter used in the half-band decimation is a finite impulse response filter, whose frequency response satisfies the symmetry between the passband and stopband about half the Nyquist frequency and the sum of the gains at the corresponding frequencies is always 1. This characteristic makes the impulse response coefficient of the filter close to 0 at half the frequency. The inverse sinc compensation characteristic is superimposed on the half-band filter, which improves the high-frequency components in the passband and eliminates the passband roll-off introduced by the CIC filter, thereby improving the flatness of the passband.

[0040] Based on the fractional decimation parameters, the filtered data is subjected to Farrow filtering to output the fractionally decimated data, which is the 4x oversampled narrowband data; specifically as follows:

[0041] in, The digital input signal to the Farrow filter is the filtered and decimated data. The output signal after fractional decimation. The sampling interval of the output signal, i.e. , The sampling interval of the input signal, i.e. ; make Integer multiples of , The decimal part is , . The original data point closest to the interpolation point. This represents the distance between the interpolation point and the original data point.

[0042] In this embodiment, to facilitate hardware implementation, the filter length is limited to [value missing]. .

[0043]

[0044] Constructing filters using polynomials Substituting these values ​​into the above formula, we obtain the final result:

[0045] in, For the filter coefficients, the above formula is implemented using a single-channel Farrow structure, such as... Figure 3 As shown.

[0046] The filter coefficients are fixed values, and the delay parameter is changed. The interpolation position can be changed without real-time adjustments. Perform the calculation.

[0047] In this embodiment, the Farrow filter coefficients are obtained according to the Lagrange interpolation formula, as follows:

[0048]

[0049] in, Let be the order of the Lagrange interpolation, and also the minimum number of points required for interpolation. Comparing the above formulas, we can see that when... hour, Farrow filter coefficients , Delay for decimals .

[0050] In the FPGA implementation of this embodiment, an 8-point Farrow filter is used, resulting in:

[0051] in, As the initial input sampling points, the matrix The input is the initial data point matrix, and the output is the filtered and extracted data matrix. for The Lagrange coefficient matrix, matrix As a fractional delay matrix This is the output after interpolation. This formula indicates that interpolation at the corresponding position can be achieved by determining the decimal delay.

[0052] The output narrowband data with 4x oversampling is subjected to low-pass filtering to output filtered data; wherein the coefficients of the low-pass filtering are pre-simulated, generated and stored in the FPGA.

[0053] Based on the narrowband data and the preset parameters, identification and demodulation are performed, and the result of whether the signal was detected and the demodulation result of the detected signal are output, as follows: In the FPGA, the output fractionally decimated data is subjected to matched filtering, and the filtered data is output. The matched filter coefficients are pre-simulated, generated, and stored in the FPGA. Based on the synchronization sequence waveform, differential correlation processing is performed on the filtered data in the FPGA to detect whether the correlation result is greater than the set correlation peak threshold. Based on the comparison result, it is identified whether it is the current satellite signal. The position of the maximum peak value is detected through the correlation result to determine the accurate start position of the signal. The differential correlation processing is as follows:

[0054]

[0055] in, This represents the received signal after matched filtering. This represents the known synchronization sequence waveform of the configuration. Represents the difference correlation length. The value is different from 0 and , This is the final normalized output value of the differential correlation.

[0056] Based on the signal burst length and the maximum peak position, the filtered data is processed by taking one point every four points, starting from the maximum peak position, as the symbol synchronization output data; In this embodiment, the symbol synchronization algorithm used in the symbol synchronization output process is the Gardner algorithm, as detailed below: Assuming each symbol in the matched filter output has two sampling points, its timing error estimate is:

[0057] in, This is a value representing the timing error. For timing error, It is the moment of judgment. and Sample values ​​of each symbol I / Q channel. Indicates the first and The formula uses the intermediate sampled values ​​of two symbol points and the intermediate sampled points in between, meaning the input data rate for error detection is twice the symbol rate. Figure 4 The image shows the Gardner algorithm under different timing errors.

[0058] from Figure 4 From this, we can see that when Less than 0, intermediate sample value When the value is 0, the timing error is 0, indicating that the sampling is correct; from Figure 5 From this, we can see that when Less than 0, intermediate sample value When the value is greater than 0, the timing error value is less than 0, indicating advance sampling; from Figure 6 From this, we can see that when Less than 0, intermediate sample value When the value is less than 0, the timing error value is greater than 0, indicating delayed sampling. This shows that different sampling deviations cause different timing error values, thus requiring adjustment of the direction.

[0059] In this embodiment, since the relevant maximum value is the initial point of the optimal sampling point, symbol synchronization directly takes one point every four points starting from the maximum peak position, thereby reducing the complexity of FPGA engineering implementation.

[0060] Carrier synchronization calculation is performed on the output data, and demodulated constellation point data is output. like Figure 7 As shown, in this embodiment, the carrier synchronization algorithm for carrier synchronization calculation is a Costas ring based on a symbol multiplier; The main working principle of the Costas ring is to estimate the carrier frequency offset through closed-loop feedback, thereby completing carrier acquisition and tracking.

[0061] like Figure 8 As shown, the loop filter is the core component of the Costas loop. The loop filter can be used to control the output frequency of the oscillator (NCO), thus enabling frequency capture and tracking of the Costas loop.

[0062] In a phase-locked loop (PLL), loop filtering is a crucial component, and its performance has a significant impact on the overall performance of the entire loop. Figure 8 In the middle, parameters and These are the proportional constant and the integral constant, respectively. Adjusting their values ​​can regulate the characteristics of the loop to enable the carrier synchronization module to capture and track data. and The calculation is as follows:

[0063] in, This is the damping coefficient, typically taken as 0.707; This is the frequency of the loop damped oscillation; For loop gain, The sampling period of the digital system.

[0064] Assume the input signal of the loop filter is Then its output signal is:

[0065] Suppose the input satellite signal is represented in complex form as follows:

[0066] in, Indicates the carrier frequency. Indicates frequency offset. This represents the phase. Assuming no noise, after down-conversion, low-pass filtering, symbol synchronization, and carrier synchronization, the baseband signal with frequency offset can be obtained as follows:

[0067] The real and imaginary parts are respectively:

[0068] Based on the above formula, the output of the phase detector is:

[0069] By inputting the output of the phase detector into the loop filter, a stable phase output can be obtained as the frequency control word of the NCO, thereby realizing carrier frequency acquisition and tracking of the Costas loop.

[0070] The demodulated constellation point data is subjected to constellation mapping calculation, and the demodulated symbol data is output; the constellation mapping is as follows: For an M-PSK constellation diagram, the complex baseband form of an M-ary PSK signal mapped using binary sequential symbols is as follows:

[0071] in, It is the initial phase.

[0072] By performing constellation mapping on the output data, the demodulated symbol data can be obtained:

[0073] For example, the values ​​of the QPSK signal are shown in Table 1 below; Table 1: QPSK Signal Values

[0074] Example 2 Embodiment 2 of the present invention discloses an identification and demodulation system for FPGA-based variable rate satellite signals, based on Embodiment 1 described above, as follows: The parameter calculation module performs FPGA parameter calculations on the satellite signal to be identified and demodulated. Based on the symbol rate and broadband sampling rate of the signal, it outputs preset FPGA parameters, which include the integral comb filter decimation factor, fractional decimation parameters, number of multi-level half-band decimation stages, synchronization sequence waveform, and signal burst length. The digital downconversion module performs digital downconversion calculations based on the preset parameters of the FPGA and outputs narrowband data with 4x oversampling. The identification and demodulation module performs identification and demodulation based on the narrowband data and the preset parameters, and outputs the result of whether the signal was detected and the demodulation result of the detected signal. This invention is not limited to the specific embodiments described above. The invention extends to any new feature or combination disclosed in this specification, as well as any new method or process step or combination disclosed herein.

Claims

1. A method for identifying and demodulating variable-rate satellite signals based on FPGA, characterized in that, include: Acquire the satellite signal to be identified and demodulated, and output FPGA preset parameters based on the symbol rate and broadband sampling rate of the satellite signal to be identified and demodulated; The preset parameters of the FPGA include the integral comb filter decimation factor, fractional decimation parameter, number of decimation stages of the multi-stage half-band filter, synchronization sequence waveform, and signal burst length; Based on the preset parameters of the FPGA, digital down-conversion processing is performed to output narrowband data oversampled by a preset factor, as follows: Based on the decimation factor of the integral comb filter, a 6-level CIC filter is used in the FPGA to decimate the data and output the decimated data. Based on the number of multi-level half-band filtering extraction stages, the extracted data is subjected to multi-level half-band filtering extraction in the FPGA, and the filtered data is output. Based on the fractional extraction parameters, the filtered data is subjected to Farrow filtering to output the fractional extracted data. Based on the narrowband data and the preset parameters, identification and demodulation are performed, and the result of whether the signal was detected and the demodulation result of the detected signal are output. The identification and demodulation are specifically as follows: In the FPGA, the output data after fractional decimation is subjected to matched filtering, and the filtered data is output. Based on the synchronization sequence waveform, differential correlation processing is performed on the filtered data in the FPGA to detect whether the correlation result is greater than the set correlation peak threshold. Based on the comparison result, it is identified whether it is the current satellite signal. The position of the maximum peak value is detected through the correlation result to determine the accurate start position of the signal. Based on the signal burst length and the position of the maximum peak, the filtered data is processed by taking one point every four points, starting from the position of the maximum peak, as the symbol synchronization output data; Carrier synchronization calculation is performed on the output data, and demodulated constellation point data is output. Perform constellation mapping calculations on the demodulated constellation point data and output demodulated symbol data.

2. The FPGA-based variable-rate satellite signal identification and demodulation method according to claim 1, characterized in that, Also includes: The output data after fractional extraction is subjected to low-pass filtering, and the filtered data is output.

3. The FPGA-based variable-rate satellite signal identification and demodulation method according to claim 1, characterized in that, The filtered data is then subjected to Farrow filtering, as follows: Acquire the digital signal input to the Farrow filter and the output signal after fractional decimation, and determine the relationship between the sampling interval of the output signal and the sampling interval of the input signal; The integer multiple of the output signal sampling interval is used as the initial sampling point index, and the fractional part of the ratio of the output signal sampling interval to the input signal sampling interval is used as the distance between the interpolation point and the nearest original data point, i.e., the fractional delay parameter. Set the filter length, construct a polynomial filter, and obtain the output signal by weighting the polynomial with the fractional delay parameter as a variable and the neighboring input data points.

4. The FPGA-based variable-rate satellite signal identification and demodulation method according to claim 3, characterized in that, The polynomial coefficients of the polynomial filter are obtained as follows: The interpolation result is obtained by using the Lagrange interpolation method, based on the sum of the products of the function values ​​of each interpolation node and the corresponding Lagrange basis functions. The Lagrange basis function is expanded with the interpolation position as the variable, and the polynomial coefficients are extracted as the fixed coefficients of the Farrow filter. The interpolation position is used as the fractional delay parameter.

5. The method for identifying and demodulating FPGA-based variable-rate satellite signals according to claim 1, characterized in that, The differential correlation processing is calculated as follows: in, The received signal after matched filtering. Given the waveform of the synchronization sequence, For the differential correlation length, For the difference interval, The value is different from 0 and , This is the final normalized output value of the differential correlation.

6. The method for identifying and demodulating FPGA-based variable-rate satellite signals according to claim 1, characterized in that, The symbol synchronization employs the Gardner algorithm, and the timing error estimation is as follows: in, This is a value representing the timing error. For timing error, It is the moment of judgment. and Sample values ​​of each symbol I / Q channel. Indicates the first and The intermediate sample value of each symbol.

7. A variable-rate satellite signal identification and demodulation system based on FPGA, characterized in that, include: The parameter calculation module performs FPGA parameter calculations on the satellite signal to be identified and demodulated. Based on the symbol rate and broadband sampling rate of the signal, it outputs FPGA preset parameters, which include the integral comb filter decimation factor, fractional decimation parameters, multi-stage half-band filter decimation level, synchronization sequence waveform, and signal burst length. The digital downconversion module performs digital downconversion calculations based on the preset parameters of the FPGA and outputs narrowband data with 4x oversampling, as detailed below: Based on the decimation factor of the integral comb filter, a 6-level CIC filter is used in the FPGA to decimate the data and output the decimated data. Based on the number of multi-level half-band filtering extraction stages, the extracted data is subjected to multi-level half-band filtering extraction in the FPGA, and the filtered data is output. Based on the fractional extraction parameters, the filtered data is subjected to Farrow filtering to output the fractional extracted data. Based on the narrowband data and the preset parameters, identification and demodulation are performed, and the result of whether the signal was detected and the demodulation result of the detected signal are output. The identification and demodulation module performs identification and demodulation based on the narrowband data and the preset parameters, and outputs the result of whether the signal was detected and the demodulation result of the detected signal. The identification and demodulation are specifically as follows: In the FPGA, the output data after fractional decimation is subjected to matched filtering, and the filtered data is output. Based on the synchronization sequence waveform, differential correlation processing is performed on the filtered data in the FPGA to detect whether the correlation result is greater than the set correlation peak threshold. Based on the comparison result, it is identified whether it is the current satellite signal. The position of the maximum peak value is detected through the correlation result to determine the accurate start position of the signal. Based on the signal burst length and the position of the maximum peak, the filtered data is processed by taking one point every four points, starting from the position of the maximum peak, as the symbol synchronization output data; Carrier synchronization calculation is performed on the output data, and demodulated constellation point data is output. Perform constellation mapping calculations on the demodulated constellation point data and output demodulated symbol data.

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