A multi-protocol supported vehicle optical fiber communication network system

Abstract

The application discloses a vehicle optical fiber communication network system supporting multiple protocols, comprising a network controller NC node and multiple network terminal NT nodes, wherein the NC node and the NT node each comprise a node board card integrated with a multiple protocol processing engine, and the internal logic of an FPGA chip in the node board card is configured to perform the following: receiving and identifying Ethernet data, CAN data and RS485 data from various heterogeneous data interfaces; encapsulating and recombining the identified data into internal data frames containing a protocol type identification field according to a unified frame format; sending the encoded data through an optical module; restoring the internal data frames when receiving, and distributing the internal data frames according to the protocol type to restore original protocol signals. The application also realizes differentiated scheduling of different protocol data. The application realizes hardware-level integrated transmission of multiple protocol data on a single node board card, eliminates an external protocol conversion gateway, simplifies a network architecture, reduces system complexity and data transmission delay, and improves network resource utilization and system expansion flexibility.

Description

Technical Field

[0001] This invention relates to the field of optical fiber communication technology, specifically to a vehicle optical fiber communication network system that supports multiple protocols, and more particularly to a vehicle-mounted optical fiber communication network system that can integrate and transmit Ethernet, Controller Area Network and RS485 signals under a unified optical fiber network architecture. Background Technology

[0002] In-vehicle communication networks are evolving towards higher bandwidth, lower latency, and stronger anti-interference capabilities. Fiber optic communication, due to its significant advantages such as high bandwidth, light weight, and resistance to electromagnetic interference, is being widely used in in-vehicle platforms.

[0003] In existing technologies, vehicle-mounted fiber optic communication network nodes mostly adopt a board architecture based on network controllers (NC) and network terminals (NT), and implement command / response communication based on specific protocols (such as FC-AE-1553). However, this architecture has the following technical problems: First, its design is mainly for a single protocol and cannot directly and efficiently handle common heterogeneous data protocols in vehicles, such as Ethernet, Controller Area Network (CAN), and RS485. This necessitates the introduction of external protocol conversion gateways or interface cards during actual system integration, which not only significantly increases system complexity, cost, and physical space occupation, but also introduces additional data transmission latency. Second, when connecting low-speed devices (such as RS485 devices), the high-speed processing capabilities of the single-protocol NT node board are wasted, resulting in resource mismatch. Finally, the system has poor scalability. When new types or new protocol devices need to be connected, it is often necessary to redesign or replace the entire node board, resulting in low flexibility and high maintenance costs.

[0004] Therefore, there is an urgent need in this field for a method and system that can natively integrate the processing capabilities of multiple vehicle-mounted heterogeneous protocols on a single fiber optic network node hardware platform, in order to simplify network architecture, reduce costs, improve data transmission efficiency, and enhance system scalability. Summary of the Invention

[0005] The present invention aims to solve the technical problems of existing vehicle-mounted fiber optic communication network node boards that only support a single protocol, which leads to the need to rely on external gateways when processing heterogeneous data of multiple protocols, resulting in high system complexity, high cost, high latency, low resource utilization and poor scalability.

[0006] To address the aforementioned technical problems, this invention provides a vehicle fiber optic communication network system supporting multiple protocols, comprising a network controller (NC) node and multiple network terminal (NT) nodes.

[0007] The NC node is connected to the vehicle's integrated electronic control box, and each NT node is connected to different devices in the vehicle. The NC node and multiple NT nodes form a bus topology network through optical fibers.

[0008] The NC node and each NT node include a node board with an integrated multi-protocol processing engine; the node board includes a field-programmable gate array (FPGA) chip, an optical module connected to the FPGA chip, and at least one heterogeneous data interface connected to the FPGA chip for connecting to external devices, the heterogeneous data interface including an Ethernet interface, a CAN bus interface and an RS485 interface.

[0009] The internal logic of the FPGA chip is configured to perform the following operations:

[0010] Data reception and identification: Receive different types of protocol data from each of the heterogeneous data interfaces, and identify Ethernet data, CAN data and RS485 data according to the source interface or data frame header;

[0011] Data Reassembly and Unified Mapping: The identified protocol data is encapsulated and reassembled according to a preset internal unified frame format, and uniformly mapped into an internal data frame suitable for optical fiber transmission; the internal unified frame format includes a frame header, a protocol type identifier field, a data payload field, and a check field.

[0012] Unified encoding and transmission: The internal data frame is encoded in 8B / 10B and converted into a high-speed current mode logic CML serial signal, which is then transmitted to the optical fiber network through the optical module;

[0013] Optical signal reception and decoding: The optical module receives optical signals from the optical fiber network, converts them into high-speed differential electrical signals, and then performs 8B / 10B decoding to restore the internal data frames;

[0014] Data demapping and distribution: Based on the protocol type identifier field in the restored internal data frame, the data payload is demapped and distributed to the corresponding protocol processing logic to restore the original Ethernet, CAN or RS485 signal, and output to the connected device through the corresponding heterogeneous data interface.

[0015] As a preferred technical solution, the internal logic of the FPGA chip is further configured to: at the network control level, adaptively modify the command / response communication mechanism based on the FC-AE-1553 protocol to achieve differentiated scheduling and encapsulation of data from different protocols;

[0016] In this process, RS485 data is configured as the first priority in scheduling and continuously broadcast from the NC node to each NT node. In terms of encapsulation, it is mapped as a broadcast internal data frame, and the destination address of its frame header is the broadcast address.

[0017] The CAN data is configured as the second priority in scheduling and mapped to an identifiable internal data frame in encapsulation. The frame header contains the CAN frame identifier (ID) and frame length information.

[0018] Ethernet data is configured as the third priority in scheduling and mapped to a full-payload internal data frame in encapsulation. Its payload field is used to carry a complete Ethernet UDP frame containing the destination MAC address, source MAC address, protocol type, and CRC checksum.

[0019] As a preferred technical solution, the specific configuration of the transmitting end processing link of each protocol signal in the node board is as follows:

[0020] For gigabit Ethernet signals, the Ethernet physical layer PHY chip first outputs a high-speed SERDES signal, which is then decoded by the FPGA's Gigabit transceiver GTX interface in 8B / 10B before entering the data recognition and reconstruction logic. The reconstructed data is then encoded by the FPGA's GTX interface in 8B / 10B into a CML high-speed serial signal to drive the optical module to emit light.

[0021] For RS485 signals, they are first converted into Universal Asynchronous Receiver / Transmitter (UART) signals by the serial interface chip, and then enter the data identification and reconstruction logic. The reconstructed data is then encoded into CML high-speed serial signals by 8B / 10B through the FPGA's GTX interface to drive the optical module to emit light.

[0022] For CAN signals, the data is first processed by a level conversion chip and then enters the data recognition and reconstruction logic. The reconstructed data is then encoded into a CML high-speed serial signal by 8B / 10B through the FPGA's GTX interface to drive the optical module to emit light.

[0023] As a preferred technical solution, the specific configuration of the receiving end processing link for each protocol signal in the node board is as follows:

[0024] The optical module converts the received optical signal into a high-speed differential electrical signal, then decodes it into an 8B / 10B signal via the FPGA's GTX interface, and finally the data demapping and distribution logic distinguishes and processes the signal based on the protocol type identifier field in the internal data frame.

[0025] When identified as Ethernet data, the data payload is demapped and sent to the Ethernet MAC layer module, and then restored to a gigabit Ethernet signal output by the PHY chip;

[0026] When identified as CAN data, the data payload is demapped and the CAN frame identifier, frame length, and frame data are extracted. The data is then converted back into a CAN bus signal output by a level conversion chip.

[0027] When the data is identified as RS485, the UART signal is extracted after demapping the data payload and then restored to an RS485 differential signal output via the serial interface chip.

[0028] As a preferred technical solution, after the NC node is powered on, it executes a node polling state machine and manages data transmission requests in the network by sending command frames to each NT node and receiving status frames; the data exchange modes include NC to NT mode, NT to NT mode and NT to NC mode.

[0029] As a preferred technical solution, the optical receiving module of the node board has a sensitivity of -15dBm, a maximum saturated optical power of 0dBm, and an allowable dynamic range of 15dB; the estimated total optical loss of the in-vehicle all-optical network is 9.2dB, and the system has a 5.8dB optical power fluctuation redundancy.

[0030] As a preferred technical solution, the protocol type identifier field in the internal unified frame format is used to distinguish whether the protocol type carried by the internal data frame is Ethernet, CAN or RS485 during demapping; the value of the protocol type identifier field corresponds one-to-one with the source heterogeneous data interface type.

[0031] Beneficial effects

[0032] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0033] 1. High integration and simplified architecture: By directly integrating a multi-protocol processing engine inside the FPGA of the NC and NT node boards, hardware-level identification, reassembly and unified mapping transmission of Ethernet, CAN and RS485 data are realized on a single board. This eliminates the need for external protocol conversion gateways or interface cards that must be used in traditional solutions, fundamentally simplifying the architecture of the vehicle fiber optic communication network and reducing the system space occupation and complexity.

[0034] 2. Direct Data Flow, Reduced Latency: An end-to-end direct path is established from the heterogeneous data interface to the fiber optic transmission channel, eliminating the need for multiple electrical-protocol conversion-electrical processes in external devices. This invention completes protocol identification and unified encapsulation within the FPGA, directly performing 8B / 10B encoding and photoelectric conversion, eliminating intermediate steps, significantly reducing data transmission latency, and improving communication real-time performance and efficiency.

[0035] 3. Flexible Resources and Strong Scalability: The NT node board of this invention features multi-protocol interfaces and flexible data processing capabilities driven by software. Through FPGA logic reconfiguration, a single NT board can efficiently serve devices connected to it using different protocols, avoiding the resource waste caused by using a high-speed single-protocol board for low-speed devices. When the system needs to add or upgrade devices, only software configuration is required to adapt to the new protocol; there is no need to replace the hardware board, greatly improving the system's scalability and maintenance flexibility.

[0036] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0037] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0038] Figure 1 This is a schematic diagram of the composition of a vehicle fiber optic communication network system.

[0039] Figure 2 This is a schematic diagram of the components of an in-vehicle all-optical network system.

[0040] Figure 3 This is a schematic diagram of the components of an optical fiber communication network system.

[0041] Figure 4 This is a schematic diagram of the hardware components of the in-vehicle fiber optic communication network node.

[0042] Figure 5 This is a schematic diagram of the optical path connection of the in-vehicle optical network node.

[0043] Figure 6 This is a schematic diagram of the software composition of the in-vehicle fiber optic communication network nodes.

[0044] Figure 7 This is a schematic diagram of the operation of the in-vehicle fiber optic communication network node software. Detailed Implementation

[0045] The embodiments of the present invention are described in detail below. These embodiments are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0046] (I) System Overall Architecture

[0047] This embodiment provides a multi-protocol vehicle fiber optic communication network system. The system consists of an in-vehicle all-optical network and an inter-vehicle fiber optic Ethernet network. The in-vehicle all-optical network is composed of multiple network nodes, enabling all-optical network communication between devices within the vehicle. Specifically, the system includes a network controller (NC) node and multiple network terminal (NT) nodes (such as NT1, NT2, NT3, and NT4), forming a bus-like topology. Figure 1 As shown, optical network node 1 includes network terminals such as in-vehicle optical network node control box 1, in-vehicle optical network node control box 2, in-vehicle optical network node control box 3, and in-vehicle optical network node control box 4; optical network node 3 includes optical transceiver 1 and optical transceiver 2. In-vehicle optical network node control boxes 1-4 receive data and video information from their respective control boxes, complete electro-optical conversion, and then transmit the data and video information to optical network node 2 via optical fiber network. Optical network node 2 transmits the optical information from in-vehicle optical network node control boxes 1-4 to optical transceiver 1 via optical fiber. Optical transceiver 1 converts the received optical information into electrical signals and transmits them to the various subsystem units via cables. Optical transceiver 1 receives and forwards data from the measurement and control box and provides a test interface.

[0048] The specific components of this network system are: Figure 2 The system consists of five nodes (NC, NT1, NT2, NT3, and NT4) and one optical network node (2). The NC node, or optical transceiver 1, controls and schedules the in-vehicle all-optical network. The optical network node 2 performs optical switching. The four node boards (NT1, NT2, NT3, and NT4) are installed in the optical network node control box 1, the in-vehicle optical network node control box 2, the in-vehicle optical network node control box 3, and the in-vehicle optical network node control box 4, respectively, enabling photoelectric-to-optical conversion and node network access for their respective control boxes. A bus-type topology fiber optic network system connects all devices, constructing the communication network for the entire system and enabling transparent transmission of communication interfaces between devices. The overall scheme adopts time-division multiplexing transmission, with two Ethernet transmissions, bidirectional bus-type CAN data transmission, and unidirectional RS485 signal transmission. Uplink and downlink each use two wavelengths for transmission, with the two wavelengths of signal transmitted in a single optical fiber using wavelength division multiplexing, ensuring the optical signal passes through a rotary contact device.

[0049] (ii) Network data flow

[0050] Figure 3 This diagram illustrates the transmission relationships of data frames in a network. The fiber optic communication network consists of one network switch, one master node, and four slave nodes. The network switch is connected to the master and slave nodes via optical fibers, transmitting three types of heterogeneous data between the master and slave nodes: Ethernet data frames, CAN data frames, and RS485 data frames.

[0051] The Ethernet data frame has a transmission rate of 1Gbps and a frame length of 64 to 1518 bytes, following the UDP protocol. The Ethernet data frame flow is bidirectional and point-to-point. The master node (NC) contains two Ethernet interfaces, which establish bidirectional data transmission channels with the Ethernet interfaces of slave node 1 (NT1) and slave node 2 (NT2), respectively. Slave node 3 (NT3) and slave node 4 (NT4) do not contain Ethernet interfaces in this embodiment.

[0052] The CAN data frame has a transmission rate of 500kbps, is an extended frame type, and has a frame length of 6 to 13 bytes. CAN data frames are transmitted bidirectionally in a broadcast manner, meaning that CAN data can be sent from the CAN interface of any node and broadcast to the CAN interfaces of all other nodes in the network.

[0053] The RS485 data frame has a transmission rate of 9600bps and a variable frame length. The RS485 data frame flows in a one-way broadcast manner, continuously broadcast from the RS485 interface of the master node (NC) to the RS485 interfaces of all slave nodes (NT) to meet its strict real-time requirements.

[0054] (III) Hardware composition of node board and signal processing link

[0055] Figure 4 The hardware composition of the in-vehicle fiber optic communication network nodes in this embodiment is described. The NC node and each NT node contain a node board with the same architecture and an integrated multi-protocol processing engine. This node board is based on a Field-Programmable Gate Array (FPGA) chip; in this embodiment, the selected device is the JFMQL15T485. The external interface chips connected to it include an Ethernet PHY chip, an RS485 interface chip, a CAN level converter chip, and an optical module for driving fiber optic communication.

[0056] The FPGA's bank resources are divided as follows: BANK500, BANK501, and BANK502 are PS section banks, connected to QSPIFlash, responsible for program booting and firmware installation; BANK9, BANK10, BANK11, BANK12, and BANK13 are HR I / O banks, responsible for processing RS485 signals, CAN signals, and some Ethernet signals; BANK33, BANK34, and BANK35 are HP I / O banks, responsible for processing Ethernet RGMII interface signals; BANK109 and BANK110 are MGT high-speed banks, responsible for transmitting and receiving CML high-speed serial signals connected to the optical module.

[0057] The clock configuration in this embodiment is as follows: the PS clock is 33.3MHz, the PL single-ended clock is 50MHz, and the GTX reference clock is a 125MHz differential clock. For power supply, a dedicated power chip provides 1.0V, 1.2V, 1.8V, and 3.3V voltages, with the power-on sequence being 28V→5V→VCC1V0→VCC1V2→VCC1V8→VCC3V3.

[0058] Each protocol signal is processed within the FPGA by an integrated multi-protocol processing engine. The core functional modules of this engine are the "data identification and reassembly" module and the symmetrical "data demapping and distribution" module. Together, these form an end-to-end multi-protocol data pass-through path. The complete processing chain of each protocol signal from the transmitting end to the receiving end is described in detail below.

[0059] (1) Gigabit Ethernet signal processing link

[0060] At the transmitting end, the gigabit Ethernet signal is first output as a high-speed SERDES signal by the Ethernet PHY chip, which then enters the FPGA's GTX interface for 8B / 10B decoding. The decoded parallel data enters the data recognition and reassembly logic. This logic recognizes it as Ethernet data and encapsulates it according to a preset internal unified frame format. A complete Ethernet UDP frame containing the destination MAC address, source MAC address, protocol type, and CRC checksum is loaded into the data payload field, and the corresponding protocol type identifier is written into the frame header, forming an internal data frame. The reassembled internal data frame is then encoded using 8B / 10B via the FPGA's GTX interface, converted into a CML high-speed serial signal, and used to drive the optical module to emit light, converting the electrical signal into an optical signal for transmission into the fiber optic network.

[0061] At the receiving end, the optical module converts the received optical signal into a high-speed differential electrical signal, which is then decoded in 8B / 10B via the FPGA's GTX interface to reconstruct the internal data frame. The data demapping and distribution logic determines whether the frame carries Ethernet data based on the protocol type identifier field in the internal data frame header. It then demaps the data payload and sends it to the Ethernet MAC layer module, where the PHY chip restores it to a standard Gigabit Ethernet signal for output to the connected device.

[0062] (2) CAN signal processing link

[0063] At the transmitting end, the CAN bus signal is first converted into a level signal receivable by the FPGA by the CAN level conversion chip, and then enters the data identification and reassembly logic. This logic identifies it as CAN data and encapsulates it according to the internal unified frame format. The CAN frame identifier (ID) and frame length information are written into the corresponding fields of the frame header, and the CAN frame data (1 to 8 bytes) is loaded into the data payload field to form an internal data frame. The reassembled internal data frame is then encoded in 8B / 10B via the FPGA's GTX interface and converted into a CML high-speed serial signal to drive the optical module to emit light.

[0064] At the receiving end, the optical module converts the received optical signal into a high-speed differential electrical signal, which is then decoded in 8B / 10B via the FPGA's GTX interface to reconstruct the internal data frame. The data demapping and distribution logic determines whether the frame carries CAN data based on the protocol type identifier field in the frame header. It then demaps the data payload, extracts the CAN frame identifier, frame length, and frame data, and restores it to a standard CAN bus differential signal output via a CAN level conversion chip.

[0065] In this embodiment, the delay budget of the CAN signal processing link is as follows: FPGA signal acquisition time t1 is less than 100μs, FPGA parallel-to-serial conversion time t2 is less than 1μs, optical module electro-optical conversion time t3 is less than 0.5μs, optical module photoelectric conversion time t4 is less than 0.5μs, FPGA serial-to-parallel conversion time t5 is less than 1μs, and FPGA signal output time t6 is less than 100μs, which fully meets the requirement that the random delay error of the CAN signal is less than 275μs.

[0066] (3) RS485 signal processing link

[0067] At the transmitting end, the external RS485 differential signal is first converted into a UART signal by the RS485 interface chip, and then enters the data identification and reassembly logic. The RS485 interface chip supports a maximum rate of 10Mbps. The data identification and reassembly logic identifies the UART signal as RS485 data and encapsulates it according to the internal unified frame format to form an internal data frame. The reassembled internal data frame is then encoded in 8B / 10B via the FPGA's GTX interface and converted into a CML high-speed serial signal to drive the optical module to emit light.

[0068] At the receiving end, the optical module converts the received optical signal into a high-speed differential electrical signal, which is then decoded in 8B / 10B via the FPGA's GTX interface to reconstruct the internal data frame. The data demapping and distribution logic determines whether the frame carries RS485 data based on the protocol type identifier field in the frame header. It then demaps the data payload, extracts the UART signal, and restores it to an RS485 differential signal output via the serial interface chip.

[0069] In this embodiment, the delay budget of the RS485 signal processing link is as follows: FPGA signal acquisition time t1 is less than 0.5μs, FPGA parallel-to-serial conversion time t2 is less than 1μs, optical module electro-optical conversion time t3 is less than 0.5μs, optical module photoelectric conversion time t4 is less than 0.5μs, FPGA serial-to-parallel conversion time t5 is less than 1μs, and FPGA signal output time t6 is less than 0.5μs, which fully meets the requirement that the random delay error of RS485 signal is less than 4μs.

[0070] (iv) Unified frame format within the FPGA

[0071] In this embodiment, the internal unified frame format preset within the FPGA is defined by adaptive modification based on the standard FC-AE-1553 protocol frame structure. Its basic structure includes a frame header, a protocol type identifier field, a data payload field, and a check field.

[0072] The protocol type identifier field is the core basis for distinguishing protocol types during demapping. The value of this field corresponds one-to-one with the heterogeneous data interface type of the source. For example, the value can be defined as "01" to represent Ethernet data, "02" to represent CAN data, and "03" to represent RS485 data.

[0073] Depending on the bearer protocol, the encapsulation method of the data payload field also varies: For RS485 data, broadcast encapsulation is used, and the destination address in the frame header is the broadcast address; for CAN data, identifiable encapsulation is used, and the frame header contains the CAN frame identifier (ID) and frame length information; for Ethernet data, full payload encapsulation is used, and the data payload field is used to carry a complete Ethernet UDP frame containing the destination MAC address (6 bytes), source MAC address (6 bytes), protocol type (2 bytes), data area (46 to 1500 bytes), and CRC check (4 bytes).

[0074] (v) Network control and scheduling strategies

[0075] Figure 6 The software functional modules inside the FPGA chip in this embodiment are shown. Its overall architecture is divided into three main parts: fiber optic communication, interface communication, and communication control.

[0076] The fiber optic communication section mainly includes the FC_MAC layer driver module, the FC-1553 protocol processing module, and the AXI_FULL module. The FC_MAC layer driver module is responsible for driving the transmission and reception of the optical module's physical layer. The FC-1553 protocol processing module is the core protocol processing module, and the AXI_FULL module is responsible for mapping FC-1553 protocol data to the AXI bus inside the FPGA.

[0077] The interface communication section mainly consists of an Ethernet MAC layer module, a CAN protocol module, an RS485 protocol module, an RS422 protocol module, and an AXI_FULL to AXI_STREAM conversion module. The AXI_FULL to AXI_STREAM conversion module is responsible for mapping the heterogeneous data interfaces to the internal unified bus data, thus completing the core functions of data identification and reconstruction.

[0078] The communication control section consists of a DMA module, a register control module, a polling control module, and a BRAM control module. The DMA module is responsible for transferring high-bandwidth data between the DDR3 memory and the interface. The register control module configures the registers of each interface in the communication section. The polling control module controls the polling of the NT node and caches the polling results. The BRAM control module handles the transfer and processing of temporary cached data.

[0079] Figure 7 The software operation flow of the system in this embodiment is illustrated. After the system powers on and starts, it initializes according to a pre-programmed procedure and waits for the host computer's online dynamic configuration command for the serial port. Upon arrival of the command, the node polling state machine operates on each node (NC, NT1, NT2, NT3, NT4) according to the command. If a node has no request or only a bandwidth request, it returns to the node polling state machine to continue waiting; if a node requests data transmission, it enters the data transmission state machine.

[0080] The data transmission state machine enters the corresponding data exchange mode based on the judgment. This system supports three exchange modes:

[0081] (1) NC-NT switching mode: Data is sent from the NC node to the target NT node. First, the existing data is written to the buffer, then a command frame is broadcast and a timer is started. The timer length is calculated based on the length of the data packet being transmitted. After sending the data frame, the system waits for a status frame. If the timer times out, the process ends; if a status frame is received, the data transmission is complete.

[0082] (2) NT-NT switching mode: The NC node coordinates the transmission of data from one NT node to another. After receiving the information, the NC node sends command frames to both the sending NT and receiving NT, starts a timer, and waits for a status frame. If the timer times out, the process ends; if a status frame is received, the data transmission is complete.

[0083] (3) NT-NC switching mode: The NT node reports data to the NC node. After receiving the information, the NC node sends a command frame to the sending NT, starts a timer, and waits for a status frame. If the timer times out, the process ends; if a status frame is received, the target data frame is received, and the data transmission is complete.

[0084] (vi) Optical power budget

[0085] Figure 5 The optical path connection of the in-vehicle optical network node in this embodiment is shown. In this embodiment, the maximum saturation optical power of the optical receiving module is 0dBm, and the sensitivity is -15dBm. Therefore, the allowable dynamic range of the receiving end is 15dB.

[0086] A cost estimate is performed on the overall optical link loss: R1 is the insertion loss of the upper-mounted optical network node, taken as 0.5 dB; R2 is the insertion loss of the chassis optical network node, taken as 0.5 dB; C1 is the slip ring connection point loss, taken as 2 dB; C2 and C3 are the external connection point losses, each taken as 0.5 dB on average; T1 is the single-core fiber loss, taken as 0.2 dB on average; α1 is the static loss of the connecting optical cable, taken as 5 dB. The overall optical loss is calculated as the sum of the above items, resulting in an overall optical loss value of 9.2 dB.

[0087] The allowable dynamic range of the in-vehicle all-optical network is 15dB, and the total optical loss is 9.2dB. Therefore, the system has a 5.8dB optical power fluctuation redundancy. This redundancy can effectively cope with optical power fluctuations caused by factors such as temperature changes and vibrations in the vehicle environment, ensuring that the network can still communicate reliably in harsh environments.

[0088] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention without departing from the principles and spirit of the present invention.

Claims

1. A vehicle fiber optic communication network system supporting multiple protocols, characterized in that, It includes one network controller (NC) node and multiple network endpoints (NT) nodes; The NC node is connected to the vehicle's integrated electronic control box, and each NT node is connected to different devices in the vehicle. The NC node and multiple NT nodes form a bus topology network through optical fibers. The NC node and each NT node include a node board with an integrated multi-protocol processing engine; the node board includes a field-programmable gate array (FPGA) chip, an optical module connected to the FPGA chip, and at least one heterogeneous data interface connected to the FPGA chip for connecting to external devices, the heterogeneous data interface including an Ethernet interface, a CAN bus interface and an RS485 interface. The internal logic of the FPGA chip is configured to perform the following operations: Data reception and identification: Receive different types of protocol data from each of the heterogeneous data interfaces, and identify Ethernet data, CAN data and RS485 data according to the source interface or data frame header; Data Reassembly and Unified Mapping: The identified protocol data is encapsulated and reassembled according to a preset internal unified frame format, and uniformly mapped into an internal data frame suitable for optical fiber transmission; the internal unified frame format includes a frame header, a protocol type identifier field, a data payload field, and a check field. Unified encoding and transmission: The internal data frame is encoded in 8B / 10B and converted into a high-speed current mode logic CML serial signal, which is then transmitted to the optical fiber network through the optical module; Optical signal reception and decoding: The optical module receives optical signals from the optical fiber network, converts them into high-speed differential electrical signals, and then performs 8B / 10B decoding to restore the internal data frames; Data demapping and distribution: Based on the protocol type identifier field in the restored internal data frame, the data payload is demapped and distributed to the corresponding protocol processing logic to restore the original Ethernet, CAN or RS485 signal, and output to the connected device through the corresponding heterogeneous data interface.

2. The system according to claim 1, characterized in that, The internal logic of the FPGA chip is further configured to: at the network control level, adaptively modify the command / response communication mechanism based on the FC-AE-1553 protocol to achieve differentiated scheduling and encapsulation of data from different protocols; In this process, RS485 data is configured as the first priority in scheduling and continuously broadcast from the NC node to each NT node. In terms of encapsulation, it is mapped as a broadcast internal data frame, and the destination address of its frame header is the broadcast address. The CAN data is configured as the second priority in scheduling and mapped to an identifiable internal data frame in encapsulation. The frame header contains the CAN frame identifier (ID) and frame length information. Ethernet data is configured as the third priority in scheduling and mapped to a full-payload internal data frame in encapsulation. Its payload field is used to carry a complete Ethernet UDP frame containing the destination MAC address, source MAC address, protocol type, and CRC checksum.

3. The system according to claim 1, characterized in that, The specific configuration of the transmitting end processing link for each protocol signal in the node board is as follows: Gigabit Ethernet signal transmission link: First, the Ethernet physical layer PHY chip outputs a high-speed SERDES signal, which is then decoded by the FPGA's Gigabit transceiver GTX interface in 8B / 10B and enters the data identification and reconstruction logic; the reconstructed data is then encoded into a CML high-speed serial signal by the FPGA's GTX interface in 8B / 10B to drive the optical module to emit light. RS485 signal transmission link: First, the serial port interface chip converts the signal into a Universal Asynchronous Receiver / Transmitter (UART) signal, which then enters the data identification and reconstruction logic. The reconstructed data is then encoded into a CML high-speed serial signal via the FPGA's GTX interface using 8B / 10B encoding to drive the optical module to emit light. CAN signal transmission link: First, the signal is processed by a level conversion chip and then enters the data recognition and reconstruction logic. The reconstructed data is then encoded into a CML high-speed serial signal by 8B / 10B through the FPGA's GTX interface to drive the optical module to emit light.

4. The system according to claim 1 or 3, characterized in that, The specific configuration of the receiving end processing link for each protocol signal in the node board is as follows: The optical module converts the received optical signal into a high-speed differential electrical signal, then decodes it into an 8B / 10B signal via the FPGA's GTX interface, and finally the data demapping and distribution logic distinguishes and processes the signal based on the protocol type identifier field in the internal data frame. When identified as Ethernet data, the data payload is demapped and sent to the Ethernet MAC layer module, and then restored to a gigabit Ethernet signal output by the PHY chip; When identified as CAN data, the data payload is demapped and the CAN frame identifier, frame length, and frame data are extracted. The data is then converted back into a CAN bus signal output by a level conversion chip. When the data is identified as RS485, the UART signal is extracted after demapping the data payload and then restored to an RS485 differential signal output via the serial interface chip.

5. The system according to claim 1 or 2, characterized in that, After the NC node is powered on, it executes the node polling state machine and manages data transmission requests in the network by sending command frames to each NT node and receiving status frames. Data exchange modes include NC to NT, NT to NT, and NT to NC.

6. The system according to claim 1, characterized in that, The optical receiver module of the node board has a sensitivity of -15dBm, a maximum saturated optical power of 0dBm, and an allowable dynamic range of 15dB. The estimated total optical loss of the in-vehicle all-optical network is 9.2dB, and the system has a redundancy of 5.8dB for optical power fluctuation.

7. The system according to claim 1, characterized in that, The protocol type identifier field in the internal unified frame format is used to distinguish whether the protocol type carried by the internal data frame is Ethernet, CAN or RS485 during demapping; the value of the protocol type identifier field corresponds one-to-one with the source heterogeneous data interface type.

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