A TAP-based Ethernet protocol digital transmission method and system

Abstract

The application relates to the technical field of network communication, and discloses an Ethernet protocol digital transmission method and system based on TAP, wherein the method comprises the following steps: performing local clock synchronization calibration; performing hardware timestamp marking; performing pre-output processing delay compensation based on an original data packet mirror copy; performing multi-port timestamp unification based on a correction timestamp; and performing timestamp field encapsulation and mirror frame insertion according to the unified global timestamp. Compared with the prior art, the TAP device relies on a single local clock or static delay parameter to insert a timestamp, and under the conditions of high-speed burst traffic, multi-port mirroring and distributed monitoring, the technical problem that high-precision time correlation between different mirror data streams cannot be realized is solved. Through unified time reference, frame start trigger marking and port offset compensation, high-precision unified timestamp output of the mirror data packet is realized, and the timing accuracy of network monitoring data is improved.

Description

Technical Field

[0001] This invention relates to the field of network communication technology, and in particular to a digital transmission method and system based on the TAP Ethernet protocol. Background Technology

[0002] In the fields of network monitoring, security auditing, and performance analysis, accurate timestamping of network traffic is crucial. Traditional methods typically rely on the monitoring device's own system clock or a simple Network Time Protocol (NTP) for time synchronization, with accuracy often at the millisecond level. These methods are also susceptible to factors such as operating system scheduling and software processing delays, making it difficult to meet the needs for precise sorting and correlation analysis of network events at the microsecond or even nanosecond level.

[0003] Especially when using multi-port TAP devices for high-throughput data mirroring, packets entering from different physical ports and passing through different internal processing paths introduce inconsistent latency. Current technologies lack effective mechanisms to compensate for the variable latency introduced from the physical layer capture point of the packet, through internal queues and switching chip processing, to the output from the monitoring port. This results in the inability to compare the timestamps of packets output from different ports under the same high-precision time base, severely hindering the implementation of advanced applications such as cross-port traffic correlation analysis and distributed system fault root cause localization. Therefore, there is an urgent need for a TAP data transmission scheme that can achieve high-precision clock synchronization at the hardware level, dynamically compensate for internal processing latency, and unify the time output of multiple ports to improve the accuracy and reliability of network visualization. Summary of the Invention

[0004] To address the aforementioned technical shortcomings, the purpose of this invention is to propose a TAP-based Ethernet protocol digital transmission method. This method aims to solve the technical problem that existing TAP devices rely on a single local clock or static delay parameter to insert timestamps, which makes it impossible to achieve high-precision time correlation between different mirrored data streams, especially under conditions of high-speed burst traffic, multi-port mirroring, and distributed monitoring.

[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: The present invention provides a digital transmission method for Ethernet protocol based on TAP.

[0006] The TAP-based Ethernet protocol digital transmission method includes: Step S10: Obtain the PTP master clock interaction message, and perform a local clock synchronization calibration task based on the PTP master clock interaction message using the PI servo clock correction method, and output the local clock time reference. ; Step S20: Obtain a mirror copy of the data packet based on the local clock time base. The hardware timestamp marking task is executed using a frame start delimiter-triggered latching method, and the output contains the marked timestamp. A mirror copy of the original data packets; Step S30: Based on the timestamp with marking The original data packet mirror copy is used to perform a pre-output timestamp preprocessing task using a queuing delay estimation method that correlates packet length with queue depth, and the corrected timestamp is output. ; Step S40: Based on the correction timestamp The multi-port timestamp unification task is performed using a reference port offset measurement method, and a unified global timestamp is output. ; Step S50: Based on the unified global timestamp Perform timestamp field encapsulation and mirror frame insertion, and output a mirror data packet stream with a unified timestamp.

[0007] Preferably, in step S10, a PTP master clock interaction message is obtained, and a local clock synchronization calibration task is performed using the PI servo clock correction method based on the PTP master clock interaction message, and a local clock time reference is output. The steps specifically include: Step S101: Parse the PTP master clock interaction message and extract the master clock transmission time. Receive time from clock Send time from clock and master clock receiving time ; Step S102: Based on the master clock transmission time Receive time from clock Send time from clock and master clock receiving time Calculate master-slave path latency Master-slave clock offset ; Step S103: Offset the master-slave clock The input PI servo clock corrector performs phase and frequency correction on the local crystal oscillator count value of the TAP device to obtain the local clock time base. .

[0008] Preferably, in step S20, a mirror copy of the data packet is obtained based on the local clock time reference. The hardware timestamp marking task is executed using a frame start delimiter-triggered latching method, and the output contains the marked timestamp. The steps for creating a mirror copy of the original data packets specifically include: Step S201: Copy the bidirectional Ethernet data frames in the link through the TAP physical layer interface to obtain a mirror copy of the data packets; Step S202: When the Start-of-Frame Delimiter (SFD) of the data packet mirror copy is detected, the hardware latch unit is triggered to read the local clock time base. The corresponding current count value yields the original hardware timestamp. ; Step S203: Utilize the fixed delay compensation amount pre-stored in the delay calibration register Correct the original hardware timestamp Get the marked timestamp and the marked timestamp Bind to the image copy of the data packet, and output with a tagged timestamp. A mirror copy of the original data packets.

[0009] Preferably, in step S203, the fixed delay compensation amount The timestamp is the sum of the frame start delimiter detection circuit delay, the physical layer receive path signal propagation delay, and the hardware latch trigger delay. It is obtained according to the following formula: ; in, The value ranges from 60ns to 70ns.

[0010] Preferably, in step S30, based on the timestamp with markings... The original data packet mirror copy is used to perform a pre-output timestamp preprocessing task using a queuing delay estimation method that correlates packet length with queue depth, and the corrected timestamp is output. The steps specifically include: Step S301: From the time stamped item Extract the current packet length from the original packet mirror copy ; Step S302: Combine with the current output port processing rate and current output queue depth Calculate the processing delay of the data packet mirror copy from the timestamp marker point to the output port. ; Step S303: Utilize the processing delay For the marked timestamp Compensation is performed to obtain the corrected timestamp. .

[0011] Preferably, in step S302, the processing delay Calculate using the following formula: ; in, As a benchmark for hardware processing latency, The current data packet length, This represents the current output port processing rate. This represents the current output queue depth. Queue latency factor adjusted based on real-time throughput; In step S303, the correction timestamp It is obtained according to the following formula: ; Preferably, in step S40, based on the correction timestamp The multi-port timestamp unification task is performed using a reference port offset measurement method, and a unified global timestamp is output. The steps specifically include: Step S401: Select one monitoring port from the multi-port TAP device as the reference port, and set the local clock time base. The corresponding clock signal is distributed to each monitoring port; Step S402: Send offset measurement frames between each monitoring port and the reference port to measure the offset of the first monitoring port. Port time offset of each monitoring port relative to the reference port ; Step S403: Based on the port time offset The correction timestamp for the corresponding monitoring port Alignment is performed to obtain a unified global timestamp. ; Among them, the unified global timestamp It is obtained according to the following formula: ; in, For the first Port time offset of each monitoring port relative to the reference port.

[0012] The present invention also provides a TAP-based Ethernet protocol digital transmission system comprising: The clock synchronization calibration module is used to acquire PTP master clock interaction messages, perform local clock synchronization calibration tasks based on the PTP master clock interaction messages using the PI servo clock correction method, and output a local clock time reference. ; The image packet timestamp module is used to obtain a mirror copy of the data packet based on the local clock time reference. The hardware timestamp marking task is executed using a frame start delimiter-triggered latching method, and the output contains the marked timestamp. A mirror copy of the original data packets; The output delay compensation module is used to compensate for delays based on the timestamp marked on the output. The original data packet mirror copy is used to perform a pre-output timestamp preprocessing task using a queuing delay estimation method that correlates packet length with queue depth, and the corrected timestamp is output. ; A multi-port time unification module is used to base the time on the corrected timestamp. The multi-port timestamp unification task is performed using a reference port offset measurement method, and a unified global timestamp is output. ; The timestamp encapsulation and output module is used to encapsulate and output the unified global timestamp. Perform timestamp field encapsulation and mirror frame insertion, and output a mirror data packet stream with a unified timestamp.

[0013] The present invention also provides a TAP-based Ethernet protocol digital transmission device, the TAP-based Ethernet protocol digital transmission device comprising: a memory, a processor, and a TAP-based Ethernet protocol digital transmission program stored in the memory and executable on the processor, wherein the TAP-based Ethernet protocol digital transmission program implements the above method when executed by the processor.

[0014] The present invention also provides a computer program product, the computer program product including a TAP-based Ethernet protocol digital transmission program, which implements the above method when executed by a processor.

[0015] The beneficial effects of this invention are as follows: This invention introduces a PTP-based PI servo clock correction mechanism to establish a highly stable and accurate local time reference for TAP devices, fundamentally solving the problem of insufficient clock synchronization accuracy and providing a reliable time source for all subsequent timestamp operations.

[0016] This invention achieves precise marking of data packet arrival times at the physical layer by combining hardware-triggered latching of Start-of-Frame Delimiter (SFD) with fixed delay compensation, avoiding the large and unstable delay of software timestamps and significantly improving the original accuracy and consistency of timestamps.

[0017] This invention establishes a dynamic delay estimation model that correlates packet length, port processing rate, and queue depth, effectively compensating for the processing delay of data packets within the TAP device. This allows the output timestamp to more accurately reflect the arrival time of the data packets on the original link, eliminating the time distortion caused by internal processing within the device. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating a first embodiment of a TAP-based Ethernet protocol digital transmission method according to the present invention. Figure 2 This is a comparative analysis diagram of the clock synchronization error surface and time series of a TAP-based Ethernet protocol digital transmission method according to the present invention. Figure 3 This is a comparison diagram of the three-dimensional surface of the dynamic delay model and the delay compensation residual of the TAP-based Ethernet protocol digital transmission method of the present invention. Figure 4 This invention presents a bubble chart and an error distribution histogram for the output data packet timestamp accuracy of a TAP-based Ethernet protocol digital transmission method. Detailed Implementation

[0019] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0020] Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Example 1: As Figure 1 The diagram shown is a flowchart of a first embodiment of a TAP-based Ethernet protocol digital transmission method according to the present invention, which presents a first embodiment of a TAP-based Ethernet protocol digital transmission method according to the present invention.

[0022] In the first embodiment, the TAP-based Ethernet protocol digital transmission method includes: Step S10: Obtain the PTP master clock interaction message, and perform a local clock synchronization calibration task based on the PTP master clock interaction message using the PI servo clock correction method, and output the local clock time base Tbase. In this step, "PTP master clock interaction messages" specifically refers to synchronization messages conforming to the IEEE 1588 Precision Time Protocol (PTP), such as Sync, Follow_Up, Delay_Req, and Delay_Resp messages, used to exchange precise time information between the master clock (Grandmaster) and the slave clock (this TAP device). "PI servo clock correction method" refers to a proportional-integral control algorithm whose input is the calculated master-slave clock offset. By adjusting the drive signal of the local voltage-controlled crystal oscillator (VCXO) or digital phase-locked loop (DPLL), closed-loop adjustment of the local clock phase and frequency is achieved, thereby outputting a highly stable "local clock time base Tbase." This Tbase is a continuously increasing high-resolution count value, serving as the source and reference for all subsequent hardware timestamp markings.

[0023] This step lays the foundation for high-precision timing throughout the invention. By parsing PTP messages and applying PI control, this TAP device is no longer an isolated clock source, but can closely track the authoritative master clock in the network, improving its own clock accuracy to sub-microsecond or even nanosecond levels. This ensures that subsequent timestamps are globally comparable, rather than just relative times within the device.

[0024] Compared to traditional TAP devices that rely solely on their own crystal oscillator or software NTP synchronization (which typically has millisecond-level accuracy and is highly susceptible to system load), this step achieves precise hardware-level clock synchronization. Traditional methods cannot eliminate long-term clock drift and short-term jitter, leading to large accumulated timestamp errors under long-term monitoring and time misalignment between different devices. The PI servo correction of this invention can dynamically compensate for clock skew and frequency deviations. Even under asymmetrical network path delays, it can calculate and correct accurate offsets through PTP message exchange, thereby obtaining a stable, reliable, and highly accurate time reference synchronized with the network master clock.

[0025] For example, in a financial transaction data center, nanosecond-level precision is required to pinpoint the arrival order of all transaction instructions across the network. This TAP device is deployed next to the core switch link. Through step S10, the TAP device synchronizes its time with the PTP Grandmaster clock source deployed in the same data center. Even if the TAP device's own crystal oscillator has initial errors and drift due to temperature changes, the PI server can continuously fine-tune it to ensure that Tbase and Grandmaster time remain highly consistent. In this way, subsequent transaction data packets mirrored from different switch links will all have timestamps based on the same authoritative, high-precision clock source, making it possible to analyze the causal relationships between transaction instructions.

[0026] Step S20: Obtain a mirror copy of the data packet, and execute the hardware timestamp marking task using the frame start delimiter triggered latch method based on the local clock time reference, and output the original data packet mirror copy with the marked timestamp; In this step, the "data packet mirror copy" refers to the original Ethernet data frame bitstream that is losslessly copied from the monitored network link through the physical layer interface (such as an optical splitter or electrical coupler) of the TAP device. The "Frame Start Delimiter (SFD) Triggered Latch" is a hardware circuit design. When the physical layer chip detects the SFD field (fixed to 0xD5) of the data frame, it immediately generates a hardware trigger signal, controlling a latch to instantly capture the instantaneous count value corresponding to the "local clock time base Tbase." This value is the "raw hardware timestamp Traw." Subsequently, the Traw is additively corrected using a "fixed delay compensation amount Cfix" (mainly including the SFD detection circuit delay, the PHY chip internal signal propagation delay, and the path delay from the trigger signal to the latch) pre-calibrated and stored in a register, resulting in the final "tagged timestamp Tstamp," which is then bound to the data packet mirror copy as metadata.

[0027] Understandably, this step assigns a high-precision timestamp to the data packet at the very beginning of its processing flow within the TAP device, i.e., at the physical layer. Hardware triggering ensures strict synchronization between the timestamp marking action and the arrival of the packet's specific bit (SFD), resulting in extremely low latency and deterministic timing. This guarantees a high degree of consistency in the timestamp marking point (always matching the SFD arrival time), providing an accurate starting reference point for subsequent delay compensation.

[0028] It should be understood that, compared to software timestamp schemes (timestamping at the network card driver layer or in the operating system kernel network stack), the hardware marking method in this step eliminates the unpredictable and often significant latency (ranging from a few microseconds to hundreds of microseconds) caused by operating system scheduling, interrupt handling, and context switching. Software timestamps have large jitter and are not suitable for high-precision analysis. This invention uses dedicated hardware circuitry at the physical layer to reduce the marking latency to the nanosecond level and essentially fix it, greatly improving the original accuracy and reliability of the timestamp, making the timestamp more accurately reflect the actual arrival time of data packets on the link.

[0029] For example, when monitoring a VoIP voice stream, it's necessary to analyze the end-to-end jitter of each voice data packet. Traditional software solutions only timestamp the data packet after it arrives at the network card, generates an interrupt, and is processed by the driver. This processing can be delayed by tens of microseconds due to system busyness, leading to severe distortion in the calculated network jitter. In this invention, however, the hardware circuit immediately latches the time the moment the SFD bit of the voice data packet arrives at the TAP physical interface. The entire process is completed within nanoseconds with a fixed delay. The resulting timestamp is almost the actual moment the data packet arrives at the link, making the calculated network jitter value accurate and reliable.

[0030] Step S30: Based on the original data packet mirror copy with the marked timestamp, perform the pre-output timestamp preprocessing task using the queuing delay estimation method that associates packet length with queue depth, and output the corrected timestamp; This step addresses the uncertain delay experienced by data packets after they are timestamped (Tstamp) and while they wait for processing and queuing within the TAP device until they are sent out from the designated monitoring port. This delay is dynamic and mainly depends on the "current data packet length L" (affecting serialization transmission time), the "current output port processing rate R" (port bandwidth), and the "current output queue depth Qlen" (reflecting instantaneous congestion). A dynamic delay model, Dproc = Dbase + L / R + k·Qlen, is constructed based on the "packet length and queue depth correlation queuing delay estimation method." Here, Dbase is a fixed baseline hardware processing delay, L / R is the time required for the data packet to be sent at the port rate, and k·Qlen is the estimated queuing waiting time (the coefficient k can be adjusted according to real-time throughput). The calculated Dproc is used to compensate for the original timestamped Tstamp, resulting in a "corrected timestamp Tcorrected," which aims to approximate the ideal moment when the data packet's SFD arrives at the TAP physical layer interface if it were transmitted directly on the original link without being mirrored.

[0031] This step is a "refinement" of the raw hardware timestamp, designed to eliminate the additional latency introduced by the TAP device's internal processing, enabling the final output timestamp to be "pushed back" to the precise arrival time of the data packet on the original link. It makes the timestamp no longer just the moment the data packet enters the TAP, but closer to the actual moment the network event occurred, which is crucial for applications that need to sequence events across devices and nodes.

[0032] Traditional TAP devices or network probes typically ignore or use fixed values ​​to roughly compensate for internal latency. While this may be insignificant when traffic is stable and queues are idle, it can lead to significant and variable latency (potentially milliseconds) under high load or sudden traffic surges causing queue congestion. This results in output packet timestamps lagging far behind their actual network arrival times, leading to complete distortion of timestamp-based traffic analysis and anomaly detection. This invention achieves real-time, adaptive compensation for internal processing latency by dynamically estimating packet length-related latency and queue depth-related queuing latency, significantly improving the accuracy of timestamps in reflecting real network timing.

[0033] Suppose a TAP device is monitoring a 1Gbps link. A sudden traffic surge causes its internal output queue to instantly accumulate 10 packets with an average length of 1500 bytes. A newly timestamped packet needs to wait for these packets to finish sending. Traditional fixed compensation cannot handle this situation; the timestamp of the new packet will be approximately 120 microseconds (10*1500*8 / 1e9) later than its actual arrival time. This invention, however, by real-time monitoring of the queue depth Qlen (=10) and combining it with the current packet length L and port rate R, can accurately estimate this 120-microsecond queuing delay and subtract it from Tcorrected, thus outputting a timestamp closer to the actual arrival time of the packet, avoiding timing misalignment caused by internal TAP congestion.

[0034] Step S40: Based on the corrected timestamp Tcorrected, perform a multi-port timestamp unification task using the reference port offset measurement method, and output a unified global timestamp Tunified; This step addresses the issue of unifying the time stamp reference for data packets output from each port in a TAP device with multiple independent monitoring ports (such as a 1-to-4 or 1-to-8 TAP). Even when sharing the same Tbase, differences in the path length of the clock signal distributed to each port, as well as slight differences in the characteristics of the PHY chip and transmitting circuit of each port, result in a "port time offset Δport,i" in the clock phase actually used for marking or transmitting at each port. The "reference port offset measurement method" refers to pre-selecting a port as a time reference base (reference port), and then using internal loopback or sending of a special "offset measurement frame" to each of the other monitoring ports (the i-th port), measuring the round-trip time of the frame from the reference port to the target port (or vice versa), and combining this with the known fixed path delay to calculate the static offset Δport,i of each port relative to the reference port. When outputting data, the corrected timestamp Tcorrected obtained in step S30 for a certain port is added to (or subtracted from) the corresponding offset Δport,i to obtain a "unified global timestamp Tunified" for all ports based on the "reference port time base".

[0035] This step ensures that data streams output from different physical monitoring ports of the same TAP device carry timestamps with a consistent global time base. This allows users to directly merge and analyze data streams captured from multiple ports without worrying about inherent time deviations caused by differences in port hardware. It achieves timestamp "standardization" within the TAP device, a prerequisite for multi-link correlation analysis.

[0036] In traditional applications of multi-port TAP devices, users typically assume that the time across all ports is consistent. However, due to the aforementioned hardware path differences, there may be a fixed offset ranging from tens to hundreds of nanoseconds. When it is necessary to correlate and analyze data packets from different ports that belong to the same session or transaction (e.g., analyzing two opposing links: a client-to-server request and a server-to-client response), this port offset introduces errors, potentially leading to incorrect causal judgments (e.g., misjudging the response as preceding the request). This invention fundamentally eliminates systematic time deviations between ports by actively measuring and compensating for the offset of each port relative to a common reference, ensuring the comparability of cross-port data timestamps.

[0037] On a TAP with four monitoring ports, a bidirectional communication request stream (port 1) and response stream (port 2) are simultaneously captured. Without this step, due to a slightly longer internal clock path, the timestamps of all packets on port 2 may be systematically 50 nanoseconds later than those on port 1. When security analysts attempt to match requests and responses, this fixed 50-nanosecond deviation may cause the matching algorithm to fail or require a larger time tolerance window, reducing matching accuracy. After the unified processing in step S40, the timestamps of the packets output from port 2 have been reduced by this 50-nanosecond offset, making them completely based on the same benchmark as the timestamps of port 1, enabling requests and responses to be accurately matched with extremely high time precision.

[0038] Step S50: Encapsulate the timestamp field and insert mirror frames according to the unified global timestamp Tunified, and output a mirror data packet stream with a unified timestamp.

[0039] This step is the final encapsulation and output stage of the timestamp information. "Timestamp field encapsulation" refers to encapsulating the "Tunified Global Timestamp" value obtained in step S40 into a specific header field according to a predefined format (e.g., a 64-bit or 80-bit nanosecond count). This header can be a standard protocol extension (such as an ERSPAN header with a timestamp, or a timestamp field defined in the IPFIX / NetFlow template) or a custom encapsulation protocol header. "Mirror frame insertion" refers to combining this encapsulated timestamp header with the original "data packet mirror copy" (i.e., a complete Ethernet frame copied from the link, including the MAC header, payload, and FCS). The combination method typically involves adding a new encapsulation header containing the timestamp before the original frame, or inserting a timestamp field at a specific position in the original frame (e.g., after the Layer 2 header), ultimately forming a new "mirror data packet stream" with a precise timestamp, which is then sent to the backend analysis system (such as a probe, data logger, or Security Information and Event Management (SIEM) platform) through the monitoring port.

[0040] This step firmly binds the high-precision and uniform timestamp information calculated in the previous steps to the original data packet content in a structured, machine-readable form, and outputs it as a standard data packet format. This allows the backend analysis system to obtain the accurate, globally significant arrival time information of each output data packet directly by parsing its encapsulation header, without the need for complex parsing or additional synchronization signals, greatly simplifying the development and use of upper-layer applications.

[0041] Traditionally, TAP devices output raw mirror data, with timestamp information provided either through a separate out-of-band channel (such as a separate PPS pulse with a sequence number) or mixed in the data stream in inconsistent formats. This necessitates complex hardware interfaces and synchronization logic in the backend system to associate data packets with timestamps, leading to complex system integration and a high risk of errors. Some solutions don't even provide accurate timestamps. This invention standardizes and encapsulates timestamps as part of the data packet metadata, making the output stream self-contained. Any standard analysis tool that supports this encapsulation format can use it directly, reducing the complexity and deployment cost of the entire monitoring solution while ensuring the reliability of timestamp information transmission. For example, in a distributed system performance monitoring scenario, multiple TAP devices are deployed on links in different locations, and data converges to a central analysis platform. Each TAP outputs an encapsulated data packet with a unified global timestamp (synchronized to the same PTP domain) through step S50. The central platform can simply extract the Tunified field from the header of each received data packet to sort and correlate all data packets from different geographical locations and links according to an absolute and accurate global timeline. This allows for precise location of the propagation path and latency distribution of a performance failure in each part of the system, without worrying about clock synchronization or timestamp format differences between TAP devices.

[0042] Example 2: Furthermore, the present invention provides a TAP-based Ethernet protocol digital transmission system, employing a TAP-based Ethernet protocol digital transmission method from the above embodiments, which can solve a technical problem related to TAP-based Ethernet protocol digital transmission. The beneficial effects of the TAP-based Ethernet protocol digital transmission system provided by the present invention are the same as those of the TAP-based Ethernet protocol digital transmission method provided in the above embodiments, and other technical features of the TAP-based Ethernet protocol digital transmission system are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0043] Example 3: This invention provides a TAP-based Ethernet protocol digital transmission device. The TAP-based Ethernet protocol digital transmission device includes: at least one processor; and a memory communicatively connected to the at least one processor. The memory stores instructions executable by the at least one processor, which, when executed, enable the at least one processor to perform the TAP-based Ethernet protocol digital transmission method described in Example 1. The TAP-based Ethernet protocol digital transmission device in this embodiment may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital radio receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), and in-vehicle terminals (e.g., in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. This TAP-based Ethernet protocol digital transmission device is merely an example and should not limit the functionality or scope of the embodiments of this invention. A TAP-based Ethernet protocol digital transmission device may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes based on a program stored in a read-only memory or a program loaded from a storage device into a random access memory. The random access memory also stores various programs and data required for the operation of a TAP-based Ethernet protocol digital transmission device. The processing unit, read-only memory, and random access memory are interconnected via a bus. The I / O interface is also connected to the bus. Typically, the following systems can be connected to the I / O interface: input devices including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices including, for example, magnetic tapes, hard disks, etc.; and communication devices. The communication device allows a TAP-based Ethernet protocol digital transmission device to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows a TAP-based Ethernet protocol digital transmission device with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented alternatively.

[0044] Example 4: This invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the TAP-based Ethernet protocol digital transmission method described above. The computer program product provided by this invention can solve the technical problem of TAP-based Ethernet protocol digital transmission. Compared with the prior art, the beneficial effects of the computer program product provided by this invention are the same as those of the TAP-based Ethernet protocol digital transmission method provided in the above embodiments, and will not be repeated here.

[0045] In particular, according to the embodiments disclosed in this invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this invention include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device, or installed from a read-only memory. When the computer program is executed by a processing device, it performs the functions defined in the methods of the embodiments disclosed in this invention.

[0046] Figure 2 This is a comparative analysis of the clock synchronization error surface and time series of a TAP-based Ethernet protocol digital transmission method according to the present invention. The left side shows the clock synchronization error surface of dynamic calibration, corresponding to the clock synchronization calibration process in step S10 of the present invention. The input is the PTP master clock signal and network environment parameters, and the output is the local clock reference Tbase. The target error is controlled within ≤50ns. In the figure, the horizontal axis represents time, the vertical axis represents temperature, and the vertical axis and color bars represent synchronization error, intuitively showing the changes in clock synchronization error of the dynamic calibration scheme under different time and temperature conditions. The right side is a comparison of the synchronization error time series, with the horizontal axis representing time and the vertical axis representing synchronization error. The green area marks the sub-microsecond accuracy target area: 0-50ns. The red curve represents the error performance of the traditional static synchronization scheme, which fluctuates drastically, generally remaining between 130-230ns, far exceeding the sub-microsecond target area, and lacking both accuracy and stability. The blue curve represents the error performance of the dynamic calibration scheme of the present invention, with the error stable between 20-35ns, always within the sub-microsecond target area, without significant drift or drastic fluctuations, significantly better than the traditional scheme.

[0047] Figure 3This diagram presents a comparison of the three-dimensional surface of the dynamic delay model and the delay compensation residuals of the TAP-based Ethernet protocol digital transmission method of this invention. The left side shows the three-dimensional surface of the dynamic delay model, with the horizontal axis representing the data packet length, the vertical axis representing the output queue depth, and the vertical axis representing the processing delay. This visually illustrates the dynamic delay calculation relationship in step S30 of this invention, showing that the processing delay changes in real time with the data packet length and queue depth, rather than being a fixed value. The right side shows a comparison of the delay compensation residuals, with the horizontal axis representing the data packet sample number and the vertical axis representing the absolute value of the compensation residuals. This compares the compensation effects of traditional methods and this method. It can be seen that the traditional method has large compensation residuals with significant fluctuations, with a maximum error approaching 120 nanoseconds; the compensation residuals of this method are extremely small and stable, approaching zero error, proving that dynamic delay compensation can significantly eliminate timing deviations caused by the internal processing of the TAP device.

[0048] Figure 4 This invention presents a bubble chart and error distribution histogram for the output data packet timestamp accuracy of a TAP-based Ethernet protocol digital transmission method. The left side shows the bubble chart of output data packet timestamp accuracy, with the horizontal axis representing the output data packet sequence and the vertical axis representing the global timestamp error. The sub-microsecond accuracy target line is marked on the graph. Traditional methods have scattered error points far from the sub-microsecond line, resulting in poor accuracy and large jitter. This method, however, has highly concentrated error points, closely aligned with the sub-microsecond line, achieving stable sub-microsecond timestamp accuracy. The right side shows the error distribution histogram, with the horizontal axis representing timestamp error and the vertical axis representing the number of data packets and cumulative probability. This method exhibits a narrower error distribution and more concentrated peaks, with the error of the vast majority of data packets controlled within ±50 nanoseconds. The cumulative probability curve converges to 100% more quickly, demonstrating higher consistency and reliability.

[0049] It should be understood that the various parts disclosed in this invention can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0050] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the present invention and its equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A digital transmission method for Ethernet protocol based on TAP, characterized in that, The methods include: Step S10: Obtain the PTP master clock interaction message, and perform a local clock synchronization calibration task based on the PTP master clock interaction message using the PI servo clock correction method, and output the local clock time reference. ; Step S20: Obtain a mirror copy of the data packet based on the local clock time base. The hardware timestamp marking task is executed using a frame start delimiter-triggered latching method, and the output contains the marked timestamp. A mirror copy of the original data packets; Step S30: Based on the timestamp with marking The original data packet mirror copy is used to perform a pre-output timestamp preprocessing task using a queuing delay estimation method that correlates packet length with queue depth, and the corrected timestamp is output. ; Step S40: Based on the correction timestamp The multi-port timestamp unification task is performed using a reference port offset measurement method, and a unified global timestamp is output. ; Step S50: Based on the unified global timestamp Perform timestamp field encapsulation and mirror frame insertion, and output a mirror data packet stream with a unified timestamp.

2. The Ethernet protocol digital transmission method based on TAP as described in claim 1, characterized in that, In step S10, the PTP master clock interaction message is obtained, and a local clock synchronization calibration task is performed using the PI servo clock correction method based on the PTP master clock interaction message, and a local clock time reference is output. The steps specifically include: Step S101: Parse the PTP master clock interaction message and extract the master clock transmission time. Receive time from clock Send time from clock and master clock receiving time ; Step S102: Based on the master clock transmission time Receive time from clock Send time from clock and master clock receiving time Calculate master-slave path latency Master-slave clock offset ; Step S103: Offset the master-slave clock The input PI servo clock corrector performs phase and frequency correction on the local crystal oscillator count value of the TAP device to obtain the local clock time base. .

3. The Ethernet protocol digital transmission method based on TAP as described in claim 1, characterized in that, In step S20, a mirror copy of the data packet is obtained based on the local clock time reference. The hardware timestamp marking task is executed using a frame start delimiter-triggered latching method, and the output contains the marked timestamp. The steps for creating a mirror copy of the original data packets specifically include: Step S201: Copy the bidirectional Ethernet data frames in the link through the TAP physical layer interface to obtain a mirror copy of the data packets; Step S202: When the Start-of-Frame Delimiter (SFD) of the data packet mirror copy is detected, the hardware latch unit is triggered to read the local clock time base. The corresponding current count value yields the original hardware timestamp. ; Step S203: Utilize the fixed delay compensation amount pre-stored in the delay calibration register Correct the original hardware timestamp Get the marked timestamp and the marked timestamp Bind to the image copy of the data packet, and output with a tagged timestamp. A mirror copy of the original data packets.

4. The Ethernet protocol digital transmission method based on TAP as described in claim 3, characterized in that, In step S203, the fixed delay compensation amount The timestamp is the sum of the frame start delimiter detection circuit delay, the physical layer receive path signal propagation delay, and the hardware latch trigger delay. It is obtained according to the following formula: ； in, The value ranges from 60ns to 70ns.

5. The Ethernet protocol digital transmission method based on TAP as described in claim 1, characterized in that, In step S30, based on the timestamp with marking The original data packet mirror copy is used to perform a pre-output timestamp preprocessing task using a queuing delay estimation method that correlates packet length with queue depth, and the corrected timestamp is output. The steps specifically include: Step S301: From the time stamped item Extract the current packet length from the original packet mirror copy ; Step S302: Combine with the current output port processing rate and current output queue depth Calculate the processing delay of the data packet mirror copy from the timestamp marker point to the output port. ; Step S303: Utilize the processing delay For the marked timestamp Compensation is performed to obtain the corrected timestamp. .

6. The Ethernet protocol digital transmission method based on TAP as described in claim 5, characterized in that, In step S302, the processing delay Calculate using the following formula: ； in, As a benchmark for hardware processing latency, The current data packet length, This represents the current output port processing rate. This represents the current output queue depth. Queue latency factor adjusted based on real-time throughput; In step S303, the correction timestamp It is obtained according to the following formula: 。 7. The Ethernet protocol digital transmission method based on TAP as described in claim 1, characterized in that, In step S40, based on the correction timestamp The multi-port timestamp unification task is performed using a reference port offset measurement method, and a unified global timestamp is output. The steps specifically include: Step S401: Select one monitoring port from the multi-port TAP device as the reference port, and set the local clock time base. The corresponding clock signal is distributed to each monitoring port; Step S402: Send offset measurement frames between each monitoring port and the reference port to measure the offset of the first monitoring port. Port time offset of each monitoring port relative to the reference port ; Step S403: Based on the port time offset The correction timestamp for the corresponding monitoring port Alignment is performed to obtain a unified global timestamp. ; Among them, the unified global timestamp It is obtained according to the following formula: ； in, For the first Port time offset of each monitoring port relative to the reference port.

8. A TAP-based Ethernet protocol digital transmission system, applied to the TAP-based Ethernet protocol digital transmission method according to any one of claims 1 to 7, characterized in that, The TAP-based Ethernet protocol digital transmission system includes: The clock synchronization calibration module is used to acquire PTP master clock interaction messages, perform local clock synchronization calibration tasks based on the PTP master clock interaction messages using the PI servo clock correction method, and output a local clock time reference. ; The image packet timestamp module is used to obtain a mirror copy of the data packet based on the local clock time reference. The hardware timestamp marking task is executed using a frame start delimiter-triggered latching method, and the output contains the marked timestamp. A mirror copy of the original data packets; The output delay compensation module is used to compensate for delays based on the timestamp marked on the output. The original data packet mirror copy is used to perform a pre-output timestamp preprocessing task using a queuing delay estimation method that correlates packet length with queue depth, and the corrected timestamp is output. ; A multi-port time unification module is used to base the time on the corrected timestamp. The multi-port timestamp unification task is performed using a reference port offset measurement method, and a unified global timestamp is output. ; The timestamp encapsulation and output module is used to encapsulate and output the unified global timestamp. Perform timestamp field encapsulation and mirror frame insertion, and output a mirror data packet stream with a unified timestamp.

9. A TAP-based Ethernet protocol digital transmission device, characterized in that, The TAP-based Ethernet protocol digital transmission device includes: a memory, a processor, and a TAP-based Ethernet protocol digital transmission program stored in the memory and executable on the processor. When the TAP-based Ethernet protocol digital transmission program is executed by the processor, it implements a TAP-based Ethernet protocol digital transmission method according to any one of claims 1 to 7.

10. A computer program product, characterized in that, The computer program product includes a TAP-based Ethernet protocol digital transmission program, which, when executed by a processor, implements a TAP-based Ethernet protocol digital transmission method according to any one of claims 1 to 7.

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