Clock phase compensation method, system, and apparatus based on digitally controlled delay chain

Abstract

The application discloses a clock phase compensation method, system and equipment based on a digital control delay chain, comprising: obtaining an original clock signal and a target compensation value of a clock phase, and calling a pre-stored lookup table, in which code values and actual delay amounts are in one-to-one correspondence; selecting an optimal actual delay amount from the pre-stored lookup table according to the target compensation value, and locking an optimal control code value corresponding to the optimal actual delay amount; converting the optimal control code value into a digital control word; generating a signal path based on the digital control delay chain according to the digital control word, wherein the digital control delay chain is composed of a plurality of delay units, a plurality of NOR gates and a plurality of NMOS switches; and realizing clock phase compensation through the signal path by the original clock signal. The special digital control delay chain is composed of a large number of same basic delay units in cascade, and the enable of each unit is controlled by an independent digital bit, so that sub-microsecond clock synchronization is realized.

Description

Technical Field

[0001] This invention relates to the field of clock phase compensation technology, and in particular to a clock phase compensation method, system and device based on a digitally controlled delay chain. Background Technology

[0002] In automotive Ethernet-based Advanced Driver Assistance Systems (ADAS), the phase of the local clock needs to be dynamically fine-tuned to compensate for drift caused by factors such as temperature, voltage, and aging. Existing phase compensation technologies have the following main shortcomings: Software compensation suffers from large delays and low accuracy: Adjusting the parameters or delay threads of the phase-locked loop (PLL) via software results in response delays on the order of milliseconds, and the adjustment granularity is coarse, making it impossible to achieve real-time, fine-grained phase control at the nanosecond or picosecond level. Analog phase interpolators are complex and sensitive to process, voltage, and temperature (PVT): Although traditional analog phase interpolators can provide high resolution, their circuit design is complex, power consumption is high, and their gain and linearity are extremely sensitive to changes in process, voltage, and temperature. Their performance is difficult to maintain stability in the wide temperature range of automotive applications, requiring complex calibration circuits, which increases cost and design difficulty. The adjustment range and accuracy of digitally controlled oscillators are contradictory: When the adjustment method based on digitally controlled oscillators (DCO) covers a large frequency range, its phase adjustment step (resolution) usually becomes coarser, making it difficult to meet the requirements of bandwidth and ultra-high accuracy at the same time. Therefore, how to achieve sub-microsecond clock synchronization has become an urgent problem to be solved. Summary of the Invention

[0003] The main objective of this invention is to provide a clock phase compensation method, system, and device based on a digitally controlled delay chain, addressing the technical problem of how to achieve sub-microsecond clock synchronization.

[0004] To achieve the above objectives, the present invention provides a clock phase compensation method based on a digitally controlled delay chain, the clock phase compensation method based on a digitally controlled delay chain comprising: Obtain the original clock signal and the target compensation value of the clock phase, and call the pre-stored lookup table, wherein the code value in the pre-stored lookup table corresponds one-to-one with the actual delay amount; The optimal actual delay is selected from the pre-stored lookup table based on the target compensation value, and the optimal control code value corresponding to the optimal actual delay is locked. Convert the optimal control code value into a digital control word; The signal path is generated based on the digital control delay chain according to the digital control word. The digital control delay chain is constructed by combining multiple delay units, multiple NOR gates and multiple NMOS switches. Clock phase compensation is achieved by passing the original clock signal through the signal path.

[0005] Optionally, selecting the optimal actual delay from the pre-stored lookup table based on the target compensation value includes: Calculate the absolute error between the target compensation value and each actual delay value in the pre-stored lookup table; The actual delay corresponding to the minimum absolute error value is taken as the optimal actual delay.

[0006] Optionally, the generation of a signal path based on the digital control delay chain according to the digital control word includes: The digital control word determines the level of each delay unit in the digital control delay chain, the channel state of each NOR gate, and the state of each NMOS switch. Signal paths are generated based on the level of each delay unit, the channel state of each NOR gate, and the state of each NMOS switch.

[0007] Optionally, the step of performing clock phase compensation on the original clock signal through the signal path includes: The activated delay units within the signal path are determined, and a bias current signal is generated via a digital-to-analog converter according to the digital control word; Based on the bias current signal and the original clock signal, a delayed clock signal is output through the activated delay unit. Clock phase compensation is achieved based on the delayed clock signal according to the signal path.

[0008] Optionally, the delay unit is constructed by combining a symmetrical load current module, an inverter, a differential current control switch, a delay adjustment terminal, and an adjustable delay unit. The step of outputting a delayed clock signal through the activated delay unit based on the bias current signal and the original clock signal includes: The bias current signal is delayed by a three-terminal resistor and transmitted to the symmetrical load current module to obtain the processed bias current. The processed bias current is used to generate a voltage control signal through the inverter; The voltage control signal is input to the differential current control switch so that the differential current control switch outputs a path switching signal; An external control signal is generated through the delay adjustment terminal according to the digital control word; Based on the path switching signal and the external control signal, the original clock signal is output as a delayed clock signal through the adjustable delay unit.

[0009] Optionally, generating a voltage control signal through the inverter based on the processed bias current includes: The processed bias current and the original clock signal are mixed to obtain a mixed current signal; The inverter converts the mixed current signal into a voltage control signal.

[0010] Optionally, inputting the voltage control signal to the differential current control switch to cause the differential current control switch to output a path switching signal includes: The voltage control signal is input to the differential current control switch so that the differential current control switch drives the internal complementary MOS switch to turn on or off according to the level state of the voltage control signal, and outputs the corresponding path switching signal.

[0011] Optionally, the step of outputting a delayed clock signal from the original clock signal through the adjustable delay unit based on the path switching signal and the external control signal includes: Delay control constraints are constructed based on the path switching signal and the external control signal; According to the delay control constraint, the original clock signal is output as a delayed clock signal through the adjustable delay unit.

[0012] Furthermore, to achieve the above objectives, the present invention also proposes a clock phase compensation system based on a digitally controlled delay chain. The system includes a digitally controlled delay chain, which is composed of multiple cascaded delay units. Each delay unit is constructed by combining a symmetrical load current module, an inverter, a differential current control switch, a delay adjustment terminal, and an adjustable delay unit. The symmetrical load current module is used to perform load processing on the bias current signal to obtain the processed bias current, and control the current summing node to mix the processed bias current and the original clock signal, and transmit the mixed current signal to the inverter. The inverter is used to convert the mixed current signal into a voltage control signal and transmit the voltage control signal to the differential current control switch; The differential current control switch is used to output a path switching signal according to the voltage control signal, and transmit the path switching signal to the adjustable delay unit; The delay adjustment terminal is used to generate an external control signal according to the digital control word and send the external control signal to the adjustable delay unit; The adjustable delay unit is used to adjust the delay of the original clock signal based on the path switching signal and the external control signal, and output a delayed clock signal.

[0013] Furthermore, to achieve the above objectives, the present invention also proposes a clock phase compensation device based on a digitally controlled delay chain. The device includes: a memory, a processor, and a clock phase compensation program based on a digitally controlled delay chain stored in the memory and executable on the processor. The clock phase compensation program based on a digitally controlled delay chain is configured to implement the steps of the clock phase compensation method based on a digitally controlled delay chain as described above.

[0014] Furthermore, to achieve the above objectives, the present invention also proposes a storage medium storing a clock phase compensation program based on a digitally controlled delay chain, wherein when the clock phase compensation program based on the digitally controlled delay chain is executed by a processor, the clock phase compensation method based on the digitally controlled delay chain described above is implemented.

[0015] This invention first obtains the original clock signal and the target compensation value for the clock phase, and then calls a pre-stored lookup table. The code values ​​in the lookup table correspond one-to-one with the actual delay amounts. Next, based on the target compensation value, the optimal actual delay amount is selected from the lookup table, and the optimal control code value corresponding to the optimal actual delay amount is locked. The optimal control code value is converted into a digital control word. Then, a signal path is generated based on the digital control delay chain according to the digital control word. The digital control delay chain is constructed by combining multiple delay units, multiple NOR gates, and multiple NMOS switches. Finally, the original clock signal is used to achieve clock phase compensation through the signal path. This invention uses a dedicated digital control delay chain composed of a large number of cascaded identical basic delay units. The enable of each unit is controlled by an independent digital bit, thereby achieving sub-microsecond clock synchronization. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a clock phase compensation device based on a digitally controlled delay chain in the hardware operating environment involved in the embodiments of the present invention; Figure 2 This is a flowchart illustrating the first embodiment of the clock phase compensation method based on a digitally controlled delay chain according to the present invention. Figure 3 This is a schematic diagram of the delay chain structure in the first embodiment of the clock phase compensation method based on digitally controlled delay chain of the present invention. Figure 4 This is a schematic diagram of the delay unit structure of the first embodiment of the clock phase compensation method based on digital control delay chain of the present invention.

[0017] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0018] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0019] Reference Figure 1 , Figure 1 This is a schematic diagram of the end-to-end robust time synchronization device structure of the Advanced Driver Assistance Systems (ADAS) hardware operating environment involved in the embodiments of the present invention.

[0020] like Figure 1 As shown, the clock phase compensation device based on a digitally controlled delay chain may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to establish communication between these components. The user interface 1003 may include a display screen or an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wireless-Fidelity (Wi-Fi) interface). The memory 1005 may be high-speed random access memory (RAM) or stable non-volatile memory (NVM), such as a disk drive. Optionally, the memory 1005 may also be a storage system independent of the aforementioned processor 1001.

[0021] Those skilled in the art will understand that Figure 1 The structure shown does not constitute a limitation on clock phase compensation devices based on digitally controlled delay chains, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0022] like Figure 1 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a network access module, a user interface module, and a clock phase compensation program based on a digital control delay chain.

[0023] exist Figure 1In the clock phase compensation device based on digital control delay chain shown, the network interface 1004 is mainly used for data communication with the network server; the user interface 1003 is mainly used for data interaction with the user; the processor 1001 and memory 1005 in the clock phase compensation device based on digital control delay chain of the present invention can be set in the clock phase compensation device based on digital control delay chain. The clock phase compensation device based on digital control delay chain calls the clock phase compensation program based on digital control delay chain stored in memory 1005 through processor 1001 and executes the clock phase compensation method based on digital control delay chain provided in the embodiment of the present invention.

[0024] This invention provides a clock phase compensation method based on a digitally controlled delay chain, referring to... Figure 2 , Figure 2 This is a flowchart illustrating the first embodiment of the clock phase compensation method based on a digitally controlled delay chain according to the present invention.

[0025] In this embodiment, the clock phase compensation method based on a digitally controlled delay chain includes the following steps: S1, obtain the target compensation value of the original clock signal and clock phase, and call the pre-stored lookup table, wherein the code value in the pre-stored lookup table corresponds one-to-one with the actual delay amount.

[0026] It is easy to understand that the execution subject of this embodiment can be a clock phase compensation system based on a digitally controlled delay chain with functions such as data processing, network communication and program execution, or other computer devices with similar functions. This embodiment does not limit it.

[0027] It should be noted that the master clock periodically sends hardware timestamp synchronization probe frames during network idle windows. The transmission time T1 is precisely recorded by the Media Access Control (MAC) hardware. The slave clock records T2 at the moment of reception at the physical layer and immediately organizes a hardware response frame. It records T3 at the moment of transmission and encapsulates [T1, T2, T3] for transmission back. The master clock records T4 when receiving the response frame.

[0028] Among them, T1, T2, T3 and T4 are the frame recording timestamps between the master clock and the slave clock.

[0029] The offset is obtained from the frame recording timestamp through a synchronization error analyzer; the offset is then filtered by a Kalman filter to obtain the actual synchronization phase error value.

[0030] In the specific implementation, the synchronization error analyzer within the master clock calculates: Offset = (T2-T1)-[(T4-T1)-(T3-T2)] / 2 This offset is the current objective synchronization error. This offset is passed as input to the Kalman filter for filtering to obtain the actual synchronization phase error value.

[0031] Furthermore, the temperature difference ΔT and the squared difference ΔT² are calculated based on the current chip temperature and the reference temperature T_ref. The voltage deviation ΔV is calculated based on the current power supply voltage and the standard power supply voltage of the clock circuit (usually 3.3V or 1.8V). The relative frequency deviation is calculated based on the current oscillation frequency F_ro and the factory reference frequency F_ro_base. The relative frequency deviation is used as the aging index A. The temperature difference, the squared difference, the voltage deviation, and the aging index are input into the multivariate compensation model, and the phase compensation value is output.

[0032] It should be noted that the reference temperature is determined based on the inflection point temperature of the crystal oscillator frequency-temperature characteristic curve, that is, the temperature point where the frequency error is the smallest. Temperature-compensated crystal oscillators (TXCOs) are usually at 25°C, but other crystal oscillators may be different.

[0033] The aging characterization quantity A is defined as the relative deviation between the current frequency and the factory reference frequency: A=(F_ro-F_ro_base) / F_ro_base It should also be understood that the parameter update conditions for the multivariate compensation model are that the rate of temperature change is lower than a preset threshold and the actual synchronization phase error value φ_true is greater than the preset threshold.

[0034] The multivariate compensation model is as follows: P_comp=a ΔT+b ΔT²+c ΔV+d A+e In the formula, P_comp is the phase compensation value (i.e., the target compensation value), ΔT is the temperature difference, ΔT² is the square of the difference, ΔV is the voltage deviation, A is the aging index, and a, b, c, d and e are model parameters.

[0035] It should also be noted that during chip production testing or system power-on initialization, a high-precision time measurement circuit was used to actually measure the total delay of the delay chain, T_measured(K)≈K, under different control code values ​​K. t_unit represents the average delay of a single unit under the current PVT, and K is the number of active delay units. A "code value-actual delay" lookup table (i.e., a pre-stored lookup table) is constructed and stored in non-volatile memory, where the code values ​​and actual delay values ​​in the pre-stored lookup table correspond one-to-one.

[0036] S2, select the optimal actual delay amount from the pre-stored lookup table according to the target compensation value, and lock the optimal control code value corresponding to the optimal actual delay amount.

[0037] Furthermore, the method for selecting the optimal actual delay amount from the pre-stored lookup table based on the target compensation value is as follows: based on the pre-stored lookup table, calculate the absolute error value between the target compensation value and each actual delay amount in the pre-stored lookup table; and take the actual delay amount corresponding to the smallest absolute error value as the optimal actual delay amount.

[0038] In the specific implementation, the target compensation value P_comp is compared with the difference between each set of actual measured delay T_measured(K) in the lookup table to calculate the absolute error between the two. The calculation formula is |T_measured(K)-P_comp|. All error values ​​are compared in turn, and the set of actual delay with the smallest absolute error is selected. This delay is the matching delay that best fits the phase compensation requirement and is taken as the optimal actual delay. Then, the control code value bound to the optimal matching actual delay value is locked and defined as the optimal target control code K_target required for dynamic compensation.

[0039] S3, convert the optimal control code value into a digital control word.

[0040] The optimal target control code K_target in integer form is converted into a multi-bit parallel digital control word Ctrl[0...n], with the number of bits in the control word consistent with the total number of delay units in the delay chain.

[0041] Ctrl[i]=1 indicates that the i-th level delay unit is connected to the link, and Ctrl[i]=0 indicates bypassing.

[0042] refer to Figure 3 , Figure 3 This is a schematic diagram of the delay chain structure in the first embodiment of the clock phase compensation method based on a digitally controlled delay chain according to the present invention. The delay chain consists of a series of identical delay units cascaded together. All units are driven by a unified digital control word, and each bit of the control word controls the enable state of a delay unit. Assuming K_target=2, the delay chain has 5 levels of delay units, corresponding to the control word Ctrl[0…4]=11000, and the digital control word is: the first 2 bits are 1, and the remaining bits are 0.

[0043] S4, Based on the digital control delay chain, a signal path is generated according to the digital control word. The digital control delay chain is constructed by combining multiple delay units, multiple NOR gates and multiple NMOS switches.

[0044] Furthermore, the processing method for generating signal paths based on the digital control delay chain according to the digital control word is as follows: determine the level of each delay unit, the channel state of each NOR gate, and the state of each NMOS switch in the digital control delay chain according to the digital control word; generate signal paths according to the level of each delay unit, the channel state of each NOR gate, and the state of each NMOS switch.

[0045] refer to Figure 3 Delay units: 5 levels (DelayCell1~5); NOR gates: 4 in total, located between levels 1~2, 2~3, 3~4, and 4~5 respectively; Control word: Ctrl[0…4] 5 bits in total, where: Ctrl[0~3] controls the path of the 4 NOR gates and the corresponding delay units at the same time, and Ctrl[4] controls the bypass logic of the 5th level delay unit (in conjunction with the rightmost global bypass). The original input signal (i.e. the original clock signal) D enters the first delay unit, generates several delays, and is then passed to the next level. The rightmost Input is used as the bypass input port. When the control word Ctrl[0...n] selects the bypass mode, it can be used with NOR gates to skip the complete delay chain. The NMOS switch, in conjunction with the NOR gate, further optimizes the selection logic of the delay unit. Q represents the feedback output port of the delay unit. The signal after multi-level dynamic adjustment is finally output from Output.

[0046] In the specific implementation, if K_target=2 and control word Ctrl[0…4]=11000, refer to Table 1, which is the status table of each level of the path: Table 1

[0047] S5, clock phase compensation is achieved by passing the original clock signal through the signal path.

[0048] Furthermore, the processing method for achieving clock phase compensation of the original clock signal through the signal path is as follows: determine the activated delay unit within the signal path, and generate a bias current signal through a digital-to-analog converter (DAC) according to the digital control word; output a delayed clock signal through the activated delay unit based on the bias current signal and the original clock signal; and achieve clock phase compensation based on the delayed clock signal according to the signal path.

[0049] refer to Figure 4 , Figure 4This is a schematic diagram of the delay unit structure in the first embodiment of the clock phase compensation method based on a digitally controlled delay chain according to the present invention. To ensure linearity and stability, the delay unit is constructed by combining a symmetrical load current module, an inverter, a differential current control switch, a delay adjustment terminal (i.e., an RC delay network), and an adjustable delay unit. Its delay is mainly achieved by adjusting the magnitude of the drive current. This design allows t_unit to be finely adjusted within a certain range and provides a certain degree of suppression of power supply noise.

[0050] Further, the processing method for outputting a delayed clock signal through the activated delay unit based on the bias current signal and the original clock signal is as follows: the bias current signal is delayed by a three-terminal resistor and transmitted to the symmetrical load current module to obtain the processed bias current; the processed bias current and the original clock signal are mixed to obtain a mixed current signal; the mixed current signal is converted into a voltage control signal through an inverter; the voltage control signal is input to the differential current control switch to make the differential current control switch output a path switching signal; an external control signal is generated through the delay adjustment terminal according to the digital control word; based on the path switching signal and the external control signal, the original clock signal is output as a delayed clock signal through the adjustable delay unit.

[0051] Further, inputting the voltage control signal to the differential current control switch to cause the differential current control switch to output a path switching signal includes: inputting the voltage control signal to the differential current control switch to cause the differential current control switch to drive the internal complementary MOS switch to be turned on or off according to the level state of the voltage control signal, and outputting a corresponding path switching signal.

[0052] In the specific implementation, a stable bias current (generated by the on-chip DAC based on the digital control word) is input to the circuit from the "current input" port. This bias current is buffered and delayed by a three-terminal resistor before being sent to the symmetrical load current module. The bias current processed by the symmetrical load current module is then sent to the current summing node to participate in signal mixing. This module, as the core load of the adjustable delay unit, converts the input bias current into a control current for charging and discharging the signal path, providing a linear and stable current drive basis for subsequent delay adjustment.

[0053] The current summing node simultaneously receives two signals: 1. the bias current output from the symmetrical load current module; 2. the input signal from the current delay unit of this stage. The current summing node mixes the two signals and outputs the mixed current signal; then, the inverter converts this current signal into a voltage control signal and sends it to the differential current control switch to provide the drive level for the differential current control switch.

[0054] The differential current control switch consists of a set of complementary MOSFET switches. Its core logic is to control the on / off state of the complementary switches by changing the level of the voltage control signal, thereby achieving dynamic switching of the signal path. Based on the voltage control signal, the differential current control switch outputs a path switching signal (i.e., the current signal after path switching), realizing dynamic adjustment of the drive current. The differential current control switch then sends the current signal after path switching to an adjustable delay unit.

[0055] It should also be noted that the voltage control signal output from the pre-amplifier is sent to the control terminal of the differential current control switch. The level detection circuit inside the switch identifies the high or low level state of this signal and determines the current demand direction (increase / decrease). When the voltage control signal is high: it drives one set of MOSFET switches to turn on, and the other set of complementary switches to turn off. The turned-on switch switches the signal path to the high-current drive branch of the delay unit, increasing the node charging and discharging current, shortening the signal time through the delay unit, and reducing the delay. When the voltage control signal is low: it drives the other set of MOSFET switches to turn on, and the first set of switches to turn off. The turned-on switch switches the signal path to the low-current drive branch of the delay unit, reducing the node charging and discharging current, extending the signal time through the delay unit, and increasing the delay.

[0056] The differential current control switch outputs a corresponding path switching signal based on the conducting switching branch. This signal contains two pieces of information: the magnitude of the current in the current-driven branch after the switch; and the state of the signal path after the switch (high / low current mode). This path switching signal is sent to the subsequent adjustable delay unit, directly controlling its internal charging and discharging rate, and achieving fine adjustment of the single-stage delay time.

[0057] The capacitor and three-terminal resistor at the "delay adjustment terminal" form an RC delay network. By adjusting the control signal to change the equivalent resistance value, the charging and discharging rate of the node can be adjusted, thereby achieving fine-tuning of the delay time. The fine-tuning control signal (i.e., the external control signal) output by the RC delay network, together with the signal output by the differential current control switch, is sent to the adjustable delay unit.

[0058] The adjustable delay unit receives two signals: the path switching signal output by the differential current control switch and the external control signal input by the delay adjustment terminal.

[0059] Furthermore, the processing method for outputting a delayed clock signal from the original clock signal through the adjustable delay unit based on the path switching signal and the external control signal is as follows: constructing delay control constraints based on the path switching signal and the external control signal; and outputting a delayed clock signal from the original clock signal through the adjustable delay unit according to the delay control constraints.

[0060] In the specific implementation, the path switching signal serves as a coarse adjustment constraint, determining the current magnitude of the charging and discharging main circuit within the adjustable delay unit, defining the basic delay interval for clock signal transmission delay (when the path switching signal is of high current type, the high current drive branch is activated to accelerate the charging and discharging speed of the circuit nodes, setting the basic parameters for short delay, and determining the minimum delay reference for this stage; when the path switching signal is of low current type, the low current drive branch is activated to slow down the charging and discharging speed of the circuit nodes, setting the basic parameters for long delay, and determining the maximum delay reference for this stage), thus determining the main range of delay duration. External control signals serve as fine adjustment constraints, acting on the RC delay network, changing the equivalent resistance value and RC time constant, continuously fine-tuning the delay within the basic delay interval, and correcting delay deviations (increasing the equivalent resistance lengthens the RC charging and discharging cycle, adding a positive fine-tuning delay to the basic delay parameters; decreasing the equivalent resistance shortens the RC charging and discharging cycle, reducing excess delay on the basic delay parameters).

[0061] The dual control conditions (i.e. delay control constraints) formed by the path switching signal output by the differential current control switch and the external control signal connected to the delay adjustment terminal are used to compensate the original clock signal. After the original clock signal enters the adjustable delay unit, its internal transmission speed, node charging and discharging speed, and signal dwell time are constrained by the joint delay parameters formed by the two signals. The timing delay is completed strictly according to the total delay obtained by the combination of coarse setting and fine adjustment, and finally the clock signal with precise delay is output.

[0062] In this embodiment, the original clock signal and the target compensation value for the clock phase are first obtained, and a pre-stored lookup table is invoked. The code values ​​in the lookup table correspond one-to-one with the actual delay amounts. Then, based on the target compensation value, the optimal actual delay amount is selected from the lookup table, and the optimal control code value corresponding to the optimal actual delay amount is locked. The optimal control code value is converted into a digital control word. Subsequently, a signal path is generated based on the digital control delay chain according to the digital control word. The digital control delay chain is constructed by combining multiple delay units, multiple NOR gates, and multiple NMOS switches. Finally, the original clock signal is used to achieve clock phase compensation through the signal path. This embodiment uses a dedicated digital control delay chain composed of a large number of cascaded identical basic delay units. The enable of each unit is controlled by an independent digital bit, thereby achieving sub-microsecond clock synchronization.

[0063] refer to Figure 3 and Figure 4 The present invention also proposes a clock phase compensation system based on a digitally controlled delay chain. The system includes a digitally controlled delay chain, which is composed of multiple cascaded delay units. Each delay unit is constructed by combining a symmetrical load current module, an inverter, a differential current control switch, a delay adjustment terminal, and an adjustable delay unit. The symmetrical load current module is used to perform load processing on the bias current signal to obtain the processed bias current, and control the current summing node to mix the processed bias current and the original clock signal, and transmit the mixed current signal to the inverter. The inverter is used to convert the mixed current signal into a voltage control signal and transmit the voltage control signal to the differential current control switch; The differential current control switch is used to output a path switching signal according to the voltage control signal, and transmit the path switching signal to the adjustable delay unit; The delay adjustment terminal is used to generate an external control signal according to the digital control word and send the external control signal to the adjustable delay unit; The adjustable delay unit is used to adjust the delay of the original clock signal based on the path switching signal and the external control signal, and output a delayed clock signal.

[0064] Other embodiments or specific implementations of the clock phase compensation system based on digital control delay chain of the present invention can be referred to the above-described method embodiments, and will not be repeated here.

[0065] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0066] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0067] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as read-only memory / random access memory, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0068] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A clock phase compensation method based on a digitally controlled delay chain, characterized in that, The method includes the following steps: Obtain the original clock signal and the target compensation value of the clock phase, and call the pre-stored lookup table, wherein the code value in the pre-stored lookup table corresponds one-to-one with the actual delay amount; The optimal actual delay is selected from the pre-stored lookup table based on the target compensation value, and the optimal control code value corresponding to the optimal actual delay is locked. Convert the optimal control code value into a digital control word; The signal path is generated based on the digital control delay chain according to the digital control word. The digital control delay chain is constructed by combining multiple delay units, multiple NOR gates and multiple NMOS switches. Clock phase compensation is achieved by passing the original clock signal through the signal path.

2. The method as described in claim 1, characterized in that, The step of selecting the optimal actual delay from the pre-stored lookup table based on the target compensation value includes: Calculate the absolute error between the target compensation value and each actual delay value in the pre-stored lookup table; The actual delay corresponding to the minimum absolute error value is taken as the optimal actual delay.

3. The method as described in claim 1, characterized in that, The digitally controlled delay chain generates a signal path based on the digital control word, including: The digital control word determines the level of each delay unit in the digital control delay chain, the channel state of each NOR gate, and the state of each NMOS switch. Signal paths are generated based on the level of each delay unit, the channel state of each NOR gate, and the state of each NMOS switch.

4. The method as described in claim 1, characterized in that, The step of performing clock phase compensation on the original clock signal through the signal path includes: The activated delay units within the signal path are determined, and a bias current signal is generated via a digital-to-analog converter according to the digital control word; Based on the bias current signal and the original clock signal, a delayed clock signal is output through the activated delay unit. Clock phase compensation is achieved based on the delayed clock signal according to the signal path.

5. The method as described in claim 4, characterized in that, The delay unit is constructed by combining a symmetrical load current module, an inverter, a differential current control switch, a delay adjustment terminal, and an adjustable delay unit. The step of outputting a delayed clock signal through the activated delay unit based on the bias current signal and the original clock signal includes: The bias current signal is delayed by a three-terminal resistor and transmitted to the symmetrical load current module to obtain the processed bias current. The processed bias current is used to generate a voltage control signal through the inverter; The voltage control signal is input to the differential current control switch so that the differential current control switch outputs a path switching signal; An external control signal is generated through the delay adjustment terminal according to the digital control word; Based on the path switching signal and the external control signal, the original clock signal is output as a delayed clock signal through the adjustable delay unit.

6. The method as described in claim 5, characterized in that, The step of generating a voltage control signal through the inverter based on the processed bias current includes: The processed bias current and the original clock signal are mixed to obtain a mixed current signal; The inverter converts the mixed current signal into a voltage control signal.

7. The method as described in claim 5, characterized in that, The step of inputting the voltage control signal to the differential current control switch, so that the differential current control switch outputs a path switching signal, includes: The voltage control signal is input to the differential current control switch so that the differential current control switch drives the internal complementary MOS switch to turn on or off according to the level state of the voltage control signal, and outputs the corresponding path switching signal.

8. The method as described in claim 5, characterized in that, The step of outputting a delayed clock signal from the original clock signal through the adjustable delay unit based on the path switching signal and the external control signal includes: Delay control constraints are constructed based on the path switching signal and the external control signal; According to the delay control constraint, the original clock signal is output as a delayed clock signal through the adjustable delay unit.

9. A clock phase compensation system based on a digitally controlled delay chain, characterized in that, The system includes a digitally controlled delay chain, which is composed of multiple cascaded delay units. Each delay unit is constructed by combining a symmetrical load current module, an inverter, a differential current control switch, a delay adjustment terminal, and an adjustable delay unit. The symmetrical load current module is used to perform load processing on the bias current signal to obtain the processed bias current, and control the current summing node to mix the processed bias current and the original clock signal, and transmit the mixed current signal to the inverter. The inverter is used to convert the mixed current signal into a voltage control signal and transmit the voltage control signal to the differential current control switch; The differential current control switch is used to output a path switching signal according to the voltage control signal, and transmit the path switching signal to the adjustable delay unit; The delay adjustment terminal is used to generate an external control signal according to the digital control word and send the external control signal to the adjustable delay unit; The adjustable delay unit is used to adjust the delay of the original clock signal based on the path switching signal and the external control signal, and output a delayed clock signal.

10. A clock phase compensation device based on a digitally controlled delay chain, characterized in that, The device includes: a memory, a processor, and a clock phase compensation program based on a digitally controlled delay chain stored in the memory and executable on the processor, the clock phase compensation program based on a digitally controlled delay chain configured to implement the steps of the clock phase compensation method based on a digitally controlled delay chain as described in any one of claims 1 to 8.

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