Adaptive rate control method and device, network card, storage medium and program product

Abstract

The application relates to a self-adaptive rate control method and device, a network card, a storage medium and a program product, which are applied to an RDMA engine, and the method and device comprise the following steps: acquiring a Cache miss rate and / or a DMA read delay of the RDMA engine, and determining whether to adjust a scheduling rate of a sending pipeline according to the Cache miss rate and / or the DMA read delay; if it is determined to adjust, acquiring a Cache bandwidth and / or a DMA bandwidth currently occupied by a receiving pipeline, acquiring a bandwidth currently available for the sending pipeline according to a preset bandwidth upper limit and the bandwidth currently occupied by the receiving pipeline; and updating the scheduling rate of the sending pipeline according to the bandwidth currently available for the sending pipeline. Through monitoring on-chip resources and traffic load, the scheduling rate of the sending pipeline is dynamically adjusted, the resource balance between the sending pipeline and the receiving pipeline in the RDMA engine is improved, and the overall performance is improved.

Description

Technical Field

[0001] This application relates to the field of RDMA (Remote Direct Memory Access) technology, specifically to an adaptive rate control method and apparatus for an RDMA engine, a network interface card, a computer-readable storage medium, and a computer program product. Background Technology

[0002] RDMA is a high-efficiency communication technology widely used in high-performance computing and data center networks. RDMA supports various semantics, such as send / write / read / atomic, etc., each with different implementations and processing flows, and requiring different data and entries. For uniformity, current RDMA implementations typically divide these semantic processing flows into four sub-flows: send request, receive request, send response, and receive response. Furthermore, for high performance and low latency, RDMA engines usually employ a pipelined approach to implement these sub-flows, with each pipeline stage having a defined function. The RDMA engine pipeline is divided into a TX pipeline (used for sending requests and responses) and an RX pipeline (used for receiving requests and responses). Each RDMA semantic selects the corresponding pipeline stage within the RDMA engine based on its specific implementation and processing flow (and sub-flows). Unnecessary pipeline stages are passed through to the next stage. Each pipeline stage within the RDMA engine relies on reading the necessary context and entries from the cache or through a DMA interface (such as PCIe) to process the service. Therefore, for different RDMA semantics, the occupancy of each pipeline stage of the RDMA engine and the performance requirements of cache or PCIe are not consistent, and the theoretical performance that can be achieved in the same RDMA engine is also different.

[0003] In current RDMA implementations, the TX and RX pipelines of an RDMA engine operate independently, unaware of each other's real-time load and bandwidth requirements for the DMA interface. Furthermore, there is competition for bandwidth and performance across the cache and DMA interfaces between the TX and RX pipelines, and between different pipeline stages within each TX / RX pipeline. Since the bandwidth and performance of the cache and DMA interfaces are fixed, excessive bandwidth and performance consumption by a particular pipeline or stage inevitably reduces the available bandwidth and performance for other pipelines or stages, thus lowering their performance. Ultimately, the actual performance of a complete RDMA semantic within the RDMA engine is determined by the performance of the lowest-performing pipeline or stage; insufficient performance balance leads to an overall performance degradation of the RDMA engine. Summary of the Invention

[0004] The purpose of this application is to propose an adaptive rate control method and device, network interface card, computer-readable storage medium, and computer program product for RDMA engines, so as to improve the balance of RDMA engines.

[0005] To achieve the above objectives, according to a first aspect, embodiments of this application provide an adaptive rate control method, the method comprising:

[0006] The cache miss rate and / or DMA read latency of the RDMA engine are obtained, and the scheduling rate of the transmit pipeline is adjusted based on the cache miss rate and / or DMA read latency. The cache miss rate is the on-chip cache miss rate of the RDMA engine, and the DMA read latency is the latency for the DMA module of the RDMA engine to read host memory data. If it is determined that the scheduling rate of the transmit pipeline should be adjusted, the cache bandwidth and / or DMA bandwidth currently occupied by the receive pipeline should be obtained, and the cache bandwidth and / or DMA bandwidth currently available to the transmit pipeline should be obtained according to the preset cache bandwidth limit and / or DMA bandwidth limit and the cache bandwidth and / or DMA bandwidth currently occupied by the receive pipeline. The scheduling rate of the transmission pipeline is updated based on the cache bandwidth and / or DMA bandwidth currently available to the transmission pipeline.

[0007] In some specific implementations, determining whether to adjust the transmission pipeline scheduling rate based on the cache miss rate and / or DMA read latency includes: Based on the cache miss rate and a preset miss rate threshold, and / or the DMA read latency and a preset read latency threshold, the current maximum allowed total number of tasks for the RDMA engine is obtained, and the current maximum allowed number of tasks for the receive pipeline is obtained. The current maximum allowed number of tasks in the sending pipeline is obtained based on the current maximum allowed total number of tasks and the current maximum allowed number of tasks in the receiving pipeline, and the current number of tasks in the sending pipeline is also obtained. Whether to adjust the scheduling rate of the sending pipeline is determined based on the current number of tasks in the sending pipeline and the current maximum allowed number of tasks in the sending pipeline.

[0008] In some specific implementations, determining whether to adjust the scheduling rate of the sending pipeline based on the current number of tasks in the sending pipeline and the current maximum allowed number of tasks in the sending pipeline includes: When the current number of tasks in the sending pipeline exceeds the current maximum allowed number of tasks in the sending pipeline, reduce the scheduling rate of the sending pipeline; When the current number of tasks in the sending pipeline is less than the current maximum allowed number of tasks in the sending pipeline, increase the scheduling rate of the sending pipeline; When the current number of tasks in the sending pipeline is equal to the current maximum allowed number of tasks in the sending pipeline, the scheduling rate of the sending pipeline remains unchanged.

[0009] In some specific implementations, updating the scheduling rate of the transmission pipeline based on the available cache bandwidth and / or DMA bandwidth includes: Obtain the cache bandwidth and / or DMA bandwidth currently occupied by the transmit pipeline, and obtain the first scheduling rate based on the cache bandwidth and / or DMA bandwidth currently available to the transmit pipeline and the cache bandwidth and / or DMA bandwidth currently occupied by the transmit pipeline. The total scheduling rate of the sending pipeline is updated based on the first scheduling rate.

[0010] In some specific implementations, updating the scheduling rate of the transmission pipeline based on the available cache bandwidth and / or DMA bandwidth includes: Obtain the current scheduling rate of the sending pipeline, and obtain a second scheduling rate based on the current scheduling rate of the sending pipeline, the current number of tasks in the sending pipeline, and the current maximum allowed number of tasks in the sending pipeline; The total scheduling rate of the transmission pipeline is updated based on the first scheduling rate and the second scheduling rate.

[0011] In some specific implementations, the method further includes: After obtaining the total scheduling rate of the sending pipeline, the number of request traffic tasks and the number of response traffic tasks currently being processed by the sending pipeline are obtained. Based on the number of request traffic tasks and the number of response traffic tasks, as well as the total scheduling rate of the sending pipeline, the request traffic task scheduling rate and response traffic task scheduling rate of the sending pipeline are obtained.

[0012] In some specific implementations, the method further includes: After obtaining the request traffic task scheduling rate and response traffic task scheduling rate of the sending pipeline, the current scheduling rate of any one of the RDMA semantics in the request traffic or response traffic is obtained. The corresponding cache bandwidth and / or DMA bandwidth is determined according to the current scheduling rate of the RDMA semantic. The scheduling rate of the RDMA semantic is obtained according to the current scheduling rate of the RDMA semantic and its corresponding cache bandwidth and / or DMA bandwidth, as well as the cache bandwidth and / or DMA bandwidth currently available in the sending pipeline.

[0013] According to a second aspect, embodiments of this application provide an adaptive rate control device, including a module for performing the method described in the first aspect.

[0014] According to a third aspect, embodiments of this application provide a network interface card (NIC), including: A communication interface used for communicating with other electronic devices; Memory is used to store computer program instructions; A processor for executing the computer program instructions to support the network interface card in implementing the method described in the first aspect of this application.

[0015] According to a fourth aspect, embodiments of this application provide a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the method described in the first aspect of this application.

[0016] According to a fifth aspect, embodiments of this application provide a computer program product, including computer program instructions that instruct a computer device to perform an operation corresponding to the method described in the first aspect of this application.

[0017] The adaptive rate control method and apparatus, network interface card, computer-readable storage medium, and computer program product applied to an RDMA engine according to embodiments of this application have the following beneficial effects: This application embodiment dynamically calculates and adjusts the scheduling rate of the transmit pipeline by real-time monitoring parameters such as the cache miss rate, DMA read latency, cache bandwidth and DMA bandwidth usage of the receive pipeline. It can adaptively adjust the scheduling rate of the transmit pipeline according to real-time traffic changes, so that the bandwidth resource competition between the transmit and receive pipelines for on-chip cache and DMA interfaces is effectively balanced, avoiding the performance degradation of one pipeline due to excessive resource consumption by one pipeline. Especially in large-scale connection and mixed traffic scenarios, this application embodiment can maintain the stability and high level of the overall throughput performance of the RDMA engine, and improve the balance, flexibility and robustness of the RDMA engine. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings required in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of an adaptive rate control method in an embodiment of this application.

[0020] Figure 2 This is a schematic diagram of the structure of an RDMA engine in an embodiment of this application. Detailed Implementation

[0021] The detailed description of the accompanying drawings is intended to illustrate the present embodiments of this application and is not intended to represent only the forms in which this application can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included within the spirit and scope of this application.

[0022] See Figure 1 One embodiment of this application provides an adaptive rate control method, the method comprising the following steps: Step S10: Obtain the cache miss rate and / or DMA read latency of the RDMA engine, and determine whether to adjust the scheduling rate of the transmit pipeline based on the cache miss rate and / or DMA read latency; wherein, the cache miss rate is the on-chip cache miss rate of the RDMA engine, and the DMA read latency is the latency of the DMA module of the RDMA engine reading host memory data. Specifically, the on-chip cache of the RDMA engine is used to cache the context and entries read from the host memory. The cache miss rate directly reflects the current pipeline's dependence on memory access. The DMA read latency reflects the response speed of the RDMA engine when reading data from the host memory. When the cache miss rate increases or the DMA read latency increases, it indicates that the current transmit or receive pipeline has put a lot of pressure on the storage system, and it is necessary to appropriately reduce the scheduling rate of the transmit pipeline to avoid further congestion.

[0023] Step S20: If it is determined that the scheduling rate of the transmitting pipeline is adjusted, the cache bandwidth and / or DMA bandwidth currently occupied by the receiving pipeline are obtained, and the cache bandwidth and / or DMA bandwidth currently available to the transmitting pipeline are obtained according to the preset cache bandwidth limit and / or DMA bandwidth limit and the cache bandwidth and / or DMA bandwidth currently occupied by the receiving pipeline. Specifically, the receive pipeline processes requests and responses from the peer device, therefore its operating priority is higher than that of the transmit pipeline, because the traffic in the receive direction is uncontrollable and bursty. Therefore, this application embodiment proposes prioritizing the resource requirements of the receive pipeline by subtracting the currently actual cache bandwidth limit or DMA bandwidth limit currently occupied by the receive pipeline from the preset cache bandwidth limit or DMA bandwidth limit; the remaining cache bandwidth or DMA bandwidth is the bandwidth resource currently available to the transmit pipeline. Specifically, cache bandwidth includes cache read bandwidth and cache write bandwidth, and DMA bandwidth includes DMA read bandwidth and DMA write bandwidth. Let the upper limit of cache read bandwidth be CACHE.rd_thrd, the upper limit of cache write bandwidth be CACHE.wr_thrd, the upper limit of DMA read bandwidth be DMA.rd_thrd, the upper limit of DMA write bandwidth be DMA.wr_thrd, and the current cache read bandwidth, cache write bandwidth, DMA read bandwidth, and DMA write bandwidth occupied by the receive pipeline be CACHE.rx_rd, CACHE.rx_wr, DMA read bandwidth, and DMA write bandwidth be DMA.rx_rd, then the bandwidth currently available to the transmit pipeline can be calculated using any of the following methods based on actual needs: Method 1: Based solely on cache read bandwidth, the currently available cache read bandwidth for the send pipeline is CACHE.tx_rd_avd = CACHE.rd_thrd - CACHE.rx_rd.

[0024] Method 2: Based solely on cache write bandwidth, the currently available cache write bandwidth for the send pipeline is CACHE.tx_wr_avd = CACHE.wr_thrd - CACHE.rx_wr.

[0025] Method 3: Based solely on DMA read bandwidth, the currently available DMA read bandwidth for the transmit pipeline is DMA.tx_rd_avd = DMA.rd_thrd - DMA.rx_rd.

[0026] Method 4: Based solely on DMA write bandwidth, the currently available DMA write bandwidth for the transmit pipeline is DMA.tx_wr_avd = DMA.wr_thrd - DMA.rx_wr.

[0027] Method 5: Combined use. When multiple bandwidth resources need to be considered comprehensively, a weighted summation method can be used to calculate a comprehensive bandwidth availability ratio. For example: Available bandwidth ratio = β1 × (CACHE.tx_rd_avd / CACHE.rd_thrd) + β2 × (CACHE.tx_wr_avd / CACHE.wr_thrd) + β3 × (DMA.tx_rd_avd / DMA.rd_thrd) + β4× (DMA.tx_wr_avd / DMA.wr_thrd); Among them, β1, β2, β3, and β4 are preset weights, and β1+β2+β3+β4=1. Each weight can be adjusted according to the actual application scenario. For example, increase the values ​​of β2 and β4 in write-intensive scenarios, and increase the values ​​of β1 and β3 in read-intensive scenarios.

[0028] Step S30: Update the scheduling rate of the transmission pipeline based on the cache bandwidth and / or DMA bandwidth currently available to the transmission pipeline; Specifically, the sending pipeline calculates the direction and magnitude of the scheduling rate adjustment based on the currently available cache bandwidth and / or DMA bandwidth, combined with its own currently occupied bandwidth. Specifically, if the available bandwidth is greater than the currently occupied bandwidth, it means that resources are sufficient and the scheduling rate can be increased; otherwise, the scheduling rate needs to be reduced, and the updated scheduling rate will be used for the sending scheduling of subsequent tasks.

[0029] As described in the above embodiments, this application embodiment dynamically adjusts the total scheduling rate of the transmit pipeline by real-time monitoring of cache miss rate, DMA read latency, bandwidth usage of the receive pipeline, and the number of tasks in each pipeline, effectively alleviating resource contention between the transmit and receive pipelines. When the receive traffic is high, the scheduling rate of the transmit pipeline automatically decreases to avoid excessive resource occupation of the receive direction by the transmit direction; when the receive traffic is low, the scheduling rate of the transmit pipeline automatically increases to make full use of idle resources. This adaptive mechanism enables the RDMA engine to maintain high resource utilization and stable throughput performance under different traffic models.

[0030] In some specific embodiments, step S10 specifically includes: Step S101: Based on the cache miss rate and a preset miss rate threshold, and / or the DMA read latency and a preset read latency threshold, obtain the current maximum allowed total number of tasks for the RDMA engine, and obtain the current maximum allowed number of tasks for the receive pipeline. Specifically, in this embodiment, a missing rate threshold (e.g., 5%) and a read latency threshold (e.g., 1 microsecond) are preset before execution. These preset thresholds are used as reference benchmarks. When the real-time monitored cache missing rate exceeds these thresholds, it indicates excessive cache pressure, requiring a reduction in the system's maximum allowed number of tasks. Conversely, if the missing rate is below these thresholds, it indicates less cache pressure, allowing for an appropriate increase in the number of tasks. Similarly, the number of tasks is reduced when the DMA read latency is above the threshold and increased when it is below the threshold.

[0031] Specifically, if the preset missing rate threshold is MISS.thrd and the real-time monitored cache missing rate is CACHE.miss, then the adjustment coefficient β1 calculated based on the cache missing rate is (MISS.thrd - CACHE.miss) / CACHE.miss; if the current maximum allowed number of tasks is JOB.thrd_cur, then the maximum allowed number of tasks adjusted based on the cache missing rate is JOB.thrd_new1 = JOB.thrd_cur × (1 + β1); Similarly, if the preset read latency threshold is DMA.rd_d_thrd and the real-time monitored DMA read latency is DMA.rd_d, then the adjustment coefficient β2 calculated based on the DMA read latency is (DMA.rd_d_thrd - DMA.rd_d) / DMA.rd_d, and the maximum number of allowed tasks after adjustment is JOB.thrd_new2 = JOB.thrd_cur × (1 + β2); The final maximum allowed total number of tasks, JOB.thrd, can be the weighted average of JOB.thrd_new1 and JOB.thrd_new2, or the minimum of the two; for example: JOB.thrd = δ1 × JOB.thrd_new1 + δ2 × JOB.thrd_new2, where δ1+δ2=1; or JOB.thrd = min(JOB.thrd_new1, JOB.thrd_new2).

[0032] Step S102: Obtain the current maximum allowed number of tasks in the sending pipeline based on the current maximum allowed total number of tasks and the current maximum allowed number of tasks in the receiving pipeline, and obtain the current number of tasks in the sending pipeline. Specifically, the current maximum allowed number of tasks in the receiving pipeline can be preset according to the processing capacity of the receiving pipeline itself, or dynamically adjusted in a manner similar to step S101; the current maximum allowed number of tasks in the sending pipeline is equal to the total maximum allowed number of tasks calculated in step S101 minus the current maximum allowed number of tasks in the receiving pipeline, so as to prioritize the task processing of the receiving pipeline; and the current number of tasks in the sending pipeline is obtained by real-time statistics through a counter. Let the current maximum allowed total number of tasks be JOB.thrd, and the current maximum allowed number of tasks in the receiving pipeline be JOB.rx (this value can be preset according to the processing capacity of the receiving pipeline, or dynamically adjusted in a manner similar to step S101), then the current maximum allowed number of tasks in the sending pipeline is JOB.tx_avd = JOB.thrd - JOB.rx; Let the current number of tasks in the sending pipeline be JOB.tx, then the task quantity ratio coefficient α1 = (JOB.tx_avd - JOB.tx) / JOB.tx.

[0033] Step S103: Determine whether to adjust the scheduling rate of the sending pipeline based on the current number of tasks in the sending pipeline and the current maximum allowed number of tasks in the sending pipeline. Specifically, by comparing the current number of tasks in the sending pipeline with its current maximum allowed number of tasks, it can be determined whether the current load exceeds the allowable range. If it does, it means that the sending pipeline's processing capacity is insufficient and the scheduling rate needs to be reduced to decrease the injection of new tasks. If it does not exceed the allowable range, it means that there is still room for maneuver and the scheduling rate can be increased.

[0034] In some specific embodiments, step S103 specifically includes: When the current number of tasks in the sending pipeline exceeds the current maximum allowed number of tasks in the sending pipeline, reduce the scheduling rate of the sending pipeline; When the current number of tasks in the sending pipeline is less than the current maximum allowed number of tasks in the sending pipeline, increase the scheduling rate of the sending pipeline; When the current number of tasks in the sending pipeline is equal to the current maximum allowed number of tasks in the sending pipeline, the scheduling rate of the sending pipeline remains unchanged.

[0035] In some specific embodiments, step S30 includes: Obtain the cache bandwidth and / or DMA bandwidth currently occupied by the transmit pipeline, and obtain the first scheduling rate based on the cache bandwidth and / or DMA bandwidth currently available to the transmit pipeline and the cache bandwidth and / or DMA bandwidth currently occupied by the transmit pipeline. The total scheduling rate of the sending pipeline is updated based on the first scheduling rate.

[0036] Specifically, this embodiment proposes a scheduling rate calculation method, which calculates the total scheduling rate of the transmit pipeline based on the available ratio of cache bandwidth and / or DMA bandwidth. The cache bandwidth includes cache write bandwidth and cache read bandwidth, and the DMA bandwidth includes DMA write bandwidth and DMA read bandwidth. Therefore, the calculation of the total scheduling rate of the transmit pipeline in this embodiment includes: Let the current total scheduling rate of the transmit pipeline be V_cur, the current cache read bandwidth occupied by the transmit pipeline be CACHE.tx_rd, the cache write bandwidth be CACHE.tx_wr, the DMA read bandwidth be DMA.tx_rd, and the DMA write bandwidth be DMA.tx_wr; the current available cache read bandwidth of the transmit pipeline be CACHE.tx_rd_avd, the cache write bandwidth be CACHE.tx_wr_avd, the DMA read bandwidth be DMA.tx_rd_avd, and the DMA write bandwidth be DMA.tx_wr_avd. The scheduling rate based on cache read bandwidth is: V_rd_cache = V_cur × (CACHE.tx_rd_avd / CACHE.tx_rd); The scheduling rate based on cache write bandwidth is: V_wr_cache = V_cur × (CACHE.tx_wr_avd / CACHE.tx_wr); The scheduling rate based on DMA read bandwidth is: V_rd_dma = V_cur × (DMA.tx_rd_avd / DMA.tx_rd); The scheduling rate based on DMA write bandwidth is: V_wr_dma = V_cur × (DMA.tx_wr_avd / DMA.tx_wr); The first scheduling rate V_new1 can be any one of the four scheduling rates mentioned above, or multiple scheduling rates can be selected and weighted summed; for example: V_new1 = ε1 × V_rd_cache + ε2 × V_wr_cache + ε3 × V_rd_dma + ε4 ×V_wr_dma, where ε1 to ε4 are preset weights, and their sum is 1.

[0037] In some specific embodiments, step S30 includes: Obtain the current scheduling rate of the sending pipeline, and obtain a second scheduling rate based on the current scheduling rate of the sending pipeline, the current number of tasks in the sending pipeline, and the current maximum allowed number of tasks in the sending pipeline; The total scheduling rate of the transmission pipeline is updated based on the first scheduling rate and the second scheduling rate.

[0038] Specifically, in this embodiment, the scheduling rate is further adjusted based on the proportion of the number of tasks. Let the current total scheduling rate of the sending pipeline be V_cur, the current maximum allowed number of tasks in the sending pipeline be J_avd, the current number of tasks be J_cur, and the second scheduling rate be V_new2. Then, V_new2 = V_cur × (J_avd / J_cur). This proportion reflects the margin of task processing capacity. When the allowed number of tasks is greater than the current number of tasks, the total scheduling rate is increased proportionally; otherwise, it is decreased. Furthermore, a weighted average method can be used: V_new = α × V_new1 + (1-α) × V_new2, where α is a preset weight (such as 0.5); or a minimum value method can be used: V_new = min(V_new1, V_new2), taking the bottleneck resource as the standard, and the merged scheduling rate as the final total scheduling rate.

[0039] In some specific embodiments, the method further includes: After obtaining the total scheduling rate of the sending pipeline, the number of request traffic tasks and the number of response traffic tasks currently being processed by the sending pipeline are obtained. Based on the number of request traffic tasks and the number of response traffic tasks, as well as the total scheduling rate of the sending pipeline, the request traffic task scheduling rate and response traffic task scheduling rate of the sending pipeline are obtained.

[0040] Specifically, after obtaining the total scheduling rate of the sending pipeline, this total scheduling rate needs to be further allocated to two different types of traffic: sending requests and sending responses. In this embodiment, the allocation weight is determined based on the number of request traffic tasks and the number of response traffic tasks currently being processed. Specifically, let the number of request traffic tasks currently being processed be J_req and the number of response traffic tasks currently being processed be J_rsp. Then, the scheduling weight for request traffic is J_rsp / (J_req+J_rsp), and the scheduling weight for response traffic is J_req / (J_req+J_rsp). The scheduling weight is calculated using the number of tasks for both traffic types to allow the side with fewer tasks to obtain a higher scheduling rate, thereby achieving load balancing between the two types of traffic. Then, the total scheduling rate is multiplied by the corresponding weight to obtain the scheduling rate for request traffic tasks and the scheduling rate for response traffic tasks.

[0041] In some specific embodiments, the method further includes: After obtaining the request traffic task scheduling rate and response traffic task scheduling rate of the sending pipeline, the current scheduling rate of any one of the RDMA semantics in the request traffic or response traffic is obtained. The corresponding cache bandwidth and / or DMA bandwidth is determined according to the current scheduling rate of the RDMA semantic. The scheduling rate of the RDMA semantic is obtained according to the current scheduling rate of the RDMA semantic and its corresponding cache bandwidth and / or DMA bandwidth, as well as the cache bandwidth and / or DMA bandwidth currently available in the sending pipeline.

[0042] Specifically, request traffic includes various RDMA operation types, such as Send, Write, Read, and Atomic, each with different requirements for cache and DMA bandwidth. Similarly, response traffic also includes different types such as ACK, ReadResponse, and Atomic ACK. Therefore, after obtaining the task scheduling rates for request and response traffic, it is necessary to further subdivide them into each specific RDMA semantic.

[0043] The method adopted in this embodiment is as follows: obtain the current scheduling rate of each RDMA semantic, and obtain the cache bandwidth and / or DMA bandwidth occupied by the corresponding RDMA semantic based on the current scheduling rate and the preset mapping relationship / calculation formula. The mapping relationship / calculation formula is preset before the method of this embodiment is executed; then, calculate the new scheduling rate of the RDMA semantic based on the ratio of the cache bandwidth and / or DMA bandwidth occupied by each RDMA semantic to the currently available cache bandwidth and / or DMA bandwidth of the transmit pipeline.

[0044] The cache bandwidth includes cache write bandwidth and cache read bandwidth, and the DMA bandwidth includes DMA write bandwidth and DMA read bandwidth. Therefore, the scheduling rate calculation for a certain RDMA semantic in this embodiment includes: Let V_sem_cur be the current scheduling rate of a certain RDMA semantic, and let CACHE.sem_rd, CACHE.sem_wr, DMA read bandwidth, and DMA write bandwidth be the current occupancy of this RDMA semantic. Let CACHE.tx_rd_avd, CACHE.tx_wr_avd, DMA read bandwidth, and DMA write bandwidth be the current available Cache read bandwidth, CACHE.tx_rd_avd, DMA write bandwidth, and DMA write bandwidth be the current available DMA read bandwidth and DMA write bandwidth.tx_wr_avd. The scheduling rate based on cache read bandwidth is: V_sem_rd_cache = V_sem_cur × (CACHE.tx_rd_avd / CACHE.sem_rd); The scheduling rate based on cache write bandwidth is: V_sem_wr_cache = V_sem_cur × (CACHE.tx_wr_avd / CACHE.sem_wr); The scheduling rate based on DMA read bandwidth is: V_sem_rd_dma = V_sem_cur × (DMA.tx_rd_avd / DMA.sem_rd); The scheduling rate based on DMA write bandwidth is: V_sem_wr_dma = V_sem_cur × (DMA.tx_wr_avd / DMA.sem_wr); The new scheduling rate V_sem_new for this RDMA semantics can be any one of the four scheduling rates mentioned above, or multiple scheduling rates can be selected and weighted summed; for example: V_sem_new = η1 × V_sem_rd_cache + η2 × V_sem_wr_cache + η3 × V_sem_rd_dma + η4 × V_sem_wr_dma; Where η1 to η4 are preset weights, and their sum is 1; In addition, a priority adjustment coefficient γ can be introduced based on the priority of the RDMA semantic, i.e., V_sem_new = V_sem_new × γ, and the higher the priority of the RDMA semantic, the larger the value of γ.

[0045] Another embodiment of this application provides an adaptive rate control device, including a module for performing the method described in the above embodiments.

[0046] Specifically, the apparatus of this embodiment includes functional modules for performing the steps of the methods described in the above embodiments. For example: a monitoring module for acquiring cache miss rate, DMA read latency, the number of tasks in each pipeline, and bandwidth usage; a calculation module for calculating the maximum allowed number of tasks, available bandwidth, scheduling rate, etc., based on the monitoring data; and a scheduling module for executing actual transmission scheduling based on the calculation results. Each module can be implemented using hardware circuits (such as state machines, counters, comparators, multipliers), or using a microprocessor in conjunction with firmware, or a combination of hardware and software. The module division is only a logical functional division; in actual physical implementation, they can be merged or further split.

[0047] It should be noted that the adaptive rate control device in this embodiment corresponds to the adaptive rate control method in the above embodiments. The contents of the adaptive rate control device in this embodiment that are not described in detail can be obtained by referring to the contents of the adaptive rate control method in the above embodiments. The adaptive rate control device in this embodiment will not be described in detail again.

[0048] Another embodiment of this application provides a network interface card (NIC), including: A communication interface used for communicating with other electronic devices; Memory is used to store computer program instructions; A processor is configured to execute the computer program instructions to support the network card in implementing the adaptive rate control method according to the above embodiments.

[0049] In this embodiment, the memory mainly includes a program storage area and a data storage area. The program storage area can store the operating device, applications required for at least one function, etc., and the data storage area can store related data, etc. Furthermore, the memory can be a high-speed random access memory, or a non-volatile memory, such as a plug-in hard disk, a smart media card (SMC), a secure digital card (SD), and a flash card, or other volatile solid-state storage devices.

[0050] The processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor, or the processor can be any conventional processor. The processor is the control center of the network card and uses various interfaces and lines to connect the various parts of the network card.

[0051] Another embodiment of this application provides a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the adaptive rate control method as described in the above embodiments.

[0052] Specifically, the computer-readable storage medium provided in this application includes, but is not limited to, non-volatile or volatile media such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks. When the computer program instructions stored in this storage medium are executed by a processor (e.g., an embedded processor in a network card, a host CPU, or a dedicated processing unit), they can implement all or part of the steps of the aforementioned adaptive rate control method. This medium can be sold or used independently, or it can be pre-installed in the network card as part of the network card firmware.

[0053] Another embodiment of this application provides a computer program product, including computer program instructions that instruct a computer device to perform operations corresponding to the adaptive rate control method described in the above embodiments.

[0054] Specifically, the computer program product provided in this application embodiment can take the form of a software installation package, firmware upgrade package, or directly executable program file. This computer program product contains computer program instructions, which, when loaded and executed by a computer device (e.g., a server, host, or network card), instruct the device to perform the operations corresponding to the aforementioned adaptive rate control method. This program product can be downloaded and distributed via a network (e.g., the Internet, a local area network), or it can be pre-stored in a storage medium.

[0055] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technological improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. An adaptive rate control method applied to an RDMA engine, characterized in that, The method includes: The cache miss rate and / or DMA read latency of the RDMA engine are obtained, and the scheduling rate of the transmit pipeline is adjusted based on the cache miss rate and / or DMA read latency. The cache miss rate is the on-chip cache miss rate of the RDMA engine, and the DMA read latency is the latency for the DMA module of the RDMA engine to read host memory data. If it is determined that the scheduling rate of the transmit pipeline should be adjusted, the cache bandwidth and / or DMA bandwidth currently occupied by the receive pipeline should be obtained, and the cache bandwidth and / or DMA bandwidth currently available to the transmit pipeline should be obtained according to the preset cache bandwidth limit and / or DMA bandwidth limit and the cache bandwidth and / or DMA bandwidth currently occupied by the receive pipeline. The scheduling rate of the transmission pipeline is updated based on the cache bandwidth and / or DMA bandwidth currently available to the transmission pipeline.

2. The method according to claim 1, characterized in that, The step of determining whether to adjust the scheduling rate of the transmit pipeline based on the cache miss rate and / or DMA read latency includes: Based on the cache miss rate and a preset miss rate threshold, and / or the DMA read latency and a preset read latency threshold, the current maximum allowed total number of tasks for the RDMA engine is obtained, and the current maximum allowed number of tasks for the receive pipeline is obtained. The current maximum allowed number of tasks in the sending pipeline is obtained based on the current maximum allowed total number of tasks and the current maximum allowed number of tasks in the receiving pipeline, and the current number of tasks in the sending pipeline is also obtained. Whether to adjust the scheduling rate of the sending pipeline is determined based on the current number of tasks in the sending pipeline and the current maximum allowed number of tasks in the sending pipeline.

3. The method according to claim 2, characterized in that, The step of determining whether to adjust the scheduling rate of the sending pipeline based on the current number of tasks in the sending pipeline and the current maximum allowed number of tasks in the sending pipeline includes: When the current number of tasks in the sending pipeline exceeds the current maximum allowed number of tasks in the sending pipeline, reduce the scheduling rate of the sending pipeline; When the current number of tasks in the sending pipeline is less than the current maximum allowed number of tasks in the sending pipeline, increase the scheduling rate of the sending pipeline; When the current number of tasks in the sending pipeline is equal to the current maximum allowed number of tasks in the sending pipeline, the scheduling rate of the sending pipeline remains unchanged.

4. The method according to claim 2, characterized in that, The step of updating the scheduling rate of the transmission pipeline based on the available cache bandwidth and / or DMA bandwidth of the transmission pipeline includes: Obtain the cache bandwidth and / or DMA bandwidth currently occupied by the transmit pipeline, and obtain the first scheduling rate based on the cache bandwidth and / or DMA bandwidth currently available to the transmit pipeline and the cache bandwidth and / or DMA bandwidth currently occupied by the transmit pipeline. The total scheduling rate of the sending pipeline is updated based on the first scheduling rate.

5. The method according to claim 4, characterized in that, The step of updating the scheduling rate of the transmission pipeline based on the available cache bandwidth and / or DMA bandwidth of the transmission pipeline includes: Obtain the current scheduling rate of the sending pipeline, and obtain a second scheduling rate based on the current scheduling rate of the sending pipeline, the current number of tasks in the sending pipeline, and the current maximum allowed number of tasks in the sending pipeline; The total scheduling rate of the transmission pipeline is updated based on the first scheduling rate and the second scheduling rate.

6. The method according to claim 4 or 5, characterized in that, The method further includes: After obtaining the total scheduling rate of the sending pipeline, the number of request traffic tasks and the number of response traffic tasks currently being processed by the sending pipeline are obtained; based on the number of request traffic tasks and the number of response traffic tasks, as well as the total scheduling rate of the sending pipeline, the request traffic task scheduling rate and response traffic task scheduling rate of the sending pipeline are obtained.

7. The method according to claim 6, characterized in that, The method further includes: After obtaining the request traffic task scheduling rate and response traffic task scheduling rate of the sending pipeline, the current scheduling rate of any one of the RDMA semantics in the request traffic or response traffic is obtained; the corresponding cache bandwidth and / or DMA bandwidth is determined according to the current scheduling rate of the RDMA semantic; the scheduling rate of the RDMA semantic is obtained according to the current scheduling rate of the RDMA semantic and its corresponding cache bandwidth and / or DMA bandwidth, as well as the cache bandwidth and / or DMA bandwidth currently available in the sending pipeline.

8. An adaptive rate control device applied to an RDMA engine, characterized in that, Includes a module for performing the method according to any one of claims 1 to 7.

9. A network interface card (NIC), characterized in that, include: A communication interface used for communicating with other electronic devices; Memory is used to store computer program instructions; A processor for executing the computer program instructions to support the network interface card in implementing the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions that, when executed by a processor, implement the method as described in any one of claims 1 to 7.

11. A computer program product, characterized in that, It includes computer program instructions that, when executed by a processor, implement the method as described in any one of claims 1 to 7.

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