Encoding and decoding method for transmitting c-pky signals

Abstract

The application relates to an encoding and decoding method for transmitting C-PHY signals, a method for storing and transmitting a bit stream, wherein the encoding method comprises the following steps: identifying a mode in which a transmission channel of C-PHY is located; decoding line states of A lines, B lines and C lines of the transmission channel of C-PHY into 3-bit data according to the mode in which the transmission channel of C-PHY is located; in response to identifying that the mode in which the transmission channel of C-PHY is located is an HS mode, outputting the 3-bit data and adjusting the length of the 3-bit data representing a preamble, so that the length of the output 3-bit data representing the preamble meets the C-PHY protocol; and reflecting the output 3-bit data into a binary sequence and outputting the binary sequence through a transmission medium. The method avoids the problems of data loss or transmission failure in the process of transmitting C-PHY signals.

Description

Technical Field

[0001] The embodiments of this application relate to the field of optical fiber technology, and more specifically, to encoding and decoding methods for transmitting C-PHY signals, and methods for storing and transmitting bit streams. Background Technology

[0002] The Mobile Industry Processor Interface (MIPI) is an open standard developed by the MIPI Alliance for mobile application processors. MIPI's physical layer includes three types: D-PHY, M-PHY, and C-PHY. C-PHY is currently the most widely used due to its more efficient encoding mechanism and higher bandwidth utilization.

[0003] The MIPI Alliance's publicly released C-PHY protocol (Specification for C-PHY Version 2.1) uses a channel configuration called "Trio." Each Trio consists of three wires used for data transmission, representing a data channel. C-PHY transmission channels have three modes: HS (high speed) Mode, LP (Low-Power) Mode, and ALP (Alternate Low-Power) Mode. HS Mode transmission lines have six states: +x, -x, +y, -y, +z, and –z. LP Mode transmission lines have four states: LP-000, LP-001, LP-100, and LP-111. In addition to the six states of HS Mode, ALP Mode defines two more states: ALP-Pause state (VOD = 0) and ALP-Pause Wake state (VOD = |VOD| Strong). Except for the two states related to ALP Pause, ALPMode has the same states as HS wire states. These states are also called wire states.

[0004] Wire State: The wire state of the C-PHY protocol is the combination of analog signal levels driven on the three lines (A line / B line / C line) of a lane in C-PHY.

[0005] Symbol: In the C-PHY protocol, the symbol value is defined by the change in wire state values ​​from one unit interval to the next.

[0006] In the C-PHY protocol, the two communicating parties are called the Primary and Secondary. The Primary and Secondary communicate using line states transmitted via three lines (A / B / C). To send data, the Primary encodes the data to be sent into line states, while the Secondary receives the line states and decodes them to obtain the data sent by the Primary.

[0007] See Figure 1 This diagram illustrates a prior art scenario where the Primary and Secondary devices communicate using copper wires according to the C-PHY protocol. The C-PHY Primary (also known as the master device) encodes the received binary data into line status values ​​and drives the A, B, and C lines to their corresponding line states via drivers. C-PHY is based on 3-Phase Symbol encoding technology, using three wires (A / B / C) to transmit signals instead of the previously used differential pairs. It transmits 2.28 bits / symbol via three-wire trios, with a target rate of 8 G Symbols / s. C-PHY uses 5-ary transmission, which is 2.28 times more efficient than the binary transmission of D-PHY.

[0008] The master device encodes binary data into line status values. The specific process includes: In HS mode, each 16-bit binary number (16-bit HS Data) is mapped into 21 bits representing 7 symbols using the mapping relationship defined by the C-PHY protocol. These 21 bits are then converted from parallel to serial to obtain 7 symbols to be transmitted sequentially. Each symbol is represented by a 3-bit number, and this 3-bit symbol is encoded into line status according to the C-PHY protocol. In HS mode, symbols transmitted at specific times for control, synchronization, training, etc., are called special symbols. Special symbols are transmitted in 21-bit increments. These 21 bits are also converted from parallel to serial to obtain 7 3-bit symbols, and each symbol is encoded into line status according to the C-PHY protocol. Special symbols typically include Preamble, Sync Word, and Post. Low-speed signals (LP data) are transmitted in LP mode.

[0009] High-speed signals (HS data) and low-speed signals share a physical transmission channel between the C-PHY Primary and C-PHY Secondary (also known as the slave device). On the Secondary side, the received line status is restored to a binary number and output. Specifically, for HS mode, the C-PHY Secondary detects the line status, decodes it into a 3-bit symbol, and then serializes seven consecutive symbols into 21-bit data. This 21-bit data is then mapped to a 16-bit binary number using the inverse mapping relationship defined by the C-PHY protocol. Special symbols in HS mode are directly generated from the 21-bit data. If it is an LP mode signal, an LP mode detection circuit is used to detect the signal and obtain the LP mode data.

[0010] exist Figure 1 In this system, a three-phase cable is used to transmit line status between the Primary and Secondary schools. The three-phase cable consists of three copper wires (A, B, and C) that directly connect the Primary and Secondary schools. The cable is relatively thick and sensitive to electromagnetic interference; higher speeds result in shorter transmission distances, limiting its application scenarios.

[0011] The HS mode specified in the C-PHY protocol uses High Speed ​​Transmission in Burst, which means that the line status is transmitted intermittently in blocks at extremely high speeds. Figure 2This diagram illustrates the timing sequence of high-speed burst transmission in HS mode. The CPHY protocol defines HS mode high-speed burst transmission as consisting of four parts: Preamble, Sync word, Packet data, and Post. The Preamble is the preamble, serving as the start marker for data transmission. It consists of consecutive "3" symbols, with a length of at least 14 symbols. The Sync word precisely identifies the start of the data packet and the timing alignment of word boundaries; it follows the Preamble for synchronization. The Sync word is a fixed 7-symbol sequence: "3-4-4-4-4-4-3". Packet data represents the data packet, and Post marks the end of Packet data transmission. Post consists of consecutive "4" symbols, with a length of at least 14 symbols. According to the protocol, to achieve data synchronization for high-speed data transmission, a Preamble and Post sequence should be added to the data burst at the transmitter side to assist the receiver in achieving synchronization. At the receiving end, the effects of the high-speed transmitter can be eliminated by detecting certain detectable events designed by the receiver, thus allowing the receiver to ignore the ambiguous operating state during mode transitions. Preamble and Post can only be observed during transmission.

[0012] With the rapid development of intelligent driving, in-vehicle systems now involve multiple displays and video captures, making them increasingly sensitive to transmission latency and placing higher demands on the number and distance of system cables. Transmitting C-PHY signals via active cables effectively reduces cable diameter and increases transmission distance. In active cables, the transmitted data is extracted from the line status data sent by the Primary according to the C-PHY protocol, and then the line status is regenerated using the transmitted data and provided to the Secondary according to the C-PHY protocol. Furthermore, optical fiber can be used for transmission in active cables, thus eliminating the need for the three-phase cables specified in C-PHY and achieving virtually unlimited transmission distances.

[0013] In the C-PHY protocol, the secondary end uses a preamble to identify high-speed burst transmissions. However, when transmitting C-PHY signals using active cables, the receiver of the active cable uses a mode detection unit to determine whether the received signal is in HS mode or a non-HS mode. This mode detection unit requires 1 to 4 unit intervals (UIs, the time defined by C-PHY for transmitting one symbol). For the secondary, this does not affect the reception of the Sync Word and Packet Data following the preamble. However, when using a similar technique to extract data from high-speed burst transmissions in an active cable, it results in the active cable only recognizing the high-speed burst transmission and starting transmission to the secondary after 1 to 4 UIs. This causes the 1 to 4 UIs before the mode detection unit recognizes the preamble to be discarded, preventing the secondary from receiving these UIs. This leads to the secondary receiving a preamble that does not conform to the protocol (the protocol specifies a minimum of 7 symbols for a preamble), resulting in data loss or transmission failure.

[0014] In summary, one or more of the technical issues mentioned above need to be addressed. Summary of the Invention

[0015] The embodiments described herein provide an encoding and decoding method for transmitting C-PHY signals, and a method for storing and transmitting bit streams, in order to solve the problem of data loss or transmission failure during the transmission of C-PHY signals.

[0016] According to a first aspect of this application, a transmitter for C-PHY signals is provided, comprising a mode detection unit, a decoding unit, a high-speed processing unit, and a demapping unit; wherein, the mode detection unit is used to identify the mode of the C-PHY transmission channel; the decoding unit is used to receive the line status of the A, B, and C lines of the C-PHY transmission channel and decode the line status into 3-bit data; the input terminal of the high-speed processing unit is connected to the mode detection unit and the decoding unit respectively; in response to the mode detection unit identifying that the C-PHY transmission channel is in HS mode, the high-speed processing unit is enabled, outputs the received 3-bit data, and adjusts the length of the received 3-bit data representing the preamble so that the length of the output 3-bit data representing the preamble meets the C-PHY protocol requirements; the input terminal of the demapping unit is connected to the high-speed processing unit and is used to demapping the received data into a binary sequence and outputting it.

[0017] Optionally, the 3-bit data includes a Symbol and an LP mapping code. The Symbol is a symbol defined by the C-PHY protocol. When the C-PHY transmission channel is in HS mode, the decoding unit decodes the line status to obtain the Symbol. When the C-PHY transmission channel is in LP mode, the decoding unit decodes the line status to obtain the LP mapping code.

[0018] Optionally, the high-speed processing unit includes a buffer for buffering Symbols representing preambles; in response to receiving a Symbol representing a synchronization word, and if the number of Symbols representing preambles output by the high-speed processing unit is not an integer multiple of 7, the high-speed processing unit repeatedly outputs the Symbols representing preambles buffered in the buffer before outputting the Symbol representing the synchronization word, so that the length of the output Symbol representing the preamble is an integer multiple of 7.

[0019] Optionally, the high-speed processing unit includes a buffer; before receiving the Symbol representing the synchronization word, the high-speed processing unit buffers the received Symbol representing the preamble in the buffer; in response to receiving the Symbol representing the synchronization word, the high-speed processing unit outputs the Symbol representing the preamble in the buffer in groups of 7; in response to the number of Symbols representing the preamble in the buffer being less than 7, the high-speed processing unit repeatedly outputs the buffered Symbols representing the preamble so that the number of Symbols representing the preamble is 7.

[0020] Optionally, the high-speed processing unit includes a buffer for buffering symbols representing the preamble; the high-speed processing unit outputs the preamble symbols buffered in the buffer in groups of 7 symbols; in response to the number of preamble symbols in the buffer being less than 7, the high-speed processing unit repeatedly outputs the buffered preamble symbols so that the number of preamble symbols is 7.

[0021] Optionally, in response to the C-PHY transmission channel being in LP mode, the mode detection unit generates control signals and indication signals based on the received line status. The indication signal is used to indicate the mode of the C-PHY transmission channel, and the decoding unit also generates LP mapping codes based on the control signals.

[0022] Optionally, the demapping unit demaps the received data into a 17-bit binary sequence.

[0023] Optionally, in response to the C-PHY transmission channel being in HS mode, the demapping unit demaps 7 consecutively received Symbols into a 17-bit binary sequence; in response to the C-PHY transmission channel being in LP mode, the demapping unit demaps the LP mapping code into a 17-bit binary sequence.

[0024] Optionally, it also includes a serial-to-parallel conversion unit, wherein the input of the serial-to-parallel conversion unit is connected to the high-speed processing unit and the output is connected to the demapping unit. In response to the C-PHY transmission channel being in HS mode, the serial-to-parallel conversion unit converts every 7 consecutive Symbols into parallel 21-bit data, so that the demapping unit demappings the parallel 21-bit data into a 17-bit binary sequence.

[0025] Optionally, an alignment unit is also included, wherein the input of the alignment unit is connected to the high-speed processing unit and the mode detection unit respectively; in response to the C-PHY transmission channel being in LP mode and the number of LP mapping codes not being an integer multiple of 7, the alignment unit adjusts the received LP mapping codes so that the number of LP mapping codes is an integer multiple of 7.

[0026] Optionally, in response to the C-PHY transmission channel being in LP mode and the number of received LP mapping codes not being an integer multiple of 7, the alignment unit repeatedly outputs the LP mapping code corresponding to line state LP-000 so that the number of LP mapping codes is an integer multiple of 7.

[0027] Optionally, the alignment unit is also used to align the 3-bit data output by the high-speed processing unit.

[0028] Optionally, it also includes a serial-to-parallel conversion unit, the input of which is connected to the alignment unit, for converting seven consecutive 3-bit data into parallel 21-bit data, so as to inversely map the parallel 21-bit data into a 17-bit binary sequence.

[0029] Optionally, in response to the C-PHY's transmission channel switching from LP mode to HS mode or from HS mode to LP mode, the demapping unit generates 17 bits of data representing the user synchronization code.

[0030] Optionally, it also includes a parallel-to-serial conversion unit, wherein the input of the parallel-to-serial conversion unit is connected to the inverse mapping unit, and is used to convert the received binary sequence into a serial binary sequence; wherein the serial binary sequence is transmitted through a transmission medium.

[0031] Optionally, a scrambling unit is also included, wherein the input of the scrambling unit is connected to the inverse mapping unit and the output is connected to the parallel-to-serial conversion unit, and is used to scramble the binary sequence output by the inverse mapping unit.

[0032] According to a second aspect of this application, a receiver for C-PHY signals is provided, comprising a mapping unit, an encoding unit, and a driving unit; wherein, the mapping unit is used to acquire 17-bit binary data and map the 17-bit binary data into 21-bit data, the 21-bit data consisting of seven 3-bit data; the encoding unit is used to encode the output of the mapping unit into line status values; and the driving unit is used to drive the A, B, and C lines of the C-PHY transmission channel to voltages corresponding to the line status values, respectively, according to the line status values.

[0033] Optionally, it also includes a synchronization code detection unit, wherein the output of the synchronization code detection unit is connected to the encoding unit, and is used to detect the user synchronization code in the binary sequence and generate an indication signal based on the user synchronization code. The indication signal is used to indicate the mode of the C-PHY transmission channel; the encoding unit encodes the output of the mapping unit into a line status value based on the indication signal.

[0034] Optionally, the user synchronization code includes a first user synchronization code and a second user synchronization code; in response to the user synchronization code being the first user synchronization code, the synchronization code detection unit generates an indication signal indicating that the C-PHY transmission channel is in HS mode based on the first user synchronization code; in response to the user synchronization code being the second user synchronization code, the synchronization code detection unit generates an indication signal indicating that the C-PHY transmission channel is in LP mode based on the second user synchronization code.

[0035] Optionally, the synchronization code detection unit generates an indication signal indicating that the C-PHY transmission channel is in HS mode or LP mode based on the number of times the user synchronization code is detected.

[0036] Optionally, the output of the synchronization code detection unit is connected to the mapping unit to output the received binary data to the mapping unit.

[0037] Optionally, when the encoding unit receives an indication signal that the C-PHY transmission channel is in HS mode, the 3-bit data received by the encoding unit is a Symbol, and the encoding unit encodes the Symbol into a line status value of HS mode, where Symbol is a symbol specified by the C-PHY protocol; when the encoding module receives an indication signal that the C-PHY transmission channel is in LP mode, the 3-bit data received by the encoding unit is an LP mapping code, and the encoding unit encodes the LP mapping code into a line status value of LP mode of the C-PHY transmission channel.

[0038] Optionally, it also includes a parallel-to-serial conversion unit, wherein the input of the parallel-to-serial conversion unit is connected to the mapping unit and the output is connected to the encoding unit, and is used to convert 21-bit data into multiple 3-bit data in parallel and serial, and output them sequentially, so that the encoding unit encodes the 3-bit data into the corresponding line status value.

[0039] Optionally, a clock data recovery unit is also included, wherein the output of the clock data recovery unit is connected to the synchronization code detection unit, and is used to acquire the binary sequence through the transmission medium and reshape the binary sequence according to the recovered clock signal.

[0040] Optionally, a clock data recovery unit is also included, wherein the output of the clock data recovery unit is connected to the synchronization code detection unit and the mapping unit, and is used to acquire the binary sequence through the transmission medium and reshape the binary sequence according to the clock signal recovered from the binary sequence.

[0041] Optionally, it also includes a serial-to-parallel conversion unit, wherein the input of the serial-to-parallel conversion unit is connected to the synchronization code detection unit and the output is connected to the mapping unit, and is used to convert the sequentially received 17-bit binary sequence into serial-to-parallel data and output parallel 17-bit binary data.

[0042] Optionally, a descrambling unit is also included, wherein the output of the descrambling unit is connected to the mapping unit and is used to descramble the data input to the mapping unit before inputting it into the mapping unit.

[0043] According to a third aspect of this application, an active transmission device is provided, comprising a transmitting end for C-PHY signals as described in any of the first aspects, a receiving end for C-PHY signals as described in any of the second aspects, and a high-speed signal transmission medium located between the transmitting end and the receiving end; wherein the transmitting end is configured to connect to a master device according to the C-PHY protocol to receive the line status of the A line, B line, and C line of the C-PHY transmission channel and encode the line status into a binary sequence, and the receiving end receives the binary sequence from the transmission medium, decodes the binary sequence into line status, and provides it to the slave device according to the C-PHY protocol.

[0044] According to a fourth aspect of this application, an encoding method for transmitting C-PHY signals is provided. The method includes: identifying the mode of the C-PHY transmission channel; decoding the line states of the A, B, and C lines of the C-PHY transmission channel into 3-bit data according to the mode of the C-PHY transmission channel; in response to identifying that the mode of the C-PHY transmission channel is HS mode, outputting the 3-bit data, and adjusting the length of the 3-bit data representing the preamble so that the length of the output 3-bit data representing the preamble meets the C-PHY protocol requirements; and inversely mapping the output 3-bit data into a binary sequence and outputting it through a transmission medium.

[0045] Optionally, the 3-bit data includes Symbol and LP mapping code. Symbol is a symbol defined by the C-PHY protocol. When the C-PHY transmission channel is in HS mode, the line status of the A, B, and C lines of the C-PHY transmission channel is decoded into Symbol. When the C-PHY transmission channel is in LP mode, the line status of the A, B, and C lines of the C-PHY transmission channel is decoded into LP mapping code.

[0046] Optionally, the encoding method includes: in response to the transmission channel of the C-PHY being in HS mode, buffering the Symbol representing the preamble; when the number of Symbols representing the preamble that are decoded before the Symbol representing the synchronization word is not an integer multiple of 7, repeatedly adding the buffered Symbol representing the preamble before the Symbol representing the synchronization word, so that the length of the Symbol representing the preamble is an integer multiple of 7.

[0047] Optionally, the encoding method includes: in response to the C-PHY transmission channel being in HS mode, buffering the symbol representing the preamble before the symbol representing the synchronization word; outputting the buffered symbols representing the preamble sequentially in groups of 7; and when the number of buffered symbols representing the preamble is less than 7, repeatedly outputting the buffered symbols representing the preamble so that the number of symbols representing the preamble is 7.

[0048] Optionally, the encoding method includes: in response to the transmission channel of the C-PHY being in HS mode, buffering the symbols representing the preamble, and outputting the buffered symbols representing the preamble in groups of 7; when the number of buffered symbols representing the preamble is less than 7, repeatedly outputting the buffered symbols representing the preamble so that the number of symbols representing the preamble is 7.

[0049] Optionally, the encoding method further includes: in response to the C-PHY transmission channel being in LP mode, generating control signals and indication signals according to the line status of the A, B, and C lines of the C-PHY transmission channel, and generating LP mapping codes according to the control signals; wherein, the indication signals are used to indicate the mode of the C-PHY transmission channel.

[0050] Optionally, the encoding method includes: remapping every 7 consecutive 3-bit data into a 17-bit binary sequence.

[0051] Optionally, the encoding method includes: in response to the transmission channel of C-PHY being in HS mode, mapping 7 consecutive Symbols into a 17-bit binary sequence; in response to the transmission channel of C-PHY being in LP mode, mapping the LP mapping code into a 17-bit binary sequence.

[0052] Optionally, the method further includes: in response to the C-PHY transmission channel being in HS mode, performing serial-to-parallel conversion on every 7 consecutive Symbols to generate parallel 21-bit data, so as to inversely map the parallel 21-bit data into a 17-bit binary sequence.

[0053] Optionally, the encoding method further includes: in response to the C-PHY transmission channel being in LP mode and the number of LP mapping codes not being an integer multiple of 7, adjusting the number of LP mapping codes to make the number of LP mapping codes an integer multiple of 7.

[0054] Optionally, the encoding method further includes: in response to the C-PHY transmission channel being in LP mode and the number of LP mapping codes not being an integer multiple of 7, repeatedly outputting the LP mapping code corresponding to the line state LP-000 so that the number of LP mapping codes is an integer multiple of 7.

[0055] Optionally, the encoding method may also include: aligning the output 3-bit data.

[0056] Optionally, after aligning the output 3-bit data, the encoding method further includes: converting 7 consecutive 3-bit data into parallel 21-bit data, so as to inversely map the parallel 21-bit data into a 17-bit binary sequence.

[0057] Optionally, the encoding method also includes: generating 17 bits of data representing the user synchronization code in response to the C-PHY's transmission channel switching from LP mode to HS mode or from HS mode to LP mode.

[0058] Optionally, the encoding method also includes: converting the binary sequence from parallel to serial to generate a serial binary sequence.

[0059] Optionally, the encoding method may also include scrambling the binary sequence before performing parallel-to-serial conversion on the binary sequence.

[0060] According to a fifth aspect of the embodiments of this application, a method for storing a bit stream is provided, comprising generating a bit stream by performing an encoding method for transmitting C-PHY signals according to any one of the preceding fourth aspects; and storing the bit stream.

[0061] According to a sixth aspect of the embodiments of this application, a method for transmitting a bit stream is provided, comprising generating a bit stream by performing an encoding method for transmitting C-PHY signals according to any one of the preceding fourth aspects; and transmitting the bit stream.

[0062] According to a seventh aspect of the present application, a decoding method for C-PHY signals is provided. The method includes: acquiring 17-bit binary data and mapping the 17-bit binary data to 21-bit data, wherein the 21-bit data consists of seven 3-bit data; encoding the 21-bit data into line status values; and, according to the line status values, driving the A-line, B-line, and C-line of the transmission channel of the C-PHY to be at voltages corresponding to the line status values.

[0063] Optionally, the decoding method further includes: generating an indication signal based on the user synchronization code in the binary sequence, the indication signal being used to indicate the mode of the C-PHY transmission channel; and encoding 21 bits of data into a line status value based on the indication signal.

[0064] Optionally, the user synchronization code includes a first user synchronization code and a second user synchronization code; in response to the user synchronization code being the first user synchronization code, an indication signal indicating that the C-PHY transmission channel is in HS mode is generated based on the first user synchronization code; in response to the user synchronization code being the second user synchronization code, an indication signal indicating that the C-PHY transmission channel is in LP mode is generated based on the second user synchronization code.

[0065] Optionally, the decoding method further includes: obtaining the number of times the user synchronization code is obtained, and generating an indication signal indicating that the C-PHY transmission channel is in HS mode or LP mode based on the number of times the user synchronization code is obtained.

[0066] Optionally, in response to an indication signal indicating that the C-PHY transmission channel is in HS mode, the 3-bit data is a Symbol, which is encoded into a line status value for HS mode, where Symbol is a symbol defined by the C-PHY protocol; in response to an indication signal indicating that the C-PHY transmission channel is in LP mode, the 3-bit data is an LP mapping code, which is encoded into a line status value for LP mode for the C-PHY transmission channel.

[0067] Optionally, after mapping the 17-bit binary data to 21-bit data, the decoding method further includes: converting the 21-bit data into multiple 3-bit data in parallel and serial, and encoding the 3-bit data into corresponding line status values.

[0068] Optionally, before generating an indication signal based on the user synchronization code in the binary sequence, the decoding method further includes: acquiring the binary sequence through the transmission medium and shaping the binary sequence based on the recovered clock signal.

[0069] Optionally, the decoding method also includes: converting the 17-bit binary sequence into parallel 17-bit binary data.

[0070] Optionally, before acquiring the 17-bit binary data, the decoding method may further include descrambling the 17-bit binary data.

[0071] According to an eighth aspect of this application, a method for storing a bit stream is provided, comprising generating a bit stream by performing a decoding method for transmitting C-PHY signals according to any one of the preceding seventh aspects; and storing the bit stream.

[0072] According to a ninth aspect of this application, a method for transmitting a bit stream is provided, comprising generating a bit stream by performing a decoding method for transmitting a C-PHY signal according to any one of the preceding seventh aspects; and transmitting the bit stream.

[0073] In summary, this application has the following advantages:

[0074] 1. When the C-PHY channel is in HS mode, the sending end supplements the Symbol representing the preamble. Even if the mode detection unit recognizes that the preamble of HS mode requires 1 to 4 UIs, resulting in 1 to 4 UIs (symbol "3") of the preamble being missed in the link, the data received by the Secondary end still conforms to the C-PHY protocol, thereby avoiding data loss or transmission failure; 2. The transmitting end can also decode the line status in LP mode through the mode detection unit and decode it into the corresponding LP mapping code in the decoding unit, which improves the reliability, anti-interference ability and transmission distance of line status transition in LP mode; 3. By extending the original C-PHY protocol's mapping table to unify the mapping of high-speed and low-speed signals, the anti-mapping unit can map all HS and LP mode line states output by the master device into 17-bit binary data through a 21-17 mapping relationship. The 17-bit binary encoding space includes 7 consecutive Symbols for HS mode and possible values ​​for LP mode line states. The 17-bit binary data is then transmitted to the RX end of the active transmission device, ensuring that no line state is lost. 4. By generating 17 bits of data representing the user synchronization code when switching between HS mode and LP mode of C-PHY channel, the RX end of the active transmission device can accurately identify whether the current C-PHY channel is in HS mode or LP mode based on the 17 bits of data representing the user synchronization code, thereby avoiding the inability of the RX end to encode the received binary sequence into the line status value received by the transmitter. 5. The TX end of the active transmission device encodes the line status of the C-PHY protocol transmitted on lines A, B and C into a binary number sequence before transmitting it through the transmission medium. This reduces the cable diameter, lowers the requirements for timing offset, provides excellent anti-interference capability, and enables long-distance transmission of C-PHY. 6. When the C-PHY channel switches between HS mode and LP mode, the first user synchronization code can be used to replace the binary sequence corresponding to the 17-bit line status LP-000, and the second user synchronization code can be used to replace the binary sequence corresponding to the 17-bit line status LP-111; this avoids bandwidth occupation and timing adjustment caused by directly inserting user synchronization codes, and simplifies the processing at the RX end. 7. By setting a scrambling unit on the TX end and a decoding unit on the RX end, the accuracy of data recovery is ensured. Attached Figure Description

[0075] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this application and are not intended to limit this application, wherein: Figure 1 This diagram illustrates a prior art technique in which the Primary and Secondary communicate using copper wires according to the C-PHY protocol. Figure 2 A timing diagram of the sequence of high-speed burst transmissions in HS mode line states is shown; Figure 3 A schematic diagram of the structure of a C-PHY communication system applying an embodiment of this application is shown; Figure 4 This paper shows a schematic diagram of the structure of a transmitter (TX) according to an embodiment of this application; Figure 5 A flowchart of a data transmission method of the transmitting end TX according to an embodiment of this application is shown; Figure 6 This paper shows a schematic diagram of the structure of a receiver RX in an embodiment of this application; Figure 7 A flowchart of a data receiving method for the receiving end RX in an embodiment of this application is shown; Figure 8 This paper shows a schematic diagram of another transmitter (TX) structure according to an embodiment of this application; Figure 9 This illustration shows a binary sequence generated by inverse mapping using a user synchronization code to replace part of the LP mapping code, according to an embodiment of this application. Figure 10 A schematic diagram of another receiver RX according to an embodiment of this application is shown; Figure 11 This paper shows a schematic diagram of the structure of another transmitting end TX according to an embodiment of this application; Figure 12 This paper shows a schematic diagram of the structure of the RX of another receiving end according to an embodiment of the present application; Figure 13 This paper illustrates a schematic diagram of a communication system structure for another C-PHY according to an embodiment of this application. The elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0076] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the described embodiments of this application without creative effort are also within the scope of protection of this application.

[0077] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, statements of “connecting” or “coupling” two or more parts shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0078] In all embodiments of this application, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0079] Example 1 Figure 3 This illustration shows a schematic diagram of a C-PHY communication system applying an embodiment of this application. It includes a C-PHY Primary and a C-PHY Secondary that communicate with each other. The C-PHY Primary and C-PHY Secondary are connected via an active transmission device 300 according to an embodiment of this application. The active transmission device 300 of this embodiment is, for example, an active optical cable or an active copper cable. The active transmission device 300 includes a transmitting end (TX) and a receiving end (RX), and a high-speed signal transmission medium located between them. The transmitting end is for transmitting C-PHY signals, used to connect to the master device (C-PHY Primary) to receive C-PHY line status, encode it, output binary data, and transmit it to the receiving end via the transmission medium. The receiving end is for receiving C-PHY signals, used to remap the received binary data back to line status, and send it to the slave device (C-PHY Secondary). The active transmission device of this embodiment replaces the existing three-phase cable for transmitting line status between the Primary and Secondary devices.

[0080] Furthermore, in this embodiment, the transmitting end TX encodes the received C-PHY line status into binary data for output. The specific encoding process includes: detecting the mode corresponding to the current C-PHY line status; if it is HS mode, decoding the line status into a Symbol according to the C-PHY protocol definition; if it is LP mode, mapping the LP mode line status into an LP mapping code according to the mapping relationship of this application. Each Symbol and LP mapping code is 3 bits, but with different meanings. For the Symbol representing the Preamble in HS mode, a preamble needs to be added according to the C-PHY protocol specification. The added Symbol is then reverse-mapped into binary data and transmitted on the transmission medium. Thus, even if the mode detection unit loses some UI Symbols when identifying the Preamble, the RX end of the active cable still sends the line status conforming to the C-PHY protocol to the Secondary end, thereby avoiding data loss or transmission failure.

[0081] It should be noted that in the background technology, the transmitter side adds preamble and post to data bursts. Here, the transmitter side refers to the end of the device that sends signals, either the primary or secondary. When the primary needs to send a signal to the secondary, the primary acts as the transmitter and the secondary as the receiver. When the secondary needs to send a signal to the primary, the data transmission direction can be reversed through a lane turnaround procedure, in which case the secondary becomes the transmitter and the primary becomes the receiver. It is understandable that the transmitter end (TX) of an active cable differs from the transmitter side in the C-PHY protocol. When the data transmission direction of the link is reversed, the receiving end (RX) of the active cable receives the C-PHY line status output from the slave device (C-PHY Secondary), encodes it, and outputs it as binary data. This binary data is then transmitted through the transmission medium to the transmitting end (TX) of the active cable. The transmitting end (TX) of the active cable remaps the received binary data back to the line status and sends it to the master device (C-PHY Primary). For simplicity, this explanation uses the Primary end as the transmitting end as an example. It should be understood that the working process is similar when the Secondary end is the transmitting end, so it will not be elaborated further.

[0082] Example 2 like Figure 4As shown in the figure, this application proposes a schematic diagram of the structure of a transmitter (TX). It includes a mode detection unit 110, a decoding unit 120, a high-speed processing unit 130, a serial-to-parallel conversion unit 140, an inverse mapping unit 150, and a parallel-to-serial conversion unit 160.

[0083] The input terminal of the mode detection unit 110 is connected to the main device via the A / B / C lines of the C-PHY, receiving the line status output by the main device. Based on the received line status, the mode detection unit 110 identifies the mode of the C-PHY transmission channel and outputs a control signal EN1 and an indication signal HS / LP_Flag. The indication signal HS / LP_Flag indicates whether the current transmission channel is in HS mode or LP mode. The specific method for identifying the current transmission channel mode is existing technology, such as distinguishing by voltage value, different line status values, or the rate of change of line status.

[0084] The EN1 signal output by the mode detection unit 110 has four possible values: EN1=2'b10, indicating that the current transmission channel is in HS mode; EN1=2'b00, representing the LP_000 state of LP mode; EN1=2'b01, representing the LP_001 state of LP mode; and EN=2'b11, representing the LP_111 state of LP mode. This establishes a direct correspondence between the EN1 signal and the line state of the LP mode it represents. By adding one bit of data to the EN1 signal, the decoding result of the line state can be obtained, thus simplifying the decoding unit 120. It is understandable that the mode detection unit 110 can also output EN1 signals with other different values ​​to represent the line state of LP mode.

[0085] In one embodiment, the input terminal of the decoding unit 120 is connected to the A / B / C three-wire connection of the master device, and also to the control signal EN1 output by the mode detection unit 110. When EN1=2'b10, it indicates that the current transmission channel is in HS mode, and the received line status is the HS mode line status. The decoding unit 120 decodes each received line status into a 3-bit binary number representing a Symbol according to the C-PHY protocol. If EN1=2'b00, it indicates that the current transmission channel is in LP mode, and the received line status is LP_000. The decoding unit 120 decodes the line status LP_000 into 3 bits 000. Similarly, when EN1=2'b01, the decoding unit 120 decodes the line status LP_001 into 001; when EN1=2'b11, the decoding unit 120 decodes the line status LP_111 into 111. In this application, the decoding result of the LP mode line status output by the decoding unit 120 is called the LP mapping code.

[0086] In existing technologies, the process of mapping the received line status to binary data in LP mode by the Secondary layer involves the physical layer LP-RX module monitoring the A / C line levels in real time, comparing voltage levels to map continuous line statuses to a raw bit stream, and then the protocol layer assembling the data packets according to byte alignment rules. For schemes using an active transmission device 300 to transmit data between the Primary and Secondary layers, if the transmitting end TX uses this scheme to identify the line status in LP mode, it not only requires the introduction of additional active repeater devices, increasing system cost and design complexity, but also the LP-RX module's detection accuracy is easily affected by signal attenuation, noise interference, and process deviations, leading to bit misjudgment. Finally, timing offsets or glitches during cable transmission can easily cause boundary misalignment, resulting in data packet parsing errors. In this embodiment, the transmitting end TX, with decoding unit 120 outputting the corresponding LP mapping code through mode detection unit 110, improves the reliability, anti-interference capability, and transmission distance of LP mode line status transitions.

[0087] In another embodiment, the input terminal of the decoding unit 120 is connected to the A / B / C lines of the master device, and also to the control signal EN1 and the indication signal HS / LP_Flag output by the mode detection unit 110. When the indication signal indicates that the current transmission channel is in HS mode and the received line status is in HS mode, the decoding unit 120 decodes each received line status into a 3-bit binary number representing a Symbol according to the C-PHY protocol; when the indication signal indicates that the current transmission channel is in LP mode, the decoding unit 120 outputs the corresponding LP mapping code according to the received control signal EN1.

[0088] The input terminal of the high-speed processing unit 130 is connected to the decoding unit 120 and the mode detection unit 110. The high-speed processing unit 130 determines whether the currently received 3-bit data is a Symbol in HS mode or an LP mapping code in LP mode based on the indication signal HS / LP_flag output by the mode detection unit 110.

[0089] If a 3-bit data symbol in HS mode is received, the high-speed processing unit 130 completes the preamble at the start of high-speed burst transmission and sends out the subsequently received symbols in sequence. Because the mode detection unit 110 needs 1 to 4 UIs to identify the HS mode preamble, it means that 1 to 4 UIs (symbol "3") of the preamble will be missed in the link. At this time, the mode detection unit 110 has not yet output the HS / LP flag indicating the HS mode, so the high-speed processing unit 130 will not receive or process these preamble symbols.

[0090] To meet the requirements of the C-PHY protocol, the number of symbols in the preamble must conform to the protocol. Missing the detection of 1 to 4 UI symbols will result in the high-speed processing unit 130 receiving preamble symbols that do not meet the protocol requirements. To solve this problem, after the mode detection unit 110 outputs the HS / LP flag indicating the HS mode, the high-speed processing unit 130 buffers the received symbols representing the preamble and sends the received symbols to the serial-to-parallel conversion unit 140. When a Symbol representing the Sync Word is detected, if the number of Symbols representing the Preamble already sent to the serial-to-parallel conversion unit 140 is less than a multiple of 7, cached Symbols representing the Preamble are sent to the serial-to-parallel conversion unit 140 as supplementary Symbols representing the Preamble. This ensures that the number of Symbols representing the Preamble sent to the serial-to-parallel conversion unit 140 is a multiple of 7, guaranteeing that the Preamble before the Sync Word conforms to the C-PHY protocol specification. The Symbols representing the Sync Word received at this time are cached in the high-speed processing unit 130. Subsequently, the newly received Symbols are cached, and the cached Symbols are sent to the serial-to-parallel conversion unit 140.

[0091] Optionally, before detecting the Symbol of the Sync Word, the high-speed processing unit 130 buffers the received Symbol of the Preamble in a buffer; after detecting the Symbol of the Sync Word, it sends a group of 7 Symbols from the buffer to the serial-to-parallel conversion unit 140 in sequence, with the Symbol of the Sync Word as the boundary. If the number of Symbols representing the Preamble in the buffer is less than 7, the buffered Symbols are sent repeatedly to make up the 7.

[0092] For example, such as Figure 2 As shown, according to the C-PHY protocol, a preamble consists of a sequence of symbols with a value of "3" in a data burst. In this embodiment, the symbols lost due to the establishment of the pattern detection unit 110 are generally the first few symbols with a value of "3" in the preamble sequence. Accordingly, the symbols used to supplement the preamble are the symbols with the missing values ​​of "3" to conform to the protocol specification. Therefore, the high-speed processing unit 130 can generate the symbols for supplementation not only using the cached symbols representing the preamble, but also using the symbols with a value of "3".

[0093] In one embodiment, the high-speed processing unit 130 caches some of the symbols in the preamble. The high-speed processing unit 130 sends the cached preamble symbols to the serial-to-parallel conversion unit 140 in groups of 7. When the Sync Word symbol is detected, the high-speed processing unit 130 sends 7 symbols from the cache to the serial-to-parallel conversion unit 140 with the Sync Word as the boundary. If there are less than 7 preamble symbols, the cached symbols are sent repeatedly to make up the 7.

[0094] The following example illustrates the scheme: the master device sends a preamble containing 21 symbols, the high-speed processing unit 130's buffer can only hold 14 symbols, and the high-speed processing unit 130 receives 18 symbols from the preamble. The master device sequentially sends a preamble containing 21 symbols. The pattern detection unit 110 identifies that the preamble is missing the first 3 symbols. The high-speed processing unit 130 sequentially receives 14 of the remaining 18 symbols and stores them in the buffer. Then, it outputs 7 symbols as a group from the buffer. After detecting the Sync Word symbol, the high-speed processing unit 130's buffer now holds 4 symbols from the preamble. Since the buffer contains fewer than 7 symbols from the preamble, the high-speed processing unit 130 outputs 3 additional symbols (preamble symbols) in addition to the 4 symbols in the buffer to complete the 7-symbol set.

[0095] For LP mode, the high-speed processing unit 130 forwards the 3-bit LP mapping code received from the decoding unit 120 to the serial-to-parallel conversion unit 140. Optionally, since the LP mapping code for LP mode does not need to be processed in the high-speed processing unit 130, the LP mapping code for LP mode can also skip the high-speed processing unit 130 and directly enter the subsequent unit after being decoded by the decoding unit 120.

[0096] The serial-to-parallel conversion unit 140 converts every 7 consecutively received Symbols or every 7 LP mapping codes into serial-to-parallel data, generating 21 bits of data, and sends it to the de-mapping unit 150.

[0097] In HS mode, the Symbol output by the high-speed processing unit 130 meets the requirements of the C-PHY protocol, ensuring that the number of Symbols is an integer multiple of 7. The serial-to-parallel conversion unit 140 can easily generate 21 bits of data from every 7 Symbols.

[0098] However, LP mapping codes need to be handled differently depending on the case. For example, if the number of LP mapping codes is exactly a multiple of 7, it can be directly converted into 21-bit data in groups of 7; if the number of LP mapping codes is not a multiple of 7, it needs to be padded to be a multiple of 7 first, and then converted into 21-bit data in groups of 7.

[0099] The input of the demapping unit 150 is connected to the serial-to-parallel conversion unit 140, and is used to demapping the received 21-bit binary data into 17-bit binary data according to a predetermined mapping rule.

[0100] The C-PHY protocol defines a mapping from 16-bit data to 21 bits (7 symbols), and a reverse mapping from 21 bits (7 symbols) to 16-bit data. In this embodiment, after the serial-to-parallel conversion unit 140 outputs a 21-bit number, the reverse mapping unit 150 does not use the original 21-16 bit reverse mapping relationship of the C-PHY protocol, but expands it to a 21-17 bit mapping, mapping the 21-bit data representing 7 symbols or 7 LP mapping codes to a 17-bit number. This allows the 17-bit number to represent both the 7 symbols of HS mode and the LP mapping codes, as well as other information that is optional and required for communication between the transmitting end (TX) and receiving end (RX) in this embodiment, but not defined by the C-PHY protocol. Thus, regardless of HS mode, LP mode, or other modes, the data transmitted by the Primary is transmitted in units of 17 bits in the transmission medium of the active transmission device 300. Other information required for communication between the transmitter (TX) and receiver (RX) of the active transmission device 300, and which is not defined by the C-PHY protocol, is also transmitted in units of 17 bits.

[0101] Because the packet data in HS mode corresponds to 7 consecutive Symbols, totaling 5 7 =78125 possibilities (as specified by the C-PHY protocol). The HS mode special symbol has 3 possibilities, and the LP mode LP mapping code includes LP_111, LP_001, and LP_000. The 21-17 bit inverse mapping needs to accommodate all the above possible values ​​to be transmitted in HS and LP modes, which means it needs to satisfy 2... L Greater than or equal to 5 7 The smallest positive integer of "+3+3" is L, which is at least 17. Therefore, at least 17 bits of binary data are needed (there are 2...). 17 =131072 (possibly) satisfies the requirement of mapping all HS and LP mode line states output by the master device to binary numbers.

[0102] In one embodiment, when demapping the 21-bit number representing the 7 Symbols of the HS mode, the demapping unit 150 first demaps the 21 bits into a 16-bit binary number according to the demapping method defined by the C-PHY protocol, and then adds a "0" as the highest bit to obtain 17-bit binary data. For the LP mode, the highest bit of the 17-bit number output by the demapping unit is "1" to distinguish it from the former.

[0103] The core function of the LP mode line status is to transmit control signals (such as commands and state switching) and to implement bus management. When an active transmission device is used to transmit data between the Primary and Secondary levels, if the active transmission device cannot transmit the LP mode line status to the Secondary side, it will cause the bus state machine to become chaotic, resulting in communication failure. In this embodiment, the 17-bit binary encoding space includes 7 consecutive Symbols of the HS mode and the possible values ​​of the LP mode line status. Thus, the anti-mapping unit 150 can transmit all the HS mode and LP mode line statuses output by the master device to the RX of the active transmission device 300 by mapping them to 17 bits of binary data, ensuring that no line status is lost.

[0104] In one embodiment, in response to the C-PHY channel switching from LP mode to HS mode, the demapping unit 150 generates 17 bits of data representing the user synchronization code; in response to the C-PHY channel switching from HS mode to LP mode, the demapping unit 150 generates 17 bits of data representing the user synchronization code. This user synchronization code is other information required for communication between the transmitting end (TX) and receiving end (RX) of the active transmission device 300 and not defined by the C-PHY protocol. This user synchronization code is used to enable the receiving end (RX) to detect the signal state and align the data of the received signal. According to the protocol, there may be overlap between the Symbol and the LP mapping code in the Symbol value. When the encoding unit of the receiving end (RX) receives 3 bits of data as 000, 001, or 111, the encoding unit cannot determine whether the current 3 bits of data are a Symbol or an LP mapping code, resulting in the inability to encode the 3 bits of data into the line state received by the transmitting end (TX), causing signal transmission failure. When the mode of the C-PHY channel changes, the inverse mapping unit 150 at the transmitting end (TX) inserts a user synchronization code, enabling the receiving end (RX) to accurately identify whether it is currently in HS mode or LP mode. This prevents the receiving end (RX) from being unable to encode the received binary sequence into the line status value received by the transmitting end (TX). In one embodiment, the user synchronization code has two different values, which are used to represent the switching of the C-PHY channel from LP mode to HS mode and from HS mode to LP mode, respectively. In another embodiment, the user synchronization code may have only a single value to indicate a mode switch of the C-PHY channel, which can represent either a switch from LP mode to HS mode or a switch from HS mode to LP mode.

[0105] In one embodiment, a portion of the codewords in the 17-bit data output by the demapping unit 150 consists of seven consecutive Symbols to be transmitted in HS and LP modes, corresponding to any of the three LP mapping codes. These codewords are used to transmit control information required for interaction between the transmitting end (TX) and the receiving end (RX). For example, during the switch from LP mode to HS mode, the Primary sends a line state sequence (LP-111, LP-001, LP-000). Due to the slower transmission speed in LP mode, if the number of LP mapping codes obtained for LP-111 and LP-001 in this sequence is not an integer multiple of 7 (related to the duration of the line state), the number can be increased to an integer multiple of 7 by supplementing with identical LP mapping codes. However, for the last LP-000 in this sequence, HS mode Symbols begin to appear immediately after it ends. If the number of LP mapping codes corresponding to LP-000 is not an integer multiple of 7, there is not enough time to increase the number to an integer multiple of 7 by supplementing with identical LP mapping codes. In this case, the demapping unit 150 outputs a 17-bit user synchronization code to replace LP-000.

[0106] Optionally, it is not necessary to use a user synchronization code to replace LP-000. In the example described above, since the pattern detection unit needs time to identify the Preamble, some Symbols at the beginning of the Preamble are ignored, and the high-speed processing unit 130 provides a buffer to hold several Symbols, which also provides time margin for supplementing the number of LP mapping codes corresponding to LP-000 to a multiple of 7. Subsequently, after issuing a multiple of 7 LP mapping codes corresponding to LP-000, the high-speed processing unit 130 retrieves and forwards the Preamble Symbols from the buffer.

[0107] Parallel-to-serial conversion unit 160 converts the 17-bit binary data from demapping unit 150 into parallel-to-serial data and transmits it as a serial binary sequence on the transmission medium to the receiving end (RX) of active transmission device 300.

[0108] The binary sequence output by the parallel-to-serial conversion unit 160 can be transmitted via a single optical fiber or two differential copper wires. Compared to transmission via three copper wires, this reduces cable diameter and timing offset requirements, provides excellent anti-interference capabilities, and avoids the C-PHY protocol's limitation of less than 160ps for three-wire offset. This enables long-distance transmission of C-PHY signals and significantly reduces cabling costs. It is particularly suitable for intelligent driving vehicle systems with multiple displays or video captures, or scenarios requiring long-distance C-PHY signal transmission.

[0109] Additionally, it should be noted that, according to the C-PHY protocol, the events that may occur from the “stop” state include: High-Speed ​​data transmission requests (LP-111, LP-001, LP-000), Escape Mode requests (LP-111, LP-100, LP-000, LP-001, LP-000), or Turnaround requests (LP-111, LP-100, LP-000, LP-100, LP-000). In a typical application scenario of this solution, where data is transmitted from the C-PHY Primary to the C-PHY Secondary, the only possible event starting from the "stop" state is high-speed data transmission. This means that the line status in LP mode will only appear as (LP-111, LP-001, LP-000), and not LP_100. Therefore, EN1=2'b00, EN1=2'b01, and EN1=2'b11 represent LP_000, LP_001, and LP111 respectively, while EN1=2'b10 represents the current HS signal. Thus, the EN1 signal only requires 2 bits and is easy for the decoding unit 120 to generate the LP mapping code. Alternatively, the control signal EN1 representing the line status (LP_100) can be set to EN1=2'b10. Optionally, the EN1 signal can also be expressed using 3 bits or more. In this case, all possible values ​​of the 7 consecutive Symbols to be transmitted in HS and LP modes and the LP mapping code are "5". 7 The set of 17-bit binary numbers with values ​​of "+3+4" (a total of 2... 17 =131072 (possibly) satisfies the requirement of mapping all HS and LP mode line states output by the master device to binary numbers.

[0110] As another example, after the decoding unit 120 is determined to be in HS mode, it decodes the Symbol based on the changes in line states between adjacent unit intervals (UI). Each Symbol is a 3-bit binary number consisting of three binary flags: Flip, Rotation, and Polarity. When a change in polarity (+, -) is detected between adjacent line states (+x, -x, +y, -y, +z, -z), Flip is set, and Rotation and Polarity are ignored. When a clockwise rotation of adjacent line states is detected, Rotation is set; when a counter-clockwise rotation of adjacent line states is detected, Rotation is cleared. Where x... y z The switching direction of x is defined as clockwise, and z y x The switching direction of z is defined as counterclockwise. Polarity is set when a change in both polarity (+, -) and character identifier (e.g., x becomes y, y becomes z, z becomes x, etc.) is detected in the state of an adjacent line.

[0111] In an optional implementation, the transmitting end TX may not include the serial-to-parallel conversion unit 140 and the de-mapping unit 150. Accordingly, the 3-bit Symbol or LP mapping code output by the high-speed processing unit 130 is directly provided to the parallel-to-serial conversion unit 160. The parallel-to-serial conversion unit 160 converts the 3-bit Symbol or LP mapping code into a binary sequence and sends it to the receiving end RX through the transmission medium.

[0112] Example 3 Furthermore, such as Figure 5 As shown, the corresponding Figure 4 The flowchart of the data transmission method of the transmitting end TX in the embodiment provides an encoding method for transmitting C-PHY signals. Figure 5The process is as follows: The mode detection unit 110 identifies whether the C-PHY channel is in HS mode or LP mode based on the received wire state. If it is in HS mode, the decoding unit 120 decodes adjacent wire states into 3-bit symbols. Then, the high-speed processing unit 130 supplements the number of symbols in the HS mode preamble to an integer multiple of 7, and transmits the subsequently received symbols sequentially. Next, the serial-to-parallel conversion unit 140 converts every 7 consecutive symbols into 21-bit data. Then, the inverse mapping unit 150 inverse maps the 21-bit data to obtain 17-bit data. Finally, the parallel-to-serial conversion unit 160 performs parallel-to-serial conversion on the 17-bit data to obtain a binary sequence. If it is in LP mode, the decoding unit 120 decodes the received wire state into a 3-bit LP mapping code. The high-speed processing unit 130 forwards the LP mapping code. Then, the serial-to-parallel conversion unit 140 converts every 7 consecutive LP mapping codes into 21-bit data. Then, the demapping unit 150 demaps the 21-bit data to obtain 17-bit data. The mode detection unit 110 determines that the C-PHY channel has switched from LP mode to HS mode, and the demapping unit 150 generates 17-bit data representing the user synchronization code. The parallel-to-serial conversion unit 160 then performs parallel-to-serial conversion on the 17-bit binary data to obtain a binary sequence.

[0113] Example 4 like Figure 6 As shown, corresponding to the aforementioned transmitter TX, this application proposes a schematic diagram of a receiver RX. The receiver RX includes a clock data recovery unit 210, a mapping unit 220, a parallel-to-serial conversion unit 230, an encoding unit 240, and a synchronization code detection unit 250.

[0114] In this invention, the transmitting end TX obtains binary data from the C-PHY signal according to the encoding process and outputs it to the receiving end RX. The receiving end then converts this binary data into line status according to the decoding process and outputs it to the Secondary end. The decoding process corresponds to the encoding process; the decoding process is the inverse transformation of the encoding process, and the same terms have the same definitions and interpretations.

[0115] The input of the Clock and Data Recovery (CDR) unit 210 is connected to the transmitter (TX) via optical fiber or differential copper wire. It is used to recover the clock signal from the received binary sequence, and to shape and output the received binary sequence based on the recovered clock signal. The Clock and Data Recovery unit 210 shapes the received binary sequence based on the recovered clock signal, thus removing jitter during transmission and ensuring the correct recovery of the binary sequence.

[0116] The input of the synchronization code detection unit 250 is connected to the clock data recovery unit 210. It detects the user synchronization code (User Sync Word) in the binary data output by the clock data recovery unit 210. Upon detecting the user synchronization code, it generates an indication signal HS / LP flag to determine whether the current mode is HS mode or LP mode. The user synchronization code confirms whether the received binary data is encoded using HS mode Symbols or LP mapping codes. Specifically, if the first user synchronization code is detected and an HS flag is generated, it indicates that subsequent data is HS mode Symbol encoded data; that is, the mode after the first user synchronization code is HS mode. If the second user synchronization code is detected and an LP flag is generated, it indicates a switch from HS mode to LP mode; that is, the mode starting from the second user synchronization code is LP mode.

[0117] In another embodiment, when the user synchronization code has only a single value to indicate a mode switch in the C-PHY channel, the synchronization code detection unit 250 determines whether the current mode is HS mode or LP mode based on the number of times the user synchronization code is detected. According to the C-PHY protocol, HS mode transmission and LP mode transmission alternate. Through the LP-HS mode switching and the start and end of data transmission, for this embodiment, the binary sequence received by the clock data recovery unit 210 is a sequence that starts with LP mode and alternates between HS mode and LP mode. When the synchronization code detection unit 250 detects the user synchronization code for the first time, it indicates that the subsequent data is HS mode Symbol encoded data; when the synchronization code detection unit 250 detects the user synchronization code for the second time, it indicates that the subsequent data is LP mode. And so on. When the synchronization code detection unit 250 detects the user synchronization code an odd number of times and generates an HS flag, it indicates that the subsequent data is HS mode Symbol encoded data; when the synchronization code detection unit 250 detects the user synchronization code an even number of times and generates an LP flag, it indicates that the subsequent data is LP mode LP mapping code encoded data.

[0118] The input of the mapping unit 220 is connected to the clock data recovery unit 210, and the output is connected to the encoding unit 240. The binary data output from the clock data recovery unit 210 is mapped into 21-bit data according to a predetermined mapping rule.

[0119] The predetermined mapping rule is a mapping from 17-bit data to 21-bit data, which corresponds to the 21-17 bit mapping relationship in the inverse mapping unit 150 of the aforementioned transmitter TX. The binary data output by the clock data recovery unit 210 is grouped into 17-bit groups, and the mapping unit 220 maps each group of 17-bit data to 21 bits. In HS mode, 17-bit data is mapped to 7 symbols of 21 bits through the 17-21 bit mapping relationship; in LP mode, 17-bit data is mapped to 7 LP mapping codes of 21 bits through the 17-21 bit mapping relationship.

[0120] In one embodiment of the transmitter (TX), the demapping unit 150 of the transmitter (TX) directly inserts the user synchronization code into the data, and the mapping unit 220 of the receiver (RX) does not process the user synchronization code.

[0121] In another embodiment of the transmitting end (TX), the demapping unit 150 of the transmitting end (TX) replaces the LP mapping code with 17 bits of binary data, and the mapping unit 220 of the receiving end (RX) maps the user synchronization code to the corresponding LP mapping code.

[0122] Optionally, the mapping unit 220 can also be indirectly connected to the clock data recovery unit 210 through the synchronization code detection module unit 250. The synchronization code detection unit 250 outputs the binary data output by the clock data recovery unit and generates an indicator symbol HS / LP flag based on the user synchronization code in the received binary data. The mapping unit 220 receives the binary data output by the synchronization code detection unit 250 and maps it to 21-bit data according to a predetermined mapping rule; it outputs the indicator symbol HS / LP flag to ensure that the encoding unit 240 can correctly encode the received 3-bit data.

[0123] The input of the parallel-to-serial conversion unit 230 is connected to the mapping unit 220, and the output is connected to the encoding unit 240, converting the received 21-bit number into seven 3-bit data.

[0124] The output of encoding unit 240 is connected to the A / B / C lines of the slave device. Based on the HS / LP flag, it encodes the 3-bit data output from parallel-to-serial conversion unit 230 into a corresponding wire state value. This wire state value drives the A, B, and C lines of the C-PHY to the corresponding wire states. Encoding unit 240 determines whether the C-PHY channel corresponding to the received 3-bit data is in HS or LP mode based on the HS / LP flag. If the C-PHY transmission channel is in HS mode, the currently received 3-bit data is a Symbol, and encoding unit 240 encodes the received 3-bit Symbol into the HS mode wire state according to the C-PHY protocol. If the C-PHY transmission channel is in LP mode, the currently received 3-bit data is an LP mapping code, and encoding unit 240 encodes the received 3-bit LP mapping code into the corresponding LP wire state value according to the reverse process of decoding unit 120.

[0125] In one embodiment, the input of the encoding unit 240 is connected to the output of the indication signal HS / LP flag of the synchronization code detection unit 250, so that the encoding unit 240 can directly obtain the indication signal HS / LP flag output by the synchronization code detection unit 250. Of course, the encoding unit 240 can also obtain the indication signal HS / LP flag in other ways.

[0126] In one embodiment, the output of the encoding unit 240 is also connected to a driving unit, and the output of the driving unit is connected to the three wires A, B, and C of the slave device. The driving unit drives the voltage of the three wires (A, B, C) connected to the slave device to be the level value corresponding to the wire state value output by the encoding unit 240.

[0127] In one embodiment, when the TX terminal does not include the serial-to-parallel conversion unit 140 and the de-mapping unit 150, the binary data output by the clock data recovery unit 210 is converted from serial to parallel to obtain 3 bits of parallel data. In HS mode, one 3-bit data is a Symbol; in LP mode, one 3-bit data is an LP mapping code. In this case, there is no need for mapping from 17 bits of data to 21 bits of data, so the RX may not include the mapping unit 220 and the parallel-to-serial conversion unit 230. The encoding unit 240 directly encodes the 3 bits of parallel data into a wire state value, and drives the A, B, and C lines of the C-PHY to be in the wire state corresponding to the wire state value according to the wire state value.

[0128] Example 5 like Figure 7As shown, the corresponding Figure 6 The flowchart of a data receiving method of the receiving end RX in the embodiment is provided, that is, a decoding method for transmitting C-PHY signals. Figure 7 The process is as follows: Clock data recovery unit 210 recovers the clock signal from the received binary sequence, and shapes and outputs the received binary sequence according to the recovered clock signal. Synchronization code detection unit 250 generates an indication signal HS / LP flag based on the user synchronization code in the received binary sequence. Mapping unit 220 maps the received 17-bit data to 21-bit data. Parallel-to-serial conversion unit 230 performs parallel-to-serial conversion on the received 21-bit data to generate seven 3-bit data segments. Encoding unit 240 restores the corresponding line state from the received 3-bit data based on the indication signal HS / LP flag generated by synchronization code detection unit 250.

[0129] Example 6 like Figure 8 As shown in the diagram, this application proposes another structural schematic diagram of a transmitter (TX). It includes a mode detection unit 110, a decoding unit 120, a high-speed processing unit 130, an alignment unit 170, a serial-to-parallel conversion unit 140, an inverse mapping unit 150, and a parallel-to-serial conversion unit 160.

[0130] The specific functions and roles of the pattern detection unit 110 and the decoding unit 120 are the same as those in Embodiment 2, and will not be repeated here.

[0131] The input terminals of the alignment unit 170 are connected to the outputs of the indicator signals HS / LP flag of the high-speed processing unit 130 and the mode detection unit 110, respectively, and the output terminal of the alignment unit 170 is connected to the serial-to-parallel conversion unit 140. The alignment unit 170 aligns the LP mapping codes of the LP mode in groups of seven, ensuring that the serial-to-parallel conversion unit 140 connected to it outputs completely correct parallel data, thereby achieving correct encoding of the C-PHY signal. It should be noted that for the line state of the LP mode... Figure 2 t in 3-PREPARE This refers to the time that the Primary must maintain the LP-000 driving state before HS transmission. According to the protocol, its value ranges from 38ns to 95ns. In other words, adding a certain length of LP-000 at the transmitting end will not affect the decoding of the signal at the receiving end.

[0132] In one embodiment, in response to receiving the indication signal LP flag (indicating the LP mode), the alignment unit 170 determines whether the number of received LP mapping codes is an integer multiple of 7. If it is exactly an integer multiple of 7, the LP mapping codes in groups of 7 are directly and accurately aligned. If it is not an integer multiple of 7, identical LP mapping codes need to be added to make the number an integer multiple of 7, and then the LP mapping codes are accurately aligned in groups of 7. It is understood that the C-PHY protocol does not strictly require the transmission of LP modes in groups of 7 (3 bits each). This embodiment of the application only transmits LP mapping codes in groups of 7 to facilitate the 21-to-17 bit mapping by the demapping unit 150. It should be noted that if the data of the HS that satisfies the protocol is an integer multiple of 7, further alignment is not required.

[0133] In one embodiment, after the alignment unit 170 receives the LP flag, it counts the received LP mapping codes until the alignment unit 150 receives the HS flag (an indicator signal representing the HS mode). Then, it determines whether the currently received LP mapping code is a multiple of 7. If the received LP mapping code is a multiple of 7, the alignment unit 170 directly aligns the received LP mapping codes in groups of 7. If the received LP mapping code is not a multiple of 7, the alignment unit 170 aligns the received LP mapping codes in groups of 7. When performing the alignment operation on the last group of LP mapping codes, it adds LP mapping code "000" until the number of LP mapping codes in the current group is 7. It should be noted that the timing of the line status received by the transmitting end is as follows: Figure 2 In the timing flowchart of the HS mode line state burst transmission shown, from left to right, that is, the decoding unit 120 receives LP-111, LP-001, LP-000, Preamble, Sync Word, packet data, and post in sequence. Therefore, before receiving the HS flag, the alignment unit 170 receives the LP mapping code "000" of the line state LP-000. The alignment unit 170 adds "000" to make the LP mapping code an integer multiple of 7.

[0134] In another embodiment, between receiving the LP flag and receiving the HS flag, the alignment unit 170 counts the received LP mapping codes. If the alignment unit 170 does not receive the HS flag, it can be assumed that the master device is not transmitting data. In this case, if the received LP mapping code is a multiple of 7, the alignment unit 170 directly aligns the received LP mapping codes in groups of 7. When the HS flag is received, if the received LP mapping code is not a multiple of 7, the LP mapping code "000" is added until the LP mapping code is a multiple of 7.

[0135] In another embodiment, the high-speed processing unit 130 also sends an enable signal EN2 to the alignment unit 170 after padding the number of Symbols in the Preamble to an integer multiple of 7. In response to receiving the enable signal EN2, the alignment unit 170 aligns the received Symbols in groups of 7. The alignment unit 170 can accurately define the boundaries of the Symbols, ensuring that the subsequent serial-to-parallel conversion unit 140 can correctly recover the parallel data, thus improving the stability of signal transmission.

[0136] The serial-to-parallel conversion unit 140 is configured to convert the seven 3-bit Symbol or LP mapping codes output by the alignment unit 170 into 21-bit parallel signals.

[0137] The demapping unit 150 is used to demapping the received 21-bit parallel signal into 17-bit binary data according to a predetermined mapping rule. Similar to Embodiment 2, the 21-bit data representing 7 Symbols or 7 LP mapping codes is mapped into 17-bit data through the 21-17 bit demapping relationship.

[0138] The alignment operation of the alignment unit 170 ensures that the number of LP mapping codes is a multiple of 7 during the inverse mapping, so the inverse mapping unit 150 does not need to supplement the LP mapping codes.

[0139] In Embodiment 2, an additional user synchronization code is inserted, increasing the binary sequence transmitted between the transmitter (TX) and receiver (RX). In another embodiment, the user synchronization code is used to replace part of the binary numbers representing LP-000 and LP-111. In this embodiment, the binary sequence generated by inverse mapping is generated by replacing part of the LP mapping code with the user synchronization code. The input of the inverse mapping unit 150 is connected to the indication signal HS / LP flag output by the mode detection module 110. When inverse mapping the Symbol of the HS mode, in response to receiving the LP flag, the inverse mapping unit 150 inverse maps the first 21-bit number to 17-bit binary data representing the line state LP-111, and then replaces this 17-bit binary data with the second user synchronization code. Subsequently, the inverse mapping unit 150 continues to inverse map the remaining LP mapping codes until the HS flag is received. In response to receiving the HS flag, the inverse mapping unit 150 replaces the last 17-bit binary data representing the line state LP-000 with the first user synchronization code. It should be noted that since LP-000 and LP-111 generally last for a long time, replacing part of LP-000 or LP-111 with the user synchronization code will not affect signal transmission.

[0140] The binary sequence generated by inverse mapping using user synchronization codes to replace part of the LP mapping codes is as follows: Figure 9 As shown. The sequence is as follows: binary sequence representing line status LP-111, binary sequence representing line status LP-001, binary sequence representing line status LP-000, first user synchronization code (corresponding to the HS mode of the C-Phy transmission channel), second user synchronization code (representing the LP-111 binary sequence), and so on, in a loop. The demapping unit 150 first receives the LP mapping code and sequentially demaps the received 21-bit LP mapping code into a 17-bit binary sequence. In response to receiving the HS flag, the demapping unit 150 demaps the last 21-bit LP mapping code before the HS flag into a user synchronization code. Subsequently, the demapping unit 150 receives data as Symbols and maps the seven received Symbols sequentially into 17-bit binary data. In response to receiving the LP flag, the demapping unit 150 demaps the subsequently received first 21-bit LP mapping code into 17-bit binary data. This demapping process is repeated until the received 21-bit data is demapped into a binary sequence. By replacing the 17-bit binary sequence corresponding to line state LP-000 with a first user synchronization code and replacing the 17-bit binary sequence corresponding to line state LP-111 with a second user synchronization code, the total length of the binary data output by the transmitter is not increased compared to inserting user synchronization codes. This maintains the same transmission efficiency, avoids bandwidth occupation and timing adjustments caused by inserting user synchronization codes, and simplifies processing at the receiver. It should be noted that the output of the demapping unit 150 has a delay of 1-2 clock cycles relative to its input data. That is, when the demapping unit 150 receives the HS flag, the LP mapping code corresponding to line state LP-000 has not yet been completely demapped into a binary sequence. Through the delay between the input and output of the demapping unit 150, the subsequently received 21-bit LP mapping code can be demapped into a 17-bit binary sequence. This can be understood as... Figure 9 The first user synchronization code and the second user synchronization code can be user synchronization codes with different values, or they can be user synchronization codes with the same value.

[0141] The specific functions and roles of the parallel-to-serial conversion unit 160 are the same as those in Embodiment 2. Please refer to the corresponding description in Embodiment 2 for details, which will not be repeated here.

[0142] Furthermore, to more clearly illustrate the encoding process of the transmitting end TX in the embodiment, an encoding flow including HS mode and LP mode is provided. The specific flow is as follows: First, the mode detection unit 110 identifies whether the C-PHY channel is in HS mode or LP mode; if it is in HS mode, the decoding unit 120 decodes adjacent wire states into 3-bit symbols, then the high-speed processing unit 130 supplements the symbols of the HS mode preamble to an integer multiple of 7, then the alignment unit 170 accurately aligns every group of 7 symbols, then the serial-to-parallel conversion unit 140 converts every group of 7 symbols into 21-bit data, then the inverse mapping unit 150 inverse maps the 21-bit data to obtain 17-bit data, and finally the parallel-to-serial conversion unit 160 performs parallel-to-serial conversion on the 17-bit data to obtain a binary sequence; if it is in LP mode, the decoding unit 120 decodes the wire state into a 3-bit LP mapping code, then the high-speed processing unit 130 forwards the LP mapping code, then the alignment unit 170 determines the LP flag to HS. The number of LP mapping codes between flags is ensured to be a multiple of 7, and then every 7 consecutive LP mapping codes are accurately aligned. The serial-to-parallel conversion unit 140 converts every 7 consecutive LP mapping codes into 21-bit data. The inverse mapping unit 150 then inverse maps the 21-bit data to 17-bit data. Finally, the parallel-to-serial conversion unit 160 performs parallel-to-serial conversion on the 17-bit binary data to obtain a binary sequence. When switching from LP mode to HS mode, before performing parallel-to-serial conversion on the 17-bit data to obtain a binary sequence, the 21-bit LP mapping code representing LP-000 received when receiving the HS flag is replaced with a 17-bit first user synchronization code. When switching from HS mode to LP mode, the 21-bit LP mapping code representing LP-111 received when receiving the LP flag is replaced with a 17-bit second user synchronization code.

[0143] Example 7 like Figure 10 As shown, corresponding to the aforementioned transmitter TX, this application proposes another structural diagram of the receiver RX. It includes a clock data recovery unit 210, a synchronization code detection unit 250, a serial-to-parallel conversion unit 260, a mapping unit 220, a parallel-to-serial conversion unit 230, and an encoding unit 240.

[0144] The clock data recovery unit 210 has the same function and role as in Embodiment 4, which can be found in the relevant description in Embodiment 4 and will not be repeated here.

[0145] The input of the synchronization code detection unit 250 is connected to the clock data recovery unit 210, and the output is connected to the serial-to-parallel conversion unit 260. It detects the user synchronization code (User SyncWord) in the binary data output by the clock data recovery unit 210. Upon detection, it outputs an indication signal HS / LP flag and an enable signal EN3. The user synchronization code confirms that the received binary data is encoded using HS mode Symbol or LP mapping code. Specifically, if the first user synchronization code is detected, the synchronization code detection unit 250 outputs the HS flag, indicating that subsequent data is HS mode Symbol encoded data, thus requiring a switch from LP mode to HS mode; that is, the data after the first user synchronization code is in HS mode. If the second user synchronization code is detected, the synchronization code detection unit 250 outputs the LP flag, indicating a switch from HS mode to LP mode; that is, the data starting from the second user synchronization code is in LP mode.

[0146] The serial-to-parallel conversion unit 260 starts performing serial-to-parallel conversion after receiving the enable signal EN3. It converts the binary sequence of the recovered clock into 17-bit parallel data by serial-to-parallel conversion.

[0147] Mapping unit 220 maps 17-bit parallel data into 21-bit data according to a predetermined mapping rule. Specifically, in HS mode, the 17-bit data is mapped to 21 bits of 7 Symbols through a 17-21 bit mapping relationship; in LP mode, the 17-bit data is mapped to 21 bits of 7 LP mapping codes through a 17-21 bit mapping relationship.

[0148] The function and role of the encoding unit 240 are the same as those in Embodiment 4, and can be found in the relevant description in Embodiment 4, which will not be repeated here.

[0149] Example 8 like Figure 11 As shown in the diagram, this application proposes another structural schematic diagram of a transmitter (TX). It includes a mode detection unit 110, a decoding unit 120, a high-speed processing unit 130, an alignment unit 170, a serial-to-parallel conversion unit 140, an anti-mapping unit 150, a scrambling unit 180, and a parallel-to-serial conversion unit 160.

[0150] The specific functions and roles of the pattern detection unit 110, decoding unit 120, high-speed processing unit 130, alignment unit 170, serial-to-parallel conversion unit 140, and anti-mapping unit 150 are the same as those in Embodiments 2 and 6. Please refer to the corresponding descriptions above for details, which will not be repeated here.

[0151] A scrambling unit 180 is disposed between the demapping unit 150 and the parallel-to-serial conversion unit 160. The scrambling unit 180 is, for example, a frame synchronization scrambler, which randomizes the data sequence output by the demapping unit 150 using a feedback shift register sequence. By randomizing the output data, inter-symbol interference and jitter caused by consecutive 0s or 1s are avoided.

[0152] Parallel-to-serial conversion unit 160 converts the 17-bit binary data (data after sequence randomization) from scrambling unit 180 into parallel-to-serial data and transmits it to RX on the transmission medium as a serial binary sequence.

[0153] In another embodiment, a scrambling unit is added to the TX in embodiment 2. The scrambling unit is located between the inverse mapping unit 150 and the parallel-to-serial conversion unit 160, and its function is also to randomize the data sequence of the signal output by the inverse mapping unit 150.

[0154] Example 9 like Figure 12 As shown, corresponding to the aforementioned Figure 11 In addition to the transmitting end TX, this application proposes another schematic diagram of the receiving end RX. It includes a clock data recovery unit 210, a synchronization code detection unit 250, a serial-to-parallel conversion unit 260, a descrambling code unit 270, a mapping unit 220, and an encoding unit 240.

[0155] The specific functions and roles of the clock data recovery unit 210, synchronization code detection unit 250, serial-to-parallel conversion unit 260, mapping unit 220, and encoding unit 240 are the same as those in Embodiments 4 and 7. Please refer to the corresponding descriptions above for details, which will not be repeated here.

[0156] The descrambling unit 270 is located between the serial-to-parallel conversion unit 260 and the mapping unit 220 to recover the randomized data sequence. Because the data sequence is randomized by the scrambling unit 180 in the transmitting end TX, descrambling processing is required in the receiving end RX before the signal enters the mapping unit 220 to recover the correct data sequence and ensure data integrity.

[0157] In another embodiment, a descrambling unit is added to the RX in embodiment 4. The descrambling unit is set before the mapping unit 220. Its function is also to perform descrambling processing before the signal enters the mapping unit 220 to restore the correct data sequence, so as to ensure the correctness of the data.

[0158] Furthermore, based on the RX in Embodiments 1, 4, and 7, the receiving end RX may also include a driving unit. The driving unit is coupled to the encoding unit 240, and the driving unit drives the voltage of the three wires (A, B, C) connected to the secondary end to be the level value corresponding to the wire state output by the encoding unit 240.

[0159] Furthermore, such as Figure 3 The high-speed signal transmission medium located between TX and RX in the active transmission device 300 shown includes at least a single optical fiber or two differential copper wires.

[0160] In one embodiment, the high-speed signal transmission medium is optical fiber, and the active transmission device further includes at least two photoelectric conversion modules. One photoelectric conversion module is connected to the transmitting end and is used to convert the received binary sequence into an optical signal. The other photoelectric conversion module is connected to the receiving end and is used to convert the received optical signal into a binary sequence of electrical signals. The photoelectric conversion module transmits the optical signal through the optical fiber. The photoelectric conversion module includes, for example, a photoelectric conversion driver, a photoelectric converter, and an optical component. The photoelectric converter is connected to the photoelectric conversion driver and the transmitting end or the receiving end. Based on the drive signal of the photoelectric conversion driver, the binary number output by the transmitting end is converted into an optical signal, or based on the drive signal of the photoelectric converter driver, the received optical signal is converted into a binary number output. The optical component is used to couple the photoelectric converter to the optical fiber, coupling the received optical signal to the optical fiber or outputting it through the optical fiber.

[0161] In one embodiment, the high-speed signal transmission medium is copper wire, and the active transmission device further includes a signal conditioner. The signal conditioner is used to achieve long-distance transmission of electrical signals via the copper wire. The signal conditioner includes a signal repeater and a signal regenerator. The signal repeater is used to restore the original waveform characteristics of the high-speed digital signal through signal regeneration technology. The signal regenerator is used to compensate for signal loss through equalization and pre-emphasis. It is understood that there can be one or more signal conditioners. When there are multiple signal conditioners, they can be connected to the transmitting end and the receiving end respectively. When there is only one signal conditioner, it is connected to the transmitting end.

[0162] It should be noted that the above description pertains to the encoding and decoding of data from one channel (Lane) of a C-PHY. Those skilled in the art should understand that when a C-PHY uses multiple channels for transmission, it encodes and decodes the data from each channel (Lane), and the corresponding circuits for encoding the C-PHY signal and generating the C-PHY signal will also change accordingly. Optionally, two photoelectric conversion modules can be provided for one channel (Lane) of the C-PHY; if the C-PHY uses multiple channels (Lanes) for transmission, multiple sets of photoelectric conversion modules can be used.

[0163] In one embodiment, the active transmission device 300 is a cable, with TX located inside a first plug for connection to a primary device, and RX located inside a second plug for connection to a secondary device. A transmission medium, such as optical fiber or differential copper wire, is located between the first and second plugs.

[0164] In another embodiment, the TX is located within a first adapter for connecting to the primary device, and the RX is located within a second adapter for connecting to the secondary device. The first and second adapters are independent of each other. The first adapter has an output interface, and the second adapter has a receiving interface. A transmission cable connects the output and receiving interfaces, and the transmitting end (TX) and receiving end (RX) of the cable have photoelectric conversion modules or signal conditioners. The interface can be any of the following: Type-C, Type-A, HDMI, SFP / SFP optical module, QSFP, QSFP-DD, etc.

[0165] In another embodiment, see Figure 13 The TX and Primary (master) interfaces are located within the host device, while the RX and Secondary (slave) interfaces are located within the destination device. The host device provides one output interface, and the destination device has one receive interface. A cable connects the output and receive interfaces.

[0166] Furthermore, the embodiments of this application can also be combinations of the three schemes described above. For example, the TX is located inside the host, the host provides an output interface, and the RX is located inside the plug, which is used to connect to the destination device. The output interface and the plug are connected by a cable. Alternatively, the TX is located inside the host, the RX is located inside the destination device, and photoelectric conversion modules are provided inside both the host and the destination device. An optical fiber patch cord connects the output interface and the receiving interface. The TX, RX, and photoelectric conversion modules or signal conditioners can be combined according to application requirements to form different application forms, the details of which will not be elaborated further.

[0167] Furthermore, embodiments of this application also provide a method for storing a bit stream, which involves generating a bit stream by performing the encoding method for transmitting C-PHY signals or the decoding method for transmitting C-PHY signals as described in the foregoing embodiments; and storing the bit stream.

[0168] Furthermore, embodiments of this application also provide a method for transmitting a bit stream, which involves generating a bit stream by performing the encoding method for transmitting C-PHY signals or the decoding method for transmitting C-PHY signals as described in the foregoing embodiments; and transmitting the bit stream.

[0169] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0170] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0171] Several embodiments of this application have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of this application. The scope of protection of this application is defined by the appended claims.

Claims

1. An encoding method for transmitting C-PHY signals, characterized in that, The method includes: Identify the mode of the C-PHY transmission channel; Based on the mode of the C-PHY transmission channel, decode the line status of the A, B, and C lines of the C-PHY transmission channel into 3 bits of data; In response to the identification that the transmission channel of the C-PHY is in HS mode, the 3-bit data is output, and the length of the 3-bit data representing the preamble is adjusted so that the length of the output 3-bit data representing the preamble meets the requirements of the C-PHY protocol. The output 3-bit data is reverse-mapped into a binary sequence and output through a transmission medium.

2. The encoding method for transmitting C-PHY signals according to claim 1, characterized in that, The 3-bit data includes Symbol and LP mapping code. Symbol is a symbol defined by the C-PHY protocol. When the C-PHY transmission channel is in HS mode, the line status of the A, B, and C lines of the C-PHY transmission channel is decoded into Symbol. When the C-PHY transmission channel is in LP mode, the line status of the A, B, and C lines of the C-PHY transmission channel is decoded into LP mapping code.

3. The encoding method for transmitting C-PHY signals according to claim 2, characterized in that, The method includes: in response to the transmission channel of the C-PHY being in HS mode, buffering the Symbol representing the preamble; when the number of the Symbol representing the preamble decoded before the Symbol representing the synchronization word is not an integer multiple of 7, repeatedly adding the buffered Symbol representing the preamble before the Symbol representing the synchronization word, so that the length of the Symbol representing the preamble is an integer multiple of 7.

4. The encoding method for transmitting C-PHY signals according to claim 2, characterized in that, The method includes: in response to the transmission channel of the C-PHY being in HS mode, buffering the symbol representing the preamble before the symbol representing the synchronization word; outputting the buffered symbols representing the preamble sequentially in groups of 7; and when the number of buffered symbols representing the preamble is less than 7, repeatedly outputting the buffered symbols representing the preamble so that the number of symbols representing the preamble is 7.

5. The encoding method for transmitting C-PHY signals according to claim 2, characterized in that, The method includes: in response to the transmission channel of the C-PHY being in HS mode, buffering the symbols representing the preamble, and outputting the buffered symbols representing the preamble in groups of 7; when the number of buffered symbols representing the preamble is less than 7, repeatedly outputting the buffered symbols representing the preamble so that the number of symbols representing the preamble is 7.

6. The encoding method for transmitting C-PHY signals according to claim 1, characterized in that, The method further includes: in response to the C-PHY transmission channel being in LP mode, generating control signals and indication signals according to the line status of the A, B, and C lines of the C-PHY transmission channel, and generating LP mapping codes according to the control signals; wherein the indication signals are used to indicate the mode of the C-PHY transmission channel.

7. The encoding method for transmitting C-PHY signals according to any one of claims 2-6, characterized in that, The method includes: in response to the transmission channel of the C-PHY being in HS mode, mapping 7 consecutive Symbols into a 17-bit binary sequence; and in response to the transmission channel of the C-PHY being in LP mode, mapping the LP mapping code into a 17-bit binary sequence.

8. The encoding method for transmitting C-PHY signals according to claim 7, characterized in that, The method further includes: in response to the transmission channel of the C-PHY being in HS mode, performing serial-to-parallel conversion on every 7 consecutive Symbols to generate parallel 21-bit data, and then mapping the parallel 21-bit data back to a 17-bit binary sequence.

9. The encoding method for transmitting C-PHY signals according to claim 2, characterized in that, The method further includes: in response to the transmission channel of the C-PHY being in LP mode and the number of LP mapping codes not being an integer multiple of 7, adjusting the number of LP mapping codes so that the number of LP mapping codes is an integer multiple of 7.

10. The encoding method for transmitting C-PHY signals according to claim 2, characterized in that, The method further includes: in response to the transmission channel of the C-PHY being in LP mode and the number of LP mapping codes not being an integer multiple of 7, repeatedly outputting the LP mapping code corresponding to line state LP-000, so that the number of LP mapping codes is an integer multiple of 7.

11. The encoding method for transmitting C-PHY signals according to claim 9 or 10, characterized in that, The method further includes: aligning the output 3-bit data.

12. The encoding method for transmitting C-PHY signals according to claim 11, characterized in that, After aligning the output 3-bit data, the method further includes: converting 7 consecutive 3-bit data into parallel data to generate parallel 21-bit data, so as to inversely map the parallel 21-bit data into a 17-bit binary sequence.

13. The encoding method for transmitting C-PHY signals according to claim 1, characterized in that, The method further includes: in response to the C-PHY's transmission channel switching from LP mode to HS mode or from HS mode to LP mode, generating 17 bits of data representing the user synchronization code.

14. The encoding method for transmitting C-PHY signals according to claim 1, characterized in that, The method further includes: performing a parallel-to-serial conversion on the binary sequence to generate a serial binary sequence.

15. The encoding method for transmitting C-PHY signals according to claim 14, characterized in that, The method further includes scrambling the binary sequence before performing parallel-to-serial conversion on the binary sequence.

16. A decoding method for transmitting C-PHY signals, characterized in that, The method includes: 17-bit binary data is acquired and mapped to 21-bit data, which consists of seven 3-bit data. The 17-bit binary data is obtained by encoding the 3-bit data obtained from decoding the line status of the A, B, and C lines of the C-PHY transmission channel. During the encoding process, in response to the C-PHY transmission channel being in HS mode, the length of the 3-bit data representing the preamble obtained from decoding the line status of the A, B, and C lines of the C-PHY transmission channel is adjusted to meet the C-PHY protocol requirements. The seven consecutive 3-bit data obtained from decoding the line status of the A, B, and C lines of the C-PHY transmission channel are then inversely mapped to obtain the 17-bit binary data. In response to the C-PHY transmission channel being in LP mode, the 3-bit data representing the LP mapping code obtained from decoding the line status of the A, B, and C lines of the C-PHY transmission channel are inversely mapped to the 17-bit binary data. The 21-bit data is encoded into a line status value; Based on the line status value, the A, B, and C lines of the transmission channel driving the C-PHY are respectively at voltages corresponding to the line status value.

17. The decoding method for transmitting C-PHY signals according to claim 16, characterized in that, The method further includes: An indication signal is generated based on the user synchronization code in the binary sequence, the indication signal being used to indicate the mode of the transmission channel of the C-PHY; and the 21-bit data is encoded into a line status value based on the indication signal.

18. The decoding method for transmitting C-PHY signals according to claim 17, characterized in that, The user synchronization code includes a first user synchronization code and a second user synchronization code; in response to the user synchronization code being the first user synchronization code, an indication signal indicating that the C-PHY transmission channel is in HS mode is generated based on the first user synchronization code. In response to the user synchronization code being the second user synchronization code, an indication signal indicating that the C-PHY transmission channel is in LP mode is generated based on the second user synchronization code.

19. The decoding method for transmitting C-PHY signals according to claim 17, characterized in that, The method further includes: obtaining the number of times the user synchronization code is obtained, and generating an indication signal indicating that the C-PHY transmission channel is in HS mode or LP mode based on the number of times the user synchronization code is obtained.

20. The decoding method for transmitting C-PHY signals according to claim 18 or 19, characterized in that, In response to the indication signal indicating that the C-PHY transmission channel is in HS mode, the 3-bit data is a Symbol, which is encoded into a line status value for HS mode, where Symbol is a symbol defined by the C-PHY protocol; in response to the indication signal indicating that the C-PHY transmission channel is in LP mode, the 3-bit data is an LP mapping code, which is encoded into a line status value for LP mode for the C-PHY transmission channel.

21. The decoding method for transmitting C-PHY signals according to any one of claims 16-19, characterized in that, After mapping the 17-bit binary data to the 21-bit data, the method further includes: converting the 21-bit data in parallel and serial mode into multiple 3-bit data, and encoding the 3-bit data into corresponding line status values.

22. A method for storing a bit stream, characterized in that, The bit stream is generated by performing the encoding method for transmitting C-PHY signals according to any one of claims 1-15 or the decoding method for transmitting C-PHY signals according to any one of claims 16-21; and the bit stream is stored.

23. A method for transmitting a bit stream, characterized in that, A bit stream is generated by performing the encoding method for transmitting C-PHY signals according to any one of claims 1-15 or the decoding method for transmitting C-PHY signals according to any one of claims 16-21; And the transmission of the bit stream.

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