A high-speed parallel timing synchronization method based on low sampling rate reception

Abstract

The application discloses a high-speed parallel timing synchronization method based on low sampling rate receiving and belongs to the technical field of high-speed wireless communication. The application carries out OM timing deviation estimation on the recovered four times oversampling signal, generates a control quantity through a loop filter and an improved digital controlled oscillator, generates buffer output data sequences through control of buffer data reading indexes, simultaneously dynamically adjusts the number of buffer data outputs, presets the total coefficient of a matched filter in a plurality of read-only memories according to a multi-memory interlaced storage rule based on module mapping, calculates the storage address of all required filter coefficients according to the timing deviation estimation value and realizes parallel reading, uses the matched filter with the efficient polyphase structure to filter the buffer output data sequences, generates a timing synchronization output signal, generates an additional timing synchronization output signal at a specific compensation moment according to a parallel number control signal, controls the parallel number of the timing synchronization output at the moment and carries out additional output.

Description

Technical Field

[0001] This invention relates to a timing error detection and compensation method in digital communication systems, and more particularly to a timing synchronization method for high-speed digital communication, belonging to the field of high-speed wireless communication technology. Background Technology

[0002] Because the transmitter clock and the receiver sampling clock originate from different sources, communication system reception is often affected by timing errors such as frequency and phase deviations. Timing errors have multiple impacts on the received signal. On the one hand, they cause sampling points to deviate from the optimal sampling time, resulting in signal distortion and a deterioration in the signal-to-noise ratio. On the other hand, they disrupt the overall sampling matching relationship of the system, thereby introducing inter-symbol interference and reducing reception performance. Therefore, timing synchronization is an indispensable and important component of digital communication receivers. With the development of high-speed digital communication, traditional serial timing synchronization methods are gradually being limited by hardware processing speed constraints. To achieve high-speed transmission, parallel timing synchronization methods can be adopted in high-speed digital communication systems.

[0003] Existing timing synchronization methods typically include external synchronization and self-synchronization. External synchronization involves the transmitter pre-inserting auxiliary information such as pilot signals, training sequences, or pseudocodes, which the receiver then uses to recover the timing deviation. This method is relatively straightforward but consumes additional transmission resources and reduces effective spectrum utilization. Self-synchronization, on the other hand, directly utilizes the statistical characteristics or structural features of the received signal itself to estimate and compensate for timing errors without requiring additional auxiliary information, making it more suitable for high-speed digital communication systems.

[0004] Among existing self-synchronization methods, common schemes include feedback timing synchronization algorithms and feedforward timing synchronization algorithms. Classic feedback timing synchronization algorithms include the Gardner algorithm and the Mueller and Muller (M&M) algorithm, which can achieve good symbol timing tracking under certain conditions. However, they generally suffer from limited convergence speed and high real-time processing pressure in high-speed scenarios, thus limiting their application in high-speed digital communication systems. Feedforward timing synchronization algorithms, represented by the OM timing synchronization algorithm, do not rely on closed-loop gradual convergence but directly estimate timing error information from the received signal and perform timing compensation, making them more suitable for high-speed digital communication reception scenarios.

[0005] However, traditional OM timing synchronization methods still have several shortcomings in application. The algorithm requires the receiver to receive signals at four times the oversampling rate, but practical factors such as the sampling rate of the analog-to-digital converter and insufficient system resources limit the further improvement of the receiver's communication rate. Generally, receiver timing recovery usually adopts a complex filtering or interpolation structure, which has a large amount of computation and high hardware resource consumption, making it unfavorable for high-throughput and low-overhead engineering deployment on platforms such as FPGAs. The compensation algorithm usually only relies on the sliding of the index to adjust the data processing window. When the receiver clock is slower than the transmitter clock, the receiver often needs to continuously buffer the input signal to maintain window alignment. When this state lasts for a long time, it is easy to cause the buffer demand to increase continuously, or even cause buffer overflow problems, thus affecting the system stability and real-time performance.

[0006] Therefore, while ensuring timing synchronization performance, the receiver reduces the oversampling rate and uses a parallel multiphase filter to efficiently complete timing error compensation and four-fold oversampled signal recovery. At the same time, it dynamically adjusts the number of parallel paths of the timing synchronization output signal to avoid long-term buffer backlog at the receiver. This overcomes hardware constraints, saves resources, and improves system stability and real-time performance, making it an effective method for achieving timing synchronization in high-speed digital communication. Summary of the Invention

[0007] To address the signal-to-noise ratio (SNR) degradation caused by the misalignment of the transmitting symbol clock and the receiving sampling clock in existing communication technologies, which leads to deviations from the optimal sampling time, this invention provides a high-speed parallel timing synchronization method based on low-sampling-rate reception. This method involves estimating the OM timing deviation from the recovered four-times oversampled signal and generating a control quantity using a loop filter and an improved numerically controlled oscillator. Furthermore, it generates the buffer output data sequence by controlling the low-sampling-rate data read index of the buffer, while dynamically adjusting the number of buffer data outputs to avoid buffer backlog, thus completing integer timing deviation correction. Finally, the total coefficients of the matched filter are pre-placed in multiple read-only memories (ROMs) according to a multi-memory interleaving rule based on modulus mapping. The system uses a memory (ROM) to calculate the initial address of the corresponding filter coefficients based on the timing deviation estimate from the improved numerically controlled oscillator output. It then obtains all required addresses and reads the coefficients required by the matched filter at that moment. A high-efficiency multiphase structure for the matched filter is constructed using polyphase decomposition technology. The data output from the buffer is then processed by a parallel multiphase filter to generate a timing synchronization output signal, completing the recovery of the four-fold oversampled signal and fractional timing deviation correction. Furthermore, in specific compensation scenarios, an additional timing synchronization output signal is generated using a single-point filtering calculation method based on the parallel path control signal. This invention effectively solves the problem of excessively high sampling rate requirements at the receiving end in traditional OM timing synchronization methods while ensuring timing synchronization performance. It reduces system computational complexity, saves hardware resources, and avoids the buffer backlog problem caused by continuous buffering of input data when the receiver clock is slower than the transmitter clock, thus improving system stability.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] This invention discloses a high-speed parallel timing synchronization method based on low sampling rate reception, comprising the following steps:

[0010] Step 1, record For the first At any given time, the ADC sampled at the receiving end will be... The signal is fed into a buffer, which is buffered according to the control signal output by the improved numerically controlled oscillator mNCO. The output buffer outputs a data sequence and synchronously transmits the parallel path control signal of the mNCO output. To the subsequent steps. The control signal output by the mNCO... Signals buffered from the buffer Generate buffer output data sequence The method is,

[0011] Set index ,in For the number of symbols in the matched filter, when At that time, with Output data sequence as a buffer;

[0012] when When, it indicates that a sample input point needs to be skipped at the current moment, let and output If at this time Then control the timing synchronization of the whole system. Pause calculation and output once at a time, and in Time makes And restore calculation and output;

[0013] when When, it means that at the current moment, one input sampling point needs to be retained, that is, one output sampling point needs to be added. At this time, it is... Output the data sequence as a buffer.

[0014] Step 2: Pre-place the total coefficients of the matched filter in multiple read-only memories according to the multi-memory interleaving rule based on mode mapping; according to Timing phase error of mNCO output Calculate the corresponding filter coefficient addresses; based on the filter coefficient addresses, read the required filter coefficients in parallel from multiple read-only memories and reassemble them in tap order to form a filter coefficient sequence. The specific implementation method is as follows:

[0015] Step 2.1, based on the number of symbols in the matched filter And record the number of sampling points for each symbol as The oversampling amplification factor is Generate the total storage sequence of the matched filter. :

[0016]

[0017] in The total storage sequence is uniformly addressed according to address order, and the coefficient address is denoted as... :

[0018]

[0019] Will Mapped to the The first memory cell Line address:

[0020]

[0021]

[0022] in For rounding down, This represents the number of memory units.

[0023] Accordingly, the total storage sequence is interleaved and pre-set according to the mapping relationship. In the ROM, the first All storage coefficients in each ROM satisfy:

[0024] .

[0026] Step 2.2, according to The signal undergoes mode compensation for timing phase error to obtain the corrected timing phase error. :

[0027]

[0028] in The number of channels for the timed synchronous output of the 4x oversampled signal;

[0029] Define the oversampling rate of the signal by the receiver as: , for The simplest fractional form of , and denoted as This is the interpolation multiple. To determine the next draw multiplier, expand Multiply by 1, and round to the nearest integer. Using the base address, we obtain the initial address for reading the coefficients. :

[0030]

[0031] in Rounding is performed for the nearest integer.

[0032] Step 2.3, using the initial address of the read coefficient. Based on, and with a preset step offset Form the set of target addresses to be read at the current moment. :

[0033]

[0034] Address Mapped to the The first memory cell Line address, where:

[0035]

[0036]

[0037] Based on this, extract all the filter coefficients needed at this moment; when the step parameters... With the number of storage units When the coprime relationship is satisfied, the target addresses corresponding to consecutive taps are in the modulo... In this sense, a set of distinct remainders are formed, so that each target address at the same time can be allocated to different memory banks;

[0038] After reading, the filter coefficients output from multiple read-only memories are reassembled according to the tap order based on the memory bank number corresponding to each tap, forming a filter coefficient sequence. :

[0039]

[0040] in The process of generating the starting address and forming the target address set is used to map the timing phase error on the low sampling rate side to the spatial address offset of the coefficients of the high oversampling matched filter, thereby realizing the dynamic reading of the filter coefficients under cross sampling rate conditions.

[0041] Step 3: Output the buffer data sequence obtained in Step 1 and the data obtained in Step 2. The input is convolved in a parallel multi-matched filter to obtain... Point output sequence The specific implementation method is as follows:

[0042] Step 3.1, when When the length does not meet the requirements of the polyphase decomposition structure of the subsequent filter, for Zero-padding is performed to obtain the extended coefficient sequence. :

[0043]

[0044] in The required length for the decomposed structure.

[0045] Step 3.2, will according to Set the first-level decomposition path and perform first-level decomposition to obtain... A sequence of first-level sub-filter coefficients :

[0046]

[0047] in This indicates the branch index of the first-level sub-filter. Indicates the tap index of the first-level sub-filter; for each first-level sub-filter Press again Set the number of two-level decomposition paths and perform two-level decomposition. Each path yields... A sequence of coefficients for a second-level sub-filter :

[0048]

[0049] in Indicates the branch index of the second-level sub-filter. This represents the tap index of the second-level sub-filter; it can be implemented by splitting according to the structure described above. Efficient implementation of fractional-times-multiple-signal sampling rate recovery.

[0050] Step 3.3, retrieve the first part of the output data sequence from the buffer. The data is :

[0051]

[0052] Regarding the first The first-level sub-filter branch applies a time delay processing corresponding to that first-level branch to the input data sequence, resulting in the first-level branch input sequence. :

[0053]

[0054] in For the first The time delay corresponding to the first-level sub-filter branch of each path; for each signal sequence Apply the delay processing corresponding to this second-level branch again to obtain :

[0055]

[0056] in For the first The time delay corresponds to the branch of the second-level sub-filter; then the time-delayed sequence is processed according to... Extraction is performed to obtain the input signal sequence of the second-level branch. :

[0057] .

[0059] Step 3.4, With the corresponding Perform filtering calculations to obtain the signal output of the second-level sub-filter. :

[0060]

[0061] The summation output of the first-level branch is obtained by superimposing the outputs of all second-level sub-filters within the same first-level branch. and to conduct Double interpolation process to obtain ;right Apply the advance processing corresponding to this first-level branch to obtain the phase-aligned first-level branch output. :

[0062]

[0063] in For the first The lead compensation amount corresponds to the first-order sub-filter branch of the path; for Then, the layers are stacked again, and the latency is removed. The parallel filtering output sequence of the total filter at the current time can be obtained. :

[0064] .

[0066] Step 4: When the output of Step 1... When additional output points are required, the result obtained in step three... Based on this, calculate the additional filter output point and compare it with... Together Point-to-point parallel timing synchronous output sequence The specific calculation method is as follows:

[0067] Step 4.1: To reduce the additional multiplication and addition complexity in scenarios with additional outputs, operations can be performed only on sparse terms constrained by the index set; let the length of the filter coefficients be calculated for sparse single-point filtering. ; Define the length as coefficient index set Its settings are as follows:

[0068]

[0069] Based on this, the coefficient sequence of a sparse single-point filter can be constructed. :

[0070] .

[0072] Step 4.2, take the output data sequence from the buffer output in Step 1 for use. Use data to construct a single-point filter input sequence. :

[0073] .

[0075] Step 4.3: Obtain the additional filter output point through sparse convolution as shown in the following formula. :

[0076]

[0077] That is, the additional output points are composed of the partial convolution results of the original filter under the constraints of the index set.

[0078] Step 4.4, using Form additional output sequence , convert the sequence The sequence obtained in step three Combine, form Point-to-point parallel timing synchronous output sequence .

[0079] Step 5, when When the value is 0, the method output is... ;when When the value is 1, the method outputs .

[0080] Step Six: Based on the results obtained in Step Three Timing error estimation and loop filtering are performed to obtain the calculation results. The timing error estimation uses the OM estimation algorithm, which is calculated by performing OM estimation on the signal to be estimated to obtain the OM estimate value. :

[0081]

[0082] in The output signal sequence for step three. To estimate the signal length used each time, The length of the DFT transform;

[0083] Timing error estimate for:

[0084]

[0085] In the formula, The function is used to find the argument of a complex number, and its range of values ​​is: , and Used to represent The real and imaginary parts;

[0086] The loop filtering calculation method involves filtering and calculating using a filter transfer function. for:

[0087]

[0088] in and These are the loop filter coefficients; the specific values ​​are selected based on the actual engineering requirements.

[0089] Step 7: Take the results from Step 6 The calculation is performed in the input mNCO, accumulating the output value of the loop filter:

[0090]

[0091] Determined based on whether and in which direction there is overflow. , and :

[0092] .

[0094] Step 8: Convert the output of the loop filter... , and Return to steps one and two to process the input data in a loop until timed synchronization is complete.

[0095] Beneficial effects:

[0096] 1. The present invention discloses a high-speed parallel timing synchronization method based on low sampling rate reception. By constructing a timing synchronization processing flow including parallel input buffering, parallel reading of filter coefficients, parallel multi-match filtering, single-point calculation of additional output points, and timing error estimation, parallel timing synchronization processing in a high-speed digital communication receiver is realized, and timing error correction and synchronization output generation can be completed in the time domain.

[0097] 2. The present invention discloses a high-speed parallel timing synchronization method based on low sampling rate reception, which allows the receiver to sample the input signal at a low oversampling rate and recover the four-fold oversampling synchronization output through subsequent parallel multi-matching filtering. Therefore, it reduces the dependence of the receiver's analog-to-digital conversion and subsequent processing on high sampling rate, which helps to reduce the hardware implementation pressure, overcome the hardware constraints in high-speed reception scenarios, and improve the overall communication rate of the system.

[0098] 3. The present invention discloses a high-speed parallel timing synchronization method based on low sampling rate reception. It adopts a parallel multi-matched filter structure to decompose the filter in stages and dynamically reads the corresponding filter coefficients according to the timing phase error. It simultaneously realizes four times oversampled signal recovery and timing phase correction in the same filtering process, thereby avoiding the need to set up two separate processing structures for signal recovery and timing correction, improving filtering calculation efficiency, and reducing computational complexity and hardware resource consumption.

[0099] 4. The present invention discloses a high-speed parallel timing synchronization method based on low sampling rate reception. By dynamically adjusting the number of timing synchronization output channels, it avoids the problem of long-term input data backlog caused by insufficient output in the existing fixed-channel parallel timing synchronization method when the receiver clock is slower than the transmitter clock, thereby improving the real-time performance and stability of the system. Attached Figure Description

[0100] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0101] Figure 1 This is a flowchart of a high-speed parallel timing synchronization method based on low sampling rate reception according to the present invention;

[0102] Figure 2 This is a processing block diagram of a high-speed parallel timing synchronization method based on low sampling rate reception according to the present invention.

[0103] Figure 3 This is a comparison diagram of the constellation before and after timing synchronization under 16QAM modulation provided in Embodiment 1 of the present invention, wherein the upper part is the constellation before timing synchronization and the lower part is the constellation after timing synchronization.

[0104] Figure 4 This is a comparison chart of the bit error rate curve after timing error compensation under 16QAM modulation and the theoretical value provided in Embodiment 1 of the present invention. Detailed Implementation

[0105] To better illustrate the purpose and advantages of the present invention, the invention will be further described below in conjunction with the accompanying drawings and examples.

[0106] Example 1:

[0107] This embodiment discloses a high-speed parallel timing synchronization method based on low sampling rate reception, and the specific implementation steps are as follows:

[0108] Step 1, record For the first At any given time, the ADC sampled at the receiving end will be... The path signal is fed into a buffer to simultaneously store the currently processed data segment, the previous data segment, and the next data segment, thereby ensuring the continuity of the data window during the filtering calculation; the buffer operates according to the control signal output by the improved numerically controlled oscillator mNCO. The output buffer outputs a data sequence and synchronously transmits the parallel path control signal of the mNCO output. To the subsequent steps. The steps described in the first... At any given time, based on the control signal output by the mNCO Signals buffered from the buffer Generate buffer output data sequence The method is,

[0109] Set index ,in For the number of symbols in the matched filter, when At that time, with Output data sequence as a buffer;

[0110] when When, it indicates that a sample input point needs to be skipped at the current moment, let and output If at this time Then control the timing synchronization of the whole system. Pause calculation and output once at a time, and in Time makes And restore calculation and output;

[0111] when When, it means that at the current moment, one input sampling point needs to be retained, that is, one output sampling point needs to be added. At this time, it is... Output the data sequence as a buffer.

[0112] Step 2: To achieve cross-sampling rate mapping of the timing phase error on the low sampling rate side to the coefficient space of the high oversampling matched filter, and to improve the access efficiency of filter coefficients during parallel multi-matched filtering, the total coefficients of the matched filter are pre-placed in multiple read-only memories according to the multi-memory interleaving rule based on modulus mapping; according to Timing phase error of mNCO output Calculate the corresponding filter coefficient addresses; based on the filter coefficient addresses, read the required filter coefficients in parallel from multiple read-only memories and reassemble them in tap order to form a filter coefficient sequence. The specific implementation method is as follows:

[0113] Step 2.1, based on the number of symbols in the matched filter And record the number of sampling points for each symbol as The oversampling amplification factor is Generate the total storage sequence of the matched filter. :

[0114]

[0115] in The total storage sequence is uniformly addressed according to address order, and the coefficient address is denoted as... :

[0116]

[0117] Will Mapped to the The first memory cell Line address:

[0118]

[0119]

[0120] in For rounding down, Number of memory units;

[0121] Accordingly, the total storage sequence is interleaved and pre-set according to the mapping relationship. In the ROM, the first All storage coefficients in each ROM satisfy:

[0122] .

[0124] Step 2.2, according to The signal undergoes mode compensation for timing phase error to obtain the corrected timing phase error. :

[0125]

[0126] in The number of channels for the 4x oversampled signal output synchronously at a set time.

[0127] Define the oversampling rate of the signal by the receiver as: , for The simplest fractional form, i.e. And record This is the interpolation multiple. To determine the next draw multiplier, expand Multiply by 1, and round to the nearest integer. Using the base address, we obtain the initial address for taking coefficients. :

[0128]

[0129] in Rounding is performed for the nearest integer.

[0130] Step 2.3, using the starting address Based on, and with a preset step offset Form the set of target addresses to be read at the current moment. :

[0131]

[0132] Address Mapped to the The first memory cell Line address, where:

[0133]

[0134]

[0135] Based on this, extract all the filter coefficients needed at this moment; when the step parameters... With the number of storage units When the coprime relationship is satisfied, the target addresses corresponding to consecutive taps are in the modulo... In this sense, a set of distinct remainders are formed, so that each target address at the same time can be allocated to a different memory bank, avoiding parallel read conflicts at the same time;

[0136] After reading, the filter coefficients output from multiple read-only memories are reassembled according to the tap order based on the memory bank number corresponding to each tap, forming a filter coefficient sequence. :

[0137]

[0138] in The process of generating the starting address and forming the target address set is used to map the timing phase error on the low sampling rate side to the spatial address offset of the coefficients of the high oversampling matched filter, thereby realizing the dynamic reading of the filter coefficients under cross sampling rate conditions.

[0139] Step 3: Output the buffer data sequence obtained in Step 1 and the data obtained in Step 2. The input is convolved in a parallel multi-matched filter to obtain... Point output sequence The specific implementation method is as follows:

[0140] Step 3.1, when When the length does not meet the requirements of the polyphase decomposition structure of the subsequent filter, for Zero-padding is performed to obtain the extended coefficient sequence. :

[0141]

[0142] in , where is the required length for the decomposed structure, satisfying:

[0143] .

[0145] Step 3.2, will according to Set the first-level decomposition path and perform first-level decomposition to obtain... A sequence of first-level sub-filter coefficients :

[0146]

[0147] in This indicates the branch index of the first-level sub-filter. Indicates the tap index of the first-level sub-filter; for each first-level sub-filter Press again Set the number of two-level decomposition paths and perform two-level decomposition. Each path yields... A sequence of coefficients for a second-level sub-filter ;

[0148]

[0149] in Indicates the branch index of the second-level sub-filter. This represents the tap index of the second-level sub-filter; it can be implemented by splitting according to the structure described above. Efficient implementation of fractional-times-multiple-signal sampling rate recovery.

[0150] Step 3.3: Take the first 30 data points from the input data buffer. :

[0151]

[0152] Regarding the first The first-level sub-filter branch applies a time delay processing corresponding to that first-level branch to the input data sequence, resulting in the first-level branch input sequence. :

[0153]

[0154] in For the first The time delay corresponding to the first-level sub-filter branch of each path; for each signal sequence Apply the delay processing corresponding to this second-level branch again to obtain :

[0155]

[0156] in For the first The time delay corresponds to the branch of the second-level sub-filter; then the time-delayed sequence is processed according to... Extraction is performed to obtain the input signal sequence of the second-level branch. :

[0157] .

[0159] Step 3.4, With the corresponding Perform filtering calculations to obtain the signal output of the second-level sub-filter. :

[0160]

[0161] The summation output of the first-level branch is obtained by superimposing the outputs of all second-level sub-filters within the same first-level branch. and to conduct Double interpolation process to obtain ;right Apply the advance processing corresponding to this first-level branch to obtain the phase-aligned first-level branch output. :

[0162]

[0163] in For the first The lead compensation amount corresponds to the first-order sub-filter branch of the path; for Then, the layers are stacked again, and the latency is removed. The parallel filtering output sequence of the total filter at the current time can be obtained. :

[0164] .

[0166] Step 4: When the output of Step 1... When additional output points are required, the result obtained in step three... Based on this, calculate the additional filter output point and compare it with... Together The point-parallel timed synchronous output sequence is calculated using the following method:

[0167] Step 4.1: To reduce the additional multiplication and addition complexity in scenarios with additional outputs, operations can be performed only on sparse terms constrained by the index set; let the length of the filter coefficients be calculated for sparse single-point filtering. ; Define the length as coefficient index set Its settings are as follows:

[0168]

[0169] Based on this, the coefficient sequence of a sparse single-point filter can be constructed. :

[0170] .

[0172] Step 4.2, take the output data sequence from the buffer output in Step 1. Use data to construct a single-point filter input sequence. :

[0173] .

[0175] Step 4.3: Obtain the additional filter output point through sparse convolution as shown in the following formula. :

[0176]

[0177] That is, the additional output points are composed of the partial convolution results of the original filter under the constraints of the index set.

[0178] Step 4.4, using Form additional output sequence , convert the sequence The sequence obtained in step three Combine, form Point-to-point parallel timing synchronous output sequence .

[0179] Step 5, when When the value is 0, the method output is... ;when When the value is 1, the method outputs .

[0180] Step Six: Based on the results obtained in Step Three Timing error estimation and loop filtering are performed to obtain the calculation results. The timing error estimation uses the OM algorithm, which is calculated by performing OM estimation on the signal to be estimated to obtain the OM estimate value. :

[0181]

[0182] in The output signal sequence for step three. To estimate the signal length used each time, The length of the DFT transform;

[0183] Timing error estimate for:

[0184]

[0185] In the formula, The function is used to find the argument of a complex number, and its range of values ​​is: , and Used to represent The real and imaginary parts;

[0186] The loop filtering calculation method involves filtering and calculating using a filter transfer function. for:

[0187]

[0188] in and .

[0189] Step 7: Take the results from Step 6 The calculation is performed in the input mNCO, accumulating the output value of the loop filter:

[0190]

[0191] Determined based on whether and in which direction there is overflow. , and :

[0192] .

[0194] Step 8: Convert the output of the loop filter... , and Return to steps one and two to process the input data in a loop until timed synchronization is complete.

[0195] The technical achievements of this invention will be described in detail below with reference to simulation experiments.

[0196] 1. Conditions

[0197] The signal modulation method is 16QAM, the roll-off factor of the raised cosine matched filter is 0.2, and the number of experimental data points is [number missing]. .

[0198] 2. Results Analysis

[0199] Result 1: Under the above conditions, the timing synchronization performed using the present invention yielded the following results. Figure 3As shown, the upper part is the constellation diagram without timing synchronization, and the lower part is the constellation diagram after timing synchronization. After timing synchronization, the constellation points are clustered near their theoretical positions, and the individual constellation grid points are clearly separated, indicating that the method of this invention can effectively correct timing deviations.

[0200] Result 2: Under the above conditions, timing synchronization was performed using the present invention under different signal-to-noise ratios in a Gaussian channel, and the results are as follows. Figure 4 As shown. Figure 4 The horizontal axis represents The unit is decibels (dB), and the vertical axis represents the bit error rate (BER) performance. Comparing the experimental curve with the theoretical curve, the experimental method is closer to the theoretical value, and it is a timing synchronization method with excellent performance.

[0201] The above detailed description further illustrates the purpose and technical solution of the invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A high-speed parallel timing synchronization method based on low sampling rate reception, characterized in that: Includes the following steps, Step 1, record For the first At any given time, the ADC sampled at the receiving end will be... The signal is fed into a buffer, which is buffered according to the control signal output by the improved numerically controlled oscillator mNCO. The output buffer outputs a data sequence and synchronously transmits the parallel path control signal of the mNCO output. To the next steps; Step 2: Pre-place the total coefficients of the matched filter in multiple read-only memories according to the multi-memory interleaving rule based on mode mapping; according to Timing phase error of mNCO output Calculate the corresponding filter coefficient addresses, and then read the filter coefficient sequence. ; Step 3: Output the buffer data sequence obtained in Step 1 and the data obtained in Step 2. The input is filtered in a parallel multi-matched filter to obtain... Point output sequence ; Step 4, when When the value is 1, calculate the additional filter output point and compare it with... Together Point output sequence ; Step 5, when When it is 0, output ;when When it is 1, output ; Step Six: The results obtained in Step Three... Timing error estimation and loop filtering are performed to obtain the calculation results. ; Step 7: Take the results from Step 6 The calculation is performed by inputting mNCO, and the result is obtained. , and ; Step 8: Output the mNCO , and Return to steps one and two to process the input data in a loop until timed synchronization is complete.

2. The method as described in claim 1, characterized in that: The record described in step one For the first At any given time, based on the control signal output by the mNCO Signals buffered from the buffer Generate buffer output data sequence The method is, Set index ,in For the number of symbols in the matched filter, when At that time, with Output data sequence as a buffer; when When, it indicates that a sample input point needs to be skipped at the current moment, let and output If at this time Then control the timing synchronization of the whole system. Pause calculation and output once at a time, and in Time makes And restore calculation and output; when When, it means that at the current moment, one input sampling point needs to be retained, that is, one output sampling point needs to be added. At this time, it is... Output the data sequence as a buffer.

3. The method as described in claim 2, characterized in that: The method for pre-setting the total coefficients of the matched filter in multiple read-only memories according to the multi-memory interleaving rule based on mode mapping in step two is as follows: Based on the number of signs of the matched filter And record the number of sampling points for each symbol as The oversampling amplification factor is Generate the total storage sequence of the matched filter. : in The total storage sequence is uniformly addressed according to address order, and the coefficient address is denoted as... : Will Mapped to the The first memory cell Line address, where: , in For rounding down, Number of memory units; The total storage sequence is interleaved and pre-set according to the mapping relationship. In the ROM, the first All storage coefficients in each ROM satisfy: 。 4. The method as described in claim 3, characterized in that: Step two is based on Timing phase error of mNCO output The method for generating the initial address of the read coefficients required at the current moment is as follows: according to The signal undergoes mode compensation for timing phase error to obtain the corrected timing phase error. : in The number of channels for the timed synchronous output of the 4x oversampled signal; Define the oversampling rate of the signal by the receiver as: , for The simplest fractional form of , and denoted as This is the interpolation multiple. To determine the next draw multiplier, expand Multiply by 1, and round to the nearest integer. Using the base address, we obtain the initial address for reading the coefficients. : in Rounding is performed for the nearest integer.

5. The method as described in claim 4, characterized in that: Step two describes the method of reading the required filter coefficients in parallel from multiple read-only memories and reassembling them in tap order. The initial address of the read coefficient Based on, and with a preset step offset Form the set of target addresses to be read at the current moment. : Address Mapped to the The first memory cell Line address, where: , Based on the above calculation method, retrieve all the filter coefficients required at this moment. and When the coprime relationship is satisfied, the target addresses corresponding to consecutive taps are in the modulo... In this sense, a set of distinct remainders are formed, so that each target address at the same time can be allocated to different memory banks; After reading, the filter coefficients output from multiple read-only memories are reassembled according to the tap order based on the memory bank number corresponding to each tap, forming a filter coefficient sequence. : in The process of generating the starting address and forming the target address set is used to map the timing phase error on the low sampling rate side to the spatial address offset of the coefficients of the high oversampling matched filter, thereby realizing the dynamic reading of the filter coefficients under cross sampling rate conditions.

6. The method as described in claim 5, characterized in that: The specific implementation method of step three is as follows: Step 3.1, when When the length does not meet the requirements of the polyphase decomposition structure of the subsequent filter, for Zero-padding is performed to obtain the extended coefficient sequence. : in The required length for the decomposed structure; Step 3.2, will according to Set the first-level decomposition path and perform first-level decomposition to obtain... A sequence of first-level sub-filter coefficients : in This indicates the branch index of the first-level sub-filter. Indicates the tap index of the first-level sub-filter; for each first-level sub-filter Press again Set the number of two-level decomposition paths and perform two-level decomposition. Each path yields... A sequence of coefficients for a second-level sub-filter : in Indicates the branch index of the second-level sub-filter. This represents the tap index of the second-level sub-filter; it can be implemented by splitting according to the structure described above. Efficient implementation of fractional-times-multiple-signal sampling rate recovery; Step 3.3, retrieve the first part of the output data from the buffer. Data : Regarding the first The first-level sub-filter branch applies a time delay processing corresponding to that first-level branch to the input data sequence, resulting in the first-level branch input sequence. : in For the first The time delay corresponding to the first-level sub-filter branch of each path; for each signal sequence Apply the delay processing corresponding to this second-level branch again to obtain : in For the first The time delay corresponds to the branch of the second-level sub-filter; then the time-delayed sequence is processed according to... Extraction is performed to obtain the input signal sequence of the second-level branch. : ； Step 3.4, With the corresponding Perform filtering calculations to obtain the signal output of the second-level sub-filter. : The summation output of the first-level branch is obtained by superimposing the outputs of all second-level sub-filters within the same first-level branch. and to conduct Double interpolation process to obtain ,right Apply the advance processing corresponding to this first-level branch to obtain the phase-aligned first-level branch output. : in For the first The lead compensation amount corresponds to the first-order sub-filter branch of the path; for Then, the layers are stacked again, and the latency is removed. The parallel filtering output sequence of the total filter at the current time can be obtained. : 。 7. The method as described in claim 6, characterized in that: In step four, when the output of step one... When additional output points are required, the result obtained in step three... Based on this, calculate the additional filter output point and compare it with... Together The point-parallel timed synchronous output sequence is implemented as follows: Step 4.1: To reduce the additional multiplication and addition complexity in scenarios with additional outputs, operations can be performed only on the sparse terms constrained by the index set. Let the length of the sparse single-point filter coefficients be calculated. ; Define the length as coefficient index set Its settings are as follows: Based on this, the coefficient sequence of a sparse single-point filter can be constructed. : Step 4.2, take the output data sequence from the buffer output in Step 1. Use data to construct a single-point filter input sequence. : Step 4.3: Obtain the additional filter output point through sparse convolution as shown in the following formula. : That is, the additional output points are composed of the partial convolution results of the original filter under the constraints of the index set; Step 4.4, using Form additional output sequence , convert the sequence The sequence obtained in step three Combine, form Point-to-point parallel timing synchronous output sequence .

8. The method as described in claim 7, characterized in that: Step six describes the timing error estimation using the OM algorithm. Specifically, the OM estimation is performed on the signal to be estimated to obtain the OM estimate. : in For the index of the currently processed data block, The output signal sequence for step three. To estimate the signal length used each time, The length of the DFT transform; Timing error estimate for: In the formula, The function is used to find the argument of a complex number, and its range of values ​​is: , and Used to represent The real and imaginary parts; The loop filtering calculation method involves filtering and calculating using a filter transfer function. for: in and These are the coefficients of the loop filter.

9. The method as described in claim 8, characterized in that: The output control quantity described in step seven , and The method is, The output value of the loop filter is accumulated: Determined based on whether and in which direction there is overflow. , and : 。

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