Alarm control method and device for chip, chip and electronic equipment

Abstract

The application relates to the chip security technical field and discloses an alarm control method for a chip, which is applied to a master control module, a key generation module is used for generating a first key and / or a second key with random characteristics, the alarm control method comprises the following steps: encrypting an original enable signal based on the first key sent by the key generation module, generating an enable encrypted signal and sending the enable encrypted signal to a controlled module, so that the controlled module generates an enable signal based on the enable encrypted signal; receiving an alarm encrypted signal sent by the controlled module; wherein the alarm encrypted signal is generated by the controlled module based on the second key sent by the key generation module when an alarm event is detected under controlled enable; the alarm encrypted signal is decrypted based on the second key, an alarm signal is generated to perform alarm control. The alarm control method can improve the chip alarm success rate and operation safety. The application further discloses an alarm control device for a chip, a chip and an electronic device.

Description

Technical Field

[0001] This application relates to the field of chip security technology, such as an alarm control method and device for chips, chips, and electronic devices. Background Technology

[0002] Currently, with the increasing demands for chip security management, multi-module collaborative chip architectures are widely used in various functional chips. These chips typically integrate a main control module and controlled modules. The main control module serves as the chip's control center, responsible for managing chip operation. The controlled modules are distributed across different areas of the chip or in independent power domains.

[0003] To achieve alarm control of the controlled module, the relevant technology configures a single channel between the main control module and the controlled module for alarm enable control, and configures a dual channel for alarm output from the controlled module. The main control module performs alarm control based on an alarm mechanism. The alarm mechanism is as follows: no alarm is triggered when the controlled module outputs a single bit combination of 01 through the dual channels; an alarm is triggered when the output combination is any other bit combination. This other bit combination is any combination of 00, 11, or 10.

[0004] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art: When the main control module sends an enable signal to the controlled module, it is highly vulnerable to external attacks. Because the enable signal is transmitted via a single signal line, the signal level is easily interfered with or abruptly changed to a fixed level by attacks. This can cause the enable signal to be tampered with and deactivated, preventing the controlled module from triggering the alarm detection process and thus hindering the controlled module from properly feeding back alarm information to the main control module. Therefore, the alarm control method used in related technologies has security vulnerabilities, and the chip's security is insufficient.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0007] This disclosure provides an alarm control method and apparatus for chips, as well as chips and electronic devices, to improve the success rate of chip alarms and operational security.

[0008] In some embodiments, the alarm control method is applied to a main control module. The chip includes a main control module, a controlled module, and a key generation module. The key generation module is used to generate a first key and / or a second key with random characteristics. The alarm control method includes: encrypting an original enable signal based on the first key sent by the key generation module, generating an enable encrypted signal and sending it to the controlled module, so that the controlled module generates an enable signal based on the enable encrypted signal; receiving an alarm encrypted signal sent by the controlled module; wherein the alarm encrypted signal is generated by encrypting an alarm signal based on the second key sent by the key generation module when the controlled module detects an alarm event under controlled enable; and decrypting the alarm encrypted signal based on the second key to generate an alarm signal for alarm control.

[0009] In some embodiments, the key generation module includes a random number module; the key generation module generates single-bit signals through the random number module for use as a first key and / or a second key having random characteristics.

[0010] In some embodiments, encrypting the original enable signal based on the first key sent by the key generation module, generating an enable encrypted signal and sending it to the controlled module includes: performing a bit-by-bit reversible logical operation between the first key sent by the key generation module and the original enable signal to generate an enable encrypted signal and sending it to the controlled module; decrypting the alarm encrypted signal based on the second key to generate an alarm signal includes: performing a bit-by-bit reversible logical operation between the second key and the alarm encrypted signal to generate an alarm signal.

[0011] In some embodiments, the first key is the same as the second key; or, the first key is different from the second key.

[0012] In some embodiments, the alarm control method is applied to a controlled module. The chip includes a main control module, a controlled module, and a key generation module. The key generation module generates a first key and / or a second key with random characteristics. The alarm control method includes: receiving an enable encryption signal sent by the main control module; wherein the enable encryption signal is generated by the main control module encrypting an original enable signal based on the first key; decrypting the enable encryption signal based on the first key sent by the key generation module to generate an enable signal for controlled enable under the enable signal; when an alarm event is detected under controlled enable, encrypting an alarm signal based on the second key sent by the key generation module to generate an alarm encryption signal; and sending the alarm encryption signal to the main control module so that the main control module decrypts the alarm encryption signal based on the second key and generates an alarm signal for alarm control.

[0013] In some embodiments, the second key includes a first key signal and a second key signal, and the alarm signal includes a positive phase signal and a negative phase signal; when an alarm event is detected under controlled enable, the alarm signal is encrypted based on the second key sent by the key generation module to generate an alarm encrypted signal, including: when an alarm event is detected under controlled enable, encrypting the positive phase signal based on the first key signal to generate a positive phase alarm encrypted signal; and / or, when an alarm event is detected under controlled enable, encrypting the negative phase signal based on the second key signal to generate a negative phase alarm encrypted signal.

[0014] In some embodiments, the alarm control device includes a processor and a memory storing program instructions, the processor being configured to execute the alarm control method for the chip as described above when the program instructions are executed.

[0015] In some embodiments, the chip includes: a chip body, including a main control module and a controlled module; a key generation module for generating a first key and / or a second key with random characteristics; and an alarm control device for the chip as described above, installed on the chip body.

[0016] In some embodiments, the controlled module includes a sensing and detection module or a status acquisition module and a power monitoring module.

[0017] In some embodiments, the electronic device includes: a device body; and a chip, as described above, mounted on the device body.

[0018] The alarm control method, apparatus, chip, and electronic device for chips provided in this disclosure can achieve the following technical effects: The main control module obtains a first key and / or a second key with random characteristics through the key generation module. Using the first key, it encrypts the original enable signal to generate an encrypted enable signal, which is then sent to the controlled module. When the encrypted enable signal is attacked or malfunctions, the enabled signal parsed by the controlled module exhibits random characteristics instead of a fixed level. This allows the controlled module to intermittently power on under random high levels, extending the effective power-on time, making it easier to trigger alarm actions, and improving the reliability of the alarm mechanism. Simultaneously, the controlled module uses the second key to encrypt the alarm signal, forming an encrypted alarm signal, which is then fed back to the main control module. The main control module decrypts the signal and restores the original alarm signal. Even if the alarm transmission link is attacked or malfunctions, the decrypted alarm signal still retains random characteristics, increasing the probability that the alarm signal falls within the effective level range, thus improving the chip's alarm success rate and overall operational security.

[0019] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a hardware schematic diagram of a chip provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of an alarm control method for a chip provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of another alarm control method for a chip provided in an embodiment of this disclosure; Figure 4 This is an application illustration of an embodiment of the present disclosure; Figure 5-1 This is a hardware schematic diagram of a chip in a related art provided in an embodiment of this disclosure; Figure 5-2 The embodiments provided in this disclosure are based on Figure 5-1 Signal timing diagram; Figure 6-1 This is a hardware schematic diagram of another chip provided in an embodiment of this disclosure; Figure 6-2 The embodiments provided in this disclosure are based on Figure 6-1 Signal timing diagram; Figure 7 This is a schematic diagram of an alarm control device for a chip provided in an embodiment of this disclosure. Detailed Implementation

[0021] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0022] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0023] Unless otherwise stated, the term "multiple" means two or more.

[0024] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0025] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0026] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0027] In this embodiment, the key with random characteristics refers to a unique or variable sequence generated by a random number generation mechanism to control changes in the password. The random number generation mechanism includes a true random mechanism or a pseudo-random mechanism, and the key encoding includes encryption and / or decryption. This key with random characteristics differs from fixed keys and derived keys; it possesses randomness and its output sequence is unpredictable. Here, a true random mechanism refers to a mechanism that generates a random sequence based on natural random phenomena in the physical world; its randomness originates from unpredictable physical processes rather than algorithmic computation. A pseudo-random mechanism refers to a mechanism that generates a seemingly random sequence using a deterministic algorithm with an initial seed input.

[0028] Combination Figure 1 As shown, this embodiment of the present disclosure provides a chip 10, including a main control module 100, a controlled module 200, and a key generation module 300. The key generation module 300 is used to generate a first key and / or a second key with random characteristics.

[0029] Based on the above hardware diagram of the chip, combined with Figure 2 As shown, this disclosure provides an alarm control method for a chip, including: S01, the main control module encrypts the original enable signal based on the first key sent by the key generation module, generates an enable encryption signal, and sends it to the controlled module so that the controlled module generates an enable signal based on the enable encryption signal.

[0030] S02, the main control module receives the alarm encryption signal sent by the controlled module. The alarm encryption signal is generated by the controlled module encrypting the alarm signal with a second key sent by the key generation module when it detects an alarm event under controlled enable conditions.

[0031] S03, the main control module decrypts the alarm encryption signal based on the second key and generates an alarm signal for alarm control.

[0032] The alarm control method for chips provided in this disclosure involves a main control module obtaining a first key and / or a second key with random characteristics through a key generation module. Based on the first key, the main control module encrypts the original enable signal to generate an encrypted enable signal, which is then sent to the controlled module. Since the encrypted enable signal is the original enable signal encrypted with the first key, when attacked or abnormal, the enabled signal parsed by the controlled module will no longer be a fixed level, but is more likely to exhibit random characteristics. In this case, the controlled module can intermittently turn on under random high levels, effectively extending its effective on-time, thus making it easier to trigger alarm behavior during intermittent on-time.

[0033] Simultaneously, the controlled module encrypts the alarm signal using a second key to generate an alarm signal and feeds it back to the main control module. The main control module then decrypts the alarm signal using the second key to obtain the alarm signal. When the alarm transmission link is attacked or malfunctions, the decrypted alarm signal also exhibits random characteristics, significantly increasing the probability that the alarm signal falls within the valid alarm level range. This improves the reliability and success rate of the chip's alarm, thereby enhancing the overall security of the chip.

[0034] Optionally, the key generation module includes a random number module. The key generation module generates single-bit signals that serve as a first key and / or a second key with random characteristics through the random number module.

[0035] In this way, the key generation module generates a single-bit signal through the random number module, which serves as the first key and / or the second key. The single-bit signal has a simple structure and low computational load, significantly reducing the internal logic resource consumption of the chip and improving the encryption and decryption speed of key generation and the main control module and controlled modules. Furthermore, the single-bit signal is directly generated by the random number module, giving the first and / or second keys randomness and unpredictability, effectively improving the anti-attack capability during the transmission of enable and alarm signals, thereby increasing the reliability and success rate of the chip's alarms and further enhancing the overall security of the chip.

[0036] Optionally, the main control module encrypts the original enable signal based on the first key sent by the key generation module, generates an enable encryption signal, and sends it to the controlled module, including: The main control module performs bit-by-bit reversible logic operations on the first key sent by the key generation module and the original enable signal to generate an enable encryption signal and send it to the controlled module.

[0037] The main control module decrypts the alarm encryption signal based on the second key and generates an alarm signal, including: The main control module performs bit-by-bit reversible logical operations based on the second key and the alarm encryption signal to generate an alarm signal.

[0038] In this way, the main control module uses the first key to perform bit-by-bit reversible logical operations on the original enable signal, encrypting it into an encrypted enable signal before transmitting it to the controlled module. This makes the signal during transmission exhibit random characteristics, making it difficult to tamper with or forge, effectively improving the security and anti-interference capability of signal transmission. The main control module also uses the second key to perform corresponding bit-by-bit reversible logical operations on the alarm encrypted signal to restore the original alarm signal. While ensuring the security of signal transmission, it achieves lossless signal restoration. Through the above key-based bit-by-bit reversible logical operations, it can both encrypt and protect the transmitted signal and allow the receiving hardware module to restore the original signal using the same rules, combining the advantages of high encryption security, simple operational logic, and low processing latency.

[0039] Optionally, bitwise reversible logical operations include bitwise XOR operations.

[0040] This allows the receiving hardware module to recover the original signal using the same rules, simplifying the encryption and decryption logic and improving encryption security.

[0041] Optionally, the first key is the same as the second key; or, the first key is different from the second key.

[0042] In this way, when the first key and the second key are the same, the key generation and storage logic can be simplified. When the first key and the second key are different, independent security protection can be achieved for the enable encryption link and the alarm encryption link. Even if one of the keys of the enable encryption link and the alarm encryption link is illegally cracked or leaked, the communication security of the other link is still guaranteed, avoiding the collapse of the overall security mechanism due to the failure of a single key, and further improving the overall security of the chip.

[0043] Combination Figure 3 As shown in the embodiments of this disclosure, an alarm control method for a chip is also provided, including: S11, the controlled module receives the enable encryption signal sent by the master control module. The enable encryption signal is generated by the master control module based on the first key and encrypted with the original enable signal.

[0044] S12, the controlled module generates an enable signal based on the first key decryption enable encryption signal sent by the key generation module, so as to be controlled and enabled under the enable signal.

[0045] S13, when the controlled module detects an alarm event under controlled enable, it encrypts the alarm signal based on the second key sent by the key generation module and generates an alarm encryption signal.

[0046] S14, the controlled module sends an alarm encryption signal to the main control module, so that the main control module decrypts the alarm encryption signal based on the second key and generates an alarm signal for alarm control.

[0047] The alarm control method for chips provided in this disclosure involves the controlled module decrypting an enabled encryption signal sent by the main control module using a first key sent by a key generation module after receiving the encryption signal. This decryption yields an enabled signal and enables controlled activation. Since the enabled encryption signal is the original enabled signal encrypted with the first key, when it is attacked or malfunctions, the enabled signal decrypted by the controlled module will exhibit random characteristics, rather than remaining fixed at a low level after an attack. In this case, the controlled module can intermittently activate under randomly occurring high levels, effectively increasing its effective activation time and making it easier to trigger alarm behavior during intermittent activation.

[0048] When the controlled module detects an alarm event in the controlled enabled state, it encrypts the alarm signal based on the second key and generates an encrypted alarm signal, which is then sent to the main control module. The main control module decrypts the encrypted alarm signal using the second key to recover the original alarm signal. Because the encrypted alarm signal is encrypted with the second key, if it is attacked or an anomaly occurs during transmission, the alarm signal decrypted by the main control module will also exhibit random characteristics. This increases the probability that the alarm signal falls within the corresponding alarm level range, improving the reliability and success rate of the chip's alarm, and thus enhancing the overall security of the chip.

[0049] Optionally, the second key includes a first key signal and a second key signal, and the alarm signal includes a positive phase signal and a negative phase signal. The first key signal and the second key signal may be the same, or the first key signal and the second key signal may be different.

[0050] When the controlled module detects an alarm event under controlled enable, it encrypts the alarm signal based on the second key sent by the key generation module, generating an encrypted alarm signal, including: When an alarm event is detected under controlled enable, a positive phase signal is encrypted based on a first key signal to generate a positive phase alarm encrypted signal; and / or, When an alarm event is detected under controlled enable, a negative phase signal is encrypted based on the second key signal to generate a negative phase alarm encrypted signal.

[0051] In this way, when the controlled module is triggered to alarm during intermittent operation, it simultaneously configures the first and second key signals and supports independent encryption of the positive and negative phase signals in the alarm signal, further realizing dual security protection for the alarm differential link. Even if one link in the alarm differential link is illegally attacked or tampered with, the encryption protection of the other link can still take effect independently, avoiding the collapse of the entire alarm mechanism due to the failure of a single security path. In addition, the above-mentioned security protection method of the alarm differential link is compatible with the chip's differential signal transmission architecture, without the need to modify the original hardware transmission link. Furthermore, under abnormal conditions, the signals after dual-path decryption of the alarm differential link can both exhibit random characteristics, completely avoiding the problem of missed alarms caused by single-path anomalies. This improves the reliability and success rate of the chip alarm while also enhancing its robustness.

[0052] In a practical application, such as Figure 4 As shown, the alarm control method for the chip specifically performs the following steps: S100, the key generation module sends a first key and a second key with random characteristics to the master control module and the controlled module.

[0053] S101, the main control module encrypts the original enable signal based on the first key and generates an enable encryption signal.

[0054] S102, the main control module sends an enable encryption signal to the controlled module.

[0055] S103, the controlled module decrypts the enable encryption signal based on the first key and generates an enable signal.

[0056] S104 When the controlled module detects an alarm under controlled enable, it encrypts the alarm signal based on the second key and generates an encrypted alarm signal.

[0057] S105, the controlled module sends an encrypted alarm signal to the main control module.

[0058] S106, the main control module decrypts the alarm encryption signal based on the second key and generates an alarm signal.

[0059] In another practical application, combined with Figure 5-1 and Figure 5-2 As shown, CTRL is the main control module, and SENSOR is the sensor detection module.

[0060] EN is the SENSOR enable signal; an alarm is generated when the enable signal is high. TEST_EN is the test enable signal; an alarm will definitely sound when the test enable is high, used to check if the SENSOR is working. DIG_CLK is the operating clock of the CTRL, and DIG_ALM is the alarm clock of the CTRL.

[0061] OUT is the positive phase signal in the alarm signal, and OUTN is the negative phase signal in the alarm signal. The alarm mechanism is as follows: if OUT is at level 1 and OUTN is at level 0, no alarm is triggered; otherwise, an alarm is triggered. These other level combinations include OUT being at level 1 and OUTN being at level 1, or OUT being at level 0 and OUTN being at level 1, or OUT being at level 0 and OUTN being at level 0.

[0062] Combination Figure 6-1 and Figure 6-2 As shown, TRNG is the key generation module, KEY1 is the first key, and KEY2 is the second key. KEY1 and KEY2 are identical, both being KEY. Here, KEY is a single-bit signal. DIG_CLK is the operating clock of the CTRL, and DIG_ALM is the alarm clock of the CTRL.

[0063] EN_DIG is the original enable signal, EN is the enable encryption signal, and EN_ANA is the enable signal.

[0064] After TRNG generates KEY1 and KEY2, it sends them to SENSOR and CTRL simultaneously.

[0065] CTRL performs a bitwise XOR operation between KEY1 and EN_DIG to generate EN, which is then sent to SENSOR.

[0066] The SENSOR performs a bitwise XOR operation between KEY1 and EN to generate EN_ANA.

[0067] The SENSOR is enabled under controlled conditions (EN_ANA). Specifically, when EN_ANA is high, the SENSOR can initiate alarm event detection.

[0068] When the sensor is enabled, upon detecting an alarm, it generates a positive-phase alarm encrypted signal by XORing KEY2 and OUT, and a negative-phase alarm encrypted signal by XORing KEY2 and OUTN. These encrypted alarm signals are then sent to the main control module. The alarm encrypted signals include both positive-phase and negative-phase alarm encrypted signals.

[0069] CTRL decrypts the positive phase alarm encryption signal based on KEY2 to generate the corresponding alarm signal OUT, and decrypts the negative phase alarm encryption signal based on KEY2 to generate the corresponding alarm signal OUTN.

[0070] CTRL performs alarm control based on the alarm signals corresponding to OUT and OUTN, and the alarm mechanism.

[0071] Combination Figure 7As shown, this embodiment of the disclosure provides an alarm control device 70 for a chip, including a processor 700 and a memory 701. Optionally, the device 70 may further include a communication interface 702 and a bus 703. The processor 700, communication interface 702, and memory 701 can communicate with each other via the bus 703. The communication interface 702 can be used for information transmission. The processor 700 can call logical instructions in the memory 701 to execute the alarm control method for the chip described in the above embodiment.

[0072] Furthermore, the logic instructions in the aforementioned memory 701 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0073] The memory 701, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 700 executes functional applications and data processing by running the program instructions / modules stored in the memory 701, thereby implementing the alarm control method for the chip described in the above embodiments.

[0074] The memory 701 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 701 may include high-speed random access memory and may also include non-volatile memory.

[0075] This disclosure also provides a chip 10, including: a chip body, a key generation module 300, and the aforementioned alarm control device 70 for the chip. The chip body includes a main control module 100 and a controlled module 200. The key generation module 300 is used to generate a first key and / or a second key with random characteristics. The alarm control device 70 for the chip is mounted on the chip body. The mounting relationship described herein is not limited to placement within the chip body, but also includes mounting connections with other components of the chip 10, including but not limited to physical connections, electrical connections, or signal transmission connections. Those skilled in the art will understand that the alarm control device 70 for the chip can be adapted to feasible chip bodies to achieve other feasible embodiments.

[0076] Optionally, the controlled module 200 includes a sensing and detection module or a status acquisition module and a power monitoring module.

[0077] This disclosure also provides an electronic device, including a device body and a chip 10 as described above. The chip 10 is mounted on the device body.

[0078] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to execute the aforementioned alarm control method for a chip.

[0079] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, such as a USB flash drive, external hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk, etc., and other media capable of storing program code.

[0080] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0081] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0082] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0083] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. An alarm control method for a chip, characterized in that, Applied to the main control module, the chip includes a main control module, a controlled module, and a key generation module. The key generation module is used to generate a first key and / or a second key with random characteristics. The alarm control method includes: The first key sent by the key generation module is used to encrypt the original enable signal, generate an enable encryption signal, and send it to the controlled module so that the controlled module can generate an enable signal based on the enable encryption signal. Receives an alarm encryption signal sent by the controlled module; wherein the alarm encryption signal is generated by the controlled module encrypting an alarm signal based on the second key sent by the key generation module when the controlled module detects an alarm event under controlled enable; The alarm encryption signal is decrypted based on the second key, and an alarm signal is generated for alarm control.

2. The alarm control method according to claim 1, characterized in that, The key generation module includes a random number module; the key generation module generates single-bit signals through the random number module to serve as a first key and / or a second key with random characteristics.

3. The alarm control method according to claim 2, characterized in that, Based on the first key encryption original enable signal sent by the key generation module, an enable encryption signal is generated and sent to the controlled module, including: Based on the first key sent by the key generation module, a bit-by-bit reversible logical operation is performed with the original enable signal to generate an enable encryption signal and send it to the controlled module. Based on the second key, the alarm encryption signal is decrypted, and an alarm signal is generated, including: An alarm signal is generated by performing bit-by-bit reversible logical operations based on the second key and the alarm encryption signal.

4. The alarm control method according to claim 1, characterized in that, The first key is the same as the second key; or the first key is different from the second key.

5. An alarm control method for a chip, characterized in that, Applied to the controlled module, the chip includes a main control module, a controlled module, and a key generation module. The key generation module is used to generate a first key and / or a second key with random characteristics. The alarm control method includes: Receive the enable encryption signal sent by the main control module; wherein, the enable encryption signal is generated by the main control module based on the first key to encrypt the original enable signal; Based on the first key decryption enable encryption signal sent by the key generation module, an enable signal is generated to enable it in a controlled manner under the enable signal; When an alarm event is detected under controlled enable, an alarm encrypted signal is generated by encrypting the alarm signal based on the second key sent by the key generation module. An alarm encryption signal is sent to the main control module, so that the main control module can decrypt the alarm encryption signal based on the second key and generate an alarm signal for alarm control.

6. The alarm control method according to claim 5, characterized in that, The second key includes the first key signal and the second key signal, and the alarm signal includes a positive phase signal and a negative phase signal; when an alarm event is detected under controlled enable, the alarm signal is encrypted based on the second key sent by the key generation module to generate an encrypted alarm signal, including: When an alarm event is detected under controlled enable, a positive phase signal is encrypted based on a first key signal to generate a positive phase alarm encrypted signal; and / or, When an alarm event is detected under controlled enable, a negative phase signal is encrypted based on the second key signal to generate a negative phase alarm encrypted signal.

7. An alarm control device for a chip, comprising a processor and a memory storing program instructions, characterized in that, The processor is configured to execute, when running the program instructions, the alarm control method for a chip as described in any one of claims 1 to 6.

8. A chip, characterized in that, include: The chip itself includes a main control module and a controlled module; A key generation module is used to generate a first key and / or a second key with random characteristics; The alarm control device for a chip as described in claim 7 is installed on the chip body.

9. The chip according to claim 8, characterized in that, The controlled modules include a sensor detection module or status acquisition module and a power monitoring module.

10. An electronic device, characterized in that, include: Equipment body; The chip as described in claim 8 or 9 is mounted on the device body.

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