IRIG-B time service jitter detection and calibration method, system and device based on x86 gateway machine

Abstract

The present application relates to the technical field of gateway device, specifically relates to an IRIG-B time service jitter detection and calibration method based on X86 gateway machine, and the method comprises the following steps: S1: sampling the waveform of the input IRIG-B time code signal, obtaining the voltage waveform sample sequence near each candidate rising edge and the corresponding time reference sequence.The present application resists multiple threshold interference caused by signal reflection ringing by first sampling the input signal waveform at high density, identifying the first monotonic rising interval and fitting calculation to obtain robust edge timestamp.Meanwhile, the threshold flip count is quantified to represent the link physical abnormality.Further, a ternary model integrating fixed delay, edge slope and ringing strength is established to systematically calibrate the timestamp.Finally, the jitter index and link abnormality index are jointly output to realize comprehensive and accurate evaluation of the time service quality and link health status, and effectively distinguish real jitter and transmission artifacts.

Description

Technical Field

[0001] This invention relates to the field of gateway device technology, and more specifically to an IRIG-B timing jitter detection and calibration method, system and device based on an x86 gateway. Background Technology

[0002] In scenarios such as power, rail transportation, industrial automation, wide-area measurement and control, and edge computing, field devices require a unified and traceable time reference to support event sequence determination, fault waveform alignment, distributed data fusion, and control closed loop. The Type B time code, developed by intermodulation distance measuring instruments, is widely used to provide absolute time information to terminal devices due to its clear structure, high engineering applicability, and ability to be distributed via dedicated time sources or clock systems. A common implementation involves the time source outputting a Type B time code signal, which is then transmitted via cable and intermediate connecting devices to the receiving device. The receiving device then performs edge detection, symbol recognition, and time alignment, thereby providing a unified time for the local system.

[0003] In recent years, general-purpose processor architecture gateway devices have gradually taken on responsibilities such as edge data aggregation, protocol conversion, and time base distribution due to their advantages of general computing power, rich interfaces, ease of deployment, and centralized operation and maintenance. These gateway devices typically run general-purpose operating systems, using general-purpose peripheral buses, general-purpose timers, and interrupt or polling methods to collect edge timestamps of input signals, and perform decoding and synchronization in software. Compared with dedicated timing boards or hardware timestamp engines, general-purpose processor architecture platforms have greater complexity and uncertainty in clock architecture, task scheduling, driver links, and peripheral latency, making timing jitter detection and calibration more challenging in engineering implementation.

[0004] Existing Type B timecode timing implementations for gateway devices based on general-purpose processor architectures typically employ fixed-threshold edge triggering or input capture to acquire timestamps and statistically evaluate timing jitter. However, in real-world engineering environments, timing codes are often connected to gateway devices via coaxial cables and various adapter protection circuits. Inevitably, mismatches between characteristic impedance and input equivalent impedance, as well as imperfect grounding return paths, can occur in these links. This can cause signal reflection and superposition, resulting in overshoot, oscillation, and ringing near the rising edge. Since gateway devices typically use a fixed threshold for rising edge triggering, ringing can cause the same rising edge to repeatedly cross the threshold, leading to a non-unique trigger time and timestamp jumps between multiple possible arrival times. This manifests as a sudden increase in jitter and an abnormal statistical distribution. Existing jitter detection methods often assume that each symbol edge generates only one stable trigger. When multiple threshold crossings occur, the detection results may mistakenly interpret the trigger uncertainty caused by reflected ringing as jitter from the clock or timing source itself, thus amplifying the jitter assessment. Furthermore, if subsequent quality assessments are based solely on jitter statistics, it will be difficult to distinguish between a true decline in time synchronization quality and triggering anomalies caused by link reflection ringing. This can easily lead to false alarms or false access, thereby affecting the reliability and stability of the time synchronization provided by the gateway device.

[0005] Therefore, a method, system, and device for IRIG-B timing jitter detection and calibration based on an X86 gateway are proposed to solve the aforementioned problems. Summary of the Invention

[0006] Technical problems to be solved To address the aforementioned shortcomings of existing technologies, this invention provides an IRIG-B timing jitter detection and calibration method, system, and apparatus based on an x86 gateway device. This effectively solves the technical problem in existing general-purpose processor architecture gateway devices that, when receiving IRIG-B codes, experience signal reflection and ringing, causing the same edge to cross multiple times near a fixed threshold, thus being misjudged as timing jitter. This achieves the technical objective of accurately distinguishing between actual timing quality degradation and link physical anomalies, thereby improving the reliability of timing quality assessment.

[0007] Technical solution To achieve the above objectives, the present invention provides the following technical solution: This invention provides an IRIG-B timing jitter detection and calibration method based on an x86 gateway, the method comprising the following steps: S1: Sample the waveform of the input IRIG-B timing code signal to obtain the voltage waveform sample sequence and the corresponding time base sequence near each candidate rising edge; S2: Based on the voltage waveform sample sequence, identify the first monotonic rising interval of each candidate rising edge; S3: Based on the sample points and their time reference within the first monotonically rising interval, determine the threshold crossing time of the rising edge; S4: Based on the voltage waveform sample sequence, determine the number of state flips near the voltage threshold caused by reflected ringing; S5: Establish a calibration model. The input variables of the calibration model include the threshold crossing time, the effective slope of the edge determined based on the first monotonically rising interval, and the number of state flips. The output is the calibrated timestamp. S6: Solve for the parameters of the calibration model using the reference time base; S7: Based on the calibration model after solving the parameters, the threshold crossing time of each rising edge is compensated to obtain the calibrated timestamp sequence, and the linear trend is removed from the calibrated timestamp sequence to extract the residual sequence that represents the short-term jitter characteristics. S8: Calculate the jitter evaluation index based on the residual sequence; S9: Based on the number of state flips, calculate the triggering anomaly indicators caused by link reflection ringing; S10: Combine the jitter evaluation index and the triggering anomaly index to output the timing quality evaluation result.

[0008] Further, in step S3, determining the threshold crossing time of the rising edge includes: Within the first monotonically increasing interval, select M consecutive sampling points to form a set of fitting points; Based on the time coordinates and voltage values ​​of each sampling point within the set of fitted points, a least-squares linear fit is performed to obtain the slope. With intercept ; The formula for calculating the threshold crossing time is: In the formula, This is the estimated threshold crossing time for the k-th rising edge; This is the preset voltage threshold.

[0009] Furthermore, in step S3, before determining the threshold crossing time, the method further includes determining the effective slope of the edge. The steps include: S501: Within the stable voltage range after the rise edge is completed, determine the final plateau voltage of the rise edge. ; S502: Within the first monotonically increasing interval, filter those that meet the following conditions. The sampling points constitute the filtered set. ,in This is the filtered voltage value; S503: Based on the filtered set Time coordinates in With voltage transformation value Least squares linear fitting is performed to obtain the logarithmic domain parameters. and ; The formula for calculating the effective slope of the edge is: ; S505: Calculate the optimized threshold-crossing timestamp based on the logarithmic domain parameters and the platform final voltage, i.e.: In the formula, For threshold timestamps; When the preset consistency conditions are met, the threshold timestamp is used. As the threshold crossing time in step S3, and with the effective slope of the edge. As the effective slope of the edge in step S5; Otherwise, the threshold crossing time estimate calculated in claim 2 shall be used. As the threshold crossing time, and with a slope This refers to the effective slope of the edge in step S5.

[0010] Further, in step S4, determining the number of state flips includes: Based on the filtered voltage sequence With voltage threshold Generate a sequence of symbolic states, i.e.: In the formula, A sequence of symbolic states; For sign decision function; Within a fixed back window following the threshold crossing time, the number of state flips is calculated, i.e.: In the formula, For threshold flip count; To fix the rear window.

[0011] Further, in step S5, the calibration model is: ; In the formula, Use a fixed delay factor; The slope correlation coefficient; Ringing intensity coefficient; This is the calibrated timestamp.

[0012] Further, step S6 includes: S601: Obtain the reference time base corresponding to multiple rising edges ; S602: Based on the threshold crossing time estimate With the reference time base Calculate observation error ; S603: Construct the regression feature vectors corresponding to the multiple rising edges. With observation error vector And form a regression matrix ; S604: Solving for the calibration coefficient vector using the least squares method : In the formula This represents the calibration coefficient vector obtained through least squares estimation, i.e.: .

[0013] Further, in step S7, the removal of linear trends and extraction of residual sequences includes: For the calibrated timestamp sequence Performing least-squares linear fitting yields results that satisfy... The long-term trend parameter; where, This is the equivalent phase offset within the window; This represents the equivalent average step size within the window. Calculate jitter residuals based on parameter vectors .

[0014] Further, in step S8, the jitter evaluation metric includes the root mean square jitter calculated based on the residual sequence. Peak-to-peak jitter The calculation formula is: ; In step S9, the triggering anomaly indicator includes the multiple threshold crossing rate. Number of state flips The calculation formula is: In the formula, This is an indicator function.

[0015] An IRIIG-B timing jitter detection and calibration system based on an x86 gateway, the system includes: The signal access and acquisition module is used to stably connect external IRIG-B signals to the gateway and complete the synchronous sampling of waveforms and local time base, providing raw observation data for subsequent processing; The edge modeling and timestamp extraction module is used to extract the arrival time of each rising edge at the threshold from the sampled waveform, eliminating the systematic deviation caused by the nonlinearity of the edge shape, so as to obtain a timestamp with higher physical consistency. The multiple threshold detection and risk characterization module is used to detect and quantify the phenomenon of signals repeatedly crossing the voltage threshold due to reflected ringing, transforming this physical problem into a calculable index to distinguish it from real jitter. The calibration participation online compensation module is used to solve the compensation coefficient of systematic time deviation during the calibration phase and to perform real-time compensation for each newly extracted timestamp during the operation phase in order to remove fixed delay, slope-related walk and ringing-related deviations. The jitter calculation and quality output module is used to perform trend elimination and statistical calculation on the calibrated timestamp sequence, output jitter quantification indicators, and combine them with link risk indicators to form a comprehensive quality assessment result.

[0016] An IRIG-B timing jitter detection and calibration device based on an X86 gateway, the device includes: The signal input and conditioning unit is used to receive external IRIG-B signals and perform electrical adaptation, protection and filtering. The sampling and timestamp unit is connected to the signal access and conditioning unit and is used to sample the processed signal and mark the sampling points with timestamps based on the local clock. A data processing unit is connected to the sampling and timestamp unit. The data processing unit includes a memory and one or more processors. The memory stores a computer program that, when executed by the one or more processors, causes the device to implement the method as described in any one of claims 1-8. A communication interface, connected to the data processing unit, is used to output the timing quality assessment result.

[0017] Beneficial effects The technical solution provided by this invention has the following advantages compared with the prior art: This invention does not employ the conventional method of using a fixed voltage threshold comparator to trigger and obtain the edge arrival time. Instead, it first captures the complete voltage waveform sequence and its corresponding time axis near each candidate rising edge at a high sampling rate. Next, by analyzing this waveform sequence, it actively identifies the first monotonic rising interval to avoid ringing back segments caused by signal reflection. Finally, within this robust interval, the true threshold crossing time is extrapolated using linear or exponential model fitting. This method fundamentally changes the timestamp generation mechanism, effectively resisting ringing interference caused by link impedance mismatch and preventing multiple triggering times from the same physical edge crossing the threshold multiple times. This eliminates the spurious jitter introduced at the source, resulting in a more accurate and stable original timestamp, laying the foundation for subsequent high-precision calibration.

[0018] Furthermore, by defining and calculating the threshold-crossing count—that is, the number of times the filtered voltage signal oscillates around the threshold within a fixed time window after the threshold is crossed—this metric directly quantifies the intensity of signal reflection ringing. While physically closely related to timestamp fluctuations, they are mathematically independent. This provides the system with an observational dimension that directly reflects the physical health of the link (such as impedance matching and termination status). This allows the scheme to distinguish between real-time jitter caused by instability in the timing source itself and triggering time uncertainty caused by poor signal transmission links, achieving accurate fault location and avoiding misdiagnosis of link problems as clock quality issues.

[0019] Furthermore, a comprehensive timestamp calibration model was constructed. This model not only compensates for the fixed delays in the link and processing stages but also innovatively introduces a compensation term inversely proportional to the effective slope of the edge to eliminate systematic deviations caused by edge shape changes, and a compensation term proportional to the over-threshold flip count to actively counteract trigger time wandering caused by ringing. Subsequently, by introducing a reference time base, the optimal calibration coefficient vector is solved in one go using the least squares method. This model can systematically and adaptively isolate various deterministic deviations, attributing the residuals in the calibrated timestamp sequence mainly to real random jitter, thereby significantly improving the accuracy and reliability of subsequent jitter evaluation results and ensuring that the evaluation conclusions truly reflect the quality of the time signal source.

[0020] Finally, while calculating traditional time jitter metrics, link anomaly metrics generated by creation point two are also statistically analyzed in parallel. Ultimately, these two types of metrics are combined to form a comprehensive quality assessment set. This provides a multi-dimensional diagnostic report: operations and maintenance personnel can not only see the magnitude of the jitter but also simultaneously see if there are link problems and their severity. This greatly enhances the observability and maintainability of the system, elevating the assessment of gateway device timing performance from a single, vague jitter value to a comprehensive and accurate status profile, effectively supporting fault diagnosis, preventative maintenance, and system optimization decisions. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0022] Figure 1 This is a schematic diagram of the IRIG-B timing jitter detection and calibration method in an embodiment of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0024] The present invention will be further described below with reference to embodiments.

[0025] Example 1: See appendix Figure 1 This paper proposes an IRIG-B timing jitter detection and calibration method based on an X86 gateway, which includes the following steps: S1; Synchronously acquire and process the IRIG-B timing code input signal and local acquisition time base established by the intermodulation rangefinder group to obtain the raw observation data required for subsequent detection and calibration, and retain edge morphology information. Specifically: S101: With a preset sampling period Collect the voltage sequence near each candidate rising edge, i.e.: In the formula, This represents the input voltage amplitude corresponding to the nth sampling point within the acquisition window near the kth candidate rising edge; it is used to preserve edge morphology, including rising slope, overshoot, sway, ringing, etc., to provide the original basis for subsequent robust threshold estimation and multiple threshold identification; k is the index number of the candidate rising edge; n is the index number of the sampling point within the sampling period; This indicates the total number of sampling points contained in a single sampling period.

[0026] Simultaneously record the local time of the corresponding sampling point, that is: In the formula, This represents the time stamp corresponding to the nth sampling point within the acquisition window near the kth candidate rising edge under the local time reference of the gateway. It is used to convert the voltage sample into a calculable object of voltage change over time, so that the edge arrival time can be estimated and jitter measurement and calibration can be performed subsequently. This represents the time stamp of the starting point of the acquisition window near the k-th candidate rising edge in the local time base. It is used to provide the time anchor point of the window and ensure that the time coordinates of all sampling points within the window can be traced back to the same local time base. This represents the time increment from the start of the acquisition window to the nth sampling point.

[0027] And record the voltage threshold used to determine whether the threshold has been exceeded. This is used to define the criteria for edge arrival and serves as a benchmark reference for subsequent threshold estimation and multiple threshold statistics.

[0028] S102: Perform linear time-invariant filtering on the voltage sequence to obtain the filtered voltage sequence. , represents the filtered amplitude corresponding to the nth sampling point within the acquisition window near the kth candidate rising edge; it is used as the input waveform for all subsequent calculations to suppress noise and non-target frequency band interference, enhance the stability of edge morphology, and thus improve the reliability and consistency of threshold estimation and multiple threshold detection results.

[0029] S2: The acquired edge segments are processed for trend and effective rising segment identification to pinpoint the stable interval that best represents the arrival of the true edge, thereby reducing reflection ringing interference. Specifically: S201: Calculates the discrete derivative based on the filtered voltage sequence to locate the first monotonically rising segment, i.e.: In the formula, This represents the voltage increment between two adjacent sampling points, used to explicitly indicate whether the waveform is rising / falling, thus distinguishing the rising edge segment from the ringing swing segment; when When, it indicates that the voltage is rising within that sampling interval; when When the voltage drops within the sampling interval, it indicates that the voltage is decreasing, usually caused by ringing or noise.

[0030] S202: Find the earliest index within a time window that satisfies monotonically increasing conditions for subsequent consecutive L points based on voltage increments. Specifically: At a certain starting point Then, it is required that L consecutive voltage increments be positive, that is: ; And the earliest one that meets the conditions As a candidate for the initial upward segment, that is: In the formula, This represents the sampling point index of the first monotonically rising segment of the k-th candidate rising edge.

[0031] S3: Robustly estimate the arrival time of the locked valid edge intervals to obtain unique and repeatable edge timestamps for jitter calculation and time alignment. Specifically; S301: Based on the earliest index that satisfies monotonically increasing conditions Select the set of rising edges to fit, that is: In the formula, The set of sampling point indices for the k-th candidate rising edge used for local linear fitting is used to limit the range of data involved in the fitting, so that the fitting only focuses on the first monotonically rising segment and avoids being contaminated by subsequent ringing segments; M represents the fitting window length, that is, the number of sampling points involved in the fitting, used to adjust the trade-off between robustness and locality; the more points, the more noise-resistant, but the more likely to include nonlinearity or ringing; the fewer points, the closer to the local, but the more sensitive to noise.

[0032] S302: Based on the rising edge fitting set, the sampling point indices are uniformly mapped to the true time axis to robustly characterize the rising edge trend and suppress noise and ringing interference, i.e., let ;in This represents the time coordinate corresponding to the sampling point with index n within the k-th candidate rising edge. It is used to place each sampling point on the real time axis so that subsequent linear fitting of voltage and time and inverse calculation of threshold time can be performed.

[0033] S303: Based on the time coordinates within the rising edge fitting set and the filtered voltage sequence, least-squares linear fitting is performed to obtain linear model parameters. These parameters are used to inversely calculate the threshold crossing time to form a stable timestamp and provide input features for subsequent jitter detection and calibration modeling; that is: In the formula, The slope of the fitted line is used to characterize the local climbing speed along the rising edge and to inversely solve for the threshold crossing time. The intercept of the fitted straight line is used to characterize the baseline bias of the local linear model on the time axis and is used to inversely solve for the threshold crossing time; that is: In the formula, This represents the mean of the time samples within the fitted set at the rising edge. It is used to center the time and improve the stability of the least squares slope calculation. ; The mean of the voltage samples within the set is fitted to the rising edge, used to center the voltage, and to calculate the slope and intercept; that is: .

[0034] S304: Calculate the threshold crossing time estimate based on the slope and intercept, which is used as the timestamp of the rising edge, i.e.: In the formula, This is the estimated threshold crossing time of the kth rising edge, representing the time point at which the kth rising edge reaches the threshold voltage.

[0035] S4: Statistical analysis of crossing behavior near the edge threshold yields a strength index indicating that ringing caused by reflections is not unique, reflecting the degree of physical anomalies in the link. Specifically: S401: Define a symbol sequence near the voltage threshold, discretizing the positional relationship of the continuous voltage waveform relative to the decision threshold into a state sequence above or below the threshold, thereby transforming the threshold-crossing behavior into a stable statistical event; that is: In the formula, The state sequence represents the upper and lower states of the k-th rising edge at the n-th sampling point relative to the voltage threshold. It is used to count the number of state flips caused by threshold crossing, so as to quantify the intensity of multiple threshold crossings caused by ringing and support jitter calibration and quality assessment. This is a symbolic decision function used to map the positive and negative relationships of the input into discrete states.

[0036] S402: Based on the state sequence within a fixed window after the rising edge, calculate the number of sign flips to quantify the degree of repeated threshold crossings caused by ringing and reflection near the voltage threshold on the same rising edge, transforming the physical phenomenon of non-unique triggering into a calculable frequency index; that is: In the formula, The threshold-crossing flip count represents the total number of symbol state flips occurring within a fixed back window on the k-th rising edge. It is used to identify and evaluate the intensity of pseudo-jitter caused by multiple threshold-crossings, thus providing a basis for timestamp calibration compensation and time synchronization quality assessment. This directly indicates the presence of multiple threshold crossings caused by ringing; For a fixed back window, it represents a set of sampling point indices selected after the threshold crossing time of the k-th rising edge. This is used to limit the statistical range and only count the threshold crossing flips related to ringing after the rising edge, avoiding the inclusion of changes before the rising edge or other edges.

[0037] S5: Decompose the timestamp deviation into a fixed delay term and an edge morphology-related term, and establish a calibration relationship to model and separate the pseudo-jitter component from the time observation. Define the pre-calibration timestamp as the threshold crossover time estimate. The calibrated timestamp is These are used to clearly define the uncompensated original edge reaching the observation reference and the unified standard timestamp after error compensation, which can be used for time synchronization output and performance evaluation. Then, based on the pre-calibration and post-calibration timestamps, a deviation model is established to obtain the calibration coefficient parameters used to calculate the compensation amount and achieve timestamp calibration, namely: In the formula, For fixed delay coefficient, there is a constant bias term that is independent of edge shape, used to compensate for the fixed time delay caused by link and processing, so that the timestamp is aligned with the reference time as a whole; The slope correlation coefficient represents the time walk compensation weight coefficient caused by the change in edge slope, which is used to map the systematic drift of the trigger moment caused by the speed of edge rise into a compensable time term; The ringing intensity coefficient represents the compensation weighting coefficient for the impact of multiple threshold crossings near the voltage threshold on time deviation. It is used to incorporate the risk of non-unique triggering caused by reflected ringing into the compensation amount, thereby reducing the impact of pseudo jitter on the timestamp.

[0038] In S3, although ringing-induced secondary threshold crossing has been avoided through monotonic segment selection, in the x86 gateway input link, due to the combined effects of ESD / limiting / isolation / termination networks and ADC front-end bandwidth limitations, the rising edge often approaches an exponential response or underdamped change rather than a nonlinear change, resulting in a non-zero waveform curvature near the threshold. Extrapolating the threshold intersection point using linear fitting at this time will produce a deterministic time deviation related to the threshold position. Furthermore, when temperature, power supply, or load changes cause the equivalent time constant to drift, this deviation will slowly vary with operating conditions. This, in turn, leads to problems in the calibration model. The system will be forced to absorb the system bias caused by such nonlinear edges, resulting in unstable calibration coefficients and poor generalization ability across operating conditions. At the same time, the environment-related slow drift and thick tail features are introduced into the final jitter residual, which raises the jitter index or drifts over time, thereby reducing the reliability of jitter detection and quality assessment conclusions.

[0039] Therefore, upon the arrival of each candidate rising edge, the final plateau value of the edge is robustly estimated from the waveform after the rise is completed, serving as a reference baseline. Then, within the first monotonically rising segment, the waveform is transformed according to the exponential edge characteristics and regressed to obtain the edge dynamic parameters. Subsequently, based on this model, the threshold crossing time is directly and analytically calculated, and the effective slope at the threshold is simultaneously calculated. Finally, the fit consistency is self-checked, and in abnormal cases, the model reverts to the original linear estimation to ensure continuous and stable output. The aim is to eliminate the systematic time bias caused by the nonlinear curvature of the edge due to input link bandwidth and the front-end network, making the threshold crossing timestamp and slope estimation more consistent with the real physical process, thereby improving the stability of subsequent calibration parameters and the consistency and reliability of jitter evaluation results. More specifically: S501: Within the same window, take the platform sample set located after the rise is completed and before the next structural change, to obtain reliable steady-state data in the interval where the rising edge has stabilized and the next change has not yet occurred; then calculate the final voltage of this edge based on the platform sample set, i.e.: In the formula, This represents the final voltage that the k-th rising edge should reach after it has finished rising. It is used as the final value reference for the edge model to support subsequent logarithmic transformation and analytical calculation of the threshold moment, and is also used to calculate the effective slope at the threshold. The median operator represents taking the median of all samples in the set. It is used to suppress the influence of ringing residue, overshoot slew, and occasional spike noise that may exist in the plateau segment on the final value estimation, making the final voltage more robust and repeatable. This is the platform's sample set.

[0040] S502: Based on the first monotonically increasing segment set selection in S2, satisfying... The points are used to avoid invalid points caused by overshoot / noise from ruining the exponential model fit; that is: In the formula, The first set of monotonically increasing segments serves as the initial candidate range. First, ensure that the samples come from the monotonically increasing intervals, and then perform further effectiveness screening based on this. This represents the set of the first monotonically increasing segments after the selection of the k-th edge, used to provide the effective range of sample points for subsequent logarithmic transformation and regression fitting.

[0041] S503: For each sampling point in the first monotonically rising segment set after filtering, take its natural logarithm and record the time coordinate corresponding to that sampling point, i.e.: In the formula, This represents the logarithm of the remaining voltage from the k-th edge at sample point n to the final value. This represents the time coordinate corresponding to the k-th edge at the n-th sample point.

[0042] S504: Based on the logarithmic fitting of the time coordinate corresponding to each sampling point in the first monotonically rising segment set after screening and the remaining voltage at that point to the final value, an exponential edge model is used to achieve a quantitative description of the waveform change process and subsequent time calculation; that is: In the formula, This represents the rate of change of the logarithm of the remaining voltage at the sample point n from the k-th edge to the final value over time. This represents the baseline level of the logarithmic value when the time reference is zero; its least squares solution is: In the formula, Represents all segments used for fitting in the k-th segment. The average time, i.e.: ; This indicates that among all sampling points used for fitting in the k-th segment... The average value, that is: .

[0043] S505: Based on the fitted logarithmic domain linear model parameters and The physical parameters of the exponential edge are converted, and the fitted straight line is restored to the magnitude term and dynamic speed index of the physical edge model, which are used for subsequent analysis to calculate the threshold crossing time and characterize the edge response speed; that is: In the formula, This represents the amplitude coefficient related to the initial deviation in the exponential edge model. It is used to restore the logarithmic domain fitting result to the original voltage domain exponential model, and to calculate the threshold crossover time for subsequent analysis. This represents the equivalent time constant of the rising edge, used to characterize edge dynamics such as fast / slow, bandwidth / front-end RCRC impact, and to improve the physical consistency of threshold crossing time estimation.

[0044] S506: Based on the exponential edge model, the threshold crossing time is analytically solved, outputting a more stable and curvature-bias-resistant threshold crossing timestamp for subsequent jitter detection and calibration; the exponential edge model is equivalent to: In the formula, This represents the instantaneous voltage at the rising edge of the input IRIG-B during continuous time t; Transform the event of exceeding the threshold into a constraint. ,in Let represent the instantaneous voltage at the threshold crossing time of the k-th rising edge of the input IRIG-B edge. Then: Therefore, we can conclude that: In the formula, This is the threshold timestamp.

[0045] S507: Calculate the effective slope at the threshold based on the threshold-crossing timestamp, used to provide a consistent, comparable, and physically meaningful local slope index for each rising edge at the threshold crossing point; that is, by differentiating from the exponential edge model, we can obtain: ; exist Use have to: In the formula, This represents the effective slope at the edge, i.e., the effective slope at the threshold.

[0046] S508: Calculates the logarithmic fitting residuals and residual energy based on the parameters of the logarithmic domain linear model. This is used to quantify the fit consistency of the exponential model and as a gating criterion to determine whether to backtrack to the linear method to ensure reliable output; that is: In the formula, This represents the logarithmic fit residual of the k-th edge at the n-th sampling point; It represents the mean squared value of the logarithmic domain fitting residual at the k-th edge.

[0047] S509: Quality gating is performed based on the rate of change of logarithmic values ​​over time, the logarithmic fitting residuals, and the residual energy, and the original linear method is reverted to in case of anomalies. exist If the exponential decay direction is incorrect, the process fails and reverts to the threshold crossing time estimate output in the original S3. and slope And calculate the calibrated timestamp; exist If the number of points is insufficient, it indicates that the data is not enough to support the fit, and the result is judged as a failure, reverting to the threshold crossing time estimate output in the original S3. and slope And calculate the calibrated timestamp; exist If the threshold is exceeded, it indicates that the logarithmic domain fitting residual is too large and the consistency is poor. The result is a failure, and the process reverts to the threshold crossing time estimate output in the original S3. and slope And calculate the calibrated timestamp; Otherwise, if none of the above are triggered, the result is considered successful, the result of the exponential method is retained, and the result is based on the threshold timestamp. and effective slope at the threshold Calculate the calibrated timestamp, i.e.:

[0048] S6: The parameters of the calibration relationship are solved and solidified using a reference time base to form calibration parameters that can be applied online, ensuring traceable consistency in the output timestamps. Specifically: S601: During the calibration phase, the reference time is obtained synchronously. The observation error is defined based on the pre-calibration timestamp and reference time, and is used as a dependent variable in the linear least squares solution to obtain the calibration coefficients and quantify the systematic time delay bias; that is: In the formula, The observation error represents the time difference between the arrival time of the k-th rising edge and the corresponding time at the reference time scale.

[0049] S602: Construct a regression feature vector for a single rising edge based on slope and over-threshold flip count, i.e.: In the formula, This is the regression feature vector, used to explain the observation error of the event and participate in subsequent matrix stacking.

[0050] S603: The regression matrix and observation error vector are obtained by stacking the regression eigenvectors of all rising edges and the set of observation errors, i.e.: In the formula, X is the regression matrix, and y is the observation error vector, which serves as the direct input for the least squares solution and is used to estimate the global calibration coefficients in one step. This is the transpose of the regression feature vector, which means converting the column vector into a row vector.

[0051] S604: Define the vector of calibration coefficients to be determined as follows: A linear regression relationship is established based on the calibration coefficient vector, the regression matrix, and the observation error vector, i.e. .

[0052] S605: Calculates the calibration coefficients in the linear regression relationship based on least squares, i.e.: In the formula, This represents the analytical solution of ordinary least squares under the condition of invertibility, which is used as the final calibration parameter to compensate and correct timestamps during operation, reducing the impact of systematic bias and pseudo-jitter; where This represents the calibration coefficient vector obtained through least squares estimation, i.e.: .

[0053] S606: Generates a calibrated timestamp in real time for each new rising edge event based on the output calibration coefficient vector. and output the calibrated timestamp sequence. .

[0054] S7: Perform long-term trend removal on the calibrated timestamp sequence and extract the residuals to obtain an error sequence that mainly reflects short-term jitter characteristics for objective evaluation. Specifically: S701: A linear fit is performed on the calibrated timestamp sequence based on the index number of the candidate rising edge. This extracts and removes any slow-changing components still present in the calibrated timestamp sequence, ensuring that subsequent jitter calculations only reflect short-term, rapid fluctuations and are not contaminated by frequency offset or slow drift. That is: In the formula, This is the equivalent phase offset within the window, used to absorb the overall constant offset, so that the residual is not affected by the fixed phase offset; It is the equivalent average step size within the window, used to characterize and remove linear drift caused by frequency offset or slow drift, so that the residual mainly retains short-term jitter.

[0055] S702: Rewrite the linear trend model in scalar form into a unified matrix form, i.e.: In the formula, This represents a column vector composed of all observed calibrated timestamp samples in order, used as the target data for fitting, enabling the model to approximate and extract the long-term trend component; that is: A represents the design matrix consisting of known independent variables. Each row corresponds to a sample model structure, used to organize the intercept term and the linear term that varies with the sample index, etc., so that the parameter estimates can be uniformly solved using linear least squares, i.e.: ; This represents the parameter vector to be estimated, used to characterize and quantify the long-term drift, so that the residuals can be calculated to obtain the pure jitter sequence; that is: .

[0056] S703: Solving the parameter vector based on least squares, i.e.: The final output is a parameter vector used to equivalently describe long-term drift.

[0057] S704: Calculates jitter residuals based on parameter vectors, used to construct pure jitter sequences and calculate jitter indices and time synchronization quality assessments, reflecting the level of short-term random time series fluctuations; that is: In the formula, The jitter residual is the pure jitter bias value after removing slow drift. It is used to make the long-term drift model more representative of the real slow drift, rather than being contaminated by occasional triggering anomalies or outliers.

[0058] S8: Summarize and calculate the jitter residuals and output key jitter indicators to form comparable and reportable timing jitter detection results to support equipment status determination; that is: In the formula, The root mean square jitter of the residual sequence is used to characterize the overall jitter level and is suitable for continuous quality tracking and calibration effect comparison. Peak-to-peak jitter is used to reflect the maximum amplitude of jitter within the statistical window. It is sensitive to outliers and facilitates the detection of occasional anomalies. This indicates that the maximum value of the quantity in parentheses is taken over all sample index k. It is used to find the latest deviation within the observation window, i.e., the maximum positive deviation, which reflects the worst-case upward deviation. This indicates that the minimum value of the quantity in parentheses is taken over all sample sequence numbers k. This is used to find the earliest deviation within the observation window, i.e., the maximum negative deviation, which reflects the worst-case downbias.

[0059] S9: Statistical analysis of the occurrence and intensity of reflected ringing-related indicators reveals the persistence and severity of the non-uniqueness of link triggering issues from a quality perspective; that is: In the formula, This indicates the occurrence rate of multiple threshold-crossing events throughout the entire observation period. It is used to quantify how frequently the physical problem occurs and serves as input for quality assessment and alarm threshold criteria. This is an indicator function that represents a binary judgment result. It takes one when the threshold flip count of the k-th rising edge is greater than one, and zero otherwise. This represents the average number of threshold flips for a single edge during the entire observation period. It is used to quantify the average level of the overall severity of multiple threshold flips and to help determine the impact of link reflection ringing on trigger stability.

[0060] S10: Combine jitter metrics with link anomaly metrics to form a quality assessment output, used to distinguish between actual time synchronization quality changes and measurement distortion caused by link physical problems, and to guide subsequent operation and maintenance and optimization, i.e., output a set of quality assessment results. .

[0061] Example 2: Based on Example 1, this paper proposes an IRIG-B timing jitter detection and calibration system based on an X86 gateway, including a signal access and acquisition module, an edge modeling and timestamp extraction module, a multiple threshold detection and risk characterization module, a calibration participation online compensation module, and a jitter calculation and quality output module. Among them: The signal access and acquisition module is used to stably connect the external IRIG-B timing signal to the x86 gateway and complete the synchronous acquisition of waveforms and the local time base. First, necessary electrical adaptation and protection are performed on the input signal. Then, window sampling is performed near the rising edge of each candidate symbol to obtain the voltage sequence and sampling time axis, while retaining threshold information and sampling configuration. This provides reproducible raw observations for subsequent edge modeling and ensures that each edge event has a corresponding time base, reducing the uncertainty introduced by the acquisition link from the source.

[0062] The edge modeling and timestamp extraction module is used to extract the arrival time of each rising edge at a threshold from the sampled waveform, and to minimize systematic biases caused by nonlinear edge shapes. It first locates the initial monotonically rising segment within a window to avoid ringing back segments. Then, it prioritizes logarithmic linearization fitting of exponential edges to estimate the final plateau value and edge parameters, analytically solving for the threshold crossing time and calculating the effective slope at the threshold. When the fitting consistency is not satisfied, it falls back to local linear fitting to ensure continuous and usable output. This is used to obtain more physically consistent timestamp and slope characteristics, avoiding misjudging front-end bandwidth limitations and curvature errors as jitter.

[0063] The multiple threshold crossing detection and risk characterization module is used to characterize the multiple threshold crossing problem caused by reflected ringing, in order to distinguish pseudo jitter from real jitter. It maps the waveform to a symbol sequence near a threshold and counts the number of symbol flips within a fixed back window after the threshold is crossed, obtaining the threshold crossing flip count for each edge. Simultaneously, it accumulates and calculates the occurrence rate and average intensity of multiple threshold crossings over time. By describing the link health status with computable and directly physical-problem-related features, it provides an independent dimension for calibration and quality assessment, avoiding misjudgments based solely on jitter statistics.

[0064] The calibration participation online compensation module is used to separate systematic time deviations from timestamps, forming a calibration output that can operate stably over the long term. By introducing a reference timescale during the calibration phase, a linear model is constructed with constant terms, the reciprocal of the effective slope, and the threshold flip count as independent variables. The calibration coefficients are solved using least squares. During the runtime phase, online compensation is performed on each newly extracted timestamp, outputting a calibrated timestamp sequence. By simultaneously compensating for fixed delays, slope-related time walks, and systematic deviations related to multiple threshold flips, subsequent jitter calculations primarily reflect true time synchronization stability rather than link artifacts.

[0065] The jitter calculation and quality output module converts calibrated timestamps into jitter results and quality conclusions, providing external interfaces and recording capabilities. It obtains the time interval error residual by removing linear slow drift from the calibrated timestamp sequence, then calculates the root mean square (RMS) and peak-to-peak (peak-to-peak) jitter metrics, and jointly outputs the multiple threshold crossing rates and average intensity to form a comprehensive quality set. Finally, the results are reported or stored to support alarm, traceability, and maintenance decisions. Ultimately, it provides a closed-loop output that can be used for both timing performance quantification and link physical risk diagnosis, giving the system calibrable, evaluable, and maintainable engineering attributes.

[0066] Example 3: Based on Embodiments 1 and 2, this application proposes an IRIG-B timing jitter detection and calibration device based on an X86 gateway, the device comprising: The chassis structure is used to install and secure various boards and cables, provide electromagnetic shielding and grounding reference, and carry power distribution and high-speed interconnect channels; The IRIG-B input interface and protection termination unit includes an external connector, surge and electrostatic protection devices, a limiting and DC blocking network, and a configurable termination resistor network, used to safely introduce external IRIG-B signals and form controllable load conditions. The analog conditioning and threshold decision unit includes a bandwidth-controlled buffer amplification, anti-aliasing filter, threshold reference and comparator, outputs a clean threshold decision signal, and retains the analog observation path for edge modeling. The high-speed sampling and timestamp hardware unit consists of an analog-to-digital converter and timestamp logic. The timestamp logic can be implemented using programmable logic devices and internally includes sampling clock allocation, edge window capture, window data buffering required for exponential edge fitting, hardware counter, and time stamp register. The local high-stability clock and reference input unit includes a local oscillator and clock distribution circuit, and provides an external reference input port for introducing a reference time scale during the calibration stage, providing a unified time base to the timestamp hardware; The X86 gateway motherboard and data interface unit, including processor, memory, storage and high-speed peripheral interfaces, are used to carry algorithm flow, calibration parameter calculation, jitter statistics and quality assessment, and provide external communication interfaces such as Ethernet for result reporting and operation and maintenance management. The power supply and monitoring unit includes input power conversion, analog and digital partitioned voltage regulation, power-on timing control and voltage and temperature monitoring to ensure stable operating conditions for the threshold reference, sampling and clock.

[0067] After the external IRIG-B signal enters the device through the input connector, it is connected to the protection termination unit in sequence, and then enters the analog conditioning and threshold decision unit. The analog conditioning unit outputs two internal signals in parallel to the high-speed sampling and timestamp hardware unit.

[0068] One path is for the analog observation signal used for sampling modeling, which is then input to the analog-to-digital converter. The other path is the threshold decision digital signal output by the comparator, which is then used as the trigger input for the timestamp logic. The high-speed sampling and timestamp hardware unit is connected to the X86 gateway motherboard via a high-speed interconnect on the backplane, providing the motherboard with intermediate quantities and status information such as window waveform data, timestamp register values, and effective slope.

[0069] The local high-stability clock unit provides the sampling clock to the analog-to-digital converter (ADC) and simultaneously provides the counting clock and synchronization signal to the timestamp logic. If an external reference input is connected, the reference time stamp is sent to the timestamp logic or the motherboard interface for reference alignment during the calibration parameter calculation phase. The power supply and monitoring unit supplies power to the analog conditioning, threshold reference, sampling and logic, and motherboard respectively, and sends voltage and temperature status data to the motherboard for health monitoring and quality assessment assistance. The x86 gateway motherboard outputs calibrated timestamps, jitter metrics, and quality sets via Ethernet and other interfaces, and supports the issuance of control commands such as configuration termination mode, threshold parameters, sampling window, and calibration mode. When necessary, the device also provides a maintenance interface for firmware upgrades and log export.

[0070] When the device is running, the input interface and protection termination unit first electrically stabilizes the external IRIG-B signal and suppresses abnormal energy. The analog conditioning and threshold decision unit forms a sampleable edge pattern and a stable threshold decision output under controlled bandwidth.

[0071] The high-speed sampling and timestamp hardware unit samples and buffers the rising edge window using a unified time base, and prepares the data required for edge segment localization and fitting based on the window data. It generates features such as threshold crossing timestamp and effective slope, and at the same time, it statistically analyzes the original decision sequence required for the flip behavior near the threshold.

[0072] The x86 gateway motherboard receives the timestamps and feature values ​​sent by the hardware, performs calibration to participate in online compensation, obtains the calibrated timestamp sequence, then completes the jitter residual calculation after slow drift removal and outputs the jitter index, and gives a quality conclusion based on the occurrence rate and intensity of multiple threshold crossings.

[0073] The power supply and monitoring unit are integrated throughout the entire process, providing assurance for simulation thresholds, sampling, and time base stability, and using environmental and power supply status as auxiliary criteria for quality assessment, thereby forming a closed-loop physical device working system that is detectable, calibrable, and evaluable.

[0074] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for detecting and calibrating IRIG-B timing jitter based on an X86 gateway, characterized in that, The method includes the following steps: S1: Sample the waveform of the input IRIG-B timing code signal to obtain the voltage waveform sample sequence and the corresponding time base sequence near each candidate rising edge; S2: Based on the voltage waveform sample sequence, identify the first monotonic rising interval of each candidate rising edge; S3: Based on the sample points and their time reference within the first monotonically rising interval, determine the threshold crossing time of the rising edge; S4: Based on the voltage waveform sample sequence, determine the number of state flips near the voltage threshold caused by reflected ringing; S5: Establish a calibration model. The input variables of the calibration model include the threshold crossing time, the effective slope of the edge determined based on the first monotonically rising interval, and the number of state flips. The output is the calibrated timestamp. S6: Solve for the parameters of the calibration model using the reference time base; S7: Based on the calibration model after solving the parameters, the threshold crossing time of each rising edge is compensated to obtain the calibrated timestamp sequence, and the linear trend is removed from the calibrated timestamp sequence to extract the residual sequence that represents the short-term jitter characteristics. S8: Calculate the jitter evaluation index based on the residual sequence; S9: Based on the number of state flips, calculate the triggering anomaly indicators caused by link reflection ringing; S10: Combine the jitter evaluation index and the triggering anomaly index to output the timing quality evaluation result.

2. The IRIG-B timing jitter detection and calibration method based on an X86 gateway as described in claim 1, characterized in that, In step S3, determining the threshold crossing time of the rising edge includes: Within the first monotonically increasing interval, select M consecutive sampling points to form a set of fitting points; Based on the time coordinates and voltage values ​​of each sampling point within the set of fitted points, a least-squares linear fit is performed to obtain the slope. With intercept ; The formula for calculating the threshold crossing time is: In the formula, This is the estimated threshold crossing time for the k-th rising edge; This is the preset voltage threshold.

3. The IRIG-B timing jitter detection and calibration method based on an X86 gateway as described in claim 2, characterized in that, In step S3, before determining the threshold crossing time, the method further includes determining the effective slope of the edge. The steps include: S501: Within the stable voltage range after the rise edge is completed, determine the final plateau voltage of the rise edge. ; S502: Within the first monotonically increasing interval, filter those that meet the following conditions. The sampling points constitute the filtered set. ,in This is the filtered voltage value; S503: Based on the filtered set Time coordinates in With voltage transformation value Least squares linear fitting is performed to obtain the logarithmic domain parameters. and ; The formula for calculating the effective slope of the edge is: ； S505: Calculate the optimized threshold-crossing timestamp based on the logarithmic domain parameters and the platform final voltage, i.e.: In the formula, For threshold timestamps; When the preset consistency conditions are met, the threshold timestamp is used. As the threshold crossing time in step S3, and with the effective slope of the edge. As the effective slope of the edge in step S5; Otherwise, the threshold crossing time estimate calculated in claim 2 shall be used. As the threshold crossing time, and with a slope This refers to the effective slope of the edge in step S5.

4. The IRIG-B timing jitter detection and calibration method based on an X86 gateway according to any one of claims 1-3, characterized in that, In step S4, determining the number of state flips includes: Based on the filtered voltage sequence With voltage threshold Generate a sequence of symbolic states, i.e.: In the formula, A sequence of symbolic states; For sign decision function; Within a fixed back window following the threshold crossing time, the number of state flips is calculated, i.e.: In the formula, For threshold flip count; To fix the rear window.

5. The IRIG-B timing jitter detection and calibration method based on an X86 gateway according to any one of claims 1-4, characterized in that, In step S5, the calibration model is: ； In the formula, Use a fixed delay factor; The slope correlation coefficient; Ringing intensity coefficient; This is the calibrated timestamp.

6. The IRIG-B timing jitter detection and calibration method based on an X86 gateway as described in claim 5, characterized in that, Step S6 includes: S601: Obtain the reference time base corresponding to multiple rising edges ; S602: Based on the threshold crossing time estimate With the reference time base Calculate observation error ; S603: Construct the regression feature vectors corresponding to the multiple rising edges. With observation error vector And form a regression matrix ; S604: Solving for the calibration coefficient vector using the least squares method : In the formula This represents the calibration coefficient vector obtained through least squares estimation, i.e.: .

7. The IRIG-B timing jitter detection and calibration method based on an X86 gateway according to any one of claims 1-6, characterized in that, In step S7, removing the linear trend and extracting the residual sequence includes: For the calibrated timestamp sequence Performing least-squares linear fitting yields results that satisfy... The long-term trend parameter; where, This is the equivalent phase offset within the window; This represents the equivalent average step size within the window. Calculate jitter residuals based on parameter vectors .

8. The IRIG-B timing jitter detection and calibration method based on an X86 gateway according to any one of claims 1-7, characterized in that, In step S8, the jitter evaluation metric includes the root mean square jitter calculated based on the residual sequence. Peak-to-peak jitter The calculation formula is: ； In step S9, the triggering anomaly indicator includes the multiple threshold crossing rate. Number of state flips The calculation formula is: In the formula, This is an indicator function.

9. An IRIG-B timing jitter detection and calibration system based on an X86 gateway, characterized in that, The system includes: The signal access and acquisition module is used to stably connect external IRIG-B signals to the gateway and complete the synchronous sampling of waveforms and local time base, providing raw observation data for subsequent processing; The edge modeling and timestamp extraction module is used to extract the arrival time of each rising edge at the threshold from the sampled waveform, eliminating the systematic deviation caused by the nonlinearity of the edge shape, so as to obtain a timestamp with higher physical consistency. The multiple threshold detection and risk characterization module is used to detect and quantify the phenomenon of signals repeatedly crossing the voltage threshold due to reflected ringing, transforming this physical problem into a calculable index to distinguish it from real jitter. The calibration participation online compensation module is used to solve the compensation coefficient of systematic time deviation during the calibration phase and to perform real-time compensation for each newly extracted timestamp during the operation phase in order to remove fixed delay, slope-related walk and ringing-related deviations. The jitter calculation and quality output module is used to perform trend elimination and statistical calculation on the calibrated timestamp sequence, output jitter quantification indicators, and combine them with link risk indicators to form a comprehensive quality assessment result.

10. An IRIG-B timing jitter detection and calibration device based on an X86 gateway, characterized in that, The device includes: The signal input and conditioning unit is used to receive external IRIG-B signals and perform electrical adaptation, protection and filtering. The sampling and timestamp unit is connected to the signal access and conditioning unit and is used to sample the processed signal and mark the sampling points with timestamps based on the local clock. A data processing unit is connected to the sampling and timestamp unit. The data processing unit includes a memory and one or more processors. The memory stores a computer program that, when executed by the one or more processors, causes the device to implement the method as described in any one of claims 1-8. A communication interface, connected to the data processing unit, is used to output the timing quality assessment result.

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