Bus traffic control method, traffic control platform, device, medium and product

Abstract

The present disclosure provides a bus flow control method, a flow control platform, a device, a medium and a product. The flow control platform is applied to a flow control platform in a system on chip. The flow control platform comprises a plurality of cache units. The system on chip further comprises a first master and a memory. At least one service instruction sent by the first master is received. Each service instruction in the at least one service instruction is cached in a cache unit. When a transmission window of the at least one cache unit is opened, the service instruction cached in the at least one cache unit is sent to the memory, so that the memory executes each service instruction. Thus, the differentiated isolation and ordered scheduling of different service flows are realized. The cache resource contention and transmission conflict caused by mixed flow of multiple service instructions are avoided. The memory page switching is reduced. The memory bandwidth utilization is significantly improved.

Description

Technical Field

[0001] This disclosure relates to flow control technology, and in particular to bus flow control methods, flow control platforms, devices, media and products. Background Technology

[0002] The Advanced Extensible Interface (AXI) bus is a widely used bus standard in high-performance embedded systems, supporting concurrent transmission between multiple masters and slaves. With the increasing integration of System-on-Chips (SoCs), the demand for concurrent memory access by multiple services such as general computing, AI acceleration, and data transmission within a single system is growing. Different services vary significantly in terms of data block size, transmission frequency, and latency requirements. Currently, most AXI buses in SoCs employ a unified scheduling strategy, which leads to mixed traffic from multiple services, resulting in frequent page switching in memory. This causes memory resources to be contested by various services, increasing switching overhead and significantly reducing bandwidth utilization. Summary of the Invention

[0003] To address the aforementioned technical problems, embodiments of this disclosure provide a bus flow control method, flow control platform, device, medium, and product.

[0004] One aspect of this disclosure provides a bus flow control method applied to a flow control platform in a system-on-a-chip (SoC). The flow control platform includes multiple cache units, and the SoC further includes a first type of master terminal and a memory. The method includes: receiving at least one service instruction sent by the first type of master terminal; caching each service instruction in the at least one service instruction into a cache unit; and when the transmission window of the at least one cache unit is open, sending the cached service instructions in the at least one cache unit to the memory, so that the memory executes each service instruction.

[0005] In another aspect of this disclosure, a flow control platform is provided, which is deployed in a system-on-a-chip (SoC). The flow control platform includes multiple cache units, a traffic splitting module, and an output arbitration module. The SoC further includes a first type of master terminal and a memory. The traffic splitting module is used to receive at least one service instruction sent by the first type of master terminal and cache each service instruction into a cache unit. The output arbitration module is used to send the cached service instructions in the at least one cache unit to the memory when the transmission window of the at least one cache unit is open, so that the memory executes each service instruction.

[0006] In another aspect of this disclosure, an electronic device is provided, comprising: a memory for storing a computer program; and a processor for executing the computer program stored in the memory, wherein when the computer program is executed, it implements the bus flow control method described above.

[0007] In another aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, characterized in that, when the computer program is executed by a processor, it implements the bus flow control method of the above claim.

[0008] In another aspect, this disclosure provides a computer program product including computer program instructions, characterized in that the computer program instructions, when executed by a processor, implement the bus flow control method described above.

[0009] Based on bus flow control methods, flow control platforms, devices, media, and products, different service instructions are cached in independent cache units and sent in batches when the transmission window corresponding to each cache unit is open. This achieves differentiated isolation and orderly scheduling of different service traffic, avoids cache resource contention and transmission conflicts caused by mixed flow of multiple service instructions, reduces frequent page switching of memory, and significantly improves memory bandwidth utilization.

[0010] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0011] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0012] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein: Figure 1 This is a flowchart illustrating a bus flow control method provided in an exemplary embodiment of this disclosure.

[0013] Figure 2 This is a flowchart illustrating step S110 provided in an exemplary embodiment of this disclosure.

[0014] Figure 3 This is a flowchart illustrating a bus flow control method provided in another exemplary embodiment of this disclosure.

[0015] Figure 4 This is a schematic flowchart of a bus flow control method provided in an exemplary embodiment of the present disclosure.

[0016] Figure 5 This is a flowchart illustrating a bus flow control method provided in yet another exemplary embodiment of this disclosure.

[0017] Figure 6 This is a schematic diagram of a flow control platform deployed in a system-on-a-chip, as provided in an application example of this disclosure.

[0018] Figure 7This is a schematic diagram of the structure of the flow control platform provided in an application example of this disclosure.

[0019] Figure 8 This is a schematic diagram of the structure of a flow control platform provided in an exemplary embodiment of this disclosure.

[0020] Figure 9 This is a schematic diagram of the structure of an application embodiment of the electronic device disclosed herein. Detailed Implementation

[0021] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0022] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0023] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0024] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0025] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship.

[0026] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0027] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0028] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0029] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0030] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0031] The embodiments disclosed herein can be applied to electronic devices such as terminal devices, computer systems, and servers, and can operate together with a wide range of other general-purpose or special-purpose computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments, and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, and servers include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems, etc.

[0032] Electronic devices such as terminal devices, computer systems, and servers can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in distributed cloud computing environments, where tasks are executed by remote processing devices linked through communication networks. In distributed cloud computing environments, program modules can reside on local or remote computing system storage media, including storage devices.

[0033] In implementing the technology disclosed herein, research revealed that the current AXI bus employs a unified scheduling strategy, where all services within the system-on-a-chip share storage resources and sequentially output access commands to the memory according to a first-in, first-out rule. This approach leads to data transmission conflicts between services, contention for cache resources, frequent memory page switching, and a significant decrease in bandwidth utilization.

[0034] Figure 1 This is a schematic flowchart of a bus flow control method provided in an exemplary embodiment of this disclosure. This embodiment can be applied to flow control platforms in system-on-a-chip (SoC), such as... Figure 1 As shown, the bus flow control method may include the following steps: Step S100: Receive at least one service instruction sent by the first type of master terminal.

[0035] The flow control platform is used for differentiated scheduling and flow control of access instructions sent to memory. The flow control platform can be deployed in a system-on-a-chip (SoC). The SoC includes multiple masters and at least one memory. The multiple masters include a first type of master, which can be, for example, a central processing unit (CPU), a direct memory access controller (DMA controller), a graphics processing unit (GPU), or a video codec. The SoC also includes an AXI bus compliant with the AXI bus protocol. The memory can be, for example, dynamic random access memory (DRAM), static random access memory (SRAM), or flash memory.

[0036] The flow control platform includes multiple ID buffers. Each ID buffer is an independent storage space used to cache received service instructions. The flow control platform is connected in series on the AXI bus path between the first-type master terminal and the memory. Service instructions issued by the first-type master terminal are transmitted to the flow control platform via the AXI bus. After being cached, scheduled, and controlled by the flow control platform, the instructions are output to the memory.

[0037] The service instructions are read / write requests initiated by the first-type master terminal, transmitted via the AXI bus, and used to access memory. Service instructions can include write instructions and read instructions. Write instructions are used to write data into memory, specifically including write address control information and the data to be written. Write address control information includes, for example, write address, burst length, burst size, and burst type. Read instructions are used to read data from memory, specifically including read address control information, such as read address, burst length, burst size, and burst type. After a read instruction is issued, the memory returns the corresponding read data.

[0038] In one example, the first type of master initiates a service instruction and transmits it to the flow control platform via the AXI bus. The flow control platform then receives the service instruction transmitted via the AXI bus.

[0039] Step S110: Each business instruction in at least one business instruction is cached into a cache unit.

[0040] In one example, each business instruction can be randomly assigned to a cache unit for caching; alternatively, based on the number of instructions currently cached in each cache unit, each business instruction can be preferentially assigned to the cache unit with the fewest currently cached instructions; or, each business instruction can be distributed evenly and stored in each cache unit in a round-robin fashion.

[0041] In step S120, when the transmission window of at least one cache unit is opened, the cached service instructions in at least one cache unit are sent to the memory so that the memory executes each service instruction.

[0042] In this context, a transmission window refers to a periodic logical time slice independently configured for each cache unit, used to control the transmission of instructions from that cache unit to memory. Each cache unit has a unique corresponding transmission window, and the opening and closing of each transmission window are independent of each other. Specifically, when the transmission window of a cache unit is open, that cache unit is qualified to send service instructions to memory, and the service instructions cached within it are allowed to be sent to memory continuously and in batches; when the transmission window is closed, regardless of whether there are still cached service instructions in the cache unit, transmission will not continue until the next transmission window of the cache unit opens.

[0043] In this embodiment of the disclosure, by caching different service instructions into independent cache units and sending them in batches when the transmission window corresponding to each cache unit is open, differentiated isolation and orderly scheduling of different service traffic are achieved, avoiding cache resource contention and transmission conflicts caused by mixed flow of multiple service instructions, reducing frequent page switching of memory, and significantly improving memory bandwidth utilization.

[0044] Figure 2 This is a flowchart illustrating step S110 provided in an exemplary embodiment of this disclosure. In some alternative embodiments, such as Figure 2 As shown, step S110 may include the following steps: Step S111: For each business instruction, obtain the business type and operation type of the business instruction.

[0045] Each cache unit is configured with one service type and one operation type. The service type can be set according to actual business needs, and the operation type can include read instructions and write instructions. Each first-type master terminal identifies its own service type through a preset user bit value; for example, service type 0 corresponds to a user bit value of 0 (user=0), service type 1 corresponds to user=1, service type 2 corresponds to user=2, and so on. The service type of the first-type master terminal can be used to identify the service type of the business instruction initiated by that first-type master terminal. Correspondingly, the service type of the cache unit also uses the same user bit value.

[0046] For example, the service instruction integrates the user signal bit values ​​of the first type of master terminal that initiated the service instruction, which are transmitted on the AXI bus in the form of read / write control signals. The flow control platform may also include a service splitting module (Inputswitch), which is a one-to-many switch. The service splitting module is used to determine the service type and operation type matched by each service instruction. Specifically, the service splitting module can determine the service type of the service instruction by parsing the user signal bit values. The operation type of the instruction can be determined by identifying the AXI bus channel that receives the service instruction. If the service instruction is received through the read address channel on the AXI bus, it is determined to be a read instruction; if the service instruction is received through the write address channel on the AXI bus, it is determined to be a write instruction.

[0047] Step S112: Based on the service type and operation type of the service instruction, determine the cache unit that matches the service instruction.

[0048] In one example, the service routing module is also used to determine the cache unit that matches each service instruction. Specifically, the service routing module searches for a cache unit with the same service type and operation type from multiple cache units based on the service type and operation type of the service instruction, and uses it as the cache unit that matches the service instruction, and caches the service instruction in that cache unit.

[0049] Step S113: Cache the service instruction into the cache unit that matches the service instruction.

[0050] When the business instruction is a write instruction, the write address control information and the data to be written can be cached separately when storing the business instruction in the cache unit.

[0051] In this embodiment of the disclosure, by pre-setting the service type and operation type for each cache unit, and accurately matching each service instruction to the corresponding dedicated cache unit according to its service type and operation type, strict isolation of instructions of different services and different operation types in the cache space is achieved, avoiding the problem of cache resource contention caused by the mixing of multiple service instructions in the shared cache, and laying the foundation for subsequent windowed orderly scheduling and efficient utilization of memory bandwidth.

[0052] In some alternative implementations, such as Figure 2 As shown, before step S110, the following may be included: for each cache unit in at least one cache unit, in response to the interval between the current time and the last closing time of the transmission window of the cache unit reaching the window interval duration, the transmission window of the cache unit is opened.

[0053] Each cache unit is configured with an independent window interval duration, which can be set in units of system clock cycles in the system-on-a-chip (SoC). For example, the window interval duration can be N system clock cycles, where N is an integer greater than or equal to 1. For each cache unit, after the last time its transfer window was closed, the transfer window of that cache unit is reopened after the window interval period (i.e., N clock cycles).

[0054] In some optional implementations, step S120 in this embodiment of the present disclosure may include: during the opening of the transmission window of the cache unit, when the number of service instructions cached in the cache unit reaches the instruction number threshold, sending the service instructions cached in the cache unit to the memory, until the cumulative number of sent service instructions reaches the instruction number threshold, and then closing the transmission window of the cache unit.

[0055] Each buffer unit is configured with an instruction count threshold, which determines the number of instructions that the buffer unit is allowed to send consecutively within a single transmission window. Each buffer unit is also configured with a maximum outstanding depth, which represents the maximum number of pending service instructions that the buffer unit can simultaneously accommodate. For example, the maximum outstanding depth can be configured to 8 or 16.

[0056] In one implementation, an instruction quantity threshold can be set based on the maximum over-sending depth of the cache unit. For example, the instruction quantity threshold of the cache unit can be set to be less than or equal to the maximum over-sending depth of the cache unit. When the transmission window of the cache unit is open and the number of service instructions cached in the cache unit has reached the instruction quantity threshold, the cache unit obtains transmission permission and sends its internally cached service instructions to the memory in a continuous burst manner until the cumulative number of transmitted instructions reaches the instruction quantity threshold, and then closes the transmission window.

[0057] Accordingly, in this embodiment of the present disclosure, step S120 may further include: when the transmission window of the cache unit is open for a preset waiting time limit and the number of service instructions cached in the cache unit has not reached the instruction number threshold, suspend the current transmission and close the transmission window of the cache unit, and record it as a transmission failure.

[0058] In one example, the timer starts when the transmission window of the cache unit is opened. If the number of service instructions cached in the cache unit fails to accumulate to the instruction number threshold within the preset waiting time limit, the transmission opportunity is determined to be a failure. A transmission failure is recorded for the cache unit, and the operation of pausing transmission and closing the window is performed, that is, the service instructions cached in the cache unit are not sent, and the transmission window is closed.

[0059] Accordingly, in this embodiment of the present disclosure, step S120 may further include: when the number of consecutive failed transmissions of the cache unit reaches the timeout number, when the transmission window of the cache unit is reopened, sending the currently cached service instructions in the cache unit to the memory.

[0060] Each cache unit is also configured with a timeout limit, which can be set according to actual business needs. For example, the timeout limit can be configured to 2, meaning that if the cache unit fails to send twice consecutively, when its transmission window reopens, it will not wait for the number of cached business instructions in the cache unit to reach the instruction count threshold, but will instead send all currently cached instructions to the memory at once.

[0061] In this embodiment, a dual control mechanism of windowed batch sending and timeout prevention is implemented by independently configuring the instruction quantity threshold and timeout quantity for each cache unit. During normal transmission, the batch continuous sending method ensures the orderly access to memory and high bandwidth utilization. When insufficient service instructions lead to multiple consecutive sending failures, the timeout forced sending mechanism effectively avoids service blocking caused by a long period of insufficient service instructions, thereby improving the robustness of the system and the overall transmission efficiency.

[0062] Figure 3 This is a flowchart illustrating a bus flow control method provided in another exemplary embodiment of this disclosure. In some alternative embodiments, such as Figure 3 As shown, the bus flow control method may further include the following steps: In step S200, in response to the simultaneous opening of transmission windows for multiple buffer units, the transmission order of the multiple buffer units with open transmission windows is determined based on their priorities.

[0063] Each cache unit is also configured with a priority, which can be, for example, a Quality of Service (QoS) priority. QoS priority is a static configuration mechanism used to distinguish the importance of different service transmissions. The priority of each cache unit can be configured based on the importance of the service type within that cache unit.

[0064] For example, the flow control platform also includes an output switch module. The output switch is used to determine the sending order. Specifically, the output switch module can determine the sending order based on the priority of multiple buffer units that have been opened in the transmission window, using scheduling mechanisms such as round-robin arbitration.

[0065] Step S210: Based on the sending order, send the cached service instructions in multiple buffer units that have opened the transmission window in sequence.

[0066] For example, the output arbitration module can also send the cached service instructions in multiple buffer units with open transmission windows sequentially based on the sending order. For instance, assuming that the transmission windows of ID0 buffer (buffer unit) and ID1 buffer (buffer unit) are opened simultaneously, the sending order is determined by round-robin arbitration based on the priority of ID0 buffer and ID1 buffer. If the sending order is that ID0 buffer obtains arbitration right first, the service instructions cached in ID0 buffer are sent first, and the service instructions cached in ID1 buffer are sent after the ID0 buffer is sent.

[0067] Accordingly, in this embodiment of the present disclosure, when the transmission window of any cache unit is opened, there is already a cache unit with an open transmission window. The cache unit is controlled to enter a waiting state until the transmission window of the cache unit with an open transmission window is closed, and then the service instructions cached in the cache unit are sent.

[0068] In one example, when the transmission window of any cache unit is open, if another cache unit already has its transmission window open, then that cache unit is controlled to enter a waiting state until the transmission window of the existing cache unit is closed, and then it begins to send the service instructions cached in the waiting cache unit; if the transmission window of any cache unit is open and there are no other cache units in the sending state, then that cache unit can directly obtain sending permission and begin to send the instructions cached in it.

[0069] In this embodiment of the disclosure, each cache unit is configured with an independent priority. When the transmission windows of multiple cache units are opened at the same time, the transmission order is determined according to the priority, so that the transmission window of high priority service has priority to obtain the right to send, thereby effectively reducing its transmission delay and taking into account the fairness of multi-service transmission.

[0070] Figure 4 This is a schematic flowchart of a bus flow control method provided in an exemplary embodiment of the present disclosure. In some alternative embodiments, such as Figure 4 As shown, the bus flow control method may further include the following steps: In step S300, in response to the existence of a service instruction that has not been matched with a cache unit, the service instruction that has not been matched with a cache unit is determined as a bypass instruction.

[0071] When the service type of a service instruction cannot match the service type configured in any cache unit, the service routing module determines that the service instruction is not matched with a cache unit, identifies the service instruction as a bypass instruction, and assigns the bypass instruction to the bypass path.

[0072] In step S310, in response to the simultaneous presence of a bypass instruction and at least one open transmission window, based on the priority of the bypass path and the priority of the buffer unit of at least one open transmission window, the service instruction and bypass instruction already cached in the buffer unit of at least one open transmission window are sent.

[0073] The flow control platform also includes a bypass path, which is a direct logical path without buffering used to transmit bypass commands. The bypass path is configured with a priority.

[0074] For example, the priority of the bypass path can be set to the lowest priority; specifically, when the bypass instruction and the cache unit with the transmission window already open request to send at the same time, the output arbitration module, based on the priority of each cache unit and the bypass path, gives priority to the cache unit with the higher priority, so that it can continuously send the cached service instructions within the transmission window. After all the cache units with the transmission window already open have completed the service instruction sending and closed their transmission windows, the bypass instruction is then sent to the memory through the bypass path.

[0075] In step S320, when the transfer windows of multiple cache units are all closed, a bypass instruction is sent to the memory through a bypass path.

[0076] The output arbitration module monitors the window status of each cache unit in real time. When it detects that no cache unit has an open transmission window, it immediately sends the existing bypass instruction directly to the memory through the bypass path.

[0077] It should be noted that in this embodiment, there is no specific order of execution between steps S310 and S320.

[0078] In this embodiment of the disclosure, a bypass path with the lowest priority is introduced to specifically handle unclassified miscellaneous service instructions. These instructions are designed to be sent directly only during idle periods when all dedicated buffer unit transmission windows are closed. This design eliminates the interference of miscellaneous service instructions on the windowed batch transmission of high-priority services, ensuring the transmission performance of critical services. At the same time, it makes full use of the bus idle bandwidth and avoids resource waste.

[0079] Figure 5 This is a schematic flowchart of a bus flow control method provided in yet another exemplary embodiment of this disclosure. In some alternative embodiments, such as Figure 5 As shown, the bus flow control method may further include the following steps: Step S400: The second type of master terminal sends a service instruction to the memory.

[0080] The system-on-a-chip (SoC) also includes a second type of master terminal. This second type of master terminal sends its service instructions directly to memory via a path independent of the flow control platform. For example, this second type of master terminal can employ a neural network processor (NPU), a tensor processor (TPU), or other dedicated AI accelerators.

[0081] Step S410: In response to the memory receiving the service instruction sent by the second type of master terminal and the service instruction sent by the flow control platform, the memory is controlled to execute the operation of the corresponding service instruction based on the reception time of the service instruction.

[0082] The memory simultaneously receives two sources of service instructions: one source is service instructions output after scheduling by the flow control platform, and the other source is service instructions sent directly by the second type of master terminal through an independent channel. The memory processes service instructions sequentially based on their arrival time, following a first-come, first-served principle.

[0083] In the embodiments disclosed herein, the second type of master terminal is directly connected to the memory through an independent path. Its service instructions are not scheduled by the flow control platform. The service instructions output by the flow control platform are processed in the memory according to the first-come, first-served principle. This allows the second type of master terminal to completely monopolize the access rights of the memory during the period when the transmission window of all service instructions in the flow control platform is closed, shielding it from interference from other services, thereby ensuring low latency and high stability of the second type of master terminal access.

[0084] In one application example Figure 6 This is a schematic diagram of a flow control platform deployed in a system-on-a-chip, as provided in an application example of this disclosure. Figure 7 This is a schematic diagram of the structure of the flow control platform provided in an application example of this disclosure.

[0085] like Figure 6As shown, this system-on-a-chip includes multiple first-type master terminals (not shown in the figure), a second-type master terminal, dynamic random access memory (DRAM), an AXI bus, and a flow control platform. The second-type master terminals employ a neural network processor. Service instructions 0 to 2 are initiated by one or more first-type master terminals and sent to the flow control platform via the AXI bus. The neural network processor connects directly to the DRAM through a path independent of the flow control platform; its service instructions are not scheduled by the flow control platform and go directly to the DRAM. The DRAM simultaneously faces two instruction sources: one is the instruction output after being scheduled by the flow control platform, and the other is the instruction sent directly by the neural network processor through an independent path. The DRAM processes service instructions sequentially according to their arrival time, using a first-come, first-served principle.

[0086] like Figure 7 As shown, the flow control platform includes ID0 Buffer, ID1 Buffer, ID2 Buffer to IDn Buffer, each ID Buffer being a buffer unit. The flow control platform also includes a service routing module, a bypass path, and an output arbitration module.

[0087] The service routing module parses the service identifier and read / write attributes carried by each bus access command, determines its service type and operation type, and routes the service commands to the corresponding buffer units. For example, service commands 0 to 2 are allocated to ID0 Buffer, ID1 Buffer, and ID2 Buffer, respectively. Service commands that do not match any buffer unit are identified as bypass commands and sent directly to the output arbitration module via the bypass path. When each buffer unit has its transmission window open and the number of service commands cached internally reaches the command quantity threshold, it sends the cached service commands in batches to the output arbitration module. The output arbitration module determines the sending order based on the priority of each buffer unit with an open transmission window, combined with a polling arbitration mechanism, and sends the commands to the dynamic random access memory in sequence. When the transmission windows of all buffer units are closed, the output arbitration module directly sends the bypass commands in the bypass path to the dynamic random access memory.

[0088] Figure 8 This is a schematic diagram of the structure of a flow control platform provided in an exemplary embodiment of this disclosure. The flow control platform is deployed in a system-on-a-chip (SoC) and includes multiple cache units 410, a flow splitting module 400, and an output arbitration module 420. The SoC also includes a first-type master terminal and a memory. Figure 8 As shown, it includes: The traffic splitting module 400 is used to receive at least one service instruction sent by the first type of master terminal, and cache each service instruction into a cache unit 410 respectively; The output arbitration module 420 is used to send the service instructions cached in the at least one cache unit to the memory when the transmission window of the at least one cache unit is open, so that the memory can execute the service instructions.

[0089] In one implementation, each cache unit 410 is configured with a service type and an operation type; The traffic splitting module 400 is specifically used to: obtain the service type and operation type of each service instruction; determine the cache unit matching the service instruction based on the service type and operation type of the service instruction; and cache the service instruction in the cache unit matching the service instruction.

[0090] In one implementation, each cache unit 410 is configured with a window interval duration; For each cache unit 410 in the at least one cache unit, in response to the interval between the current time and the last time the transmission window of the cache unit 410 was closed reaching the window interval duration, the transmission window of the cache unit is opened.

[0091] In one implementation, each cache unit 410 is configured with an instruction count threshold; The output arbitration module 420 is further configured to, during the period when the transmission window of the cache unit 410 is open, send the cached service instructions in the cache unit 410 to the memory when the number of cached service instructions in the cache unit 410 reaches the instruction number threshold, until the cumulative number of sent service instructions reaches the instruction number threshold, and then close the transmission window.

[0092] In one implementation, each cache unit is also configured with a timeout limit; The output arbitration module 420 is further configured to pause the current transmission and close the transmission window when the transmission window opening time reaches a preset waiting time limit and the number of service instructions cached in the cache unit does not reach the instruction number threshold, and record it as a transmission failure; when the number of consecutive transmission failures in the cache unit reaches the timeout number, when the transmission window of the cache unit reopens, the currently cached service instructions in the cache unit are sent to the memory.

[0093] In one implementation, each cache unit is also configured with a priority; The output arbitration module 420 is specifically used to respond to the simultaneous opening of transmission windows of multiple cache units, determine the transmission order of multiple cache units with open transmission windows based on the priority of the multiple cache units with open transmission windows, and send the service instructions cached in the multiple cache units with open transmission windows in sequence based on the transmission order; if there is already a cache unit with an open transmission window when the transmission window of any cache unit is opened, control the cache unit to enter a waiting state until the transmission window of the cache unit with an open transmission window is closed, and then start sending the service instructions cached in the cache unit.

[0094] In one embodiment, the flow control platform further includes a bypass path configured with priority; The traffic splitting module 400 is also used to, in response to the existence of a service instruction that has not been matched with a cache unit, determine the service instruction that has not been matched with a cache unit as a bypass instruction, and assign the bypass instruction to a bypass path; The output arbitration module 420 is further configured to, in response to the simultaneous presence of the bypass instruction and at least one open transmission window, send the service instruction and bypass instruction cached in the cache unit of at least one open transmission window based on the priority of the bypass path and the priority of the cache unit of at least one open transmission window; and in response to the transmission windows of the plurality of cache units being in a closed state, send the bypass instruction to the memory through the bypass path.

[0095] The flow control platform of this disclosure corresponds to the bus flow control method described above, and the relevant content can be referred to each other. It will not be repeated here.

[0096] The beneficial technical effects of the exemplary embodiments of the flow control platform disclosed herein can be found in the corresponding beneficial technical effects of the exemplary methods and systems described above, and will not be repeated here.

[0097] In addition, this disclosure also provides an electronic device, including: Memory, used to store computer programs; A processor is configured to execute a computer program stored in the memory, wherein when the computer program is executed, it implements the bus flow control method described in any of the above embodiments of the present disclosure.

[0098] Figure 9 This is a schematic diagram illustrating the structure of an application embodiment of the electronic device disclosed herein. Below, reference is made to… Figure 8This describes an electronic device according to embodiments of the present disclosure. The electronic device may be either or both of a first device and a second device, or a standalone device independent of them, which may communicate with the first device and the second device to receive acquired input signals from them.

[0099] like Figure 9 As shown, the electronic device includes one or more processors and memory.

[0100] A processor can be a central processing unit (CPU) or other form of processing unit with data processing and / or instruction execution capabilities, and can control other components in an electronic device to perform desired functions.

[0101] The memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor may execute the program instructions to implement the bus flow control methods of the various embodiments of this disclosure described above and / or other desired functions.

[0102] In one example, the electronic device may also include input devices and output devices, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0103] In addition, the input device may include, for example, a keyboard, a mouse, etc.

[0104] This output device can output various information to the outside, including determined distance information, direction information, etc. The output device may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0105] Of course, for the sake of simplicity, Figure 9 Only some of the components of the electronic device relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device may include any other suitable components depending on the specific application.

[0106] In addition to the methods and apparatus described above, embodiments of this disclosure may also be computer program products comprising computer program instructions that, when executed by a processor, cause the processor to perform the steps of the bus flow control methods according to various embodiments of this disclosure as described in the foregoing portions of this specification.

[0107] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0108] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions that, when executed by a processor, cause the processor to perform the steps of the bus flow control methods according to various embodiments of this disclosure as described in the foregoing portion of this specification.

[0109] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0110] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as ROM, RAM, magnetic disk, or optical disk.

[0111] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0112] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system embodiments, since they largely correspond to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0113] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0114] The methods and apparatus of this disclosure may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the methods is for illustrative purposes only, and the steps of the methods of this disclosure are not limited to the order specifically described above unless otherwise specifically stated. Furthermore, in some embodiments, this disclosure may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the methods according to this disclosure. Thus, this disclosure also covers recording media storing programs for performing the methods according to this disclosure.

[0115] It should also be noted that in the apparatus, devices, and methods of this disclosure, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions to this disclosure.

[0116] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0117] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A bus flow control method, characterized in that, A flow control platform for use in a system-on-a-chip (SoC), the flow control platform including multiple cache units, the SoC further including a first type of main terminal and memory, the method comprising: Receive at least one service instruction sent by the first type of master terminal; Each of the at least one business instruction is cached in a cache unit. When the transmission window of at least one cache unit is open, the service instructions cached in the at least one cache unit are sent to the memory so that the memory executes each service instruction.

2. The method according to claim 1, characterized in that, Each cache unit is configured with one service type and one operation type; The step of caching each service instruction in at least one service instruction into a cache unit includes: For each of the aforementioned business instructions, obtain the business type and operation type of the business instruction; Based on the business type and operation type of the business instruction, determine the cache unit that matches the business instruction; The business instruction is cached in the cache unit that matches the business instruction.

3. The method according to claim 1, characterized in that, Each cache unit is configured with a window interval duration, and the method further includes: For each of the at least one cache unit, in response to the interval between the current time and the last time the transmission window of the cache unit was closed reaching the window interval duration, the transmission window of the cache unit is opened.

4. The method according to claim 3, characterized in that, Each cache unit is configured with a threshold for the number of instructions. Sending the cached business instructions in any of the cache units to the memory includes: During the open transmission window of the cache unit, when the number of cached service instructions in the cache unit reaches the instruction number threshold, the cached service instructions in the cache unit are sent to the memory until the cumulative number of sent service instructions reaches the instruction number threshold, at which point the transmission window is closed.

5. The method according to claim 4, characterized in that, Each cache unit is also configured with a timeout limit, and the method further includes: If the transmission window of the cache unit is open for a preset waiting time limit and the number of service instructions cached in the cache unit has not reached the instruction number threshold, the current transmission is paused and the transmission window is closed, and this is recorded as a transmission failure. When the number of consecutive failed transmissions by the cache unit reaches the timeout threshold, the currently cached service instructions in the cache unit are sent to the memory when the transmission window of the cache unit reopens.

6. The method according to any one of claims 1-5, characterized in that, Each cache unit is also configured with a priority, and includes: In response to the simultaneous opening of transmission windows for multiple buffer units, the transmission order of the multiple buffer units with open transmission windows is determined based on their priorities. Based on the sending order, the service instructions cached in multiple buffer units with open transmission windows are sent sequentially; When the transmission window of any cache unit is opened, there is already a cache unit with an open transmission window. The cache unit is controlled to enter a waiting state until the transmission window of the cache unit with an open transmission window is closed, and then the service instructions cached in the cache unit are sent.

7. The method according to claim 6, characterized in that, The flow control platform also includes a bypass path, which is configured with a priority; the method further includes: In response to the existence of a service instruction that has not been matched with a cache unit, the service instruction that has not been matched with a cache unit is determined as a bypass instruction; In response to the simultaneous presence of the bypass instruction and at least one open transmission window, based on the priority of the bypass path and the priority of the buffer unit of at least one open transmission window, the service instruction and bypass instruction already cached in the buffer unit of at least one open transmission window are sent. When the transmission windows of the plurality of cache units are all closed, the bypass instruction is sent to the memory through the bypass path.

8. The method according to claim 1, characterized in that, The system-on-a-chip also includes a second type of host terminal, and the method further includes: The second type of master terminal sends service instructions to the memory; In response to the memory receiving service instructions sent by the second type of master terminal and service instructions sent by the flow control platform, the memory is controlled to execute the corresponding service instruction operation based on the reception time of the service instruction.

9. A flow control platform, characterized in that, The flow control platform is deployed in a system-on-a-chip (SoC). The flow control platform includes multiple cache units, a flow splitting module, and an output arbitration module. The SoC also includes a first-type master terminal and a memory. The traffic splitting module is used to receive at least one service instruction sent by the first type of master terminal, and cache each service instruction into a cache unit respectively; The output arbitration module is used to send the service instructions cached in at least one cache unit to the memory when the transmission window of at least one cache unit is open, so that the memory can execute each service instruction.

10. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing a computer program stored in the memory, wherein when the computer program is executed, it implements the method described in any one of claims 1-8.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1-8.

12. A computer program product comprising computer program instructions, characterized in that, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 1-8.

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