Method, device and equipment for unified access of multi-protocol edge device and storage medium

Abstract

The application discloses a kind of multi-protocol edge device unified access method, device, equipment and storage medium, the method is by obtaining the original data of heterogeneous equipment accessed by plug-in protocol adaptation layer, and original data is divided into L1 level safety interlocking data, L2 level key process data and L3 level auxiliary monitoring data using preset three-dimensional hierarchical decision function;In response to the hardware interrupt signal generated by L1 level safety interlocking data, trigger isolated CPU core direct processing to bypass user state message queue, perform feature extraction preprocessing on L2 level key process data on edge side, perform compression sampling on L3 level auxiliary monitoring data;L1 level data, L2 level data and L3 level data are reported through differential QoS interface after processing, and dynamically adjust the processing strategy and sampling rate of L2 level and L3 level data according to the abnormal state of real-time monitoring, can realize the overall optimal balance of edge access security, real-time and transmission efficiency.

Description

Technical Field

[0001] This invention relates to the field of edge computing technology for the Industrial Internet of Things (IIoT), and in particular to a unified access method, apparatus, device, and storage medium for multi-protocol edge devices. Background Technology

[0002] In the field of Industrial Internet of Things (IIoT), enterprise workshops typically contain a variety of heterogeneous devices and communication protocols. Taking a mold manufacturing workshop as an example, there are multiple devices simultaneously, including Programmable Logic Controllers (PLCs) (Modbus protocol), Computer Numerical Control (CNC) CNC equipment (MTConnect / Open Platform Communications Unified Architecture (OPC UA) protocol), Automated Guided Vehicles (AGVs) (Robot Operating System (ROS) / Hypertext Transfer Protocol (HTTP) protocol), and environmental sensors (Message Queuing Telemetry Transport (MQTT) protocol). Each device uses different communication protocols and data formats.

[0003] Traditional solutions require deploying a separate acquisition layer for each protocol, resulting in high maintenance costs and difficulty in standardizing data formats.

[0004] In the field of real-time control, the device control loop requires millisecond-level response (such as emergency stop signals). However, after the data flows from the edge gateway to the cloud platform and then to the business system, the delay reaches hundreds of milliseconds, which cannot meet the requirements of real-time closed-loop control.

[0005] Taking the milling of Cr12MoV hardened steel (Hardness HRC58) molds by a five-axis machining center as an example, under the conditions of a spindle speed of 12000 rpm and a feed rate of 3000 mm / min, the vibration spectrum of the tool before chipping will show a sudden increase in energy in the 2000~3000 Hz frequency band (more than 3 times higher than normal machining). This sudden increase in energy in the frequency band is a reliable sign that the tool is about to break.

[0006] The machining control system must trigger the feed hold command within 10 ms after detecting the above-mentioned abnormality in order to avoid complete tool breakage and mold scrap (a single precision mold is worth tens to hundreds of thousands of RMB).

[0007] If the stop signal is delayed by more than 10 ms, the tool will continue cutting under uncontrolled vibration, causing irreversible damage to the mold cavity.

[0008] However, existing general-purpose edge gateways (such as gateways using the MQTT Broker architecture) suffer from a serious problem of security signal blocking: vibration acquisition signals (typical sampling rate 5000~10000 Hz, approximately 160 kbps bitstream per channel) and emergency stop / interlocking safety signals are mixed in the same message queue of the same Transmission Control Protocol (TCP) uplink channel.

[0009] When 30 to 100 CNC machines are running simultaneously in the workshop, the vibration data stream puts a continuous high load on the TCP channel (the peak can reach tens of Mbps), causing TCP congestion window reduction or head-of-line blocking.

[0010] Under the aforementioned congestion conditions, the waiting delay for an emergency stop signal in the queue can reach more than 200 ms, far exceeding the 10 ms safety trigger window, resulting in serious consequences such as "tool chipping → scrapping of precision mold cavity → production stoppage losses".

[0011] This contradiction cannot be completely resolved by increasing network bandwidth or setting software priorities under the traditional unified queue architecture, because head-of-queue blocking at the TCP connection level is a fundamental constraint at the protocol level.

[0012] In the field of data cloudification, existing solutions upload all raw data (including a large amount of steady-state redundant data) to the cloud, causing network congestion and storage expansion.

[0013] With 100 devices, each with a sampling rate of 1000Hz, 100,000 data records are generated per second. More than 99% of these are normal steady-state data, while truly valuable abnormal data are submerged in the massive amount of redundant data.

[0014] The aforementioned safety-efficiency conflict is not unique to CNC milling scenarios; it also exists in other industrial manufacturing scenarios: during the mold closing process of an injection molding machine, an abnormal drop in the clamping force curve (drop ≥8%, duration ≥100 ms) indicates flash or cavity damage, requiring immediate injection interruption; in electrical discharge machining (EDM), a sudden change in the discharge current pulse width indicates a short circuit between the electrode and the workpiece, requiring a response within microseconds to milliseconds; in mold temperature controller linkage control, warning signals with a temperature rise rate exceeding 5 °C / min should be reported before ordinary temperature inspection data.

[0015] These scenarios all face the same structural contradiction: low-frequency but safety-critical control signals are overwhelmed by high-frequency but non-critical process monitoring data.

[0016] The common problems of the above three types of existing solutions are: lack of a unified protocol adaptation layer, lack of real-time processing capabilities at the edge, and lack of a data hierarchical optimization and uploading mechanism.

[0017] Specifically, this manifests as: fragmented access due to the coexistence of multiple protocols, excessive latency in uploading high-frequency data to the cloud, and waste of bandwidth and storage resources.

[0018] While existing general-purpose edge platforms (such as AWS IoT Greengrass, Azure IoT Edge, and EdgeX Foundry) offer multi-protocol access capabilities, they are designed for general Internet of Things (IoT) scenarios and do not provide a hard real-time secure offloading channel for the mold / injection molding industry. They also do not have built-in directional Fast Fourier Transform (FFT) preprocessing algorithms for the chipping characteristic frequency band of CNC tools (2000~3000 Hz). Their priority queue mechanism remains at the user-space software level and cannot fundamentally eliminate head-of-line blocking at the TCP layer, thus failing to meet the hard real-time requirement of 10ms-level secure triggering. Summary of the Invention

[0019] The main objective of this invention is to provide a unified access method, apparatus, device, and storage medium for multi-protocol edge devices. This invention aims to solve the technical problems in the prior art where general edge gateways, due to the unified processing of data via user-space message queues and TCP / IP protocol stacks, suffer from excessively high latency in security interlocking signals, which fails to meet hard real-time requirements. Furthermore, it addresses the issues of wasted bandwidth for uploading high-frequency process data and the lack of dynamic adjustment mechanisms.

[0020] In a first aspect, the present invention provides a unified access method for multi-protocol edge devices, the unified access method for multi-protocol edge devices comprising the following steps: The raw data of heterogeneous devices accessed through the plug-in protocol adaptation layer is obtained, and the raw data is divided into L1 level safety interlock data, L2 level key process data and L3 level auxiliary monitoring data using a preset three-dimensional classification judgment function. In response to the hardware interrupt signal generated by the L1 level safety interlock data, the isolated CPU core is triggered to directly process the data to bypass the user-mode message queue, and feature extraction preprocessing is performed on the L2 level key process data at the edge side, and compressed sampling is performed on the L3 level auxiliary monitoring data. The processed L1, L2, and L3 data are reported through a differentiated QoS interface, and the processing strategies and sampling rates of the L2 and L3 data are dynamically adjusted based on real-time monitored abnormal states.

[0021] Optionally, the step of acquiring the raw data of heterogeneous devices accessed through the plug-in protocol adaptation layer, and dividing the raw data into L1-level safety interlock data, L2-level key process data, and L3-level auxiliary monitoring data using a preset three-dimensional hierarchical judgment function, includes: The protocol adapter plugin is loaded through the operating system's dynamic link interface to obtain raw data from heterogeneous devices. The signal type encoding, source device security integrity level, and edge gateway current comprehensive load index are used as input dimensions for the preset three-dimensional classification judgment function; The original data is divided into L1 level safety interlock data, L2 level key process data and L3 level auxiliary monitoring data according to the preset three-dimensional classification judgment function.

[0022] Optionally, the step of loading the protocol adapter plugin through the operating system's dynamic link interface to obtain the raw data from the heterogeneous device includes: Protocol adapter plugins are loaded via the operating system's dynamic link interface. Each plugin package includes a JSONSchema file to describe the device type, configuration parameters, and data model. Based on the JSONSchema file, database mapping and configuration verification rules are dynamically generated to ensure that no modifications are needed to the platform layer code when adding a new protocol. Before loading the protocol adapter plugin, verify the digital signature of each plugin package. If the verification fails, refuse to load the protocol adapter plugin. After loading the protocol adapter plugin, the raw data of the heterogeneous device is obtained.

[0023] Optionally, the step of dividing the raw data into L1-level safety interlock data, L2-level key process data, and L3-level auxiliary monitoring data according to the preset three-dimensional classification judgment function includes: When the signal type is encoded as an emergency stop or safety interlock signal, it is forcibly determined to be L1 level safety interlock data regardless of the load index. When the signal type encoding is not an emergency stop or safety interlock signal, the source device's safety integrity level is higher than a preset safety threshold, and the edge gateway's current comprehensive load index is lower than a preset load threshold, it is determined to be L2 level critical process data. When the current comprehensive load index of the edge gateway is higher than the preset load threshold, the reporting window is narrowed; When the security integrity level of the source device is not higher than the preset security threshold, and the signal type is encoded as a device status signal, it is determined to be L2 level key process data low-frequency reporting; otherwise, it is determined to be L3 level auxiliary monitoring data.

[0024] Optionally, the step of responding to the hardware interrupt signal generated by the L1-level safety interlock data, triggering the isolated CPU core to directly process the data to bypass the user-mode message queue, performing feature extraction preprocessing on the L2-level critical process data at the edge, and performing compressed sampling on the L3-level auxiliary monitoring data, includes: In response to the hardware interrupt signal generated by the L1 level safety interlock data, the hardware interface for receiving L1 level safety interlock data is configured to edge-triggered interrupt mode. When the operating system starts, a specified CPU core is isolated from the general scheduling queue, and a secure interlocking kernel process is run on the specified CPU core to bypass the user-mode message queue. The original signal segments divided into the L2 level key process data are extracted, and a sampling window is formed by accumulating a preset number of sampling points in the L2 level key process data through a circular buffer. The L2-level key process data within the sampling window is processed by DC removal, windowing, and fast Fourier transform. The frequency bands are divided according to a preset standard, and the power spectral density within each frequency band is integrated to generate a feature frame containing frequency band energy values ​​and anomaly markers. The raw data stream divided into the L3 level auxiliary monitoring data is obtained, and the reporting frequency of the L3 level auxiliary monitoring data is reduced by a time-slicing downsampling strategy. A compression algorithm is applied to the downsampled L3 auxiliary monitoring data to reduce the data packet size.

[0025] Optionally, isolating a designated CPU core from the general scheduling queue during operating system startup and running a secure interlocking kernel process on the designated CPU core to bypass the user-mode message queue includes: When the operating system starts, a designated CPU core is isolated from the general scheduling queue, and a security interlock processing kernel thread dedicated to processing the L1 level security interlock data is run on the designated CPU core. The security interlock processing kernel thread adopts a real-time scheduling strategy and has a higher priority than ordinary processes and protocol parsing threads. When the L1-level security interlock data triggers a hardware interrupt, the security interlock processing kernel thread directly executes the security response logic for the L1-level security interlock data from the interrupt context, without going through the user-mode message queue and network I / O response.

[0026] Optionally, the step of reporting the processed L1, L2, and L3 data through a differentiated QoS interface, and dynamically adjusting the processing strategy and sampling rate of the L2 and L3 data based on real-time monitored abnormal states, includes: The processed L1 level data is sent to the northbound interface via a high-priority asynchronous interface to achieve non-blocking reporting. The processed L2 level data feature frames are aggregated and sent in batches via an asynchronous streaming interface; The processed L3 level data will be reported periodically at preset time intervals via a low-priority batch interface. When the feature value of the L2 level data exceeds the preset abnormal feature threshold, the device is determined to be in an abnormal state. In the abnormal state, the processing strategy for the L2 level data is switched from feature frame mode to full waveform backhaul mode, and the sampling frequency of the L3 level data is reduced. Once the abnormal state is eliminated, the processing strategies for the L2 and L3 data are restored to normal after a preset hysteresis time.

[0027] Secondly, to achieve the above objectives, the present invention also proposes a unified access device for multi-protocol edge devices, the unified access device for multi-protocol edge devices comprising: The data segmentation module is used to acquire the raw data of heterogeneous devices accessed through the plug-in protocol adaptation layer, and to use a preset three-dimensional hierarchical judgment function to segment the raw data into L1 level safety interlock data, L2 level key process data and L3 level auxiliary monitoring data. The data processing module is used to respond to the hardware interrupt signal generated by the L1 level safety interlock data, trigger the isolated CPU core to process directly to bypass the user-mode message queue, perform feature extraction preprocessing on the L2 level key process data at the edge side, and perform compressed sampling on the L3 level auxiliary monitoring data. The strategy adjustment module is used to report the processed L1, L2 and L3 data through a differentiated QoS interface, and dynamically adjust the processing strategy and sampling rate of the L2 and L3 data according to the abnormal status monitored in real time.

[0028] Thirdly, to achieve the above objectives, the present invention also proposes a unified access device for multi-protocol edge devices, the unified access device for multi-protocol edge devices comprising: a memory, a processor, and a unified access program for multi-protocol edge devices stored in the memory and executable on the processor, the unified access program for multi-protocol edge devices being configured to implement the steps of the unified access method for multi-protocol edge devices as described above.

[0029] Fourthly, to achieve the above objectives, the present invention also proposes a storage medium storing a unified access program for multi-protocol edge devices, wherein the unified access program for multi-protocol edge devices, when executed by a processor, implements the steps of the unified access method for multi-protocol edge devices as described above.

[0030] The proposed method for unified access of multi-protocol edge devices acquires raw data from heterogeneous devices accessing via a pluggable protocol adaptation layer. It then uses a preset three-dimensional hierarchical judgment function to classify the raw data into L1-level security interlocking data, L2-level critical process data, and L3-level auxiliary monitoring data. In response to a hardware interrupt signal generated by the L1-level security interlocking data, it triggers an isolated CPU core to directly process the data, bypassing the user-mode message queue. Feature extraction preprocessing is performed on the L2-level critical process data at the edge, and compressed sampling is performed on the L3-level auxiliary monitoring data. The processed L1, L2, and L3 data are reported through a differentiated QoS interface, and the relationship between the L2-level and L3 data is dynamically adjusted based on real-time monitored anomalies. The processing strategy and sampling rate of L1 level data enable unified access and differentiated processing of heterogeneous device data through plug-in adaptation and three-dimensional data hierarchical classification. It utilizes isolated CPU cores and hardware interrupt bypass user-mode queues to process L1 level data to ensure millisecond-level hard real-time response of safety interlock signals. By performing edge feature extraction on L2 level data and compressed sampling on L3 level data, it significantly reduces uplink network bandwidth usage. Combined with differentiated QoS reporting and dynamic upgrade / downgrade strategies for abnormal states, it prioritizes the complete transmission of critical diagnostic data when network resources are limited or devices malfunction. This solves the problems of high security signal latency, high-frequency data bandwidth waste, and lack of dynamic scheduling mechanisms in existing technologies, achieving an overall optimal balance between edge access security, real-time performance, and transmission efficiency. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the device structure of the hardware operating environment involved in the embodiments of the present invention; Figure 2 This is a flowchart illustrating the first embodiment of the multi-protocol edge device unified access method of the present invention; Figure 3 This is a flowchart illustrating the second embodiment of the multi-protocol edge device unified access method of the present invention; Figure 4 This is a flowchart illustrating the third embodiment of the multi-protocol edge device unified access method of the present invention; Figure 5 This is a flowchart illustrating the fourth embodiment of the multi-protocol edge device unified access method of the present invention; Figure 6 This is a functional block diagram of the first embodiment of the multi-protocol edge device unified access device of the present invention.

[0032] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0033] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0034] The solution of this invention mainly involves: acquiring raw data from heterogeneous devices accessed via a pluggable protocol adaptation layer, and dividing the raw data into L1-level safety interlock data, L2-level key process data, and L3-level auxiliary monitoring data using a preset three-dimensional hierarchical judgment function; responding to hardware interrupt signals generated by the L1-level safety interlock data, triggering isolated CPU cores to directly process the data to bypass the user-mode message queue; performing feature extraction preprocessing on the L2-level key process data at the edge side; and performing compressed sampling on the L3-level auxiliary monitoring data; reporting the processed L1-level, L2-level, and L3-level data through a differentiated QoS interface; and dynamically adjusting the processing strategies and sampling rates of the L2-level and L3-level data based on real-time monitored abnormal states. This enables unified access and differentiated processing of heterogeneous device data through pluggable adaptation and three-dimensional data hierarchical classification. This approach utilizes isolated CPU cores and hardware interrupt bypass user-space queues to process L1-level data, ensuring millisecond-level hard real-time response to safety interlock signals. It significantly reduces uplink network bandwidth usage by performing edge feature extraction on L2-level data and compressed sampling on L3-level data. Combined with differentiated QoS reporting and dynamic upgrade / downgrade strategies for abnormal states, it prioritizes the complete transmission of critical diagnostic data when network resources are limited or equipment malfunctions. This addresses the problems of high security signal latency, wasted high-frequency data bandwidth, and lack of dynamic scheduling mechanisms in existing technologies. It achieves an optimal overall balance between edge access security, real-time performance, and transmission efficiency. Furthermore, it solves the technical problems of excessively high security interlock signal latency in general edge gateways due to data processing via user-space message queues and TCP / IP protocol stacks, which fails to meet hard real-time requirements, as well as wasted bandwidth for high-frequency process data uploads and the lack of dynamic adjustment mechanisms.

[0035] Reference Figure 1 , Figure 1 This is a schematic diagram of the device structure of the hardware operating environment involved in the embodiments of the present invention.

[0036] like Figure 1As shown, the device may include: a processor 1001, such as a CPU; a communication bus 1002; a user interface 1003; a network interface 1004; and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen or an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 1005 may be high-speed RAM or non-volatile memory, such as a disk drive. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0037] Those skilled in the art will understand that Figure 1 The device structure shown does not constitute a limitation on the device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0038] like Figure 1 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a network communication module, a user interface module, and a unified access program for multi-protocol edge devices.

[0039] The device of the present invention calls the multi-protocol edge device unified access program stored in the memory 1005 through the processor 1001, and performs the operations in the embodiment of the multi-protocol edge device unified access method described below.

[0040] This embodiment, through the above-described scheme, acquires raw data from heterogeneous devices accessed via a pluggable protocol adaptation layer, and uses a preset three-dimensional hierarchical judgment function to divide the raw data into L1-level safety interlock data, L2-level critical process data, and L3-level auxiliary monitoring data. In response to a hardware interrupt signal generated by the L1-level safety interlock data, an isolated CPU core is triggered to directly process the data, bypassing the user-mode message queue. Feature extraction preprocessing is performed on the L2-level critical process data at the edge side, and compressed sampling is performed on the L3-level auxiliary monitoring data. The processed L1-level, L2-level, and L3-level data are reported through a differentiated QoS interface, and the processing of the L2-level and L3-level data is dynamically adjusted based on real-time monitored abnormal states. By implementing management strategies and sampling rates, it can achieve unified access and differentiated processing of heterogeneous device data through plug-in adaptation and three-dimensional data hierarchical classification. It utilizes isolated CPU cores and hardware interrupt bypass user-mode queues to process L1-level data to ensure millisecond-level hard real-time response of safety interlock signals. By performing edge feature extraction on L2-level data and compressed sampling on L3-level data, it significantly reduces uplink network bandwidth usage. Combined with differentiated QoS reporting and dynamic upgrade / downgrade strategies for abnormal states, it prioritizes the complete backhaul of critical diagnostic data when network resources are limited or devices malfunction. This solves the problems of high security signal latency, high-frequency data bandwidth waste, and lack of dynamic scheduling mechanisms in existing technologies, achieving an overall optimal balance between edge access security, real-time performance, and transmission efficiency.

[0041] Based on the above hardware structure, an embodiment of the multi-protocol edge device unified access method of the present invention is proposed.

[0042] Reference Figure 2 , Figure 2 This is a flowchart illustrating the first embodiment of the multi-protocol edge device unified access method of the present invention.

[0043] In the first embodiment, the unified access method for multi-protocol edge devices includes the following steps: Step S10: Obtain the raw data of heterogeneous devices accessed through the plug-in protocol adaptation layer, and use a preset three-dimensional classification judgment function to divide the raw data into L1 level safety interlock data, L2 level key process data and L3 level auxiliary monitoring data.

[0044] It should be noted that by accessing the raw data of heterogeneous devices through the plug-in protocol adaptation layer, and using the preset three-dimensional hierarchical judgment function to divide the raw data into L1 level safety interlock data, L2 level key process data and L3 level auxiliary monitoring data, the differences in the underlying protocols can be shielded to achieve unified and standardized access of multi-source data, and a hierarchical mechanism can be established based on the security attributes and criticality of the data.

[0045] Step S20: In response to the hardware interrupt signal generated by the L1 level safety interlock data, trigger the isolated CPU core to directly process the data to bypass the user-mode message queue, perform feature extraction preprocessing on the L2 level key process data at the edge side, and perform compressed sampling on the L3 level auxiliary monitoring data.

[0046] It should be understood that by responding to the hardware interrupt signal generated by the L1 level security interlock data, the isolated CPU core is triggered to directly process the data to bypass the user-mode message queue. Feature extraction preprocessing is performed on the L2 level key process data at the edge, and compressed sampling is performed on the L3 level auxiliary monitoring data. Differentiated processing paths and computing resources can be matched according to the data classification results. While ensuring the millisecond-level hard real-time response of the L1 level security signal, the uplink bandwidth occupation of L2 and L3 level data is significantly reduced through edge intelligent preprocessing and compression, thereby achieving coordinated optimization of edge-side security, real-time performance and transmission efficiency.

[0047] Step S30: Report the processed L1, L2 and L3 data through the differentiated QoS interface, and dynamically adjust the processing strategy and sampling rate of the L2 and L3 data according to the abnormal status monitored in real time.

[0048] It is understandable that by reporting the processed L1, L2, and L3 data through a differentiated QoS interface, and dynamically adjusting the processing strategies and sampling rates of the L2 and L3 data based on real-time monitored abnormal states, transmission service quality matching the importance and timeliness requirements of different levels of data can be provided, and bandwidth resources and diagnostic accuracy can be intelligently balanced when equipment malfunctions.

[0049] This embodiment, through the above-described scheme, acquires raw data from heterogeneous devices accessed via a pluggable protocol adaptation layer, and uses a preset three-dimensional hierarchical judgment function to divide the raw data into L1-level safety interlock data, L2-level critical process data, and L3-level auxiliary monitoring data. In response to a hardware interrupt signal generated by the L1-level safety interlock data, an isolated CPU core is triggered to directly process the data, bypassing the user-mode message queue. Feature extraction preprocessing is performed on the L2-level critical process data at the edge side, and compressed sampling is performed on the L3-level auxiliary monitoring data. The processed L1-level, L2-level, and L3-level data are reported through a differentiated QoS interface, and the processing of the L2-level and L3-level data is dynamically adjusted based on real-time monitored abnormal states. By implementing management strategies and sampling rates, it can achieve unified access and differentiated processing of heterogeneous device data through plug-in adaptation and three-dimensional data hierarchical classification. It utilizes isolated CPU cores and hardware interrupt bypass user-mode queues to process L1-level data to ensure millisecond-level hard real-time response of safety interlock signals. By performing edge feature extraction on L2-level data and compressed sampling on L3-level data, it significantly reduces uplink network bandwidth usage. Combined with differentiated QoS reporting and dynamic upgrade / downgrade strategies for abnormal states, it prioritizes the complete backhaul of critical diagnostic data when network resources are limited or devices malfunction. This solves the problems of high security signal latency, high-frequency data bandwidth waste, and lack of dynamic scheduling mechanisms in existing technologies, achieving an overall optimal balance between edge access security, real-time performance, and transmission efficiency.

[0050] Furthermore, Figure 3 This is a flowchart illustrating the second embodiment of the multi-protocol edge device unified access method of the present invention, as shown below. Figure 3 As shown, based on the first embodiment, a second embodiment of the multi-protocol edge device unified access method of the present invention is proposed. In this embodiment, step S10 specifically includes the following steps: Step S11: Load the protocol adapter plugin through the operating system's dynamic link interface to obtain the raw data from the heterogeneous device.

[0051] It should be noted that by loading protocol adapter plugins through the operating system's dynamic link interface to obtain raw data from heterogeneous devices, the plug-in mechanism can be used to decouple the protocol parsing logic from the platform's core code, supporting the dynamic expansion of new protocol adaptation capabilities without modifying the platform layer code.

[0052] Furthermore, step S11 specifically includes the following steps: Protocol adapter plugins are loaded via the operating system's dynamic link interface. Each plugin package includes a JSONSchema file to describe the device type, configuration parameters, and data model. Based on the JSONSchema file, database mapping and configuration verification rules are dynamically generated to ensure that no modifications are needed to the platform layer code when adding a new protocol. Before loading the protocol adapter plugin, verify the digital signature of each plugin package. If the verification fails, refuse to load the protocol adapter plugin. After loading the protocol adapter plugin, the raw data of the heterogeneous device is obtained.

[0053] It should be understood that by loading protocol adapter plugins through the operating system's dynamic link interface and dynamically generating database mapping and configuration verification rules using JSONSchema files, the protocol parsing logic and the platform's core code can be decoupled to support adding new protocols without modifying the platform layer code. At the same time, verifying the digital signature of the plugin package before loading ensures the trustworthiness and integrity of the plugin's source, thereby achieving flexible adaptation of heterogeneous device protocols and secure and unified acquisition of raw data while ensuring system security.

[0054] Step S12: The signal type encoding, source device security integrity level, and edge gateway current comprehensive load index are used as input dimensions for the preset three-dimensional hierarchical judgment function.

[0055] It is understandable that by collecting signal type encoding, source device security integrity level, and edge gateway current comprehensive load index as input dimensions of the preset three-dimensional classification judgment function, the importance of data can be comprehensively evaluated from three dimensions: business type, security level, and system load.

[0056] Step S13: Divide the original data into L1 level safety interlock data, L2 level key process data and L3 level auxiliary monitoring data according to the preset three-dimensional classification judgment function.

[0057] It should be understood that by dividing the original data into L1 level safety interlock data, L2 level key process data and L3 level auxiliary monitoring data through the preset three-dimensional classification judgment function, a hierarchical management system based on the importance and real-time requirements of the data can be established, providing a clear execution basis for subsequent differentiated hardware interruption handling, edge feature extraction and compressed sampling strategies.

[0058] Furthermore, step S13 specifically includes the following steps: When the signal type is encoded as an emergency stop or safety interlock signal, it is forcibly determined to be L1 level safety interlock data regardless of the load index. When the signal type encoding is not an emergency stop or safety interlock signal, the source device's safety integrity level is higher than a preset safety threshold, and the edge gateway's current comprehensive load index is lower than a preset load threshold, it is determined to be L2 level critical process data. When the current comprehensive load index of the edge gateway is higher than the preset load threshold, the reporting window is narrowed; When the security integrity level of the source device is not higher than the preset security threshold, and the signal type is encoded as a device status signal, it is determined to be L2 level key process data low-frequency reporting; otherwise, it is determined to be L3 level auxiliary monitoring data.

[0059] Understandably, by forcibly classifying signals encoded as emergency stop or safety interlock signals as L1-level safety interlock data regardless of load level, and classifying non-safety interlock signals as L2-level critical process data if the safety integrity level is higher than a preset threshold and the load is low, and maintaining L2-level processing even when the load is too high by narrowing the reporting window, and also including data with a safety integrity level not higher than the threshold but belonging to equipment status signals in the L2-level low-frequency reporting category, and classifying the remaining data that does not meet the above conditions as L3-level auxiliary monitoring data, a dynamic classification mechanism that prioritizes safety while taking into account the real-time load of the system can be established, thereby ensuring that critical safety signals receive the highest processing priority under any operating condition and are not affected by system congestion.

[0060] This embodiment, through the above-described scheme, loads a protocol adapter plugin via the operating system's dynamic link interface to obtain raw data from heterogeneous devices. It collects signal type encoding, source device security integrity level, and the current comprehensive load index of the edge gateway as input dimensions for a preset three-dimensional classification judgment function. Based on this function, the raw data is divided into L1-level security interlocking data, L2-level key process data, and L3-level auxiliary monitoring data. This plug-in loading mechanism shields underlying protocol differences, enabling unified access to raw data from heterogeneous devices. Furthermore, by combining signal type, security level, and system load dimensions, the data is precisely classified, providing a clear classification basis for subsequent differentiated hard real-time processing and transmission strategies. This allows for optimized allocation of edge computing resources while prioritizing security interlocking.

[0061] Furthermore, Figure 4 This is a flowchart illustrating the third embodiment of the multi-protocol edge device unified access method of the present invention, as shown below. Figure 4 As shown, based on the first embodiment, a third embodiment of the multi-protocol edge device unified access method of the present invention is proposed. In this embodiment, step S20 specifically includes the following steps: Step S21: In response to the hardware interrupt signal generated by the L1 level safety interlock data, configure the hardware interface for receiving L1 level safety interlock data to edge-triggered interrupt mode.

[0062] It should be noted that by responding to the hardware interrupt signal generated by the L1 level safety interlock data, the hardware interface for receiving L1 level safety interlock data is configured to edge-triggered interrupt mode. This allows the hardware interrupt mechanism to replace the traditional polling method, triggering the capture action immediately at the moment the safety signal state changes.

[0063] Step S22: When the operating system starts, the specified CPU core is isolated from the general scheduling queue, and a security interlocking kernel process is run on the specified CPU core to bypass the user-mode message queue.

[0064] It is understandable that by isolating a designated CPU core from the general scheduling queue at operating system startup and running a secure interlocking kernel process on the designated CPU core to bypass the user-mode message queue, exclusive computing resources can be provided for secure interlocking to avoid interference from general process scheduling, and the queuing and copying overhead of the user-mode message queue can be eliminated by directly processing in kernel mode.

[0065] Furthermore, step S22 specifically includes the following steps: When the operating system starts, a designated CPU core is isolated from the general scheduling queue, and a security interlock processing kernel thread dedicated to processing the L1 level security interlock data is run on the designated CPU core. The security interlock processing kernel thread adopts a real-time scheduling strategy and has a higher priority than ordinary processes and protocol parsing threads. When the L1-level security interlock data triggers a hardware interrupt, the security interlock processing kernel thread directly executes the security response logic for the L1-level security interlock data from the interrupt context, without going through the user-mode message queue and network I / O response.

[0066] It should be noted that by isolating a designated CPU core from the general scheduling queue during operating system startup and running a dedicated security interlocking processing kernel thread on that designated CPU core to process the L1-level security interlocking data, exclusive computing resources can be provided for security signals to avoid interference from general process scheduling. Combined with the mechanism that executes security response logic directly from the interrupt context when the L1-level security interlocking data triggers a hardware interrupt without going through the user-mode message queue and network I / O response, context switching and protocol stack processing overhead are eliminated. This ensures that the L1-level security interlocking data can still obtain millisecond-level hard real-time response under extreme load, thus guaranteeing the inherent security of device operation.

[0067] Step S23: Extract the original signal segments that are divided into the L2 level key process data, and accumulate a preset number of sampling points in the L2 level key process data through a circular buffer to form a sampling window.

[0068] It should be understood that by extracting the original signal segments that are divided into the L2 level key process data, and accumulating a preset number of sampling points in the L2 level key process data through a circular buffer to form a sampling window, the continuous signal can be divided into fixed-length analysis units, providing input for subsequent FFT frequency domain analysis.

[0069] Step S24: Perform DC removal, windowing, and fast Fourier transform processing on the L2 level key process data in the sampling window, divide the frequency bands according to the preset standard, integrate the power spectral density in each frequency band, and generate a feature frame containing frequency band energy values ​​and anomaly markers.

[0070] It is understood that by performing DC removal, windowing, and fast Fourier transform processing on the L2 level key process data within the sampling window, signal DC offset can be eliminated and spectral leakage can be suppressed to improve the accuracy of frequency domain analysis. Furthermore, frequency bands can be divided according to preset standards and the power spectral density within each frequency band can be integrated to extract key process features and generate feature frames containing frequency band energy values ​​and anomaly markers.

[0071] Step S25: Obtain the original data stream that has been divided into the L3 level auxiliary monitoring data, and use a time-slice downsampling strategy to reduce the reporting frequency of the L3 level auxiliary monitoring data.

[0072] It should be understood that by acquiring the original data stream that is divided into the L3 level auxiliary monitoring data and using a time-slicing downsampling strategy to reduce the reporting frequency of the L3 level auxiliary monitoring data, the number of redundant data points can be significantly reduced while preserving the trend characteristics of the auxiliary data, thereby effectively releasing uplink network bandwidth resources to avoid congestion of non-critical data channels.

[0073] Step S26: Perform a compression algorithm on the downsampled L3-level auxiliary monitoring data to reduce the data packet size.

[0074] It is understandable that by performing a compression algorithm on the downsampled L3 auxiliary monitoring data to reduce the data packet size, the data volume can be further compressed by utilizing the coding redundancy feature on the basis of reducing the number of data points by time downsampling, which can significantly reduce the network transmission load and bandwidth usage per transmission.

[0075] This embodiment, through the above-described scheme, configures the hardware interface receiving L1-level safety interlock data in edge-triggered interrupt mode in response to the hardware interrupt signal generated by the L1-level safety interlock data; isolates a designated CPU core from the general scheduling queue during operating system startup and runs the safety interlock processing kernel process on the designated CPU core to bypass the user-mode message queue; extracts the original signal segments divided into L2-level critical process data, accumulates a preset number of sampling points in the L2-level critical process data through a circular buffer to form a sampling window; performs DC removal, windowing, and fast Fourier transform processing on the L2-level critical process data within the sampling window, divides the frequency bands according to a preset standard, integrates the power spectral density within each frequency band, and generates a data stream containing... The system acquires feature frames of frequency band energy values ​​and anomaly markers; obtains the original data stream divided into the L3-level auxiliary monitoring data; employs a time-slicing downsampling strategy to reduce the reporting frequency of the L3-level auxiliary monitoring data; performs a compression algorithm on the downsampled L3-level auxiliary monitoring data to reduce the data packet size; and can bypass the user-mode message queue by directly processing the isolated CPU core in response to a hardware interrupt signal, ensuring that L1-level safety interlock data obtains millisecond-level hard real-time response. By performing feature extraction preprocessing on L2-level key process data and performing compression sampling on L3-level auxiliary monitoring data, the system significantly reduces uplink network bandwidth usage and storage pressure, thereby achieving differentiated optimal configuration of edge computing resources and communication load while ensuring the inherent safety of the equipment.

[0076] Furthermore, Figure 5 This is a flowchart illustrating the fourth embodiment of the multi-protocol edge device unified access method of the present invention, as shown below. Figure 5 As shown, based on the first embodiment, a fourth embodiment of the multi-protocol edge device unified access method of the present invention is proposed. In this embodiment, step S30 specifically includes the following steps: Step S31: The processed L1 level data is sent to the northbound interface via a high-priority asynchronous interface to achieve non-blocking reporting.

[0077] It should be noted that by sending the processed L1 level data to the northbound interface through a high-priority asynchronous interface to achieve non-blocking reporting, the high-priority queue can be used to send event notifications first without blocking local security responses. This avoids network I / O waiting affecting the deterministic delay of the security interlock processing path, thereby ensuring the real-time reporting of security interlock events.

[0078] Step S32: The feature frames of the processed L2 level data are aggregated and sent in batches through an asynchronous streaming interface.

[0079] It is understandable that by batch aggregating and sending the feature frames of the processed L2 data through an asynchronous streaming interface, continuous non-blocking data transmission can be achieved using the asynchronous streaming channel, and the number of network communication handshakes and protocol header overhead can be reduced through the batch aggregation mechanism.

[0080] Step S33: The processed L3 level data is reported periodically through a low-priority batch interface at preset time intervals.

[0081] It should be understood that by reporting the processed L3 level data at preset time intervals through a low-priority batch interface, such as every 30 seconds, or other values, this embodiment does not limit this; the low-priority queue can be used to avoid occupying high bandwidth resources and the frequency of communication interaction can be reduced by combining the timed batch sending mechanism.

[0082] Step S34: When the feature value of the L2 level data exceeds the preset abnormal feature threshold, the device is determined to be in an abnormal state.

[0083] It is understandable that by determining that the device has entered an abnormal state when the feature value of the L2 level data exceeds the preset abnormal feature threshold, real-time status assessment can be performed based on the key process features extracted from the edge side.

[0084] Step S35: Under the abnormal state, switch the processing strategy of the L2 level data from feature frame mode to full waveform backhaul mode, and reduce the sampling frequency of the L3 level data.

[0085] It should be understood that by switching the processing strategy of the L2 level data from feature frame mode to full waveform backhaul mode and reducing the sampling frequency of the L3 level data under the abnormal state, the complete backhaul of high-value original waveform data can be prioritized to support in-depth analysis during the critical period of equipment fault diagnosis, while uplink bandwidth resources can be released by reducing the sampling frequency of non-critical auxiliary data.

[0086] Step S36: After the abnormal state is eliminated, the processing strategies for the L2 level data and the L3 level data are restored to normal after a preset hysteresis time.

[0087] It is understandable that by restoring the processing strategies of the L2 and L3 data to normal after a preset hysteresis time when the abnormal state is eliminated, the repeated switching of processing strategies caused by the frequent jumps between normal and abnormal device states due to signal fluctuations can be avoided.

[0088] In the specific implementation, the protocol adaptation layer features pluggable multi-protocol access: a unified protocol adapter cluster is deployed on the edge side to support access to multiple protocols such as Modbus, OPC UA, MTConnect, MQTT, and HTTP through a pluggable architecture.

[0089] Each protocol corresponds to an adapter plugin, which implements a unified data access interface: connection management, data reading, data writing, and status monitoring. Heterogeneous protocols are normalized into internal standard data frames, including: device identifier, measurement point identifier, timestamp, numerical value, and quality bits.

[0090] Plugin dynamic loading mechanism: The edge gateway loads protocol adapter plugins in .so or .dll format based on the operating system's dynamic link interface (dlopen / dlsym under Linux, LoadLibrary / GetProcAddress under Windows).

[0091] Each plugin must implement a unified six-interface specification: init (initialize and register protocol metadata), handshake (perform protocol handshake and authentication), read (collect data according to the configured measurement point list and sampling period), write (issue control commands), heartbeat (periodically maintain connection activity), and unload (safely disconnect and release resources).

[0092] The plugin package includes a JSON Schema file describing the supported device types, configuration parameters, and data models. The platform layer uses this self-description of the schema for automatic configuration verification, ensuring zero code modification when adding a new protocol. Each plugin also carries a digital signature, which is verified for integrity before the gateway loads to prevent malicious plugin injection.

[0093] Protocol handshake state machine: Each device connection instance maintains a six-state state machine, with the following state transitions: IDLE (initial / disconnection) → HANDSHAKING (TCP / serial port connection establishment in progress) → AUTHENTICATING (protocol layer authentication in progress, such as OPC UA certificate verification) → READY (connection ready, normal data acquisition) → DEGRADED (heartbeat timeout or data quality degradation, reduced acquisition frequency and alarm) → ERROR (unrecoverable error, triggering reconnection).

[0094] Automatic reconnection after disconnection follows an exponential backoff strategy: Initially waits 1 second, doubling the wait time after each failure (backoff factor = 2), up to a maximum of 60 seconds. An operational alarm is reported after more than 10 cumulative reconnections. The pseudocode for the state machine is shown below: function transition(event): if state == READY and event == HEARTBEAT_TIMEOUT: state = DEGRADED; reduce_sample_rate(0.5) elif state == DEGRADED and event == HEARTBEAT_OK: state = READY; restore_sample_rate() elif state in [DEGRADED, HANDSHAKING] and event == MAX_RETRY: state = ERROR; emit_alert("device_unreachable", deviceId) elif state == ERROR and event == MANUAL_RESET: state = IDLE; schedule_reconnect(backoff=1s) Data hierarchical processing layer: hierarchical according to business priority: Normalized data is divided into three levels according to business priority: Level 1 (safety interlocks, emergency stop signals) is processed locally immediately without waiting to be uploaded to the cloud; Level 2 (equipment status, key process parameters) is preprocessed at the edge and then reported in batches; Level 3 (ambient temperature and humidity, auxiliary energy consumption) is compressed and sampled and then reported periodically.

[0095] Three-dimensional classification decision function: The classification result is determined by the three-dimensional decision function Level = f(signalType, deviceSafetyLevel, sysLoad), and the three dimensions are defined as follows: signalType: Signal type encoding, encoding rules are as follows: Emergency stop / safety interlock signal = 0x01, key process parameters (directly affecting processing quality) = 0x02, equipment operating status (indirect monitoring) = 0x03, auxiliary energy consumption / environmental parameters = 0x04; deviceSafetyLevel: The safety integrity level of the source device, defined according to the IEC 61508 standard, SIL1 (low risk) / SIL2 (medium risk) / SIL3 (high risk, such as emergency stop circuits involving personal safety). sysLoad: The current comprehensive load index of the edge gateway (0~100), which is a weighted calculation of three factors: CPU utilization, IO queue depth, and uplink bandwidth utilization.

[0096] An example of a decision matrix is ​​shown in Table 1 below: Table 1. Example of a decision matrix:

[0097] The above matrix guarantees that signalType=0x01 (emergency stop / interlock) will always be L1 regardless of the load, and will never be downgraded; under high load, only the auxiliary parameter (L3') will be downsampled, and only the reporting window of the key process parameter (L2) will be narrowed, without losing feature information.

[0098] Edge-based intelligent preprocessing layer: Feature extraction and anomaly detection: Feature extraction is performed on the edge side of L2 level high-frequency data (such as vibration signals).

[0099] The vibration signal sampling rate is configured to 10000 Hz (Nyquist frequency 5000 Hz, fully covering the 2000~3000Hz tool chipping characteristic frequency band), and is collected at the configured frequency through the read interface of the protocol adapter, allowing maintenance personnel to adjust the sampling rate online without restarting the gateway.

[0100] Set a local trigger for the emergency stop signal (L1 level): when the vibration energy exceeds the threshold, the stop signal is triggered immediately without cloud-based decision-making.

[0101] Edge FFT Seven-Step Pipeline: For L2 level vibration signals, the following seven-step feature extraction pipeline is performed on the edge side: Step ① Sampling window buffer: Accumulate 1024 sampling points in a ring buffer, corresponding to a time window of 102.4 ms at a sampling rate of 10000Hz; Step ② DC removal: Calculate the average value of 1024 points within the window and subtract it from each point to eliminate DC bias interference from the sensor; Step ③ Windowing: Multiply the 1024 data points by the Hanning window function w(n) = 0.5 × (1 - cos(2πn / 1023)) to suppress spectral leakage; adopt a 50% overlap strategy (adjacent windows offset by 512 points), with a refresh cycle of about 51.2 ms, to ensure that anomalous features are not truncated by the window boundaries; Step 4: FFT Transformation: Call the radix-2 Cooley-Tukey algorithm (or hardware-accelerated FFTW library) to perform a 1024-point complex FFT, with an output frequency resolution of ≈9.77 Hz / bin; Step 5: Frequency band energy integration: Divide the frequency bands according to the ISO 10816 vibration assessment standard, and integrate the power spectral density of all frequency bins in each frequency band: low frequency band 0~500 Hz (mechanical resonance / imbalance), mid frequency band 500~2000 Hz (gear meshing / bearing defects), high frequency band 2000~3000 Hz (tool chipping characteristic frequency band); Step 6 Threshold Comparison: A dynamic adaptive threshold mechanism is adopted, where the threshold = baseline energy × dynamic multiplier. The baseline energy is automatically updated through sliding mean filtering (window length = the results of the most recent 100 FFTs); the dynamic multiplier is adjusted according to the tool life stage (new tool multiplier = 3.0, mid-term wear multiplier = 2.5, near tool change point multiplier = 2.0), and the tool life stage is automatically determined by the cutting time and cumulative cutting amount. Step ⑦ Anomaly Marking: Encapsulate the three frequency band energy values, RMS effective value, peak value, and feature_flag (normal / warning / abnormal levels) into a feature frame and send it up. Feature frame format: 3 frequency band energy (32-bit floating point) + RMS (32-bit floating point) + peak value (32-bit floating point) + baseline energy (32-bit floating point) + feature flag (8-bit enumeration) = approximately 25 bytes in total, which is only about 4 kbps compared to the original waveform (10000 Hz × 16 bit = 160 kbps) (compression ratio of approximately 40:1).

[0102] Unified Southbound / Northbound Interface Layer: Masking Protocol Differences The southbound interface connects to heterogeneous devices (through a protocol adaptation layer), while the northbound interface connects to the platform model layer via a standardized REST / gRPC protocol.

[0103] The platform layer does not need to be aware of the underlying protocol differences; it only needs to process standard data frames. When adding a new device type, only the corresponding protocol adapter plugin needs to be developed; no modification to the platform layer code is required.

[0104] Differentiated QoS Strategy for Northbound Interfaces: To address the different timeliness requirements of L1 and L2 level data, the northbound gRPC interface employs a differentiated quality of service strategy: L1 level security events are delivered to the northbound interface via a high-priority asynchronous interface to achieve non-blocking reporting and ensure that local security responses are unaffected by network conditions; L2 level feature frames are transmitted asynchronously via gRPCServerStream, allowing for batch aggregation before sending and reducing connection establishment overhead; L3 level auxiliary data is batch POSTed via REST and reported periodically at 30-second intervals. This design isolates the potential impact of high-frequency L2 / L3 traffic on L1 control events at the interface level, forming a second line of priority defense at the interface layer.

[0105] Hard real-time security interlocking and traffic diversion mechanism: To address the fundamental problem of security signal delay caused by TCP head-of-line blocking, the L1-level security interlock signal has a dedicated hard interrupt priority processing path within the edge gateway, completely decoupling it from ordinary tasks such as protocol parsing, FFT preprocessing, and batch reporting at the OS layer. The specific implementation is as follows: Hardware interrupt binding: Level 1 safety sensors such as emergency stop buttons, safety light curtains, and overtravel switches are directly connected to the edge gateway hardware via GPIO digital input ports. The GPIO pins are configured in edge-triggered interrupt mode (IRQ), and the interrupt controller (GIC / NVIC) routes the interrupt to a dedicated processing core.

[0106] Exclusive CPU Core Isolation: At startup, the edge gateway operating system (Preempt-RTLinux or real-time Linux kernel) isolates CPU core 0 (Core0) from the general scheduling queue using the isolcpus kernel parameter, running only the safety interlocking processing kernel thread. This kernel thread employs the Linux real-time scheduling policy SCHED_FIFO with the highest priority (rtprio=99), exceeding the scheduling priority of all ordinary processes (SCHED_OTHER / NICE) and protocol parsing threads, FFT calculation threads, and network reporting threads on the same machine.

[0107] Bypassing user-space queues and TCP / IP protocol stack: When a GPIO interrupt is triggered, the kernel thread executes the safety response logic directly from the interrupt context: pulls the CNC device's safety input port (GPIO output) low or sends a FeedHold instruction via the industrial EtherCAT / PROFINET real-time bus; the entire processing path does not pass through any user-space message queues, does not pass through the Linux TCP / IP protocol stack, and does not wait for network I / O responses.

[0108] End-to-end latency analysis: The complete path timing from GPIO interrupt to CNC response is as follows: GPIO edge trigger → interrupt controller response (<1μs) → Preempt-RT kernel thread wake-up (<1ms) → safe response logic execution (<1ms) → GPIO / bus output control instructions (<1ms). The total end-to-end latency is ≤3~5ms, which meets the 10ms safe trigger window requirement and is reduced by about 97.5% compared with the 200ms latency of the traditional unified queue scheme.

[0109] The structural difference from general IoT Edge solutions: The priority queues of existing general edge platforms (such as AWS IoT Greengrass) remain at the user-space message middleware level and are still affected by TCP layer congestion control; This invention sinks the L1 signal processing path to the kernel real-time scheduling layer, fundamentally eliminating the possibility of high-frequency vibration data blocking safety signals. This design choice is a non-obvious technical decision for the 10ms safety window requirement of the mold / injection molding industry.

[0110] Data tiering dynamic upgrade / downgrade strategy: After an anomaly detection is triggered, static hierarchical configuration can no longer meet the conflicting needs of "requiring more diagnostic information during anomalies while simultaneously needing to release bandwidth to ensure a secure channel." This mechanism implements dynamic hierarchical adjustment based on anomaly states: Abnormal state triggering: When the FFT seven-step pipeline (step ⑥) detects that the high-frequency band (2000~3000Hz) energy is greater than or equal to the baseline energy × dynamic ratio, the device enters the mode=ABNORMAL abnormal state, and simultaneously: The device automatically downsamples all L3 auxiliary data to 1 / 10 of the original frequency (to release bandwidth), and the L3 data reporting interval is extended from 30 seconds to 5 minutes. The device automatically upgrades the L2 level vibration signal to a full waveform return (RawWaveformUpload) for N seconds (default N=60s, configurable) to allow for detailed spectrum review analysis and tool life modeling in the cloud. Hysteresis recovery strategy: To avoid frequent level oscillations (chattering) near the abnormal threshold, a hysteresis time T_hys (default 30s) is introduced: that is, after the abnormality is eliminated, the normal conditions must be met for T_hys seconds before the level state can be restored to normal; if the abnormality occurs again within T_hys, the timer is reset.

[0111] Cross-device linkage degradation: When the total bandwidth utilization rate of the workshop exceeds 85% (the overall system is under high load), the L3 level data of the entire workshop is uniformly downgraded to 1 / 10 sampling rate, so as to ensure that the transmission bandwidth of L1 safety channel and L2 key process data is not affected.

[0112] Upgrade / downgrade status log: All upgrade / downgrade events are recorded in the local audit log (deviceId, trigger reason, upgrade / downgrade direction, timestamp, frequency band energy value at the time of triggering), for maintenance personnel to trace and analyze production line processes.

[0113] The pluggable protocol adaptation architecture of this invention is not a simple superposition of "modularization = pluggable". Its non-obviousness is reflected in the following three aspects: Level 1: Self-description of Schema enables zero modification at the platform layer: In the traditional plug-in architecture, adding a new protocol still requires the platform layer to update the device type registry and modify the data entry logic.

[0114] This invention requires each plugin package to be accompanied by a JSON Schema file, in which the Schema declares all possible measurement point types, numerical ranges, quality bit meanings, and exception code definitions for the protocol; the platform layer dynamically generates the database mapping based on the Schema, and the platform layer code does not need to be modified when adding any protocol (Plugin-Driven Platform Design).

[0115] Level 2: Plug-in signature verification ensures industrial safety and compliance: Industrial control systems require strict control over the source of software components (IEC 62443 safety standard requirements).

[0116] This invention requires that protocol plugins must be signed by the edge gateway manufacturer or a certified third party, and verified by RSA-2048 / ECDSA signature before being loaded by the gateway; plugins that are not signed or whose signature verification fails are refused to be loaded, in order to prevent supply chain attacks and unauthorized protocol access. This is an industrial security mechanism that is lacking in general IoT Edge platforms.

[0117] Level 3: Coordinated design of protocol handshake state machine and L1 hard real-time traffic offloading: Protocol adaptation layer and hard real-time traffic offloading mechanism are not designed independently; When the protocol adapter of a device enters the DEGRADED or ERROR state, all L1 signals of the device are automatically switched to the backup GPIO hardwired channel (bypassing the software protocol stack), ensuring that even if the protocol communication fails, the safety interlock signal can still be reached; this deep collaboration between the protocol layer and the security layer is the key structural feature that distinguishes this invention from general solutions.

[0118] The graded processing parameters of this invention are customized to differentiate for the following four typical industrial manufacturing scenarios: Scenario 1: High-speed milling of molds (CNC 5-axis milling center) Key safety signals: Spindle vibration over-limit emergency stop (L1), overtravel protection (L1) Key process signals: spindle vibration (L2, sampling rate 10000 Hz, FFT target frequency band 2000~3000 Hz, anomaly magnification 3.0), spindle current (L2, sampling rate 1000 Hz). Auxiliary signals: Spindle temperature (L3, sampling rate 1 Hz), coolant flow rate (L3, sampling rate 0.1 Hz) Security trigger window: ≤10 ms Typical equipment: 40-100 five-axis machining centers Scenario 2: EDM (Electrical Discharge Machining) Key safety signals: Arc short circuit protection (L1), Overcurrent protection (L1) Key process signals: Discharge current pulse (L2, sampling rate 50000 Hz, FFT target feature: pulse peak value and width change rate), electrode gap voltage (L2, sampling rate 10000 Hz). Auxiliary signals: medium temperature (L3, sampling rate 0.1 Hz), electrode wear (L3, recorded for each electrode change). Security trigger window: ≤5 ms Dynamic upgrade / downgrade: When the arc short-circuit rate > 5%, an abnormal state is triggered, and the electrode gap monitoring data is upgraded to full data transmission. Scenario 3: Monitoring the clamping force of an injection molding machine Key safety signals: Hydraulic overpressure protection (L1), safety door interlock (L1) Key process signals: Clamping force curve (L2, sampling rate 200 Hz, anomaly detection: pressure drop ≥8% for ≥100 ms), injection pressure (L2, sampling rate 500 Hz). Auxiliary signals: mold temperature (L3, sampling rate 1 Hz), ambient temperature and humidity (L3, sampling rate 0.1 Hz) Safety trigger window: ≤50 ms (the response time requirement for injection molding machines is relatively lenient) Mold temperature controller linkage: When an abnormal clamping force is triggered, a cooling command is simultaneously sent to the mold temperature controller. Scenario 4: Mold Temperature Controller Linkage Control Key safety signals: Over-temperature protection (L1), heater overcurrent (L1) Key process signal: Mold temperature gradient (L2, sampling rate 10 Hz, warning: heating rate > 5 °C / min) Auxiliary signal: Cooling water flow rate (L3, sampling rate 1 Hz) Linkage logic: When the mold temperature controller triggers the L2 warning, the auxiliary temperature data of the associated injection molding machine automatically rises from L3 to L2 and is reported in real time.

[0119] In the actual implementation, when the edge gateway starts up, it automatically scans the protocol adapter plugins in the plugins directory and loads the MTConnect adapter, OPC UA adapter, Modbus adapter, etc.

[0120] Each adapter plugin registers its own information with the adapter manager: supported protocol types, version numbers, and configuration parameter schemas. The administrator configures device access information through the management interface: Device ID = CNC-001, Protocol Type = MTConnect, Connection Address = tcp: / / 192.168.1.100:7878, Sampling Frequency = 10000Hz (vibration) / 1Hz (temperature), Measurement Point List = Spindle Vibration, Spindle Temperature, Feed Speed. The adapter manager matches the corresponding adapter plugin based on the protocol type, creates a device connection instance, and begins data acquisition.

[0121] Plugin loading and signature verification process: Before loading each .so plugin, the adapter manager first reads the .sig signature file in the same directory and uses the RSA-2048 public key to verify the digital signature of the plugin binary file; after the signature verification is successful, dlopen is called to load the dynamic library, obtain the init symbol address and call the initialization function; the initialization function returns plugin metadata (protocol name, version, schema reference path); based on this, the adapter manager dynamically constructs device configuration verification rules and data entry mapping table from the schema file.

[0122] The entire process is completed during the gateway startup phase, taking approximately 100-500 ms, and does not affect the formal data collection startup.

[0123] CNC-001 handshake process: After the MTConnect adapter is loaded, the state machine moves from IDLE → HANDSHAKING (establishing a TCP connection) → AUTHENTICATING (sending a GET request to obtain the MTConnect Agent capability description document) → READY (parsing the DataItem list, establishing sampling point mapping, and starting a 10000 Hz vibration sampling cycle).

[0124] If the TCP connection fails after 3 retries, the state machine transitions to ERROR, triggering an alarm "CNC-001 connection failed". At the same time, the L1 safety signal of the device is switched to the backup GPIO hardwired channel for continued monitoring.

[0125] Data collected from the CNC-001 is classified according to the following rules: spindle vibration signal (10000Hz) is classified as L2 (critical process parameter) and reported in batches after edge preprocessing; spindle temperature signal (1Hz) is classified as L3 (auxiliary monitoring) and reported once per minute after compressed sampling; emergency stop button signal is classified as L1 (safety interlock) and processed locally immediately.

[0126] Examples of actual values ​​for the 3D decision matrix (CNC-001) are shown in Table 2 below: Table 2. Examples of actual values ​​for the three-dimensional decision matrix:

[0127] The aforementioned hierarchical decision is executed in real time after the normalization layer is completed and before entering the processing queue. The hierarchical delay for each data frame is less than 0.1 ms, which does not constitute a processing bottleneck.

[0128] Edge intelligent preprocessing and anomaly detection Edge preprocessing of spindle vibration signal (L2 level): 1024 points are accumulated at a sampling rate of 10000Hz (takes about 102ms), and FFT seven-step pipeline is executed; FFT is performed with 1024-point Hanning window and 50% overlap to calculate the energy of 2000~3000Hz frequency band.

[0129] If the frequency band energy exceeds a preset threshold (e.g., 3 times the normal energy), it is judged as abnormal, the abnormal state is immediately marked, and the characteristic value is uploaded to the cloud. If the frequency band energy is normal, only the effective value (RMS) and peak value are uploaded to the cloud once per minute.

[0130] FFT calculation details (CNC-001 vibration signal example): Sampling rate: 10000Hz; Window length: 1024 points; Window duration: 102.4ms; Refresh cycle: 51.2ms (50% overlap); Frequency resolution: 10000 / 1024 ≈ 9.77 Hz / bin; The 2000-3000Hz frequency band corresponds to frequencies bins 205-307; Step ⑤ Integrate the sum of squares of the amplitudes of approximately 103 bins in this frequency band to obtain the high-frequency band energy E_high; Step 6 Comparison: E_high > E_baseline × 3.0 (Tool status: New tool, magnification 3.0) → Determined as abnormal; Step 7: Write the feature frame: {deviceId:"CNC-001",pointId:"spindle_vib",ts:...,E_low:0.12,E_mid:0.31,E_high:1.87,rms:2.35,peak:8.2,baseline:0.62,feature_flag:"ALARM"}.

[0131] Data volume uploaded to the cloud: 25-byte feature frame × (1000ms / 51.2ms) ≈ approximately 20 frames per second ≈ 500B / s, with a compression ratio of approximately 40:1 compared to the original waveform of 160kbps.

[0132] Set a local hard trigger for emergency stop signals (L1 level): after the signal is triggered, the stop command is directly output to the CNC device with a response delay of <5ms, and the event is marked in the cloud for post-event analysis.

[0133] Hard interrupt binding path (CNC-001 emergency stop signal): The emergency stop button is connected to the edge gateway GPIO input pin (Pin3, configured as a falling edge IRQ) via a 24V hardwired connection. The SCHED_FIFO99 kernel thread rt-safety-handler is bound to the isolated CPU core (Core0, isocpus=0). When the interrupt is triggered: ① Read the GPIO input register to confirm the edge (<1μs); ② Execute the safety response function, setting the GPIO output pin (Pin5) low to drive the CNC safety input (FeedHold) (<1ms); ③ Record the safety event to the local log (<0.5ms); ④ Asynchronously (non-blocking) deliver the event notification to the northbound interface (without waiting). No malloc calls, file system access, or network I / O are performed throughout the process, ensuring deterministic latency. Measured latency: Approximately 2.3ms from interrupt trigger to GPIO output (99.9th percentile, 1000 measurement samples).

[0134] Standardized data on the cloud After hierarchical processing and edge preprocessing, the data is uniformly encapsulated into standard data frames for cloud upload: Device Identifier = CNC-001, Measurement Point Identifier = spindle_vibration, Timestamp = 2024-01-15T08:30:00.000Z, Value = 2.35 (valid value), Quality Bits = GOOD, Feature Marker = NORMAL. The platform layer receives data frames through a standard REST API, without needing to be aware of the underlying MTConnect protocol details. When a new Modbus PLC device is added, only the Modbus adapter plugin needs to be loaded and the connection parameters configured; no modifications are required at the platform layer.

[0135] After the northbound gRPC interface generates an anomaly flag, it delivers the L1 level alarm event to the MES / APS platform via a high-priority asynchronous interface. Upon receiving the event notification, the MES system suspends the current work order on CNC-001, and the APS system reschedules subsequent work orders to other idle machines. The entire business linkage response is completed within 50 ms, effectively preventing invalid work orders from continuing to be put into production.

[0136] Dynamic upgrade / downgrade and exception handling: When the FFT pipeline detects that the energy in the 2000~3000 Hz frequency band of the CNC-001 spindle vibration is ≥3×baseline, the following dynamic upgrade / downgrade linkage is triggered: ① Upgrade the full waveform transmission of the L2 vibration signal: The edge gateway immediately switches the CNC-001 vibration acquisition channel from the "feature frame mode" to the "full waveform mode", and uploads the original 10,000 Hz sampled data in real time for 60 seconds (configurable) for the cloud vibration analysis system to perform refined diagnosis and tool life modeling; ② Degrade the L3 auxiliary data to release bandwidth: At the same time, extend the reporting interval of L3 auxiliary measurement points such as coolant flow and spindle temperature of CNC-001 from 1 minute to 10 minutes (the sampling rate is reduced to 1 / 10), and release about 8% of the bandwidth for full waveform upload; ③ MES / APS service linkage: Deliver an exception event notification to the MES system through the northbound gRPC asynchronous interface. MES completes service linkage within 50 ms after receiving the notification, suspends the current work order of CNC-001, and APS reschedules subsequent work orders; ④ Hysteresis recovery: After the abnormal state is eliminated (E_high < E_baseline × 2.5, below the trigger threshold of 3.0 to ensure the hysteresis effect), start a 30-second timer (T_hys = 30 s); if an abnormality occurs again before the timer ends, restart the timer; after the timer ends, restore the vibration data to the feature frame mode and the L3 auxiliary data to the 1-minute reporting interval; ⑤ Upgrade and downgrade event recording: Write all upgrade and downgrade operations into the local audit log (including the band energy value at the trigger moment, the upgrade and downgrade direction, and the duration), and summarize it daily and upload it to the cloud in batches with the L3-level data for process engineers to analyze the tool wear pattern.

[0137] Differentiated implementation for injection molding machine / EDM scenarios: Clamping force monitoring for injection molding machine (taking the 250 t injection molding machine INJ-001 as an example): The injection molding machine INJ-001 is accessed through the Modbus TCP protocol, and the Modbus adapter configures the clamping force register address (holding registers 40001~40010) to collect at a sampling frequency of 200 Hz. Hierarchical determination: The hydraulic overpressure signal (digital input coil 0x0001) is L1 level; the clamping force curve (40001) is L2 level; the temperature of the mold temperature controller (40005) is L3 level.

[0138] Preprocessing of the L2-level clamping force curve (replacing FFT, using the sliding window difference algorithm): Calculate the clamping force decline rate with a 100-point sliding window (corresponding to a 500 ms time period); if the decline rate ≥ 8% and the duration ≥ 100 ms (corresponding to 20 consecutive sampling points), it is determined as a flash or cavity damage abnormality, generate an L1 alarm and trigger injection interruption; synchronously send a cooling instruction to the mold temperature controller linkage controller (to prevent local overheating caused by insufficient clamping).

[0139] This scenario does not require an FFT pipeline; instead, a sliding window difference algorithm is used, with a computational complexity of O(N), which can be completed within a 5ms sampling period. It uses the same hierarchical framework as CNC vibration monitoring but employs a different preprocessing algorithm, demonstrating the pluggable nature of the algorithm in this invention.

[0140] EDM (Electronic Discharge Machining) Monitoring (Taking Forming Machine EDM-001 as an Example): The EDM-001 connects via the OPC UA protocol and collects discharge current pulses (50,000 Hz sampling) and electrode gap voltage (10,000 Hz sampling).

[0141] Level L1 is the arc short-circuit protection signal (IEC 61508 SIL2), Level L2 is the discharge current pulse and gap voltage, and Level L3 is the dielectric liquid temperature and electrode loss count.

[0142] L2 level discharge current preprocessing: Calculate the average peak current and pulse width of continuous pulses using a 256-point window (corresponding to a 5.12 ms time period); if the width of three consecutive pulses shortens by more than 20% (indicating an arc short circuit trend), reduce the discharge energy (send an OPC UA Write command to adjust the pulse width parameter) and trigger an early warning; if the short circuit protection signal is triggered (L1), immediately shut off the discharge power supply through the hard interrupt path.

[0143] The following example, using the monitoring of CNC equipment in a mold manufacturing workshop, illustrates the application effect of this invention.

[0144] Example 1: High-speed milling workshop for molds Application Background A precision mold manufacturing workshop mainly processes automotive stamping dies and injection molds. The typical workpiece material is Cr12MoV hardened steel (heat treated to HRC58). The five-axis machining center has a spindle speed of 12,000 rpm, a feed rate of 3,000 mm / min, and uses 12 mm diameter carbide end mills.

[0145] The workshop has 40 CNC machines communicating via the MTConnect protocol, 10 PLCs using the Modbus protocol, 5 AGVs using the ROS protocol, and 20 environmental sensors using the MQTT protocol. The traditional solution involves deploying a separate data acquisition gateway for each protocol (4 in total), resulting in complex maintenance and inconsistent data formats.

[0146] The CNC spindle vibration data is sampled at 1000Hz, and all of it is uploaded to the cloud, which causes bandwidth constraints. Emergency stop signals are delayed by about 200ms after being relayed through the cloud.

[0147] Traditional solutions result in approximately 3.8 instances of tool breakage leading to mold scrapping per year, with an average loss of about 350,000 yuan per instance, and an annual loss of about 1.33 million yuan.

[0148] Implementation Results and Quantitative Comparison After adopting the unified access method of this invention, the following are six-dimensional comparison data between the traditional 4-gateway solution and the solution of this invention: Number of access gateways: Traditional solution has 4 independent gateways (1 each of MTConnect / OPC UA / Modbus / AGV) → This solution has 1 unified edge gateway with a unified operation and maintenance management interface; Uplink bandwidth usage: Traditional solution (vibration 1000 Hz full upload to cloud) about 6 Mbps → This solution (10000 Hz sampling + FFT feature extraction) about 1.8 Mbps, a reduction of about 70%; Although the sampling rate of this solution is increased to 10000Hz, the amount of data is significantly reduced after feature extraction, and the bandwidth reduction is more significant at the same sampling rate.

[0149] End-to-end delay of emergency stop signal: Traditional solution with cloud relay is about 200 ms → This solution with local response to hard interrupt is about 3 ms (99.9th percentile measured), a reduction of about 98.5%, meeting the 10 ms safety window requirement; Number of mold scrapping incidents due to tool chipping (annual average): approximately 3.8 times with the traditional solution → approximately 0.5 times with this solution (thanks to the early warning system in the 2000~3000 Hz frequency band that triggers tool replacement in advance), a reduction of approximately 87%; Average annual loss due to mold scrap: approximately 1.33 million yuan with the traditional solution → approximately 175,000 yuan with this solution, saving approximately 1.15 million yuan per year; New protocol access time (taking the addition of OPC UA protocol equipment as an example): Traditional solution takes about 1 week (new purchase of OPC UA gateway + debugging + data format integration) → This solution takes about 1 hour (loading OPC UA adapter plugin + configuration parameters + joint debugging), shortening the time by about 98%.

[0150] Example 2: Monitoring of Clamping Force in Injection Molding Machine A certain injection mold workshop is equipped with 15 250-ton injection molding machines, mainly producing automotive interior parts, with typical workpiece materials being ABS+PC modified materials. The injection molding machines use the Modbus TCP protocol, while the mold temperature controller uses a custom HTTP protocol. Traditional solutions deploy separate Modbus data acquisition gateways and HTTP polling scripts, resulting in inconsistent data formats. Furthermore, abnormal clamping force is only detected by the MES system through 5-minute polling, failing to achieve real-time response.

[0151] After adopting this invention: The Modbus TCP adapter samples the clamping force curve at 200 Hz (the holding register of INJ-001), and the HTTP adapter samples the mold temperature controller temperature at 1 Hz, both connected to the same edge gateway. The L1 level hydraulic overpressure protection signal (digital input) is processed through GPIO hard interrupt, with a response delay of ≤5 ms; The L2 level clamping force curve uses a sliding window differential algorithm (100-point window, detecting ≥8% pressure drop for ≥100 ms). Upon detecting flash abnormality, it immediately triggers injection interruption and links the mold temperature controller to cool down. Implementation results: The scrap rate of flash decreased from 1.2% to 0.15% (a reduction of approximately 87.5%), the response delay of the mold temperature controller decreased from 5 minutes (manual detection) to approximately 200 ms (automatic edge linkage), and the capacity utilization rate of the injection molding machine increased by approximately 3.5% (reducing downtime for mold cleaning due to flash).

[0152] Example 3: Monitoring of EDM (Electrical Discharge Machining) A precision mold workshop is equipped with 8 mirror EDM forming machines to process the precision surfaces of hardened steel mold cavities.

[0153] The EDM device uses the OPC UA protocol to collect discharge current pulses (50000 Hz) and gap voltages (10000 Hz).

[0154] Traditional solutions require uploading all data to the cloud (approximately 80 Mbps bandwidth), which is severely insufficient. In practice, the average current is polled at only 1 Hz, making it impossible to achieve pulse-level anomaly detection.

[0155] After adopting this invention: The OPC UA adapter connects at the highest configured sampling rate, and L2 level discharge current pulse data is extracted at the edge side using a 256-point window pulse feature extraction (peak current, pulse width, pulse ratio), with only statistical features uploaded to the cloud (approximately 1 kbps / channel, a reduction of approximately 99% compared to the original approximately 100 kbps). The L1 level arc short circuit protection signal is processed by GPIO hard interrupt. When three consecutive pulse widths are detected to be shortened by more than 20%, an early warning is triggered, and the OPC UA Write instruction reduces the discharge energy. Implementation results: Electrode losses caused by arc short circuits have been reduced from about 12 times per year (each loss of electrode value is about 2,000 yuan + 2 hours of downtime) to about 2 times, saving about 20,000 yuan and about 20 hours of downtime per year. EDM accuracy consistency (surface roughness Ra) has been improved by about 15% (thanks to stable control of discharge parameters).

[0156] Alternative Solution 1: Independent Safety PLC Hardwiring Solution Solution Description: An independent safety PLC (such as a Siemens S7-1500F safety PLC, SIL3 certified) is used to directly receive L1 level safety sensor signals from all emergency stop buttons, safety light curtains, overtravel switches, etc. via hardwiring. The safety PLC runs the safety program independently and does not rely on any network communication; process data (L2 / L3) are still collected and uploaded to the cloud by ordinary PLCs / gateways.

[0157] Advantages: Meets IEC 61508 SIL3 safety integrity level, reliability is certified by authoritative authorities, and it is suitable for scenarios with personnel safety risks (CE certification compliant).

[0158] Disadvantages and limitations: High wiring costs: Each CNC machine tool requires additional hard wiring for safety circuits (approximately 1525 24V signal lines). Including labor costs, the additional cost for each machine tool is approximately 250,000 yuan, and the additional cost for 30 machine tools is approximately 600,000 to 1,500,000 yuan. Unable to obtain vibration spectrum information: The safety PLC only responds to digital switch signals (0 / 1 transitions) and cannot analyze the energy change trend of the 2000~3000 Hz frequency band of the vibration waveform. It cannot provide early warning of tool wear and can only respond to chipping that has already occurred afterward. Expansion difficulties: Adding new machine tools requires rewiring and cannot be expanded via software; multi-workshop, cross-location collaborative monitoring requires the independent deployment of multiple safety PLC systems, making it impossible to form a unified data view.

[0159] Compared to the present invention: The present invention achieves a response speed equivalent to hard-wiring a safety PLC (≤5 ms) through edge gateway GPIO hard interrupts + Preempt-RT kernel real-time scheduling. It also additionally provides vibration spectrum prediction capabilities (10-60 seconds advance warning of blade breakage), unified multi-protocol access capabilities, and configurable software scalability, reducing wiring costs by approximately 85% (eliminating the need for separate safety circuits on each machine tool). The present invention represents a non-obvious combination that simultaneously outperforms alternatives in both "cost reduction" and "functional expansion."

[0160] Alternative Solution 2: Cloud-based Hard Real-Time Solution Based on 5G uRLLC Slicing Solution Description: Deploy a 5G private network in the workshop and enable uRLLC (Ultra-Reliable Low-Latency Communication) slicing to uniformly transmit vibration data and safety signals back to the cloud. The cloud will then make centralized decisions and issue control commands, leveraging the end-to-end latency of 5G uRLLC to meet safety triggering requirements.

[0161] Advantages: No need to modify the on-site edge gateway architecture; control logic is centralized in the cloud, facilitating unified management and AI model iteration.

[0162] Disadvantages and limitations: The deployment cost is extremely high: the deployment of 5G private network in the mold workshop requires the construction of indoor base stations (approximately RMB 50.8 million per BBU+RRU) + 5G core network transformation (UPF / SMF slicing configuration, approximately RMB 2.005 billion) + terminal module replacement (approximately RMB 3,000 to 8,000 per 5G module), and the total investment is difficult for ordinary mold manufacturing enterprises to bear; SLA Dependence on Carriers: uRLLC latency guarantees rely on carrier network SLA contracts, which enterprises cannot control independently; in workshop radio frequency interference environments (welding sparks, high-frequency induction heating), unstable 5G signal quality may lead to SLA degradation; Incompatible with existing IT assets: Existing industrial Ethernet, Modbus serial port, OPC UA and other protocol devices in the workshop cannot be directly connected to the 5G network and require an additional protocol gateway layer, which does not fundamentally eliminate the protocol fragmentation problem; Data security concerns: The transmission of core process parameters of the factory via public network / carrier network poses a risk of industrial data leakage. Some industries (aviation, military) do not allow control data to leave the factory.

[0163] Compared with the present invention: The present invention achieves a ≤5 ms secure response on the existing industrial Ethernet (100 Mbps / 1 Gbps) infrastructure through an edge computing solution. The total solution cost (approximately RMB 5.15 million for the edge gateway + approximately RMB 10.3 million for plug-in development) is reduced by more than 90% compared to the 5G private network solution (several million RMB). It is completely independent of the operator's SLA, 100% of the factory data is stored locally, it is compatible with existing industrial protocol equipment, and has stronger evolution capabilities.

[0164] This embodiment achieves non-blocking reporting by sending event notifications from the processed L1 level data to the northbound interface via a high-priority asynchronous interface; it aggregates and sends the feature frames of the processed L2 level data in batches via an asynchronous streaming interface; it reports the processed L3 level data at preset time intervals via a low-priority batch interface; when the feature value of the L2 level data exceeds a preset abnormal feature threshold, the device is determined to be in an abnormal state; in the abnormal state, the processing strategy of the L2 level data is switched from feature frame mode to full waveform backhaul mode, and the sampling frequency of the L3 level data is reduced; when the... After the abnormal state is eliminated, the processing strategies for the L2 and L3 data are restored to normal after a preset hysteresis time. It can provide transmission service quality matching the importance of different levels of data through differentiated QoS interfaces, ensuring that the L1 security response is not affected by network congestion. When an abnormality is detected, the processing strategies and sampling rates of L2 and L3 data are intelligently and dynamically adjusted. Priority is given to ensuring the complete transmission of key diagnostic waveform data while releasing bandwidth resources. Combined with the hysteresis time mechanism, frequent policy oscillations are avoided, thereby achieving the overall optimal balance between data transmission reliability, fault diagnosis accuracy and system stability in network resource-constrained scenarios.

[0165] Accordingly, the present invention further provides a unified access device for multi-protocol edge devices.

[0166] Reference Figure 6 , Figure 6 This is a functional block diagram of the first embodiment of the multi-protocol edge device unified access device of the present invention.

[0167] In a first embodiment of the multi-protocol edge device unified access device of the present invention, the multi-protocol edge device unified access device includes: The data segmentation module 10 is used to acquire the raw data of heterogeneous devices accessed through the plug-in protocol adaptation layer, and to use a preset three-dimensional hierarchical judgment function to segment the raw data into L1 level safety interlock data, L2 level key process data and L3 level auxiliary monitoring data.

[0168] Data processing module 20 is used to respond to the hardware interrupt signal generated by the L1 level safety interlock data, trigger the isolated CPU core to directly process the data to bypass the user-mode message queue, perform feature extraction preprocessing on the L2 level key process data at the edge side, and perform compressed sampling on the L3 level auxiliary monitoring data.

[0169] The strategy adjustment module 30 is used to report the processed L1, L2 and L3 data through a differentiated QoS interface, and dynamically adjust the processing strategy and sampling rate of the L2 and L3 data according to the abnormal status monitored in real time.

[0170] The steps for implementing each functional module of the multi-protocol edge device unified access device can be referred to in the various embodiments of the multi-protocol edge device unified access method of the present invention, and will not be repeated here.

[0171] Furthermore, this embodiment of the invention also proposes a storage medium storing a unified access program for multi-protocol edge devices. When the unified access program for multi-protocol edge devices is executed by a processor, it implements the operations described in the above embodiment of the unified access method for multi-protocol edge devices.

[0172] Those skilled in the art will understand that all or part of the steps in the methods described above can be implemented by a program instructing related hardware. The program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium is a computer-readable storage medium, including: USB flash drive, mobile hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and other media that can store program code.

[0173] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0174] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0175] The above are merely preferred embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A unified access method for multi-protocol edge devices, characterized in that, The unified access method for multi-protocol edge devices includes: The raw data of heterogeneous devices accessed through the plug-in protocol adaptation layer is obtained, and the raw data is divided into L1 level safety interlock data, L2 level key process data and L3 level auxiliary monitoring data using a preset three-dimensional classification judgment function. In response to the hardware interrupt signal generated by the L1 level safety interlock data, the isolated CPU core is triggered to directly process the data to bypass the user-mode message queue, and feature extraction preprocessing is performed on the L2 level key process data at the edge side, and compressed sampling is performed on the L3 level auxiliary monitoring data. The processed L1, L2, and L3 data are reported through a differentiated QoS interface, and the processing strategies and sampling rates of the L2 and L3 data are dynamically adjusted based on real-time monitored abnormal states.

2. The unified access method for multi-protocol edge devices as described in claim 1, characterized in that, The process of acquiring raw data from heterogeneous devices accessed via a plug-in protocol adaptation layer, and then using a preset three-dimensional hierarchical judgment function to divide the raw data into L1-level safety interlock data, L2-level key process data, and L3-level auxiliary monitoring data, includes: The protocol adapter plugin is loaded through the operating system's dynamic link interface to obtain raw data from heterogeneous devices. The signal type encoding, source device security integrity level, and edge gateway current comprehensive load index are used as input dimensions for the preset three-dimensional classification judgment function; The original data is divided into L1 level safety interlock data, L2 level key process data and L3 level auxiliary monitoring data according to the preset three-dimensional classification judgment function.

3. The unified access method for multi-protocol edge devices as described in claim 2, characterized in that, The process of loading a protocol adapter plugin through the operating system's dynamic link interface to obtain raw data from heterogeneous devices includes: Protocol adapter plugins are loaded via the operating system's dynamic link interface. Each plugin package includes a JSONSchema file to describe the device type, configuration parameters, and data model. Based on the JSONSchema file, database mapping and configuration verification rules are dynamically generated to ensure that no modifications are needed to the platform layer code when adding a new protocol. Before loading the protocol adapter plugin, verify the digital signature of each plugin package. If the verification fails, refuse to load the protocol adapter plugin. After loading the protocol adapter plugin, the raw data of the heterogeneous device is obtained.

4. The unified access method for multi-protocol edge devices as described in claim 2, characterized in that, The process of dividing the raw data into L1-level safety interlock data, L2-level key process data, and L3-level auxiliary monitoring data according to the preset three-dimensional classification judgment function includes: When the signal type is encoded as an emergency stop or safety interlock signal, it is forcibly determined to be L1 level safety interlock data regardless of the load index. When the signal type encoding is not an emergency stop or safety interlock signal, the source device's safety integrity level is higher than a preset safety threshold, and the edge gateway's current comprehensive load index is lower than a preset load threshold, it is determined to be L2 level critical process data. When the current comprehensive load index of the edge gateway is higher than the preset load threshold, the reporting window is narrowed; When the security integrity level of the source device is not higher than the preset security threshold, and the signal type is encoded as a device status signal, it is determined to be L2 level key process data low-frequency reporting; otherwise, it is determined to be L3 level auxiliary monitoring data.

5. The unified access method for multi-protocol edge devices as described in claim 1, characterized in that, The hardware interrupt signal generated in response to the L1 level safety interlock data triggers the isolated CPU core to directly process the data, bypassing the user-mode message queue. Feature extraction preprocessing is performed on the L2 level critical process data at the edge side, and compressed sampling is performed on the L3 level auxiliary monitoring data, including: In response to the hardware interrupt signal generated by the L1 level safety interlock data, the hardware interface for receiving L1 level safety interlock data is configured to edge-triggered interrupt mode. When the operating system starts, a specified CPU core is isolated from the general scheduling queue, and a secure interlocking kernel process is run on the specified CPU core to bypass the user-mode message queue. The original signal segments divided into the L2 level key process data are extracted, and a sampling window is formed by accumulating a preset number of sampling points in the L2 level key process data through a circular buffer. The L2-level key process data within the sampling window is processed by DC removal, windowing, and fast Fourier transform. The frequency bands are divided according to a preset standard, and the power spectral density within each frequency band is integrated to generate a feature frame containing frequency band energy values ​​and anomaly markers. The raw data stream divided into the L3 level auxiliary monitoring data is obtained, and the reporting frequency of the L3 level auxiliary monitoring data is reduced by a time-slicing downsampling strategy. A compression algorithm is applied to the downsampled L3 auxiliary monitoring data to reduce the data packet size.

6. The unified access method for multi-protocol edge devices as described in claim 5, characterized in that, The step of isolating a designated CPU core from the general scheduling queue during operating system startup and running a secure interlocking kernel process on the designated CPU core to bypass the user-mode message queue includes: When the operating system starts, a designated CPU core is isolated from the general scheduling queue, and a security interlock processing kernel thread dedicated to processing the L1 level security interlock data is run on the designated CPU core. The security interlock processing kernel thread adopts a real-time scheduling strategy and has a higher priority than ordinary processes and protocol parsing threads. When the L1-level security interlock data triggers a hardware interrupt, the security interlock processing kernel thread directly executes the security response logic for the L1-level security interlock data from the interrupt context, without going through the user-mode message queue and network I / O response.

7. The unified access method for multi-protocol edge devices as described in claim 1, characterized in that, The process of reporting the processed L1, L2, and L3 data through a differentiated QoS interface, and dynamically adjusting the processing strategies and sampling rates of the L2 and L3 data based on real-time monitored abnormal states, includes: The processed L1 level data is sent to the northbound interface via a high-priority asynchronous interface to achieve non-blocking reporting. The processed L2 level data feature frames are aggregated and sent in batches via an asynchronous streaming interface; The processed L3 level data will be reported periodically at preset time intervals via a low-priority batch interface. When the feature value of the L2 level data exceeds the preset abnormal feature threshold, the device is determined to be in an abnormal state. In the abnormal state, the processing strategy for the L2 level data is switched from feature frame mode to full waveform backhaul mode, and the sampling frequency of the L3 level data is reduced. Once the abnormal state is eliminated, the processing strategies for the L2 and L3 data are restored to normal after a preset hysteresis time.

8. A unified access device for multi-protocol edge devices, characterized in that, The unified access device for multi-protocol edge devices includes: The data segmentation module is used to acquire the raw data of heterogeneous devices accessed through the plug-in protocol adaptation layer, and to use a preset three-dimensional hierarchical judgment function to segment the raw data into L1 level safety interlock data, L2 level key process data and L3 level auxiliary monitoring data. The data processing module is used to respond to the hardware interrupt signal generated by the L1 level safety interlock data, trigger the isolated CPU core to process directly to bypass the user-mode message queue, perform feature extraction preprocessing on the L2 level key process data at the edge side, and perform compressed sampling on the L3 level auxiliary monitoring data. The strategy adjustment module is used to report the processed L1, L2 and L3 data through a differentiated QoS interface, and dynamically adjust the processing strategy and sampling rate of the L2 and L3 data according to the abnormal status monitored in real time.

9. A unified access device for multi-protocol edge devices, characterized in that, The multi-protocol edge device unified access device includes: a memory, a processor, and a multi-protocol edge device unified access program stored in the memory and executable on the processor. The multi-protocol edge device unified access program is configured to implement the steps of the multi-protocol edge device unified access method as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, The storage medium stores a unified access program for multi-protocol edge devices, which, when executed by a processor, implements the steps of the unified access method for multi-protocol edge devices as described in any one of claims 1 to 7.

Images