Short-wave radio station based on FPGA and realizing network port multi-socket expansion and communication method thereof
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING PANDA HANDA TECH
- Filing Date
- 2026-06-04
- Publication Date
- 2026-08-07
AI Technical Summary
传统电台想要实现与多台设备通信，需要增加网口PHY芯片，这必然增加了硬件成本
[0015]本发明与现有技术相比，其显著优点为：（1）利用了FPGA的逻辑资源，通过FPGA软件设计，实现了单片PHY芯片网口多socket拓展的目标，依靠FPGA的可编程性，结合PHY芯片，搭建数据高效分发与接收的桥梁，降低了短波电台硬件设计成本，提升了资源利用效率；（2）软硬件协同运用，实现了灵活的网口配置和管理，DSP软件层面通过EMIF口仅需要配置IP地址、端口号、子网掩码、网关，就能直接使用网口的多个socket，实现单台短波电台与多台接入设备通信，增强了系统的通信能力，增强了系统的灵活性，节约了硬件成本，能够适应复杂多变的通信需求。
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Figure CN122534152A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of shortwave radio technology, and in particular to a shortwave radio and its communication method based on FPGA-based multi-socket network port expansion. Background Technology
[0002] In the field of shortwave communication technology, the requirements for network communication capabilities of various devices are increasing. Currently, shortwave radios often need to interact with multiple devices simultaneously. However, traditional shortwave radios, limited by hardware architecture and cost considerations, are often equipped with only a very limited number of physical network ports, far from meeting the application scenarios requiring simultaneous connection to multiple external devices or multi-channel data transmission. Therefore, how to achieve data communication with multiple devices while maintaining the cost of radio hardware has become an urgent problem to be solved in the networking application of shortwave radios.
[0003] Traditional shortwave radio communication technology has some drawbacks in terms of cost and flexibility. To enable communication with multiple devices, traditional radios require additional network port PHY chips, which inevitably increases hardware costs. Furthermore, changing the number of network ports for different application scenarios necessitates redesigning the hardware layout and wiring, resulting in poor flexibility in practical use and increased development and maintenance costs. Summary of the Invention
[0004] The purpose of this invention is to provide a shortwave radio and its communication method based on FPGA to implement multi-socket expansion of network ports, so as to enhance the communication capability and flexibility of the shortwave radio system, save hardware costs, and adapt to complex and ever-changing communication needs.
[0005] The technical solution to achieve the purpose of this invention is: a shortwave radio based on FPGA to implement multi-socket expansion of network ports, including a main control DSP, an FPGA chip, an Ethernet PHY chip, and a switch;
[0006] The main control DSP is connected to the FPGA chip via an EMIF interface;
[0007] The FPGA chip is connected to the Gigabit Ethernet PHY chip, and the Gigabit Ethernet PHY chip is connected to the switch. The switch is used to connect multiple access devices.
[0008] The FPGA chip has multiple sockets created inside it. Each socket is bound to a local IP address, a local port number, a remote IP address, a remote port number, a subnet mask, and a gateway. The multiple sockets share the underlying hardware resources of the Gigabit Ethernet PHY chip.
[0009] The main control DSP configures the IP address, port number, subnet mask and gateway of each socket to the FPGA chip through the EMIF interface, and indicates the IP identifier of the remote device when sending data;
[0010] The FPGA chip determines the corresponding socket based on the IP identifier of the remote device, encapsulates data packets according to the Ethernet protocol based on the parameters bound to the socket, and sends the encapsulated data packets to the corresponding access device through the Gigabit Ethernet PHY chip and the switch.
[0011] The FPGA chip is also used to receive network interface data packets from the access device via the switch and the gigabit Ethernet PHY chip, parse the IP source of the network interface data packets, strip the network interface protocol information, add a socket address identifier, and transmit the processed data packets to the main control DSP through the EMIF interface.
[0012] A communication method for a shortwave radio with multi-socket network port expansion based on FPGA, the communication method comprising:
[0013] Data transmission steps: The main control DSP transmits the data to be sent and the IP identifier of the remote device to the FPGA chip through the EMIF interface; the FPGA chip determines the corresponding socket according to the IP identifier of the remote device, encapsulates the data packet according to the Ethernet protocol based on the parameters bound to the socket, and sends the encapsulated data packet to the corresponding access device through the Gigabit Ethernet PHY chip and the switch;
[0014] Data reception steps: The FPGA chip receives network data packets from the access device via the switch and the Gigabit Ethernet PHY chip, parses the IP source, strips the network protocol information, adds a socket address identifier, and then transmits the data to the main control DSP through the EMIF interface.
[0015] Compared with the prior art, the present invention has the following significant advantages: (1) It utilizes the logic resources of FPGA and achieves the goal of expanding the network port of a single PHY chip to multiple sockets through FPGA software design. Relying on the programmability of FPGA and combined with the PHY chip, it builds a bridge for efficient data distribution and reception, reduces the hardware design cost of shortwave radio, and improves the efficiency of resource utilization; (2) The software and hardware work together to achieve flexible network port configuration and management. At the DSP software level, only the IP address, port number, subnet mask, and gateway need to be configured through the EMIF port to directly use multiple sockets of the network port, realize communication between a single shortwave radio and multiple access devices, enhance the communication capability of the system, enhance the flexibility of the system, save hardware costs, and adapt to complex and ever-changing communication needs. Attached Figure Description
[0016] Figure 1 This is a block diagram of a shortwave radio based on FPGA to implement multi-socket expansion of network ports.
[0017] Figure 2 This is a flowchart illustrating the process of expanding network ports with multiple sockets based on FPGA in this invention. Detailed Implementation
[0018] This invention provides a shortwave radio based on FPGA to implement multi-socket expansion of network ports, including a main control DSP, an FPGA chip, an Ethernet PHY chip, and a switch;
[0019] The main control DSP is connected to the FPGA chip via an EMIF interface;
[0020] The FPGA chip is connected to the Gigabit Ethernet PHY chip, and the Gigabit Ethernet PHY chip is connected to the switch. The switch is used to connect multiple access devices.
[0021] The FPGA chip has multiple sockets created inside it. Each socket is bound to a local IP address, a local port number, a remote IP address, a remote port number, a subnet mask, and a gateway. The multiple sockets share the underlying hardware resources of the Gigabit Ethernet PHY chip.
[0022] The main control DSP configures the IP address, port number, subnet mask and gateway of each socket to the FPGA chip through the EMIF interface, and indicates the IP identifier of the remote device when sending data;
[0023] The FPGA chip determines the corresponding socket based on the IP identifier of the remote device, encapsulates data packets according to the Ethernet protocol based on the parameters bound to the socket, and sends the encapsulated data packets to the corresponding access device through the Gigabit Ethernet PHY chip and the switch.
[0024] The FPGA chip is also used to receive network interface data packets from the access device via the switch and the gigabit Ethernet PHY chip, parse the IP source of the network interface data packets, strip the network interface protocol information, add a socket address identifier, and transmit the processed data packets to the main control DSP through the EMIF interface.
[0025] As a specific example, the main control DSP communicates with the FPGA chip only through the EMIF interface, without setting up other data interfaces.
[0026] As a specific example, the FPGA chip is also used to generate an ARP reply packet when it receives an ARP request packet from an access device, and send it to the access device through the Gigabit Ethernet PHY chip and the switch.
[0027] As a specific example, the FPGA chip is also used to detect and update the MAC address of the IP address corresponding to the ARP reply packet when it receives the ARP reply packet sent by the access device, and to determine whether the MAC addresses of all remote IP addresses that need to communicate have been successfully updated.
[0028] If not all updates are successful, ARP request packets will be sent to the IP addresses that were not successfully updated at the first sending interval;
[0029] If all updates are successful, ARP request packets are sent to all remote IP addresses at the second sending interval, where the first sending interval is shorter than the second sending interval.
[0030] As a specific example, the data receiving and processing method is as follows:
[0031] The FPGA chip determines the ARP request packet sending interval according to the following formula:
[0032] T = 1s, when N > 0;
[0033] T = 5s, when N = 0;
[0034] Where T represents the ARP request packet sending interval, and N represents the number of remote IP addresses that failed to update their MAC addresses.
[0035] As a specific example, when the FPGA chip encapsulates the data packet to be sent from the main control DSP into an Ethernet data packet, it detects whether the MAC address corresponding to the destination IP address of the data packet has been successfully updated.
[0036] If the update has been successful, fill in the corresponding MAC address in the destination MAC address field of the Ethernet packet;
[0037] If the update is unsuccessful, fill in the broadcast MAC address in the destination MAC address field of the Ethernet packet.
[0038] This invention also provides a communication method for a shortwave radio with multi-socket network port expansion based on FPGA, the communication method comprising:
[0039] Data transmission steps: The main control DSP transmits the data to be sent and the IP identifier of the remote device to the FPGA chip through the EMIF interface; the FPGA chip determines the corresponding socket according to the IP identifier of the remote device, encapsulates the data packet according to the Ethernet protocol based on the parameters bound to the socket, and sends the encapsulated data packet to the corresponding access device through the Gigabit Ethernet PHY chip and the switch;
[0040] Data reception steps: The FPGA chip receives network data packets from the access device via the switch and the Gigabit Ethernet PHY chip, parses the IP source, strips the network protocol information, adds a socket address identifier, and then transmits the data to the main control DSP through the EMIF interface.
[0041] As a specific example, the communication method further includes a MAC address maintenance step: when the FPGA chip receives an ARP reply packet sent by the access device, it detects and updates the MAC address of the corresponding IP; the FPGA chip determines whether the MAC addresses of all remote IPs that need to communicate have been successfully updated; if not all have been successfully updated, it sends ARP request packets to the IPs that have not been successfully updated at a first sending interval; if all have been successfully updated, it sends ARP request packets to all remote IPs at a second sending interval, wherein the first sending interval is shorter than the second sending interval.
[0042] As a specific example, the FPGA chip determines the ARP request packet sending interval according to the following formula:
[0043] T = 1s, when N > 0;
[0044] T = 5s, when N = 0;
[0045] Where T represents the ARP request packet sending interval, and N represents the number of remote IPs whose MAC addresses were not successfully updated.
[0046] As a specific example, in the data transmission step, when the FPGA chip encapsulates the data packet, it detects whether the MAC address corresponding to the destination IP of the data packet has been updated; if it has been updated, the corresponding MAC address is filled in the destination MAC address field of the Ethernet data packet; if it has not been updated, the broadcast MAC address is filled in the destination MAC address field of the Ethernet data packet.
[0047] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0048] Example 1
[0049] like Figure 1As shown, the present invention provides a shortwave radio based on FPGA to implement multi-socket expansion of network ports, including a main control DSP, an FPGA chip, an Ethernet PHY chip, and a switch.
[0050] The main control DSP is connected to the FPGA chip via an EMIF interface; the FPGA chip is connected to the Ethernet PHY chip via multiple RGMII / GMII interfaces; the Ethernet PHY chip is connected to the switch via an RJ45 interface; the switch is then connected to multiple access devices via Ethernet ports; the main control DSP transmits data to the FPGA chip via the EMIF interface, and the FPGA chip uses the Ethernet PHY chip to distribute the data to multiple access devices via the switch; the multiple access devices transmit data to the Ethernet PHY chip via the switch, and the FPGA chip processes the data and transmits it back to the main control DSP, enabling simultaneous communication between a single shortwave radio and multiple access devices.
[0051] Preferably, the main control DSP communicates with the FPGA chip only through the EMIF port, without the need for other data interfaces.
[0052] Preferably, the method for the FPGA chip to implement multi-socket expansion of the network port is as follows:
[0053] At the software level, the main control DSP only needs to manage the IP address, port number, subnet mask, and gateway through the EMIF port, and indicate to the FPGA chip the IP address of the remote device to which the current data packet needs to be sent when sending data packets.
[0054] At the driver level, the FPGA chip binds the data content to the local IP address, local port number, remote IP address, remote port number, subnet mask, and gateway parameters, and sends the corresponding data packets to the specified device network port according to the network port protocol. Each socket shares the underlying hardware resources of the gigabit network port.
[0055] Each socket is independent in the system, and users can use any one or more sockets to communicate independently with the access device.
[0056] Preferably, the data transmission processing is implemented as follows:
[0057] The main DSP transmits the data to be sent to the FPGA chip through the EMIF port. The FPGA chip fills in the corresponding IP address, port number, subnet mask, gateway, and network protocol information in the data packet based on the socket address contained in the data packet. It then sends the data to the switch through the Ethernet PHY chip and to the corresponding access device through the network port, thus achieving correct data distribution.
[0058] Preferably, the data receiving and processing method is as follows:
[0059] When the FPGA chip receives network data packets from the access device, it parses the IP source of the data packets, identifies the location in the shared RAM corresponding to the current IP, removes the network protocol information from the data packets, fills in the socket address, and transmits the data to the main control DSP through the EMIF port, thus achieving correct data reception.
[0060] Example 2
[0061] This embodiment provides a shortwave radio based on FPGA to implement multi-socket expansion of the network port, such as... Figure 1 As shown, the main control DSP and FPGA chip communicate via the EMIF port. Multiple sockets are designed inside the FPGA chip, and the main control DSP specifies which socket to use. Based on the specified identifier, the corresponding MAC address, IP address, gateway, subnet mask, etc. are bound, and data packets are packaged according to the network port protocol and sent to the Ethernet PHY chip. Data packets from multiple sockets are shared by the Ethernet PHY chip and sent to the corresponding access device network port on the switch, realizing communication between multiple access devices and the radio.
[0062] like Figure 2 As shown, when the main control DSP needs to communicate with a certain access device, the shortwave radio network port will receive four types of data packets from the access device: ARP request packets, ARP reply packets, subscription information packets, and service data packets.
[0063] 1. If the radio's network port receives an ARP request packet sent by the access device, the communication steps for a shortwave radio with multi-socket network port expansion based on FPGA are as follows:
[0064] Step 1.1: The FPGA chip replies with an ARP request packet;
[0065] Step 1.2: The ARP request packet is sent to the access device through the Ethernet PHY chip.
[0066] 2. If the radio's network port receives an ARP reply packet from the access device, the communication steps for a shortwave radio with multi-socket network port expansion based on FPGA are as follows:
[0067] Step 2.1: The FPGA chip detects and updates the MAC address;
[0068] Step 2.2: Determine whether all MAC addresses have been updated successfully;
[0069] Step 2.3: If the MAC address is not completely updated successfully, send ARP requests to the IPs that have not been updated successfully at 1-second intervals; if the MAC address is completely updated successfully, send ARP request packets to all IPs in the list at 5-second intervals.
[0070] Step 2.4: The ARP request packet is sent to the access device through the Ethernet PHY chip.
[0071] 3. If the radio's network port receives a subscription information packet sent by the access device, the communication steps for a shortwave radio with multiple socket expansions on the network port based on FPGA are as follows:
[0072] Step 3.1: The FPGA chip forwards the data packet to the DSP;
[0073] Step 3.2: The main control DSP identifies the subscription information, configures the IP information contained in the information into the IP list, informs the FPGA chip, and sends a subscription reply packet to the FPGA chip, proceeding to step 3.6;
[0074] Step 3.3: The FPGA chip checks whether the MAC address of the updated IP has been completely updated;
[0075] Step 3.4: If the MAC address is not completely updated successfully, send ARP requests to the IPs that have not been updated successfully at 1-second intervals; if the MAC address is completely updated successfully, send ARP request packets to all IPs in the list at 5-second intervals.
[0076] Step 3.5: The ARP request packet is sent to the access device through the Ethernet PHY chip;
[0077] Step 3.6: The FPGA chip successfully detects whether the MAC address of the IP corresponding to the service data packet is successfully checked.
[0078] Step 3.7: If the update is successful, fill in the corresponding MAC address in the destination MAC address field of the Ethernet packet; if the update is unsuccessful, fill in the broadcast MAC address in the destination MAC address field of the Ethernet packet.
[0079] Step 3.8: Ethernet data packets are sent to the access device through the Ethernet PHY chip.
[0080] 4. If the radio's network port receives service data packets sent by the access device, the communication steps for a shortwave radio with multi-socket expansion of the network port based on FPGA are as follows:
[0081] Step 4.1: The FPGA chip forwards the data packet to the main control DSP;
[0082] Step 4.2: The main control DSP replies with service data packets;
[0083] Step 4.3: The main control DSP sends the service data packet to the FPGA chip;
[0084] Step 4.4: The FPGA chip successfully detects whether the MAC address of the IP corresponding to the service data packet is successfully checked.
[0085] Step 4.5: If the update is successful, fill in the corresponding MAC address in the destination MAC address field of the Ethernet packet; if the update is unsuccessful, fill in the broadcast MAC address in the destination MAC address field of the Ethernet packet.
[0086] Step 4.6: Ethernet data packets are sent to the access device through the Ethernet PHY chip.
[0087] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A shortwave radio based on FPGA for multi-socket network port expansion, characterized in that, This includes the main control DSP, FPGA chip, Ethernet PHY chip, and switch; The main control DSP is connected to the FPGA chip via an EMIF interface; The FPGA chip is connected to the Gigabit Ethernet PHY chip, and the Gigabit Ethernet PHY chip is connected to the switch. The switch is used to connect multiple access devices. The FPGA chip has multiple sockets created inside it. Each socket is bound to a local IP address, a local port number, a remote IP address, a remote port number, a subnet mask, and a gateway. The multiple sockets share the underlying hardware resources of the Gigabit Ethernet PHY chip. The main control DSP configures the IP address, port number, subnet mask and gateway of each socket to the FPGA chip through the EMIF interface, and indicates the IP identifier of the remote device when sending data; The FPGA chip determines the corresponding socket based on the IP identifier of the remote device, encapsulates data packets according to the Ethernet protocol based on the parameters bound to the socket, and sends the encapsulated data packets to the corresponding access device through the Gigabit Ethernet PHY chip and the switch. The FPGA chip is also used to receive network interface data packets from the access device via the switch and the gigabit Ethernet PHY chip, parse the IP source of the network interface data packets, strip the network interface protocol information, add a socket address identifier, and transmit the processed data packets to the main control DSP through the EMIF interface.
2. The shortwave radio based on FPGA for multi-socket network port expansion according to claim 1, characterized in that, The main control DSP communicates with the FPGA chip only through the EMIF interface, and no other data interfaces are provided.
3. The shortwave radio based on FPGA for multi-socket network port expansion according to claim 1, characterized in that, The FPGA chip is also used to generate an ARP reply packet when it receives an ARP request packet from an access device, and send it to the access device through the Gigabit Ethernet PHY chip and the switch.
4. The shortwave radio based on FPGA for multi-socket network port expansion according to claim 1, characterized in that, The FPGA chip is also used to detect and update the MAC address of the IP address corresponding to the ARP reply packet when it receives the ARP reply packet sent by the access device, and to determine whether the MAC addresses of all remote IP addresses that need to communicate have been successfully updated. If not all updates are successful, ARP request packets will be sent to the IP addresses that were not successfully updated at the first sending interval; If all updates are successful, ARP request packets are sent to all remote IP addresses at the second sending interval, where the first sending interval is shorter than the second sending interval.
5. The shortwave radio based on FPGA for multi-socket network port expansion according to claim 4, characterized in that, The data receiving and processing method is as follows: The FPGA chip determines the ARP request packet sending interval according to the following formula: T = 1s, when N > 0; T = 5s, when N = 0; Where T represents the ARP request packet sending interval, and N represents the number of remote IP addresses that failed to update their MAC addresses.
6. The shortwave radio based on FPGA for multi-socket network port expansion according to claim 1, characterized in that, When the FPGA chip encapsulates the data packet to be sent from the main control DSP into an Ethernet data packet, it detects whether the MAC address corresponding to the destination IP address of the data packet has been successfully updated. If the update has been successful, fill in the corresponding MAC address in the destination MAC address field of the Ethernet packet; If the update is unsuccessful, fill in the broadcast MAC address in the destination MAC address field of the Ethernet packet.
7. A communication method for a shortwave radio based on FPGA for multi-socket network port expansion as described in any one of claims 1 to 6, characterized in that, The communication method includes: Data transmission steps: The main control DSP transmits the data to be sent and the IP identifier of the remote device to the FPGA chip through the EMIF interface; the FPGA chip determines the corresponding socket according to the IP identifier of the remote device, encapsulates the data packet according to the Ethernet protocol based on the parameters bound to the socket, and sends the encapsulated data packet to the corresponding access device through the Gigabit Ethernet PHY chip and the switch; Data reception steps: The FPGA chip receives network data packets from the access device via the switch and the Gigabit Ethernet PHY chip, parses the IP source, strips the network protocol information, adds a socket address identifier, and then transmits the data to the main control DSP through the EMIF interface.
8. The communication method according to claim 7, characterized in that, It also includes a MAC address maintenance step: when the FPGA chip receives an ARP reply packet sent by the access device, it detects and updates the MAC address of the corresponding IP; the FPGA chip determines whether the MAC addresses of all remote IPs that need to communicate have been successfully updated; if not all have been successfully updated, it sends ARP request packets to the IPs that have not been successfully updated according to the first sending interval. If all updates are successful, then ARP request packets are sent to all remote IPs at the second sending interval, where the first sending interval is shorter than the second sending interval.
9. The communication method according to claim 8, characterized in that, The FPGA chip determines the ARP request packet sending interval according to the following formula: T = 1s, when N > 0; T = 5s, when N = 0; Where T represents the ARP request packet sending interval, and N represents the number of remote IPs whose MAC addresses were not successfully updated.
10. The communication method according to claim 7, characterized in that, In the data transmission step, when the FPGA chip encapsulates the data packet, it detects whether the MAC address corresponding to the destination IP of the data packet has been updated; if it has been updated, the corresponding MAC address is filled in the destination MAC address field of the Ethernet data packet. If not updated, fill in the broadcast MAC address in the destination MAC address field of the Ethernet packet.