Packet processing device

Abstract

The present disclosure provides a packet processing device. The device comprises: an analysis unit configured to obtain a plurality of network packets, and analyze the plurality of network packets to obtain respective analysis results; a port determination unit configured to determine, according to port information of a plurality of ports, the plurality of analysis results, and available storage space of the port determination unit, a split bit width of each of the plurality of analysis results; determine, according to the split bit width, a processing parameter of each of the plurality of analysis results, and determine, according to the plurality of processing parameters, a target port in the plurality of ports; and a sending unit configured to send the network packets via the target port. The device can improve packet processing efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of communication data processing technology, and in particular to a message processing apparatus. Background Technology

[0002] With the advent of programmable network chips, it has become possible to quickly meet the needs of customized data processing. In the application of programmable network chips, it is sometimes necessary to process network packets and determine the forwarding port of the network packets in order to deliver the network packets to the next level device.

[0003] In related technologies, network packets that need to be processed are sent to the control plane for processing and then returned. However, the transmission of larger data is slow and does not meet the line-speed requirements of network packet processing.

[0004] Therefore, the relevant technologies suffer from low processing efficiency when dealing with large amounts of network packet data. Summary of the Invention

[0005] In view of this, the present disclosure provides a message processing apparatus.

[0006] One aspect of this disclosure provides a message processing apparatus, comprising: a parsing unit, configured to acquire multiple network messages, parse the multiple network messages to obtain respective parsing results; a port determination unit, configured to obtain the split bit width of each of the multiple parsing results based on port information of multiple ports, multiple parsing results and available storage space of the port determination unit; determine the processing parameters of each of the multiple parsing results based on the split bit width, and determine the target port among the multiple ports based on the multiple processing parameters; and a sending unit, configured to send network messages via the target port.

[0007] According to embodiments of this disclosure, a parsing unit extracts the parsing result of each network packet to represent its key information. A port determination unit combines port information, parsing results, and available storage space to determine the bit width for splitting each parsing result. This bit width serves as the basis for splitting the parsing results, and based on the splitting, processing parameters for each parsing result are determined as the target port. This allows the sending unit to send network packets based on these parameters, improving packet processing efficiency. This achieves the determination of the target port of a network packet using its own parsing result, thus realizing path selection for traffic.

[0008] According to embodiments of this disclosure, determining processing parameters for each of the multiple parsing results based on the split bit width includes: splitting each parsing result into multiple sub-parsing results, wherein the bit width of each sub-parsing result is consistent with the corresponding split bit width; determining sub-processing parameters for each of the multiple sub-parsing results based on a first mapping relationship, wherein the first mapping relationship is used to record the correspondence between the sub-parsing results, port information, and sub-processing parameters; and obtaining the processing parameters corresponding to the parsing result based on the sum of the multiple sub-processing parameters and the port information.

[0009] According to the embodiments of this disclosure, by splitting the parsing results and obtaining sub-processing parameters, the processing difficulty can be reduced from the perspective of processing data size, preventing the chip's processing capacity from being exceeded, thereby improving processing efficiency. At the same time, the processing efficiency can be further improved by utilizing the first mapping relationship.

[0010] According to embodiments of this disclosure, port information includes the number of ports. Based on the port information of multiple ports, multiple parsing results, and the available storage space of the port determination unit, the splitting bit width of each of the multiple parsing results is obtained, including: determining a bit width threshold for the result obtained by dividing the sum of multiple sub-processing parameters by the number of ports based on the available storage space and the number of ports; for each parsing result, calculating the maximum number of segments obtained by splitting the parsing result based on the multiple preset candidate bit widths using the bit width threshold and multiple consecutive preset candidate bit widths; for each preset candidate bit width, calculating the maximum bit width that can be supported after concatenating multiple sub-parsing results when the bit width of the sub-parsing results obtained by splitting the parsing result is the preset candidate bit width and the number of sub-parsing results is the maximum number of segments; and for each parsing result, determining the splitting bit width of the parsing result based on the bit width of the parsing result, the multiple preset candidate bit widths, and the maximum bit width of each of the multiple preset candidate bit widths.

[0011] According to embodiments of this disclosure, limiting the bit width threshold using available storage space can prevent overflow of the result after summing multiple sub-processing parameters. Furthermore, by calculating the maximum representable bit width using multiple consecutive preset candidate bit widths and the maximum number of segments, and then comparing it with the bit width of the parsed result, the most suitable split bit width is selected. This prevents data overflow while ensuring that each segment after splitting contains sufficient data.

[0012] According to embodiments of this disclosure, determining a bit width threshold by quoting the sum of multiple sub-processing parameters with respect to port information based on available storage space and port information includes: obtaining the number of entries supported by the chip's unipolar pipeline based on available storage space; obtaining the bit width of the number of entries and the bit width of the number of ports based on the number of entries and the number of ports; and determining a bit width threshold obtained by dividing the sum of multiple sub-processing parameters by the number of ports based on the difference between the bit width of the number of entries and the bit width of the number of ports.

[0013] According to embodiments of this disclosure, a bit width threshold is calculated using the bit width of the number of entries and the bit width of the number of ports, thereby quantifying the usable bit width of the quotient result of the sum of multiple sub-processing parameters on the port information, and improving the efficiency of calculating the split bit width.

[0014] According to embodiments of this disclosure, determining the splitting bit width of the parsing result based on the bit width of the parsing result, multiple preset candidate bit widths, and the maximum bit width of each of the multiple preset candidate bit widths includes: if the bit width of the parsing result and the maximum bit width of each of the multiple preset candidate bit widths do not match, and if the bit width of the parsing result is between the maximum bit width of the previous preset candidate bit width and the maximum bit width of the current preset candidate bit width, then determining the splitting bit width of the parsing result based on the previous preset candidate bit width and the current preset candidate bit width.

[0015] According to embodiments of this disclosure, when the bit width of the parsing result and the maximum bit width of each of the multiple preset candidate bit widths do not match, the parsing result can be split using two different bit widths. This allows the parsing result to be split into integer multiples, and the number of segments obtained from the split is minimized, thus minimizing the number of sub-parsing results. This minimizes the number of table lookups required, reduces the table entry size, and improves processing efficiency.

[0016] According to an embodiment of this disclosure, the apparatus further includes: if the bit width of the parsing result matches one of the maximum bit widths of a plurality of preset candidate bit widths, the preset candidate bit width corresponding to the match is used as the split bit width of the parsing result.

[0017] According to the embodiments of this disclosure, if the bit width of the parsing result matches one of the maximum bit widths of the multiple preset candidate bit widths, it means that the parsing result can be split into integer multiples of the corresponding preset candidate bit width. This ensures that the number of sub-parsing results after splitting is small, and that each sub-parsing result can hold enough data without overflowing.

[0018] According to an embodiment of this disclosure, determining the splitting bit width of the parsing result based on the previous preset candidate bit width and the current preset candidate bit width includes: using the previous preset candidate bit width and the current preset candidate bit width as the splitting bit width of the parsing result, wherein the larger of the previous preset candidate bit width and the current preset candidate bit width is the splitting bit width with higher priority.

[0019] According to the embodiments of this disclosure, the larger value between the previous preset candidate bit width and the current preset candidate bit width is used as the bit width for priority splitting of the parsing result. This allows the split sub-parsing results to accommodate enough data without overflowing, and the number of corresponding sub-parsing results is relatively small. On this basis, the parsing result is further split using a smaller preset candidate bit width to ensure the integrity of the splitting.

[0020] According to embodiments of this disclosure, processing parameters corresponding to the parsing result are obtained based on the sum of multiple sub-processing parameters and port information, including: determining processing parameters of the sum of multiple sub-processing parameters based on a second mapping relationship and using them as processing parameters corresponding to the parsing result; the second mapping relationship is used to record the correspondence between the sum of multiple sub-processing parameters, port information and processing parameters.

[0021] According to embodiments of this disclosure, using a second mapping relationship to determine the processing parameters, which are the sum of multiple sub-processing parameters, can improve the efficiency and accuracy of processing.

[0022] According to embodiments of this disclosure, for each parsing result, the number of split bit widths is less than or equal to the maximum number of parallel tables supported by the chip pipeline.

[0023] According to embodiments of this disclosure, the number of split bit widths is limited, that is, the number of sub-parsing results after splitting is limited, thereby limiting the number of parallel tables to prevent exceeding the chip's capacity.

[0024] According to embodiments of this disclosure, for each parsing result, the number of times the multiple sub-processing parameters are summed is less than or equal to the number of chip pipeline stages.

[0025] According to embodiments of this disclosure, the number of summations is limited to restrict the number of chip pipeline stages, in order to prevent exceeding the chip's capacity.

[0026] Another aspect of this disclosure provides an electronic device, including: one or more processors; and a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors perform the method described above.

[0027] Another aspect of this disclosure provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the methods described above.

[0028] Another aspect of this disclosure provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0029] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0030] The above and other objects, features, and advantages of this disclosure will become clearer from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0031] Figure 1This schematically illustrates a structural block diagram of a message processing apparatus according to an embodiment of the present disclosure;

[0032] Figure 2 A flowchart illustrating a message processing method according to an embodiment of the present disclosure is shown schematically.

[0033] Figure 3 A flowchart illustrating a message processing method according to another embodiment of this disclosure is shown schematically;

[0034] Figure 4 A flowchart illustrating a message processing method according to another embodiment of this disclosure is shown schematically;

[0035] Figure 5 A flowchart illustrating the determination of subprocessing parameters according to one embodiment of the present disclosure is shown schematically;

[0036] Figure 6 A flowchart illustrating a message processing method according to another embodiment of this disclosure is shown schematically;

[0037] Figure 7 A schematic block diagram of an electronic device that can be used to implement the methods of embodiments of the present disclosure is shown. Detailed Implementation

[0038] The embodiments of this disclosure will now be described with reference to the accompanying drawings. Various details of the embodiments of this disclosure are included to aid understanding and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0039] In the technical solutions disclosed herein, the collection, storage, use, processing, transmission, provision, disclosure, and application of data (including but not limited to user personal information) comply with the provisions of relevant laws and regulations, necessary confidentiality measures have been taken, and they do not violate public order and good morals.

[0040] Programmable network chips themselves do not support complex arithmetic operations. Therefore, when processing network packets, such as performing modulo operations on the parsed results to determine the target port, alternative methods are needed to replace conventional modulo operations. For modulo values ​​of... In some cases, a mask can be used directly. However, by sending the data to be processed to the control plane for calculation and then returning it, the line-rate requirements for network packet processing cannot be met. Therefore, related technologies suffer from low processing efficiency when dealing with large amounts of network packet data.

[0041] Figure 1The schematic diagram illustrates a structural block diagram of a message processing apparatus according to an embodiment of the present disclosure.

[0042] like Figure 1 As shown, the message processing apparatus 100 of this embodiment includes a parsing unit 110, a port determination unit 120, and a sending unit 130.

[0043] The parsing unit 110 is used to acquire multiple network packets and parse them to obtain their respective parsing results. The port determination unit 120 is used to obtain the split bit width of each of the multiple parsing results based on the port information of multiple ports, the multiple parsing results, and the available storage space of the port determination unit; determine the processing parameters of each of the multiple parsing results based on the split bit width, and determine the target port among the multiple ports based on the multiple processing parameters; the sending unit 130 is used to send the network packet via the target port.

[0044] In some exemplary embodiments, for a programmable chip, the parsing unit 110 includes a parser module, the port determination unit 120 includes a match action unit (MAU), and the sending unit 130 includes a deparser module. When a network packet enters the chip, the parser module parses the network packet and stores the parsing result in the packet header vector (PHV). The PHV is then stored in the MAU, where the split bit width is obtained, the processing parameters are determined, and stored in the PHV. Finally, the PHV is sent to the deparser module, where the network packet is reassembled and forwarded.

[0045] Figure 2 A flowchart illustrating a message processing method according to an embodiment of the present disclosure is shown schematically.

[0046] like Figure 2 As shown, the message processing method of this embodiment includes operations S210 to S230.

[0047] In operation S210, the parsing unit acquires multiple network packets and parses them to obtain their respective parsing results.

[0048] Among them, network messages refer to the raw data packets transmitted in the network.

[0049] The parsing result represents the key fields extracted from the network packet. For example, the parsing result includes a 5-tuple, which consists of the source Internet Protocol address (IP address), destination IP address, source port number, destination port number, and protocol number.

[0050] In operation S220, the port determination unit obtains the split bit width of each of the multiple parsing results based on the port information of multiple ports, multiple parsing results, and the available storage space of the port determination unit; based on the split bit width, it determines the processing parameters of each of the multiple parsing results, and based on the multiple processing parameters, it determines the target port among the multiple ports.

[0051] The port information indicates the number of ports. For example, if chip A has 10 ports, then the number of ports is 10.

[0052] Available storage space represents the storage capacity allocated by the port determination unit for storing table entries. This storage capacity is provided by the memory in the port determination unit, including Static Random Access Memory (SRAM) and Ternary Content-Addressable Memory (TCAM). For example, available storage space includes the number of table entries supported by a single-stage pipeline of the chip, representing the maximum number of lookup table entries that storage resources can accommodate in a processing stage of the chip pipeline.

[0053] The splitting bit width refers to the bit width used to split the parsed result. For example, if the parsed result has a bit width of 30 bits, a splitting bit width of 6 bits can split it into 5 segments.

[0054] The processing parameters represent the parameters after processing the parsing results based on the split bit width, which are used to determine the target port.

[0055] The destination port indicates the port from which the network packet is sent.

[0056] It should be understood that after obtaining multiple network packets, in order to avoid congestion on a single link, it is necessary to ensure that the traffic is evenly distributed across multiple links. By processing the parsing results of each network packet, the corresponding processing parameters can be obtained, thereby obtaining the target port for sending network packets and realizing traffic diversion.

[0057] In operation S230, the sending unit sends network packets via the target port.

[0058] According to embodiments of this disclosure, a parsing unit extracts the parsing result of each network packet to represent its key information. A port determination unit combines port information, parsing results, and available storage space to determine the bit width for splitting each parsing result. This bit width serves as the basis for splitting the parsing results, and based on the splitting, processing parameters for each parsing result are determined as the target port. This allows the sending unit to send network packets based on these parameters, improving packet processing efficiency. This achieves the determination of the target port of a network packet using its own parsing result, thus realizing path selection for traffic.

[0059] In some exemplary embodiments, determining the processing parameters for each of the multiple parsing results based on the split bit width includes: for each parsing result, firstly, splitting the parsing result into multiple sub-parsing results; then, determining the sub-processing parameters for each of the multiple sub-parsing results based on a first mapping relationship; and finally, obtaining the processing parameters corresponding to the parsing result based on the sum of the multiple sub-processing parameters and port information.

[0060] In this process, the bit width of the sub-parse result is the same as the corresponding split bit width. For example, if the split bit width is 5 bits, then the bit width of the sub-parse result is 5 bits. If the parsing result cannot be split into an integer multiple of a certain split bit width, then there exists a sub-parse result whose bit width is inconsistent with the corresponding split bit width. For example, if the split bit width is 10 bits and the bit width of the parsing result is 25, then there exists a sub-parse result with a bit width of 5 bits.

[0061] The first mapping relationship is used to record the mapping relationship between the sub-parsing result, port information, and sub-processing parameters. The sub-processing parameters in the first mapping relationship represent the result of the sub-parsing result modulo the port information.

[0062] In practical applications, the first mapping relationship includes multiple sub-parsing results, multiple port numbers, and the result of taking the sub-parsing results modulo the port numbers. For example, if the multiple sub-parsing results are data A and data B, and the multiple port numbers are 5 and 10, then the corresponding modulo results include the result of taking data A modulo 5, the result of taking data A modulo 10, the result of taking data B modulo 5, and the result of taking data B modulo 10.

[0063] The processing parameter corresponding to the parsing result represents the result of taking the sum of multiple sub-processing parameters modulo the port information. For example, if the sum of multiple sub-processing parameters is data C and the number of ports is 5, then the processing parameter corresponding to the parsing result is the result of taking data C modulo 5.

[0064] According to the embodiments of this disclosure, by splitting the parsing results and obtaining sub-processing parameters, the processing difficulty can be reduced from the perspective of processing data size, preventing the chip's processing capacity from being exceeded, thereby improving processing efficiency. At the same time, the processing efficiency can be further improved by utilizing the first mapping relationship.

[0065] In some exemplary embodiments, port information includes the number of ports. Based on the port information of multiple ports, multiple parsing results, and the available storage space of the port determination unit, the split bit width of each of the multiple parsing results is obtained, including: determining a bit width threshold for the result obtained by dividing the sum of multiple sub-processing parameters by the number of ports based on the available storage space and the number of ports. For each parsing result, using the bit width threshold and multiple consecutive preset candidate bit widths, the maximum number of segments obtained by splitting the parsing result based on the multiple preset candidate bit widths is calculated. For each preset candidate bit width, if the bit width of the sub-parsing results obtained by splitting the parsing result is the preset candidate bit width, and the number of sub-parsing results is the maximum number of segments, the maximum bit width that can be supported after concatenating the multiple sub-parsing results is calculated. For each parsing result, the split bit width of the parsing result is determined based on the bit width of the parsing result, the multiple preset candidate bit widths, and the maximum bit width of each of the multiple preset candidate bit widths.

[0066] The bit width threshold represents the bit width threshold of the quotient obtained by summing multiple sub-processing parameters and then quotienting the port information. A clearly defined bit width threshold can prevent the result of summing multiple sub-processing parameters from overflowing and exceeding the chip's capacity.

[0067] The preset candidate bit width represents the preset bit width used to split the parsing result. Multiple consecutive preset candidate bit widths can be, for example, 4 bits, 5 bits, 6 bits, and 7 bits.

[0068] Calculate the maximum number of segments corresponding to each preset candidate bit width. In this embodiment, the bit width threshold is: The preset candidate bit width is The maximum number of segments is .

[0069] In this embodiment of the application, the maximum bit width that can be supported after concatenating multiple sub-parse results is calculated using the formula. calculate.

[0070] According to embodiments of this disclosure, limiting the bit width threshold using available storage space can prevent overflow of the result after summing multiple sub-processing parameters. Furthermore, by calculating the maximum representable bit width using multiple consecutive preset candidate bit widths and the maximum number of segments, and then comparing it with the bit width of the parsed result, the most suitable split bit width is selected. This prevents data overflow while ensuring that each segment after splitting contains sufficient data.

[0071] It should be understood that after summing multiple sub-processing parameters, the bit width of the summation result divided by the number of ports cannot exceed the available storage space. Therefore, the available storage space can be used to limit the bit width of the summation result. The ultimate goal is to obtain the processing parameters of the parsing result, which in some embodiments is to obtain the result of the parsing result modulo the port information, i.e., the result of the parsing result modulo the number of ports. The result of the parsing result modulo the number of ports is obtained by taking the sum of multiple sub-processing parameters modulo the number of ports. Therefore, the available storage space can be used to limit the bit width threshold of the result obtained by dividing the sum of multiple sub-processing parameters by the number of ports.

[0072] In some exemplary embodiments, determining a bit width threshold based on the sum of multiple sub-processing parameters divided by the number of ports, according to available storage space and the number of ports, includes: obtaining the number of entries supported by the chip's unipolar pipeline based on available storage space; obtaining the bit width of the number of entries and the bit width of the number of ports based on the number of entries and the number of ports; and determining the bit width threshold based on the difference between the bit width of the number of entries and the bit width of the number of ports.

[0073] In practical applications, the number of tables that a chip's single-stage pipeline can support for storage can be obtained from the chip's datasheet. For example, the number of tables that a chip's single-stage pipeline can support for storage is... If so, the bit width of the table entry number is 18.

[0074] When the bit width of the port number is used When representing, the bit width threshold is When the number of ports is 1000, take the power of 2 up to get the bit width of the port. =10.

[0075] In practical applications, modulo operations in network processing are commonly used in scenarios such as Equal Cost Multipath Routing (ECMP) and sampling, and the modulus is typically in the range of [missing information]. ~ In general, the modulus itself will not exceed the width of the table entries.

[0076] According to embodiments of this disclosure, a bit width threshold is calculated using the bit width of the number of entries and the bit width of the number of ports, thereby quantifying the bit width threshold obtained by dividing the sum of multiple sub-processing parameters by the number of ports, thus improving the efficiency of calculating the split bit width.

[0077] In some exemplary embodiments, determining the split bit width of the parsing result based on the bit width of the parsing result, multiple preset candidate bit widths, and the maximum bit width of each of the multiple preset candidate bit widths includes: if the bit width of the parsing result and the maximum bit width of each of the multiple preset candidate bit widths do not match, and if the bit width of the parsing result is between the maximum bit width of the previous preset candidate bit width and the maximum bit width of the current preset candidate bit width, then the split bit width of the parsing result is determined based on the previous preset candidate bit width and the current preset candidate bit width.

[0078] It should be understood that if the maximum bit width corresponding to multiple preset candidate bit widths does not match the bit width of the parsed result, it means that a single preset candidate bit width cannot divide the parsed result into integer multiples. In this case, multiple preset candidate bit width combinations can be sought. Therefore, in this case, the splitting bit width is determined by using the preset candidate bit width corresponding to the maximum bit width closest to the parsed result, that is, the parsed result is split using two different bit widths.

[0079] According to embodiments of this disclosure, when the bit width of the parsing result and the maximum bit width of each of the multiple preset candidate bit widths do not match, the parsing result can be split using two different bit widths. This allows the parsing result to be split into integer multiples, and the number of segments obtained from the split is minimized, thus minimizing the number of sub-parsing results. This minimizes the number of table lookups required, reduces the table entry size, and improves processing efficiency.

[0080] In some exemplary embodiments, the apparatus further includes: if the bit width of the parsed result matches one of the maximum bit widths of a plurality of preset candidate bit widths, the preset candidate bit width corresponding to the match is used as the split bit width of the parsed result.

[0081] If the bit width of the parsing result is 64 bits, and a preset candidate bit width m is 5 bits, and the maximum bit width corresponding to the preset candidate bit width m is 64 bits, then m=5 is used to determine the split bit width of the parsing result.

[0082] According to the embodiments of this disclosure, if the bit width of the parsing result matches one of the maximum bit widths of the multiple preset candidate bit widths, it means that the parsing result can be split into integer multiples of the corresponding preset candidate bit width. This ensures that the number of sub-parsing results after splitting is small, and that each sub-parsing result can hold enough data without overflowing.

[0083] In some exemplary embodiments, determining the splitting bit width of the parsing result based on the previous preset candidate bit width and the current preset candidate bit width includes: using the previous preset candidate bit width and the current preset candidate bit width as the splitting bit width of the parsing result, wherein the larger of the previous preset candidate bit width and the current preset candidate bit width is the splitting bit width with higher priority.

[0084] According to the embodiments of this disclosure, the larger value between the previous preset candidate bit width and the current preset candidate bit width is used as the bit width for priority splitting of the parsing result. This allows the split sub-parsing results to accommodate enough data without overflowing, and the number of corresponding sub-parsing results is relatively small. On this basis, the parsing result is further split using a smaller preset candidate bit width to ensure the integrity of the splitting.

[0085] For example, the bit width of the port number is If the bit width of the table entries is 18, then the bit width threshold is... for . Continuous preset candidate bit width Given 4 bits, 5 bits, 6 bits, and 7 bits, the corresponding number of segments obtained from the split is: ,Right now Then the maximum bit width is determined by the formula. Calculate, if ,but

[0086] The maximum bit width is... When m=6, 18-km=1, t(7,10)=7*2=14; when m=6, 18-km=2, ​​t(6,10)=6*4=24; when m=5, 18-km=3, t(5,10)=5*8=40; when m=4, 18-km=4, t(4,10)=4*16=64.

[0087] If the bit width of the parsed result is 32 bits, that is, between 24 and 40, then the previous preset candidate bit width is 5, and the current preset candidate bit width is 6. Therefore, the split bit width is determined by using m=5 and m=6, that is, the split bit width is 6 bits, 6 bits, 5 bits, 5 bits, 5 bits and 5 bits.

[0088] The larger of the previous preset candidate bit width and the current preset candidate bit width is 6, so the parsing result is first split using m=6, and then split using m=5.

[0089] In some exemplary embodiments, the processing parameters corresponding to the parsing result are obtained based on the sum of multiple sub-processing parameters and port information, including: determining the processing parameters of the sum of multiple sub-processing parameters based on the second mapping relationship and using them as the processing parameters corresponding to the parsing result.

[0090] The second mapping relationship is used to record the correspondence between the sum of multiple sub-processing parameters, port information, and processing parameters.

[0091] According to embodiments of this disclosure, using a second mapping relationship to determine the processing parameters, which are the sum of multiple sub-processing parameters, can improve the efficiency and accuracy of processing.

[0092] In some exemplary embodiments, for each parsing result, the number of split bit widths is less than or equal to the maximum number of parallel tables supported by the chip pipeline.

[0093] In practical applications, when the sub-processing parameters are obtained using each sub-parsing result and the first mapping relationship, it is done simultaneously through multiple parallel tables of a pipeline. Therefore, the number of sub-parsing results is less than or equal to the maximum number of parallel tables supported by the chip pipeline, and the number of bit widths split is less than or equal to the maximum number of parallel tables supported by the chip pipeline.

[0094] For example, if a programmable chip B supports 16 entries running in parallel in one pipeline stage, then the number of bit widths that can be split is less than or equal to 16.

[0095] According to embodiments of this disclosure, the number of split bit widths is limited, that is, the number of sub-parsing results after splitting is limited, thereby limiting the number of parallel tables to prevent exceeding the chip's capacity.

[0096] In some exemplary embodiments, the number of times multiple sub-processing parameters are summed for each parsing result is less than or equal to the number of chip pipeline stages.

[0097] In practical applications, summing multiple subprocessing parameters is limited by the fact that the adder in a programmable chip only has two input terminals. Therefore, a pipeline is used to sum them pairwise, so the number of summations is less than or equal to the number of pipeline stages in the chip.

[0098] For example, a programmable chip B supports two-operand operations. If it needs to sum n sub-processing parameters, the minimum number of pipeline stages required is... The result is rounded up.

[0099] According to embodiments of this disclosure, the number of summations is limited to restrict the number of chip pipeline stages, in order to prevent exceeding the chip's capacity.

[0100] In some exemplary embodiments, the parsing unit is also used to convert the parsing result into a message header vector and send it to the port determination unit.

[0101] Among them, the Packet Header Vector (PHV) represents a fixed-length binary data structure.

[0102] According to embodiments of this disclosure, converting the parsing result into a message header vector can reduce the length of the parsing result and convert it into a uniform format, thereby improving processing efficiency.

[0103] Figure 3 A flowchart illustrating a message processing method according to another embodiment of the present disclosure is shown schematically.

[0104] like Figure 3 As shown, the message processing method of this embodiment includes operations S310 to S340.

[0105] During operation of S310, the parsing unit obtains network packets.

[0106] In operation S320, the port determination unit splits the parsing result A corresponding to the network packet into 6 sub-parsing results based on the splitting bit width, namely A[4:0], A[9:5], A[15:10], A[20:16], A[25:21], and A[31:26]. Furthermore, it uses Tables 1, 2, 3, 4, 5, and 6 to determine the sub-processing parameters for each sub-parsing result, namely a1, a2, a3, a4, a5, and a6.

[0107] Where A represents the parsing result, and the bit width of A is 32 bits. A[4:0] represents bits 4 to 0 of A, A[9:5] represents bits 9 to 5 of A, A[15:10] represents bits 15 to 10 of A, A[20:16] represents bits 20 to 16 of A, A[25:21] represents bits 25 to 21 of A, and A[31:26] represents bits 31 to 26 of A.

[0108] During operation of S330, the port determination unit sums multiple sub-processing parameters.

[0109] In operation S340, the port determination unit uses Table 7 to obtain the processing parameter b, which is the sum of multiple sub-processing parameters.

[0110] In practical applications, if the parsed result A has a 32-bit width and the number of ports M has a 10-bit width, A can be split into 6+5+5+6+5+5. Where A6=A[31:26], A5=A[25:21], A4=A[20:16], A3=A[15:10], A2=A[9:5], A2=A[4:0], then A can be represented as... .

[0111] Can be converted ,in , , , .

[0112] At this point, the bit widths of a1, a2, a4, and a5 are less than 15 bits, and the bit widths of a3 and a6 are less than 16 bits. The sum of the bit widths of a1 to a6 can be guaranteed to be less than 18 bits, and there will be no overflow when using 18 bits in intermediate operations.

[0113] Then, for the sub-parsing results A1~A6 obtained from the splitting, parallel table lookups are performed in tables T1~T6 to obtain a1~a6, which are used as sub-processing parameters. After summing a1~a6 to obtain B, the processing parameters for this parsing result are obtained by looking up B in table T7. Using 18-bit results for table lookups results in a table size of 262144, which is sufficient to accommodate one pipeline stage in the data plane pipeline, while the control plane's delivery time remains within an acceptable range.

[0114] The logic processing of a programmable network processing chip can generally be abstracted into two planes: the data plane and the control plane. The data plane mainly includes the logic of parsing, table lookup, message modification, and packet assembly and transmission during message processing. Depending on the chip's capabilities, it also supports reading and writing some table entries. The control plane mainly controls data processing through table entry operations.

[0115] It should be understood that in tables T1~T6, T1 stores: (A1=[0……31]), T2 storage: (A2=[0……31]), T3 storage (A3=[0……63]), T4 storage: (A4=[0……31]), T5 storage: (A5=[0……31]), T6 storage: (A6=[0……63]), T0 storage: B%M(B=[0……262143]).

[0116] For tables T1 to T6, based on the number of bits n in each sub-parse result, take... The size of the tables is generally between 0 and 256, with the final T0 table being slightly larger. For programmable network processing chips, regardless of the size of the table entries, line-rate forwarding can be achieved for each pipeline's table lookup. Therefore, the table lookup in the final T0 table will not affect processing efficiency. Furthermore, the modulo operation and other packet processing flows are processed independently and in parallel, so pipeline overhead will not have a significant impact.

[0117] Figure 4 A flowchart illustrating a message processing method according to another embodiment of the present disclosure is shown schematically.

[0118] like Figure 4 As shown, the parsing unit of this embodiment includes a parser module, and the port determination unit includes multiple matching processing modules, namely matching processing module 1, ..., matching processing module n, and the sending unit 130 includes an anti-parser module. The message processing method of this embodiment includes operations S410 to S430.

[0119] When operating S410, network packets are input into the parser module.

[0120] In operation S420, the parser module converts the parsing result corresponding to the network packet into multiple header vectors and sends them to the matching processing module 1. These header vectors include header vector 1, header vector 2, ..., header vector n. The matching processing module 1 processes these header vectors using tables 1, 2, ..., m and multiple arithmetic logic units to obtain header vector 1', header vector 2', ..., header vector n'. Finally, the matching processing module n processes these header vectors again using tables 1, 2, ..., m and multiple arithmetic logic units to obtain header vector 1'', header vector 2'', ..., header vector n''.

[0121] During operation S430, the parser module obtains the output of the matching processing module n.

[0122] Figure 5 A flowchart illustrating the determination of subprocessing parameters according to one embodiment of the present disclosure is shown.

[0123] like Figure 5 As shown, the execution subject of this embodiment is the matching processing module, and this embodiment includes operations S510 to S530, which correspond to the steps of determining sub-processing parameters.

[0124] Operate S510 to obtain message header vectors 1~n;

[0125] Operate S520 to extract key fields from message header vectors 1 to n, use them as matching keys to enter the table for matching, and output actions and action data.

[0126] Here, "action" represents the name of the operation to be performed after the matching key matches a table entry. For example, the operation name is "modulo".

[0127] Action data represents the data required to perform the operation. For example, the action data could be the number of ports.

[0128] Operation S530: The arithmetic logic unit executes the action based on the action data and outputs message header vectors 1~n'.

[0129] Figure 6 A flowchart illustrating a message processing method according to another embodiment of the present disclosure is shown schematically.

[0130] like Figure 6 As shown, the message processing method of this embodiment includes operations S610 to S650.

[0131] During operation S610, the parsing unit inputs message header vector 1, message header vector 2, message header vector 3, message header vector 4, message header vector 5, and message header vector 6 to the matching processing module 1.

[0132] Among them, message header vector 1 = A[4:0], message header vector 2 = A[9:5], message header vector 3 = A[15:10], message header vector 4 = A[20:16], message header vector 5 = A[25:21], and message header vector 6 = A[31:26].

[0133] Where A represents the parsing result, A has a total of 32 bits, A[4:0] represents the 4th to 0th bits of A, A[9:5] represents the 9th to 5th bits of A, A[15:10] represents the 15th to 10th bits of A, A[20:16] represents the 20th to 16th bits of A, A[25:21] represents the 25th to 21st bits of A, and A[31:26] represents the 31st to 26th bits of A.

[0134] In operation S620, the matching processing unit 1 uses Tables 1, 2, 3, 4, 5, and 6 to determine the sub-processing parameters of the data in each message header vector, and uses the arithmetic logic unit to sum them pairwise to obtain message header vector 1', message header vector 2', and message header vector 3'.

[0135] Since there are 6 message header vectors, there will be 6 modulo results. Therefore, the matching processing unit 1 uses three arithmetic logic units to sum the 6 modulo results.

[0136] In operation S630, the matching processing unit 2 uses the arithmetic logic unit to sum the three message header vectors output by the matching processing unit 1 to obtain message header vector 1''.

[0137] In operation S640, the matching processing unit 3 uses the arithmetic logic unit to sum the message header vector 3' output by the matching processing unit 1 and the message header vector 1'' output by the matching processing unit 2 to obtain the message header vector 1'''.

[0138] In operation S650, the matching processing unit 4 uses Table 7 to determine the processing parameters of the message header vector 1''' output by the matching processing unit 3.

[0139] Figure 7 A schematic block diagram of an electronic device that can be used to implement the methods of embodiments of the present disclosure is shown.

[0140] like Figure 7As shown, an electronic device 700 according to an embodiment of the present disclosure includes a processor 701, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 702 or a program loaded from a storage portion 708 into a random access memory (RAM) 703. The processor 701 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 701 may also include onboard memory for caching purposes. The processor 701 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present disclosure.

[0141] RAM 703 stores various programs and data required for the operation of electronic device 700. Processor 701, ROM 702, and RAM 703 are interconnected via bus 704. Processor 701 executes various operations of the method flow according to embodiments of this disclosure by executing programs in ROM 702 and / or RAM 703. It should be noted that programs may also be stored in one or more memories other than ROM 702 and RAM 703. Processor 701 may also implement the methods provided in embodiments of this disclosure by executing programs stored in one or more memories.

[0142] According to embodiments of this disclosure, the electronic device 700 may further include an input / output (I / O) interface 705, which is also connected to a bus 704. The electronic device 700 may also include one or more of the following components connected to the I / O interface 705: an input section 706 including a keyboard, mouse, etc.; an output section 707 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 708 including a hard disk, etc.; and a communication section 709 including a network interface card such as a LAN card, modem, etc. The communication section 709 performs communication processing via a network such as the Internet. A drive 710 is also connected to the I / O interface 705 as needed. A removable medium 711, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 710 as needed so that computer programs read from it can be installed into the storage section 708 as needed.

[0143] This disclosure also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs that, when executed, implement the method according to the embodiments of this disclosure.

[0144] According to embodiments of this disclosure, the computer-readable storage medium can be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this disclosure, the computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of this disclosure, the computer-readable storage medium may include ROM 702 and / or RAM 703 and / or one or more memories other than ROM 702 and RAM 703 described above.

[0145] Embodiments of this disclosure also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to cause the computer system to implement the methods provided in the embodiments of this disclosure.

[0146] When the computer program is executed by the processor 701, it performs the functions defined in the system / apparatus of this disclosure embodiments. According to embodiments of this disclosure, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0147] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and may be downloaded and installed via the communication section 709, and / or installed from a removable medium 711. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0148] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 709, and / or installed from the removable medium 711. When the computer program is executed by the processor 701, it performs the functions defined in the system of this disclosure embodiment. According to embodiments of this disclosure, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0149] It should be noted that the collection, storage, use, processing, transmission, provision, disclosure, and application of user personal information in this disclosed technical solution comply with relevant laws and regulations, necessary confidentiality measures have been taken, and it does not violate public order and good morals. In this disclosed technical solution, user authorization or consent has been obtained before acquiring or collecting user personal information.

[0150] According to embodiments of this disclosure, program code for executing the computer programs provided in embodiments of this disclosure can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can execute entirely on a user's computing device, partially on a user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0151] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0152] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0153] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A message processing apparatus, characterized in that, The device includes: The parsing unit is used to acquire multiple network packets and parse the multiple network packets to obtain their respective parsing results; A port determination unit is used to obtain the split bit width of each of the multiple parsing results based on the port information of multiple ports, the multiple parsing results, and the available storage space of the port determination unit; determine the processing parameters of each of the multiple parsing results based on the split bit width; and determine the target port among the multiple ports based on the multiple processing parameters. A sending unit is used to send the network packet via the target port.

2. The apparatus according to claim 1, characterized in that, The step of determining the processing parameters for each of the multiple parsing results based on the split bit width includes: For each parsing result, the parsing result is split into multiple sub-parsing results, and the bit width of the sub-parsing result is consistent with the bit width of the corresponding split; Based on the first mapping relationship, the sub-processing parameters of each of the multiple sub-parsing results are determined. The first mapping relationship is used to record the correspondence between the sub-parsing results, port information and sub-processing parameters. The processing parameters corresponding to the parsing result are obtained based on the sum of the multiple sub-processing parameters and the port information.

3. The apparatus according to claim 2, characterized in that, The port information includes the number of ports. The step of obtaining the split bit width of each of the multiple parsing results based on the port information of multiple ports, the multiple parsing results, and the available storage space of the port determination unit includes: Based on the available storage space and the number of ports, determine the bit width threshold of the result obtained by dividing the sum of multiple sub-processing parameters by the number of ports; For each of the parsing results, using the bit width threshold and multiple consecutive preset candidate bit widths, calculate the maximum number of segments obtained by splitting the parsing result based on the multiple preset candidate bit widths; For each of the preset candidate bit widths, if the bit width of the sub-parse results obtained by splitting the parsing result is the preset candidate bit width and the number of the sub-parse results is the maximum number of segments, calculate the maximum bit width that can be supported after concatenating multiple sub-parse results; For each of the parsing results, the splitting bit width of the parsing result is determined based on the bit width of the parsing result, the multiple preset candidate bit widths, and the maximum bit width of each of the multiple preset candidate bit widths.

4. The apparatus according to claim 3, characterized in that, The step of determining the bit width threshold of the result obtained by dividing the sum of multiple sub-processing parameters by the number of ports based on the available storage space and the number of ports includes: Based on the available storage space, the number of table entries supported by the chip's unipolar pipeline is obtained; Based on the number of entries and the number of ports, the bit width of the number of entries and the bit width of the number of ports are obtained; Based on the difference between the bit width of the number of entries and the bit width of the number of ports, a bit width threshold is determined as the result of the sum of multiple sub-processing parameters divided by the number of ports.

5. The apparatus according to claim 3, characterized in that, The step of determining the split bit width of the parsing result based on the bit width of the parsing result, multiple preset candidate bit widths, and the maximum bit width of each of the multiple preset candidate bit widths includes: If the bit width of the parsed result and the maximum bit width of each of the multiple preset candidate bit widths do not match, and if the bit width of the parsed result is between the maximum bit width of the previous preset candidate bit width and the maximum bit width of the current preset candidate bit width, then the split bit width of the parsed result is determined based on the previous preset candidate bit width and the current preset candidate bit width.

6. The apparatus according to claim 5, characterized in that, The device further includes: If the bit width of the parsed result matches one of the maximum bit widths of the plurality of preset candidate bit widths, the corresponding preset candidate bit width is used as the split bit width of the parsed result.

7. The apparatus according to claim 5, characterized in that, The step of determining the splitting bit width of the parsing result based on the previous preset candidate bit width and the current preset candidate bit width includes: The previous preset candidate bit width and the current preset candidate bit width are used as the split bit width of the parsing result, wherein the larger of the previous preset candidate bit width and the current preset candidate bit width is the split bit width with higher priority.

8. The apparatus according to claim 2, characterized in that, The step of obtaining the processing parameters corresponding to the parsing result based on the sum of multiple sub-processing parameters and the port information includes: Based on the second mapping relationship, the processing parameter of the sum of the multiple sub-processing parameters is determined and used as the processing parameter corresponding to the parsing result. The second mapping relationship is used to record the correspondence between the sum of multiple sub-processing parameters, port information and processing parameters.

9. The apparatus according to claim 8, characterized in that, For each parsing result, the number of split bit widths is less than or equal to the maximum number of parallel tables supported by the chip pipeline.

10. The apparatus according to claim 8, characterized in that, For each parsing result, the number of times the multiple sub-processing parameters are summed is less than or equal to the number of chip pipeline stages.

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