A white list management method applied to a heterogeneous CCO meter reading system

Abstract

The application relates to the technical field of electric power technology, in particular to a white list management method applied to a heterogeneous CCO meter reading system, which comprises the following steps: a master control chip constructs a global hash table and initializes the same; the master control chip synchronously issues a query instruction to each coordinator through a serial port; after each coordinator receives the query instruction, the coordinator filters and reports the physical address and related information of a meter node in an online state to the master control chip; the master control chip receives the reported message containing the physical address and related information, extracts the physical address to convert into a fixed-length characteristic identifier, performs hash mapping, and generates a hash storage index; the hash storage index is taken as an addressing subscript, a linear probing method is used to search for an idle node in the global hash table, and the fixed-length characteristic identifier and related information are written into the idle node to complete registration storage. The application can solve the problem of slow serial traversal addressing when heterogeneous multi-coordinator networking is performed, and realizes fast positioning of meter information.

Description

Technical Field

[0001] This application relates to the technical field of power technology, and in particular to a whitelist management method for heterogeneous CCO meter reading systems. Background Technology

[0002] In the low-voltage distribution area electricity consumption information collection scenario of smart grids, a heterogeneous networking architecture is often adopted to improve data acquisition rate and network coverage, with a master control node and multiple coordinators working in parallel. The massive number of meter nodes at the bottom layer randomly connect to one of the working coordinators through power line carrier or low-power wireless channels, thereby virtually creating multiple parallel and interwoven communication networks within a physical distribution area to support the high-frequency meter reading and equipment management services at the upper layer.

[0003] Chinese invention patent application CN111081003A discloses a meter reading system, which mainly consists of a broadband carrier concentrator, a dual-mode communication module, and broadband and narrowband carrier energy meters. The broadband carrier concentrator sends a broadband carrier signal carrying meter reading instructions downwards. The dual-mode communication module receives this signal, performs modulation and demodulation, converts it into a narrowband carrier signal, and sends it to the narrowband carrier energy meters. Each energy meter reads its electricity consumption data and transmits it back via an upstream narrowband carrier signal. This data is then remodulated into a broadband carrier signal by the dual-mode communication module and finally transmitted to the concentrator for data aggregation and storage.

[0004] When such centralized data aggregation architectures evolve to a scenario where multiple coordinators operate in parallel, the randomness of meter node physical network access results in a dynamically discrete topology for the underlying devices. During targeted paging or high-concurrency meter reading tasks, the master control node typically only holds the physical address of the target meter node and cannot directly confirm its exact coordinator branch. Limited by conventional serial polling logic and linear storage structures, the master control node must communicate with each coordinator sequentially and perform a layer-by-layer comparison across the entire network based on the physical address. This addressing path results in a large number of redundant query messages accompanying each location operation, ineffectively consuming internal communication bus bandwidth and causing extremely slow node location identification. When dealing with large-scale, high-frequency node interactions, this inevitably leads to a significant surge in retrieval time and severe delays in network-wide scheduling. Summary of the Invention

[0005] To address the slow serial traversal addressing issue in heterogeneous multi-coordinator networking and to achieve rapid meter information location, this application provides a whitelist management method for heterogeneous CCO meter reading systems.

[0006] This application provides a whitelist management method for a heterogeneous CCO meter reading system, employing the following technical solution: A whitelist management method for a heterogeneous CCO meter reading system, wherein the system includes a main control chip, multiple coordinators, and meter nodes, and the method includes:

[0007] The main control chip constructs and initializes a global hash table;

[0008] The main control chip synchronously sends query commands to each of the coordinators via a serial port.

[0009] After receiving the query command, each of the coordinators filters and reports the physical addresses and related information of the meter nodes that are online to the main control chip;

[0010] The main control chip receives a message containing the physical address and related information, extracts the physical address, converts it into a fixed-length feature identifier, performs hash mapping, and generates a hash storage index.

[0011] Using the hash storage index as the addressing subscript, a linear probing method is used to retrieve a free node from the global hash table. The fixed-length feature identifier and the relevant information are then written into the free node to complete the registration and storage.

[0012] Optionally, the step of extracting the physical address, converting it into a fixed-length feature identifier, performing a hash mapping, and generating a hash storage index includes:

[0013] The physical address is mapped to the fixed-length feature identifier of the unsigned integer type;

[0014] The fixed-length feature identifier is shuffled by high and low bit XOR, the shuffled result is multiplied by a fixed coefficient and then superimposed with a right shift XOR, and an initial hash index is generated by taking the prime number modulo, and the initial hash index is used as the hash storage index.

[0015] Optionally, the step of retrieving free nodes from the global hash table using linear probing includes:

[0016] Starting from the hash storage index, traverse the nodes of the global hash table backward;

[0017] If the current node is already occupied and the stored fixed-length feature identifier does not match the fixed-length feature identifier of the node to be registered, the index position is sequentially extended and combined with the modulo of the total capacity of the global hash table to achieve circular addressing until the free node is found.

[0018] Optionally, the method further includes:

[0019] The main control chip is configured with a low-priority timed scheduling task to collect the operating parameters of the transformer area in real time and adaptively calculate the optimal synchronization period.

[0020] The query command is issued periodically according to the optimal synchronization period, which actively triggers each coordinator to report data, so as to periodically and dynamically update the relevant information in the global hash table.

[0021] Optionally, the method further includes:

[0022] The number and operating load of the metering nodes under each coordinator are retrieved based on the global hash table.

[0023] When it is detected that the load of a single coordinator exceeds the full load threshold, a scheduling instruction is issued to migrate some of the meter nodes under that coordinator to the remaining coordinators with low load, and the corresponding ownership number in the global hash table is updated synchronously.

[0024] Optionally, the method further includes:

[0025] Real-time monitoring of the heartbeat signals of each coordinator chip is used to determine its online status;

[0026] When a single coordinator is detected to be down, all online metering nodes under it are marked as pending migration and then assigned to the remaining normal coordinators one by one. The device ownership information in the global hash table and the coordinator's local whitelist is updated synchronously.

[0027] Optionally, each of the coordinators is internally configured with a receive buffer and memory. Before filtering and reporting online meter nodes to the main control chip, each coordinator also performs low-level admission control, which includes:

[0028] The backlog depth of the receive buffer is detected and compared with a preset security threshold;

[0029] Before the payload of the access message sent by the meter node is stored in the memory, the feature mask bits, the identifier end bits, and the service mask are extracted from the header of the access message.

[0030] Optionally, the underlying admission control also includes:

[0031] If the backlog depth exceeds the preset security threshold and the intercepted service mask does not contain an emergency identifier, then the transmission of the payload is blocked and the residual payload of the access message is discarded.

[0032] After the metering node finishes sending the access message, a backoff beacon containing the dynamic modulus and the intercepted last bit of the identifier is broadcast.

[0033] Optionally, after the broadcast includes the dynamic modulus and the backoff beacon with the intercepted end bits of the identifier, the method further includes:

[0034] The backoff beacon indicates a target meter node with a matching identifier end bit, and performs a modulo operation using a local discrete factor and the dynamic modulus to obtain the backoff duration, thereby triggering silent sleep;

[0035] It also instructs the remaining unmatched meter nodes to remain silent and back off.

[0036] Optionally, the underlying admission control also includes:

[0037] If the backlog depth does not exceed the preset security threshold, then based on the intercepted feature mask bits, a preset lookup table rule is invoked to perform an aligned copy on the complete access packet to generate a normalized string;

[0038] The normalized string is compared with the local whitelist. If the comparison is successful, the meter node is allowed to join the network. The identifier in the normalized string is extracted as the physical address, and the meter node is marked as being online.

[0039] In summary, this application includes the following beneficial technical effects:

[0040] 1. The main control chip converts the physical addresses of the meter nodes reported by each coordinator into fixed-length feature identifiers and performs hash mapping. Combined with the linear probing method, the global hash table is registered and stored. This allows meter information retrieval to be performed without relying on the coordinator affiliation to perform serial traversal. Instead, it directly achieves single-address location based on the hash storage index. This effectively avoids the problems of long addressing paths and redundant query messages occupying bus bandwidth in heterogeneous multi-coordinator networks, and realizes rapid location of meter information.

[0041] 2. After mapping the physical address to an unsigned integer fixed-length feature identifier, the high and low bits are XORed to scatter the data, the fixed coefficients are multiplied and then right-shifted and XORed, and the prime number modulo operation is performed to generate a hash storage index. The data obfuscation mechanism that combines bit operations and lightweight arithmetic operations is used to improve the address dispersion. The probability of hash collisions is reduced with extremely low computing power, so that the embedded main control chip can still maintain high hash table addressing efficiency and storage reliability under resource-constrained conditions.

[0042] 3. When the buffer backlog depth exceeds the preset security threshold and the access message does not carry an emergency flag, each coordinator will block the transmission of non-emergency message payloads to the running memory in advance. It will also use the intercepted flag end bit and the dynamic modulus broadcast backoff beacon to instruct the conflicting nodes to obtain the backoff duration based on the local discrete factor modulo operation to trigger silent sleep. This will avoid buffer overflow and message collision in high-concurrency access scenarios and effectively maintain the stability of the coordinator's underlying admission control. Attached Figure Description

[0043] Figure 1A flowchart illustrating a whitelist management method for a heterogeneous CCO meter reading system provided in this application embodiment;

[0044] Figure 2 A data flow diagram of the connection credential generation process provided in this application embodiment. Detailed Implementation

[0045] The following combination Figures 1-2 This application will be described in further detail.

[0046] This application discloses a whitelist management method for heterogeneous CCO meter reading systems. The method is applied to heterogeneous networked meter reading systems that include a main control chip, multiple coordinators, and meter nodes.

[0047] In terms of hardware system architecture topology, the main control chip is the GD32F527RST7. This microcontroller unit supports 7680KB of flash memory and 512KB of static random access memory (SRAM), and is natively configured with four Universal Asynchronous Receiver / Transmitter (UART) peripheral interfaces. UART1 is dedicated to communication with the terminal's external network, while UART2, UART3, and UART4 are physically connected to the external UART interfaces of the first, second, and third coordinators, respectively, in a one-to-one correspondence. The entire system supports a hardware watchdog timer and a hard reset mechanism. All three coordinators use the GQX3211 chip, which is based on the Cortex M3 microarchitecture and internally supports 1MBytes of SRAM and 1MByte of Flash memory. It natively supports communication features at the Media Access Control (MAC) layer, network layer, and specific application layers. This chip employs dual-mode orthogonal frequency division multiplexing (OFDM) modulation technology, combining advanced broadband power line carrier (HPLC, operating frequency band 0.7MHz~12MHz) and low-power wireless communication (HRF, operating frequency band 470MHz~510MHz). It integrates Turbo forward error correction and copy interleaving anti-interference gate circuits. Its network performance is as follows: HPLC peak rate greater than or equal to 1Mbps@Band2, HRF peak rate greater than or equal to 2Mbps@16QAM with a 1MHz bandwidth and 3 / 4 code rate, and channel attenuation resistance greater than or equal to 95dB@Band2. Each coordinator chip supports up to four UARTs, with UART1 used for communication with the corresponding UART pin on the main control chip, and UART2 dedicated to local development and debugging. Each coordinator is equipped with a physical access point (AP) that supports up to 28 times the analog signal amplification factor. It supports full-duplex independent communication for transmission (TX) and reception (RX) and is independently coupled to the three phases A, B, and C of the low-voltage AC power grid via a physical coupling transformer, thereby creating three virtual physical communication networks that work in parallel and interleaved in the low-voltage distribution area environment.

[0048] Logically, this whitelist management method is manifested as a multi-layered closed-loop network control architecture that is interconnected between local low-level access control executed in parallel by each coordinator and system-level global overall management executed by the main control chip. To clarify the logic, this application divides it into system-level global overall management at the main control chip level (Example 1) and local low-level anti-concurrency access control at the coordinator level (Example 2).

[0049] Example 1: Global Management of Heterogeneous CCO Whitelists Based on Hash Tables

[0050] After each coordinator securely and concurrently accepts local meter nodes to join the network, the main control chip performs system-level global management, efficiently archiving and finely controlling the online device information scattered across the various coordinator networks. For example... Figure 1 As shown, this method specifically includes the following core logical steps:

[0051] S1. Initialize the whitelist management vector table.

[0052] After the system is powered on, the main control chip completes the relevant initialization, establishes the global hash table storage space, and initializes the hash table parameters, empty flag bits, and status flag bits. Then, it reads all the physical addresses of the whitelist from the fixed location in the FLASH (the whitelist will be stored in the main control chip's FLASH), and then executes the subsequent hash registration operations in a loop to complete the initialization of the whitelist management vector table (i.e., the global hash table).

[0053] S2, Address Mapping Hash Table Registration

[0054] This step designs a dedicated meter whitelist structure as the smallest storage unit of the global hash table, used to uniformly store core parameters such as device identity, operating status, network topology, and communication records of meter nodes. The structure contains multiple functional fields, including: a 64-bit fixed-length feature identifier field, a node occupancy status flag, an 8-bit coordinator network number field, a device online status flag, a 32-bit recent communication timestamp field, and an 8-bit data synchronization count field. Simultaneously, to reduce embedded memory overhead, this application employs bit-field multiplexing technology to layer and compress multiple sets of low-width network parameters for storage. By splitting and multiplexing byte space through multiple bit fields, it compactly stores extended parameters such as device TEI parameters, module number, forwarding count, network layer, routing status, and link status. Based on the above structure, a global hash table storage array is constructed, and the entire table is initialized to zero. Subsequently, the unique address mapping of each meter node can correspond one-to-one with the hash array index, achieving fixed-point storage and management of device information.

[0055] In the distribution network system, each meter node is identified by a 6-byte physical address. To adapt to the native memory access and operation characteristics of the 32-bit embedded main control chip, this application uniformly maps the 6-byte physical address to a fixed-length 64-bit unsigned integer identifier. Traditional byte-by-byte reading and writing of 6-byte unaligned data triggers multiple read-modify-write operations, resulting in high instruction overhead and low bus efficiency. This solution uses a 64-bit integer to carry the address data, which can be automatically split into high and low 32-bit data segments, adapting to the main control chip's integer read-write mechanism. The compiler automatically optimizes it into batch memory access instructions, eliminating redundant boundary processing and byte-by-byte operations, and significantly improving the execution efficiency of device address comparison, retrieval, and mapping.

[0056] After address translation, this application uses a lightweight hash mapping algorithm to quickly map a 64-bit fixed-length feature identifier to a 32-bit hash storage index. The specific steps are as follows: First, the 64-bit fixed-length feature identifier is XORed with its high and low bits to scramble the data, merging the high and low bit characteristics and disrupting the original address distribution. Second, the result is multiplied by a fixed coefficient 0x12345678, followed by a 16-bit right-shift XOR operation to achieve lightweight data obfuscation and improve data dispersion. Finally, a modulo operation is performed using a prime number as the global hash table capacity to generate the final valid array index. This algorithm achieves address mapping through multi-layer bitwise operations and lightweight arithmetic operations, effectively reducing the probability of hash collisions with extremely low computational overhead. It is suitable for resource-constrained embedded chip scenarios, improving hash table addressing speed and storage reliability.

[0057] After calculating the hash index, this hash storage index is used as the address index of the global hash table storage array to initiate the device address hash registration operation. The occupancy status field of the corresponding structure is set to 1, marking the storage node as occupied. To resolve hash collisions caused by different physical addresses calculating the same index value, this application employs a linear probing method to retrieve free nodes: starting from the initially calculated hash storage index, the hash table nodes are traversed sequentially. If the current node is occupied, the index position is sequentially shifted, and a circular cyclic addressing is achieved by combining the modulo operation of the total capacity of the global hash table, while accumulating the number of probes. During the cyclic search, if the number of probes reaches the upper limit of the total hash table capacity, it is determined that the hash table storage space is exhausted and there are no free nodes. The address registration fails and the corresponding exception status code is returned. If a free node with an occupancy status field of 0 is found, a fixed-length feature identifier is written to the node, and the node is updated to occupied status. Finally, based on the output configuration, the fixed-length feature identifier and the final storage index are returned, and a registration success status code is returned, completing the single device address mapping hash table registration process.

[0058] S3, Coordinator Internal Command Information Reporting

[0059] This application adopts a multi-serial port parallel transmission architecture. The main control chip is configured with three independent serial ports, corresponding to coordinators 1 to 3 respectively, which can synchronously send internal query command messages to each coordinator. This command is a custom extension based on the 376.2 protocol framework, and realizes private interaction through a dedicated function code. Specifically, the AFN field is set to 0 and the Fn field is set to F166, serving as the system's unique private identification command, different from standard protocol commands, ensuring the independence of internal device interaction and communication security.

[0060] After receiving the dedicated query command, each coordinator traverses the locally stored whitelist, filters the meter nodes that are in online working status, counts the total number of local online meter nodes, and extracts the core data such as the 6-byte physical address, network parameters, and operating status parameters of the valid meter nodes, and completes the integration and preprocessing of the reported data.

[0061] To adapt to the frame length limitations of embedded communication and improve data transmission stability and efficiency, this application adopts a grouped framing reporting mechanism. The filtered online meter node data is batch-encapsulated into messages of 20 devices each, with the remaining data (less than 20 devices) framed separately. Simultaneously, a valid completion flag is set in the last message group to indicate that the current coordinator has finished reporting data in this round, allowing each coordinator to complete the reporting operation in parallel.

[0062] The main control chip receives reports from each serial port in real time and uses flags in the messages to identify the reporting progress of each coordinator. Multi-dimensional compliance checks are performed on the reported data, including frame format integrity and consistency of the number of reporting devices. If a check fails, the data is not updated for that round. Simultaneously, the coordinator's identity is accurately matched based on the serial port number corresponding to the message, and the data is classified and archived. Once all coordinators corresponding to the three serial ports have completed their reports and passed the checks, the entire network device information aggregation process is considered complete, achieving reliable updates to the network's online status.

[0063] S4. Data parsing and extraction processing

[0064] In the coordinator's reporting messages, each meter node's physical address field is followed by multi-byte network parameters, operational status parameters, and other core business data. This application uses the meter node's 6-byte physical address as a unique retrieval key, reusing the aforementioned mature hash indexing mechanism to quickly complete address mapping retrieval and accurately locate the meter node's exclusive storage location in the global hash table storage array.

[0065] After hash location is completed, the system performs segmented parsing and stripping of the reported message to accurately extract the valid business data corresponding to the physical address, remove redundant and invalid fields such as frame headers, frame tails, and check bits, and complete the normalization of the target data to ensure the integrity and validity of the extracted data.

[0066] Subsequently, the parsed core data, such as network topology and status, will be written in batches to the corresponding dedicated storage units of the global hash table, and the latest operating data of the devices will be refreshed in real time, enabling rapid storage of reported data. After the data storage of a single device is completed, the data of all reported nodes in this round will be traversed in a loop, and the entire process of hash index positioning, data parsing, and fixed-point storage will be completed in sequence until the data reported by all coordinators in this round is updated. This hash matching storage mode effectively solves the problems of slow addressing, data misalignment, and update lag in traditional sequential storage, ensuring the real-time, accuracy, and orderliness of data storage across the entire network.

[0067] S5. Fast Indexing and Deletion of Hash Tables

[0068] This step, based on the already registered hash table architecture, implements a fast device address index query function. It verifies whether the target physical address has completed whitelist registration and outputs the corresponding fixed-length feature identifier and hash storage index. First, the input parameter (6-byte physical address) is validated. If the address to be queried is empty, the search fails and the process terminates. For valid addresses, the aforementioned standardized conversion mechanism is used to quickly generate a 32-bit initial hash storage index.

[0069] Starting with the initial hash storage index, a linear probing method is used for cyclic matching retrieval. Provided the number of probes does not exceed the hash table capacity and the current node is already occupied, the fixed-length feature identifier stored in the node is compared with the target fixed-length feature identifier. If the identifiers match, the retrieval is considered successful, the corresponding hash storage index is output, and a successful retrieval status is returned, completing the device storage location positioning. If the identifiers do not match, a hash collision is determined, the index positions are sequentially shifted, and circular addressing is achieved by modulo the total capacity of the global hash table, synchronously accumulating the probe count and continuously traversing the table. When the number of probes reaches the hash table capacity limit, it is determined that no matching item has been found in the entire table traversal, the retrieval is terminated, and a retrieval failure status is returned.

[0070] This application presents a hash-based fast retrieval architecture that abandons the traditional full table traversal and memcmp byte-by-byte comparison scheme. The traditional scheme has a time complexity of O(N), with redundant byte-by-byte comparison instructions, large memory access overhead, and query time increasing significantly with the number of devices. The time complexity of this scheme is close to O(1), with only a small range of linear probing. Combined with the native integer operation mechanism of the main control chip, it avoids bus fragmentation and unnecessary read / write overhead. In an engineering scenario with a hash table capacity of 256 items, the traditional scheme has an average query time of 1920 machine cycles, while this scheme only requires 46 machine cycles, reducing the time by 97.6% and increasing the retrieval speed by 41.7 times. The performance advantage continues to expand as the table capacity increases, which can meet the fast query requirements of embedded devices with high real-time performance and low computing power consumption.

[0071] For fast deletion operations in the hash table, the deletion process is the same as described above. Address translation, hash calculation, and linear probing logic are reused to retrieve the target node. If the parameters are invalid or the address does not exist, the corresponding status code is returned. Upon a successful search, the node data is cleared and the occupancy mark is removed, completing the hash table data deletion operation.

[0072] S6, Whitelist data is updated periodically.

[0073] This step enables the periodic automatic synchronization and dynamic iterative update of the whitelist data across the entire network. Relying on the low-priority timed tasks of the main control chip and combined with the self-developed proprietary protocol interaction logic, it periodically triggers multiple coordinators to report whitelist data, and synchronizes the network ledger information in real time to ensure that the data stored in the system is consistent with the actual operating status of the field equipment.

[0074] This application employs an independent timed scheduling mechanism. The main control chip periodically sends dedicated private query messages, proactively triggering the whitelist data reporting of each coordinator. This synchronization task is configured with the lowest system execution priority, running only during system idle periods. It does not preempt core business resources such as data transmission and reception, and command interaction, effectively avoiding serial port data collisions and link congestion issues, and ensuring the overall stability of the system.

[0075] This application establishes a dual-mode adjustable synchronization cycle mechanism, which flexibly adapts the update frequency according to the on-site network conditions. It includes both manual configuration and intelligent dynamic adaptation modes, addressing the shortcomings of traditional fixed synchronization cycles in terms of poor adaptability and insufficient flexibility, and adapting to the network operation needs of different sized distribution areas. The manual configuration mode supports online remote modification of the synchronization cycle via internal system commands, without requiring hardware or firmware changes, adapting to special scenarios such as on-site debugging and maintenance rectification. The dynamic adaptation mode can collect operating parameters such as distribution area size, number of online devices, and device network access time in real time, and adaptively calculate and adjust the synchronization cycle through algorithms to achieve precise matching of update frequency with on-site conditions. The dual-mode adaptive synchronization mechanism can adjust the data update frequency as needed, avoiding both the computing power redundancy and serial port resource waste caused by high-frequency synchronization, and eliminating the data update lag problem caused by low-frequency synchronization. While ensuring real-time and accurate synchronization of data across the entire network, it minimizes system resource consumption and improves the long-term stability and energy efficiency of equipment operation.

[0076] S7, Distributed Load Balancing and Fault Redundancy Management

[0077] Load balancing scheduling: The main control chip relies on a global hash table to batch retrieve the number of meter nodes, channel occupancy rate, and data forwarding volume under each coordinator, and to statistically analyze the operating load status of the three coordinators in real time. When the load of a single coordinator exceeds a preset threshold, the main control chip issues a scheduling command to migrate meter nodes with good signal quality under that coordinator to low-load coordinator nodes, and simultaneously updates the coordinator affiliation number of the corresponding device in the global hash table, thereby achieving dynamic load balancing distribution across the entire network.

[0078] Fault Redundancy Management: The main control chip monitors the heartbeat signals of each coordinator in real time to determine the online status of the devices. When a single coordinator fails or a link is disconnected, all its subordinate online meter nodes are immediately marked as pending migration and assigned to the remaining normally functioning coordinator nodes. The device ownership information in the global hash table and whitelist is updated synchronously. If multiple coordinator failures occur, the remaining normally functioning coordinator nodes take over all network communication services, effectively avoiding the risk of network-wide paralysis caused by a single point of failure and achieving highly reliable redundant operation of the system.

[0079] Example 2: Concurrency Overflow Prevention Admission Control Based on Physical Layer Feature Extraction

[0080] During the local low-level admission control phase of each coordinator, the coordinator is internally configured with physical receive buffers and system running memory. The receive buffer includes a MAC layer RXFIFO register or a physical layer receive FIFO with equivalent functionality. Running memory includes MCU SRAM, Direct Memory Access (DMA) receive buffer, or network protocol stack receive queue for carrying complete access messages to be processed. Meter nodes are configured with a persistent identifier and a hardware timer. The persistent identifier is stored in an unwritable or protected ROM area, OTP area, Flash lock area, or specific security hardware element. The persistent identifier includes a 6-byte MAC identifier, an 8-byte device serial number, a 16-byte UUID identifier, or other physical signatures that uniquely identify the meter node. The hardware timer is driven by an independent external crystal oscillator, a low-power RC clock loop, or a real-time clock (RTC) to maintain an accurate backoff countdown during low-power sleep or when the RF transmit circuit is powered down. Meter nodes have pre-embedded hardware-level parsing and automatic timer writing mechanisms that support backoff beacons, enabling them to monitor the coordinator's downlink beacons in real time during or between uplink message transmissions. When a meter node fails to connect or does not receive an acknowledgment signal for an extended period, the underlying protocol stack state machine will forcibly switch to the beacon listening window before retransmission to ensure that the latest peak avoidance parameters can be received in real time.

[0081] In one specific implementation, the coordinator includes a hardware feature interception unit deployed between the receive buffer and the runtime memory access path. The pre-feature interception unit is implemented using a field-programmable gate array (FPGA) pre-gate circuit, or can be replaced by a smart MAC controller with hardware message depth filtering capabilities or a receive coprocessor peripheral embedded in the microprocessor. The feature interception unit directly reads real-time low-level data from the receive buffer through a register read port or a FIFO bypass control port, forcibly intercepts the message header field before the system triggers DMA transfer, and asynchronously interacts with the core authentication processor inside the coordinator through a separate interrupt signal line.

[0082] After a meter node performs power-on, power-off recovery, scheduled meter reading wake-up, or manual maintenance triggering, the physical layer transceiver on the node side generates a specific access message and sends it to the AC power line channel. The access message, in its physical byte arrangement, consists of a preamble, synchronization field, header, and a complete payload field at the end, arranged in a compact, adjacent order. The header contains at least a feature mask bit, an identifier end bit, a service mask, a length field, and a CRC checksum field.

[0083] In a preferred embodiment, the message header includes, in physical order: a 2-byte length field, a 1-byte feature mask bit, a 1-byte identifier end bit, a 1-byte service mask, and a 2-byte CRC16 checksum field. The feature mask bit is used to indicate the manufacturer, protocol family, identifier length, identifier encoding method, or message format version of the metering node. For example, a feature mask bit of 0x01 indicates that the access message carries a 6-byte standard MAC identifier; a feature mask bit of 0x02 indicates that the access message carries a 16-byte UUID identifier; and a feature mask bit of 0x03 indicates that the access message carries an 8-byte device serial number. The identifier end bit consists of several physical bits at the very end of the fixed identifier, preferably 8 physical bits, but can also be 4 physical bits, 12 physical bits, the XOR value of odd-numbered identifier bits, the XOR value of even-numbered identifier bits, the lower 8 bits of the fixed identifier CRC checksum, or the lower bits of the fixed identifier hash truncation. Feature mask bits, identifier end bits, and service mask can be located in the extended information element of the message header or in a dedicated hardware field, and can be implemented by updating the underlying protocol stack or firmware of the meter node.

[0084] The coordinator's pre-feature interception unit continuously monitors the backlog depth of the physical receive buffer. The backlog depth is specifically represented by the number of bytes to be processed in the receive buffer, the number of packets to be processed, the difference between the FIFO write pointer and read pointer, the number of occupied DMA descriptors, or a unified queue depth value converted from the above indicators. After the pre-feature interception unit reads the write and read pointers of the MAC layer RXFIFO register, it subtracts the read pointer from the write pointer and corrects for the ring buffer capacity to obtain the current instantaneous backlog depth. When the receive buffer operates in packet descriptor mode, the pre-feature interception unit reads the valid bits of the descriptors and accumulates the number of valid descriptors to obtain the current backlog depth. The backlog depth serves as a boundary control condition for whether to forcibly intercept payloads, broadcast backoff beacons, and trigger the ultimate circuit breaker mechanism.

[0085] The local access control in the whitelist management process is generally structured as a closed-loop branch with a conditional detection loop. When the backlog exceeds the security threshold and the service mask does not contain an emergency identifier, the processing steps are executed sequentially along the backoff intervention branches, including the blocking payload containing dynamic modulus and the identifier end bit backoff beacon. Matching nodes take the modulus of the local discrete factor and go into sleep mode, while unmatched nodes remain silent. After the metering node goes into sleep mode and backoffs and retransmits the complete access message, the logical flow forms a closed loop in space and returns directly to the node that detects the backlog depth in the receive buffer. The system must trigger a backlog depth check again for the current situation. If it fails to fall back below the preset security threshold, it continues to loop within the backoff intervention branch until the fallback condition is met before exiting the branch and merging with the initial straight-through main line that has not exceeded the threshold. Based on the feature mask bit, a lookup table is called to generate a normalized string, which is then transferred to the subsequent normalized string and compared with the local whitelist to achieve alignment, copying, and authentication for network access. After the master controller takes the normalized string as the addressing key and hashes it into the global table, as the backlog falls below the preset security threshold periodically and the beacon is broadcast to be released, the overall workflow also backtracks to the initial detection and reception buffer backlog depth node, forming a globally coherent continuous loop monitoring mechanism.

[0086] Before the payload field of the access message sent by the meter node is stored in the coordinator's running memory, the pre-feature extraction unit listens to the receive buffer and obtains the underlying raw bitstream at the physical layer receiving circuit level. The underlying bitstream is demodulated by the coordinator's physical layer transceiver and written to the MAC layer RXFIFO register. Before the payload field triggers a DMA transfer request or a microprocessor access interrupt, the pre-feature extraction unit pre-parses the access message to extract the message header. During this process, the message boundary is accurately identified based on the preamble and synchronization field in the demodulated underlying bitstream, and the position of the entire message header is located based on the message boundary and the length field of the access message. After the verification field of the message header passes, the feature mask bits, the identifier end bits, and the service mask are extracted from the message header by bit shifting. If the verification field of the packet header has not yet fully arrived, the pre-feature interception unit first caches the arrived packet header fragments and waits in place for the remaining packet header fields to arrive until the integrity of the packet header is verified before outputting the interception result; if the verification field of the packet header fails to be verified, the pre-feature interception unit directly marks the corresponding access packet as an invalid packet and forcibly prohibits the invalid packet from entering the subsequent whitelist comparison process.

[0087] Combination Figure 2The hierarchical extraction and flow relationship is presented, with the underlying bitstream of the access message macroscopically divided into preamble, synchronization field, message header, and complete payload. Within the coordinator's internal processing architecture, the MAC layer RXFIFO register output derives parallel data flow paths in the hardware topology: the main data path flows to system memory via a valve node controlled by a blocking instruction, while the pre-feature extraction unit constructs a data bypass link independent of the coordinator's running memory. Before the main data path is controlled by the blocking valve, the bypass link pre-positions the message header for diversion. For the physical bytes arranged within the message header, the hardware feature extraction precisely extracts the corresponding feature mask bits, identifier end bits, and service mask, which are then rapidly transmitted via the bypass link and merged within an independent transparent transmission splicing logic module. After processing by the transparent transmission splicing logic module, the connection certificate is generated by horizontal splicing from top to bottom according to a preset field format and directly sent to the core authentication processor for register-level processing. The connection credential uses a fixed-length field structure. The underlying mapping consists of a feature mask field, an identifier end field, and a service mask field, with the receive port field, timestamp field, and message header checksum field added synchronously to complete the packet assembly. The feature mask field serves as the index input for subsequent normalization alignment rules, the identifier end field serves as the trigger reference for node backoff and verification loop closure, the receive port field distinguishes between different power line carrier channels, wireless channels, or dual-mode channels, and the timestamp field defines the effective time window of the connection credential. The connection credential can be generated independently without relying on the complete payload entering memory, allowing the coordinator to obtain lightweight node classification features first when a large influx of high-concurrency messages arrives.

[0088] After generating the connection credential, the pre-feature extraction unit writes it to a bypass register, a shared small-capacity SRAM, or a hardware message mailbox, and notifies the core authentication processor to read it via an external interrupt pin. The core authentication processor uses the feature mask field in the connection credential to preload the corresponding lookup rules, optimizing the timing of subsequent memory comparison and data copying operations.

[0089] The pre-feature extraction unit performs a hard comparison between the current backlog depth and a preset security threshold. The preset security threshold is a first security overflow threshold, preferably set to 75% to 80% of the total receive buffer capacity. For example, if the receive buffer capacity is 4096 bytes, the preset security threshold is set to 3072 bytes or 3200 bytes. When counting by message descriptors, if the receive buffer supports 128 receive descriptors, the preset security threshold is set to 96 to 102 valid descriptors. The specific setting of the preset security threshold ensures that the coordinator reserves sufficient DMA response time, beacon transmission time, and resources for processing received message headers before the receive buffer reaches a physical overflow threshold.

[0090] If the pre-interception unit determines that the backlog depth exceeds the preset security threshold, and determines through parsing the intercepted service mask that the newly arrived access packet does not contain an emergency identifier representing emergency privileges, then for the non-emergency ordinary packet, it immediately sends a hardware shielding signal to the DMA controller to forcibly block the transmission path of the subsequent payload of the access packet to memory, and actively clears and discards the residual payload of the access packet that has not yet been read in the receive buffer. Since the underlying communication medium is a half-duplex physical channel, the meter node's RF transmitting circuit is on at full power while the receiving link is off during the transmission of the residual payload, and it cannot receive any downlink signals. Therefore, the pre-interception unit uses the length field in the packet header to calculate the expected remaining transmission time slot. The specific calculation formula is: the expected remaining transmission time slot equals the total packet length indicated by the length field minus the length of the received packet header, the remaining number of bytes, multiplied by eight, divided by the physical channel baud rate, and then superimposed with the microsecond-level state switching protection interval. The coordinator waits for the expected remaining transmission time slot to expire, i.e., until the metering node physically finishes transmitting and switches back to the beacon listening window, before the pre-feature interception unit outputs the current backlog depth to the beacon generation logic. The beacon generation logic obtains the preset time slot quota (the number of access packets the system can safely process per time slot), and based on the preset packet equivalence conversion rule, divides the backlog depth by the statistical average packet length to obtain the equivalent packet number. It then calculates the quotient and rounds it up as the dynamic modulus. If the current equivalent packet number is 192 and the time slot quota is 32, the dynamic modulus quotient is 6. If the quotient is not an integer, it is rounded up to ensure the dynamic modulus is a positive integer, and this dynamic modulus is carried by an 8-bit register with a value range of 1 to 255.

[0091] The beacon generation logic sets the enable flag to an active state. Following a block-like physical structure with the enable flag at the starting position (bounded), followed by the dynamic modulus, the truncated identifier terminal bits, and the time slot base, the enable flag, dynamic modulus, truncated identifier terminal bits, and a preset time slot base are encapsulated into a backoff beacon for radio and carrier broadcasting. The backoff beacon is emitted by the coordinator's physical layer transceiver in periodic downlink beacon time slots or dedicated control channels. After sending an uplink access message, if the meter node does not receive network access permission confirmation or detects access failure, the underlying protocol stack will forcibly switch to receive mode and open a beacon listening window to capture the backoff beacon.

[0092] The backoff beacon is configured to indicate the response action of the meter node: When the enable flag is active, the meter node extracts the last bit of the identifier captured by the interception unit from the backoff beacon and performs a precise match verification with the features in its own fixed identifier. When a successful match confirms that it is indeed the target node in this round of conflict, in order to avoid the same identifier last bit leading to the same modulo result and thus causing a secondary deadlock collision, the meter node extracts a local discrete factor, uses this local discrete factor and the dynamic modulus to perform a modulo operation, and adds a basic offset constant to obtain the final offset result. The local discrete factor is generated by the hardware timer count value inside the meter node, or by the combination of the remaining high-order special bytes in its own fixed identifier, excluding the identifier last bit. By using a local discrete factor instead of a single identifier terminal bit as the divisor, the underlying mathematical and physical mechanism ensures that concurrent conflicting nodes are truly staggered and dispersed on the timeline. If the characteristics do not match, the node is determined to be affected by macroscopic congestion. During the backoff beacon broadcast when the enable flag is valid, the meter node is forced to maintain a backoff silent state, actively suspending its own immediate access requests, thereby cutting off the concurrent source of network congestion avalanche. The dynamic modulus is carried by an 8-bit register, with a value range of 1 to 255. When the calculated quotient is less than 1, it is treated as 1; when the calculated quotient is greater than 255, it is treated as 255 saturation. The time slot base can be set from 10ms to 200ms, preferably 50ms, to balance the low-power sleep granularity of the meter node with the recovery processing capability of the coordinator.

[0093] To avoid multiple meter nodes concurrently retransmitting at the same instant due to a modulo result of zero, the base offset constant is set to 1. If the dynamic modulus is any integer, the node-side hardware backoff control logic uses an internal division modulo circuit, a lookup table modulo circuit, or an infinite loop iterative subtraction circuit to calculate the offset base; if the dynamic modulus is configured as an integer power of 2, the node-side hardware backoff control logic directly uses a high-speed bitmask arithmetic circuit to calculate the offset base.

[0094] The node-side hardware backoff control logic multiplies the dimensionless offset result by the time slot base to obtain the actual backoff duration with time dimensions, and writes this backoff duration into a hardware timer to trigger silent sleep. The countdown duration of the hardware timer can be superimposed with a fixed protection interval to completely avoid the beacon reception window. After the timer countdown ends, the node-side RF transmit circuit is powered on again and retransmits the access message to the channel. During silent sleep, the meter node's RF transmit power amplifier, uplink modulator, or carrier transmit driver is completely shut down, the node MCU can enter a deep low-power mode, the hardware timer runs independently, and outputs a hard wake-up signal when the countdown ends. Silent sleep, combined with a peak-shaving mechanism based on local discrete factors, effectively disperses conflicting meter nodes on the time axis, while the forced backoff silent mechanism of unmatched nodes constrains the overall concurrent network traffic during periods of extreme congestion.

[0095] During the broadcast backoff beacon period, the pre-feature extraction unit continues to monitor the receive buffer and calculate the slope of the backlog depth change. The slope can be obtained by dividing the difference between the backlog depth of the current sampling period and the backlog depth of the previous sampling period by the sampling interval, or by a moving average differential calculation circuit over multiple consecutive sampling periods. The coordinator sets a slope threshold and a bit width limit. The slope threshold is set to increase by 64 messages or 1024 bytes every 10 ms; the bit width limit is determined by the bit width of the dynamic modulus register, which is 255 when the register bit width is 8 bits. When the slope change is greater than the slope threshold, the pre-feature extraction unit performs a left shift operation on the dynamic modulus, causing the dynamic modulus to exponentially expand the discrete range of the backoff time slot. If the dynamic modulus after the left shift operation is greater than or equal to the bit width limit, the pre-feature extraction unit saturates and locks the dynamic modulus to the bit width limit of 255, and prohibits any form of overflow wrapback. The beacon generation logic repackages the dynamic modulus after saturation locking or after performing a left shift operation into a backoff beacon and continuously broadcasts it, forcing the node side to retransmit in the next round of access according to a wider backoff window.

[0096] The coordinator introduces a periodic threshold and counts the duration for which the backlog depth is below a preset security threshold. The periodic threshold can be 3 to 10 beacon periods, preferably 5 beacon periods. When the sampling period is 20ms and the periodic threshold is 5, the coordinator needs to confirm that the receive buffer is below the preset security threshold for 100ms consecutively before releasing the backoff intervention. When the forward feature extraction unit determines that the duration has reached the periodic threshold, the beacon generation logic will set the enable flag to an invalid state to generate a release beacon and broadcast it. The release beacon instructs all meter nodes in the network to release the backoff silence. To avoid a massive number of suspended meter nodes synchronously resuming transmission at the moment of unblocking, thereby artificially creating a catastrophic thundering herd effect and physical layer secondary synchronization collision, the release beacon prohibits bypass modulo operation. Instead, it instructs all meter nodes in the network to perform modulo operation using the local discrete factor and the preset recovery modulus, and multiplies the modulo result by the time slot base to obtain the hashing delay duration. Each meter node can only resume sending immediate access requests after its local timer has expired for the hashing delay duration. This mechanism ensures flexible peak-shifting of network traffic during the initial stage of network de-encryption from a mathematical and physical perspective. The dynamic modulus field in the decryption beacon can retain the previous valid value or write a default value, but it does not use a dynamic modulus of zero as the basis for decryption, thus avoiding division-by-zero anomalies or misjudgments of status on the node side.

[0097] When an access packet is stored completely in memory without triggering blocking, the core authentication processor directly retrieves the complete access packet from memory. Alternatively, upon receiving a complete access packet from a meter node that has ended its silent sleep and is avoiding retransmission, and with the coordinator confirming that the backlog depth has fallen below a preset safety threshold, the pre-feature interception unit removes the DMA mask, the coordinator allows the payload of the complete access packet to enter memory, and the core authentication processor retrieves the complete access packet from memory. Subsequently, the core authentication processor uses the feature mask bits carried in the complete access packet as input, calls preset lookup rules to perform alignment copying, and generates a normalized string. The lookup rules are stored in a read-only table, Flash parameter area, or compile-time fixed table. The table entries include feature mask bits, fixed identifier offset, identifier length, pre-padding length, target alignment boundary, and copy mode. For example, when the feature mask bit is 0x01, the entry indicates that the fixed identifier offset is the 2nd byte after the header, the identifier length is 6 bytes, the base length is 16 bytes, and the prepend length is 10 bytes; when the feature mask bit is 0x02, the entry indicates that the fixed identifier offset is the 4th byte after the header, the identifier length is 16 bytes, the base length is 16 bytes, and the prepend length is 0 bytes; when the feature mask bit is 0x03, the entry indicates that the fixed identifier offset is the 2nd byte after the header, the identifier length is 8 bytes, the base length is 16 bytes, and the prepend length is 8 bytes.

[0098] The core authentication processor configures a memory area and a baseline length. It retrieves the corresponding offset using the feature mask bits as index keys and obtains the identifier length corresponding to the feature mask bits based on lookup table rules. The memory area is a normalized buffer aligned to 4-byte, 8-byte, or 16-byte boundaries. The baseline length is preferably the maximum fixed identifier length supported by the system, such as 16 bytes or 32 bytes. When the identifier length is less than the baseline length, the core authentication processor performs zero-value padding in the memory area. Subsequently, based on the offset, the core authentication processor copies the fixed identifier from the complete access message to the padded end of the memory area in a single pass to generate a normalized string. When the identifier length equals the baseline length, the core authentication processor directly copies the fixed identifier to the starting address of the memory area in a single pass based on the offset. When the identifier length is greater than the baseline length or the table entry does not exist, the core authentication processor marks the corresponding message as an illegal format and refuses to include it in the whitelist comparison. A single copy can be completed by CPU block copy instructions, DMA memory-to-memory transfer, bus matrix burst transfer, or hardware string transfer units.

[0099] Each coordinator compares the generated normalized string with a pre-stored local whitelist to achieve access control for the local network. The core authentication processor introduces a storage area containing authentication records. Each authentication record includes at least the following fields: normalized identifier hash value, vendor mask, node status, transformer topology number, key index, and validity period. These authentication records are all generated and stored in advance after hashing based on the transformer key as a fixed salt value. The core authentication processor performs a salted hash calculation on the normalized string to generate a retrieval hash value. The hash calculation uses SipHash or a one-way hash function suitable for embedded authentication scenarios, and the salt value used in the calculation is the transformer key. The core authentication processor uses the retrieval hash value as the key to search the local whitelist in the storage area. When an authentication record matching the retrieval hash value exists in the local whitelist, and the vendor mask, transformer topology number, and validity period of the record all meet the requirements, a local network access license is officially issued, allowing the metering node to successfully mount and access the network on the current CCO node. To further enhance security, the coordinator can use a random number generated during operation or the current beacon sequence number as a challenge factor to initiate session-level secondary authentication to meter nodes that have passed the initial local whitelist comparison.

[0100] Under extreme congestion conditions, each coordinator also sets a second security threshold greater than the preset security threshold. This second security threshold is the critical defense threshold for the receive buffer, preferably set to 90% to 95% of the total receive buffer capacity. For example, when the receive buffer capacity is 4096 bytes, the second security threshold can be set to 3891 bytes. When counting by message descriptors, if the receive buffer supports 128 receive descriptors, the second security threshold can be set to 120 to 122 valid descriptors. Since a large number of historical ordinary messages have already flooded into the receive buffer before the first security threshold is triggered, and the underlying MAC layer RXFIFO register strictly follows the first-in-first-out physical law, it absolutely does not support the operation of randomly removing non-urgent messages from the middle of the hardware queue. Therefore, when the front-end feature interception unit detects that the backlog depth continues to worsen and reaches the second security threshold, it triggers a high-priority interrupt of the physical layer's extreme circuit breaker protection mechanism. After the core authentication processor responds to the interrupt, it immediately disables the write enable of the receive buffer to freeze the writing of new external messages, preventing physical overflow, and triggers a high-frequency sequential pop operation for the receive buffer. During pipelined readout, the core authentication processor sequentially extracts the headers of the popped access packets and retrieves the corresponding service masks. If the retrieved service mask contains an emergency identifier indicating urgent network access, and the format verification passes and the exemption frequency does not exceed the limit, its complete payload is forcibly retained, and the corresponding access packet is exempted, directly transferred to the privileged processing queue for priority processing. If the emergency identifier indicates an anonymous fault alarm, an alarm is recorded; an anonymous fault alarm does not mean successful whitelist access. For existing non-urgent access packets whose popped service masks do not contain an emergency identifier, the core authentication processor discards them directly after the data is popped into the software layer. This hardware streaming cleaning and recycling strategy fully respects the physical order of hardware popping packets sequentially and clears the receive buffer during sequential readout, completely resolving the underlying deadlock caused by illegal jump operations in traditional solutions and the causal inversion paradox of front and rear defense lines, ensuring high-priority, high-fidelity passage of urgent services under extreme stock conditions. After high-priority interrupt processing is completed, the pre-feature interception unit continues to broadcast valid backoff beacons until the backlog depth falls back and the release condition is met.

[0101] In an alternative implementation, the pre-feature extraction unit is not a standalone FPGA, but rather an intelligent MAC layer processing peripheral integrated into the coordinator's main control chip. Before a received packet enters main memory, the intelligent MAC layer processing peripheral identifies the packet header fields through a hardware filter and outputs feature mask bits, identifier end bits, and a service mask. When the backlog depth exceeds a preset security threshold and the current packet does not have an urgent identifier, the intelligent MAC layer processing peripheral directly shuts down the corresponding DMA channel and drives the physical layer transceiver to broadcast a backoff beacon. This implementation has the same data flow as the implementation using FPGA pre-feature extraction gate circuits, both making the feature extraction and judgment results before the payload enters memory the input conditions for dynamic backoff judgment.

[0102] In an alternative implementation, the input for the meter node to perform the modulo operation does not entirely depend on the beacon broadcast parameters. For scenarios where the terminal of the fixed identifier of the same batch of meter nodes continuously increments, the terminal entropy value is insufficient, or the terminal field is fixedly filled by the manufacturer, the node-side hardware backoff control logic reads the odd-numbered bits of the fixed identifier and performs an XOR operation to obtain a first discrete value, or reads the entire field of the fixed identifier and calculates the lower 8 bits of the CRC checksum to obtain a second discrete value. Then, the first or second discrete value is used as the aforementioned local discrete factor and the dynamic modulus to perform the modulo operation. This implementation maintains the causal chain of coordinator dynamically allocating the modulus, node-side backoff triggered by blind collision prevention, and hardware timer-controlled silent sleep.

[0103] In another alternative implementation, the storage area for whitelist comparison employs a hierarchical index structure. The core authentication processor first locates the vendor-level index page using the feature mask bits, then locates the authentication record within the bucket using the hash value of the normalized string, and performs secondary verification on the digest of the normalized string, the vendor mask, and the substation topology number within the bucket. If the storage area uses a security chip, the core authentication processor sends the normalized string or digest to the security chip, which performs the hash calculation involving the key and returns the matching result. If the storage area uses ordinary Flash memory, the core authentication processor verifies the CRC or ECC field of the authentication record when reading it to prevent false access caused by storage disturbances.

[0104] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, any substitutions or modifications made to the sequence of steps, module implementation methods or equivalent control logic based on the technical concept of this application should be covered within the scope of protection of this application.

Claims

1. A whitelist management method for heterogeneous CCO meter reading systems, characterized in that, The system includes a main control chip, multiple coordinators, and meter nodes; the method includes: The main control chip constructs and initializes a global hash table; The main control chip synchronously sends query commands to each of the coordinators via a serial port. After receiving the query command, each of the coordinators filters and reports the physical addresses and related information of the meter nodes that are online to the main control chip; The main control chip receives a message containing the physical address and related information, extracts the physical address, converts it into a fixed-length feature identifier, performs hash mapping, and generates a hash storage index. Using the hash storage index as the addressing subscript, a linear probing method is used to retrieve a free node from the global hash table. The fixed-length feature identifier and the relevant information are then written into the free node to complete the registration and storage.

2. The whitelist management method for heterogeneous CCO meter reading systems according to claim 1, characterized in that, The step of extracting the physical address, converting it into a fixed-length feature identifier, performing hash mapping, and generating a hash storage index includes: The physical address is mapped to the fixed-length feature identifier of the unsigned integer type; The fixed-length feature identifier is shuffled by high and low bit XOR, the shuffled result is multiplied by a fixed coefficient and then superimposed with a right shift XOR, and an initial hash index is generated by taking the prime number modulo, and the initial hash index is used as the hash storage index.

3. The whitelist management method for heterogeneous CCO meter reading systems according to claim 1, characterized in that, The step of retrieving free nodes from the global hash table using linear probing includes: Starting from the hash storage index, traverse the nodes of the global hash table backward; If the current node is already occupied and the stored fixed-length feature identifier does not match the fixed-length feature identifier of the node to be registered, the index position is sequentially extended and combined with the modulo of the total capacity of the global hash table to achieve circular addressing until the free node is found.

4. The whitelist management method for heterogeneous CCO meter reading systems according to claim 1, characterized in that, The method further includes: The main control chip is configured with a low-priority timed scheduling task to collect the operating parameters of the transformer area in real time and adaptively calculate the optimal synchronization period. The query command is issued periodically according to the optimal synchronization period, which actively triggers each coordinator to report data, so as to periodically and dynamically update the relevant information in the global hash table.

5. The whitelist management method for heterogeneous CCO meter reading systems according to claim 1, characterized in that, The method further includes: The number and operating load of the metering nodes under each coordinator are retrieved based on the global hash table. When it is detected that the load of a single coordinator exceeds the full load threshold, a scheduling instruction is issued to migrate some of the meter nodes under that coordinator to the remaining coordinators with low load, and the corresponding ownership number in the global hash table is updated synchronously.

6. The whitelist management method for heterogeneous CCO meter reading systems according to claim 1, characterized in that, The method further includes: Real-time monitoring of the heartbeat signals of each coordinator chip is used to determine its online status; When a single coordinator is detected to be down, all online metering nodes under it are marked as pending migration and then assigned to the remaining normal coordinators one by one. The device ownership information in the global hash table and the coordinator's local whitelist is updated synchronously.

7. The whitelist management method for heterogeneous CCO meter reading systems according to claim 1, characterized in that, Each of the coordinators is internally configured with a receive buffer and memory. Before filtering and reporting online meter nodes to the main control chip, each coordinator also performs low-level admission control, which includes: The backlog depth of the receive buffer is detected and compared with a preset security threshold; Before the payload of the access message sent by the meter node is stored in the memory, the feature mask bits, the identifier end bits, and the service mask are extracted from the header of the access message.

8. The whitelist management method for heterogeneous CCO meter reading systems according to claim 7, characterized in that, The underlying access control also includes: If the backlog depth exceeds the preset security threshold and the intercepted service mask does not contain an emergency identifier, then the transmission of the payload is blocked and the residual payload of the access message is discarded. After the metering node finishes sending the access message, a backoff beacon containing the dynamic modulus and the intercepted last bit of the identifier is broadcast.

9. The whitelist management method for heterogeneous CCO meter reading systems according to claim 8, characterized in that, After the broadcast includes the dynamic modulus and the backoff beacon with the intercepted last bit of the identifier, the method further includes: The backoff beacon indicates a target meter node with a matching identifier end bit, and performs a modulo operation using a local discrete factor and the dynamic modulus to obtain the backoff duration, thereby triggering silent sleep; It also instructs the remaining unmatched meter nodes to remain silent and back off.

10. The whitelist management method for heterogeneous CCO meter reading systems according to claim 7, characterized in that, The underlying access control also includes: If the backlog depth does not exceed the preset security threshold, then based on the intercepted feature mask bits, a preset lookup table rule is invoked to perform an aligned copy on the complete access packet to generate a normalized string; The normalized string is compared with the local whitelist. If the comparison is successful, the meter node is allowed to join the network. The identifier in the normalized string is extracted as the physical address, and the meter node is marked as being online.

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