A method for preparing an FP-coil

Abstract

The application discloses a preparation method of FP-Coil, comprising the following steps: blanking; first pattern transfer: pasting and pressing a photosensitive dry film on the surface of a core plate, forming a first dry film pattern through exposure and development, the first dry film pattern covering a circuit area in a preset circuit pattern and exposing a gap area in the circuit pattern; etching; second pattern transfer: pasting and pressing a photosensitive dry film on the surface of the core plate again, forming a second dry film pattern through exposure and development, the second dry film pattern covering the gap area in the circuit pattern and exposing the circuit area; electroplating; lead electroplating. The etching process is advanced to after the first pattern transfer and before the electroplating thickening, under the sequence, the functional circuit needing protection has not been formed when etching, so the circuit body will not be damaged due to etching, meanwhile, the seed layer of the gap area has been etched before the electroplating, so the gap area has no seed layer for growing the electroplating layer when the electroplating, thereby avoiding the problem of permeation plating short circuit.

Description

Technical Field

[0001] This invention relates to the field of printed circuit technology, and more specifically to a method for preparing FP-Coil. Background Technology

[0002] In response to market demand, current electronic products are developing towards thinner, smaller, and more densely integrated designs, and users have placed more stringent requirements on the size of FP-Coil (Fine Pitch Coil).

[0003] SAP (Semi-Additive Process) is the mainstream method for fabricating FP-Coil. Its basic idea is to first form an extremely thin conductive seed layer on an insulating substrate through chemical deposition. Then, a photosensitive dry film is coated on this seed layer. Exposure and development expose the areas requiring thickening of the circuitry while covering the gaps where no circuitry is needed. Electroplating is then performed to thicken the conductive layer in the exposed portion of the seed layer, forming the main circuit structure. Finally, the dry film is removed, and flash etching removes the portion of the seed layer previously covered by the dry film. Compared to traditional fabrication methods, SAP only requires etching a very thin copper layer, thus enabling the creation of finer linewidths and spacings.

[0004] However, current FP-Coil production using SAP relies on a continuous seed layer at the bottom as an electroplating channel. If the dry film is not tightly bonded, the electroplating solution can seep into areas where copper shouldn't be present, causing short circuits and directly reducing product yield. Furthermore, in the subsequent flash etching process, the etching solution not only removes excess seed layer from the circuit gaps but also erodes the main circuit material, leading to reduced linewidth and copper thickness, and increased line spacing. This limits the ability to further refine and densify the circuitry, hindering product miniaturization.

[0005] Chinese invention patent No. 201610930029.9 discloses a method for manufacturing printed circuit boards using an enhanced semi-additive process. This method employs the typical SAP (Super Additive Processing) fabrication method mentioned above, and adds a final lead plating step to address the aforementioned problems. The lead plating is used to further plating the circuit pattern, thereby widening and increasing the circuit height. However, this approach damages the circuit first and then repairs it, rather than avoiding damage altogether. It fails to solve the problem of short circuits caused by plating penetration, nor does it eliminate the damage to line width and thickness caused by flash etching. Instead, it increases process complexity and introduces new non-uniformity issues. Therefore, this method can only alleviate the problems to a certain extent, but it cannot truly advance FP-Coil towards finer pitches. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to propose a method for preparing FP-Coil with finer line width and spacing, in light of the above-mentioned technical status.

[0007] The technical solution adopted by the present invention to solve the above-mentioned technical problems is: a method for preparing FP-Coil, characterized by comprising the following steps: Material preparation: Prepare a core board with a thin copper layer on both sides, drill through holes or blind holes on the core board, and deposit a seed layer in the through holes or blind holes and on the thin copper layer. First pattern transfer: A photosensitive dry film is pressed onto the surface of the core board, and a first dry film pattern is formed by exposure and development. The first dry film pattern covers the line area in the preset line pattern, while exposing the gap area in the line pattern. Etching: The core board is etched to remove the thin copper layer exposed in the gap area, and then the first dry film pattern is removed; Second pattern transfer: A photosensitive dry film is pressed onto the surface of the core board again, and a second dry film pattern is formed by exposure and development. The second dry film pattern covers the gap area in the circuit pattern, while exposing the circuit area. Electroplating: Electroplating is performed on the exposed circuit area to thicken the thin copper layer in that area, and then the second dry film pattern is removed; Wire plating: The wire plating process further thickens and widens the circuit after the plating step.

[0008] Compared with existing technologies, the advantages of this invention are as follows: This invention advances the etching process to after the first pattern transfer and before the electroplating thickening, thus achieving a process sequence of etching followed by electroplating. In this sequence, the functional circuitry requiring protection has not yet formed during etching, therefore the circuitry itself will not be damaged by etching. Simultaneously, since the seed layer in the gap area has been etched away before electroplating, there is no seed layer in that area for growing the electroplated layer during electroplating, fundamentally avoiding the short-circuit problem caused by poor dry film bonding in traditional SAP processes. Furthermore, the final lead electroplating step actively thickens and widens the complete circuitry, effectively reducing the spacing between finished circuit lines and improving product yield.

[0009] To further ensure yield, preferably, after the material preparation step and before the first pattern transfer step, a flash plating step is included: the core board is subjected to double-sided electroplating to thicken the seed layer, resulting in an electroplated layer thickness of 3-8 μm and a total copper thickness of less than 12 μm. This is because the deposited seed layer is only 0.4-0.6 μm thick. If it were directly used as the starting layer for electroplating, it would be easily damaged after passing through multiple processes from seed layer deposition to electroplating, making it impossible to guarantee the integrity of the plating layer. Therefore, flash plating is needed to thicken it.

[0010] Preferably, during the blanking step, a separable carrier double-sided copper-clad laminate is prepared as the core board; the stacked structure of the separable carrier double-sided copper-clad laminate is: protective copper foil, thin copper layer, intermediate insulating layer, thin copper layer, and protective copper foil, and the protective copper foil can be peeled off to form the core board with thin copper layers on both sides.

[0011] Preferably, the thickness of the thin copper layer used in the blanking step is 2-5 μm.

[0012] Preferably, when performing the blanking step, a copper foil with a thickness of 12μm is selected, and then the copper is reduced to the required thickness through a copper reduction process.

[0013] Preferably, the thickness of the intermediate insulating layer is 10-300 μm.

[0014] Specifically, during the blanking step, the core board is drilled with mechanical through holes, laser through holes, die punching, or laser blind holes.

[0015] Specifically, during the material feeding step, a seed layer is deposited on the thin copper layer using chemical deposition or vacuum deposition. The seed layer is made of titanium, copper, nickel, or an alloy of different metals.

[0016] Specifically, the etching step is performed using chemical etching, plasma etching, or two-fluid etching.

[0017] Preferably, the FP-Coil circuit includes a circuit stack and a lead plating layer covering the circuit stack. The circuit stack includes a bottom thin copper layer, a seed layer formed on the thin copper layer, a flash plating layer formed on the seed layer, and an electroplating layer formed on the flash plating layer. Attached Figure Description

[0018] Figure 1 This is a cross-sectional schematic diagram of S1.1 in an embodiment of the present invention; Figure 2 This is a cross-sectional schematic diagram of S1.2 in an embodiment of the present invention; Figure 3 This is a cross-sectional schematic diagram of S1.3 in an embodiment of the present invention; Figure 4 This is a cross-sectional schematic diagram of S1.4 in an embodiment of the present invention; Figure 5 This is a cross-sectional schematic diagram of S2 in an embodiment of the present invention; Figure 6 This is a cross-sectional schematic diagram of step S3.1 in an embodiment of the present invention; Figure 7 This is a cross-sectional schematic diagram of step S3.2 in an embodiment of the present invention; Figure 8This is a cross-sectional schematic diagram of S3.3 in an embodiment of the present invention; Figure 9 This is a cross-sectional schematic diagram of step S4.1 of an embodiment of the present invention; Figure 10 This is a cross-sectional schematic diagram of S4.2 in an embodiment of the present invention; Figure 11 This is a cross-sectional schematic diagram of step S5.1 of an embodiment of the present invention; Figure 12 This is a cross-sectional schematic diagram of S5.2 in an embodiment of the present invention; Figure 13 This is a cross-sectional schematic diagram of S5.3 in an embodiment of the present invention; Figure 14 This is a cross-sectional schematic diagram of step S6.1 in an embodiment of the present invention; Figure 15 This is a cross-sectional schematic diagram of S6.2 in an embodiment of the present invention; Figure 16 This is a cross-sectional schematic diagram of S7 in an embodiment of the present invention. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0020] like Figures 1-16 The figure shown is a preferred embodiment of an FP-Coil preparation method of the present invention.

[0021] This embodiment includes the following steps.

[0022] S1. Material preparation, including the following steps: S1.1, Prepare the core board: such as Figure 1 As shown, a core board with a thin copper layer 2 on both sides is prepared. This embodiment uses a separable carrier double-sided copper-clad laminate with the following stacked structure: protective copper foil 3, thin copper layer 2, intermediate insulating layer 1, thin copper layer 2, and protective copper foil 3, wherein the protective copper foil 3 is removable. The thickness of the selected thin copper layer 2 is preferably 2~5μm; or a copper foil with a thickness of 12μm can be selected and then thinned to the required thickness through a copper reduction process. The thickness of the intermediate insulating layer 1 is 10~300μm.

[0023] S1.2, Drilling: such as Figure 2 As shown, through holes 4 or blind holes are drilled on the core board. Through holes can be drilled mechanically, through holes can be drilled with a laser, through holes can be punched with a die, or blind holes can be drilled with a laser. In this embodiment, through holes 4 are drilled mechanically.

[0024] S1.3, Remove the protective copper foil: as follows Figure 3 As shown, the protective copper foil 3 on both sides is peeled off to expose the double-sided thin copper layer 2.

[0025] S1.4, Seed layer deposition: such as Figure 4 As shown, a seed layer 5 is deposited inside the via 4 and on the thin copper layer 2 on both sides of the core board. The seed layer 5 is made of titanium, copper, nickel, or their alloys, using either chemical deposition or vacuum deposition. Because the seed layer 5 is relatively thin, it is not specifically shown on the thin copper layer 2 in the figure; it is only shown inside the wall of the via 4 for illustration.

[0026] S2, flash plating: such as Figure 5 As shown, the core board after S1 treatment is subjected to double-sided electroplating to thicken the seed layer 5 and the flash plating layer 6 to a thickness of 3~8μm. The total surface copper thickness of thin copper layer 2 + seed layer 5 + flash plating layer 6 is less than 12μm. In principle, the thinner the better, as thinner is more conducive to subsequent etching.

[0027] S3. First graphic transfer, including steps: S3.1, Molding: such as Figure 6 As shown, a photosensitive dry film 7 is pressed onto the surface of the core board after S2 treatment. The type and thickness of the photoresist used as the dry film 7 need to be selected according to the actual product design. In this embodiment, Hitachi RD1229, which has higher resolution and thinner thickness, is more conducive to etching, is used as an example for explanation.

[0028] S3.2, Exposure: such as Figure 7 As shown, the dry film 7 in the circuit area is exposed to light, causing the exposed dry film 7 to undergo fusion.

[0029] S3.3, Development: such as Figure 8 As shown, sodium carbonate is used to dissolve the unexposed area of ​​the dry film 7, leaving the dry film 7 to form a first dry film pattern 7a. The first dry film pattern 7a covers the line area in the preset line pattern, while exposing the gap area in the line pattern.

[0030] S4, Etching and Film Removal, including the following steps: S4.1, Etching: such as Figure 9 As shown, the core board is etched to remove the thin copper layer 2 exposed in the gap area, as well as the seed layer 5 and flash plating layer 6 thereon. Specifically, chemical etching, plasma etching, or two-fluid etching can be used; in this embodiment, chemical etching is used.

[0031] S4.2, Demolding: such as Figure 10 As shown, the first dry film pattern 7a is removed. The film removal solution can be an organic film removal solution or an inorganic film removal solution.

[0032] S5. Second graphic transfer, including the following steps: S5.1, Molding: such as Figure 11As shown, a photosensitive dry film 7 is laminated onto the surface of the core board after S4 treatment. The type and thickness of the photoresist used for the dry film 7 need to be selected according to the actual product design. The thicker the dry film 7, the more suitable it is for electroplating, allowing for a thicker coating. Therefore, this embodiment uses the Hitachi RD1240 as an example for illustration.

[0033] S5.2, Exposure: such as Figure 12 As shown, the dry film 7 in the gap region is exposed to light, causing the exposed dry film 7 to undergo fusion.

[0034] S5.3, Development: such as Figure 13 As shown, sodium carbonate is used to dissolve the dry film in the unexposed area, leaving a dry film 7 that forms a second dry film pattern 7b. The second dry film pattern 7b covers the gap area in the preset circuit pattern, while exposing the circuit area.

[0035] S6. Electroplating and film removal, including the following steps: S6.1, Electroplating: such as Figure 14 As shown, the exposed circuit area is electroplated to thicken the copper layer in that area, forming electroplated layer 8.

[0036] S6.2, Demolding: such as Figure 15 As shown, the second dry film pattern 7b is removed. The film removal solution can be an organic film removal solution or an inorganic film removal solution.

[0037] S7, Lead plating: such as Figure 16 As shown, the lead electroplating process further thickens and widens the circuit after the electroplating step, forming the lead electroplating layer 9.

[0038] The working principle of this embodiment is as follows: Flash plating is added before etching to thicken the seed layer 5 of the entire board by 3~8μm. This is because the seed layer 5 deposited in S1.4 is only 0.4~0.6μm thick. If it is directly used as the starting layer for S6 electroplating, it is easily damaged after passing through multiple processes from S1.4 to S6, and the integrity of the plating layer cannot be guaranteed. Therefore, flash plating is required to thicken it.

[0039] During the first pattern transfer, the first dry film pattern 7a protects the circuit area, exposing the gap area. After etching, the copper in the gap area is completely removed, leaving a complete copper layer in the circuit area. At this point, since the gap area is the surface of an insulating intermediate layer, a physical isolation is formed between the circuit area and the gap area.

[0040] In the second pattern transfer, the second dry film pattern 7b covers the gap areas of the non-circuit areas, exposing only the circuit areas. Then, electroplating is performed. Since there is no seed layer 5 in the gap areas, the electroplated layer 8 only grows in the circuit areas. Even if there are slight gaps in the lamination of the dry film 7, copper will not be deposited in the gap areas, fundamentally avoiding the problem of short circuits caused by plating penetration.

[0041] Finally, the complete circuit is further thickened and widened through wire plating. This step can also repair any minor defects that may have existed in the early stages, thereby effectively reducing the spacing between finished circuits and improving product yield.

[0042] The final FP-Coil circuit structure manufactured in this embodiment includes a circuit stack and a lead plating layer 9 covering the circuit stack. The circuit stack, from bottom to top, consists of: a bottom thin copper layer 2, a seed layer 5 formed on the thin copper layer 2 (because the seed layer is very thin, it is not shown in the attached drawings; only a portion of the seed layer 5 is shown at the hole wall of the middle insulating layer 1 for illustration), a flash plating layer 6 formed on the seed layer 5, and an electroplating layer 8 formed on the flash plating layer 6. The outermost lead plating layer 9 encapsulates the entire circuit, forming a smooth and dense conductive structure.

Claims

1. A method for preparing FP-Coil, characterized in that, Including the following steps: Material preparation: Prepare a core board with a thin copper layer on both sides, drill through holes or blind holes on the core board, and deposit a seed layer in the through holes or blind holes and on the thin copper layer. First pattern transfer: A photosensitive dry film is pressed onto the surface of the core board, and a first dry film pattern is formed by exposure and development. The first dry film pattern covers the line area in the preset line pattern, while exposing the gap area in the line pattern. Etching: The core board is etched to remove the thin copper layer exposed in the gap area, and then the first dry film pattern is removed; Second pattern transfer: A photosensitive dry film is pressed onto the surface of the core board again, and a second dry film pattern is formed by exposure and development. The second dry film pattern covers the gap area in the circuit pattern, while exposing the circuit area. Electroplating: Electroplating is performed on the exposed circuit area to thicken the thin copper layer in that area, and then the second dry film pattern is removed; Wire plating: The wire plating process further thickens and widens the circuit after the plating step.

2. The method for preparing FP-Coil according to claim 1, characterized in that, After the material feeding step and before the first pattern transfer step, a flash plating step is also included: the core board is subjected to double-sided electroplating to thicken the seed layer, the electroplating layer thickness is 3-8μm, and the total copper thickness is less than 12μm.

3. The method for preparing FP-Coil according to claim 1, characterized in that, When performing the material cutting step, a separable carrier double-sided copper-clad laminate is prepared as the core board; the stacked structure of the separable carrier double-sided copper-clad laminate is: protective copper foil, thin copper layer, intermediate insulating layer, thin copper layer, and protective copper foil, and the protective copper foil can be peeled off to form the core board with thin copper layers on both sides.

4. The method for preparing FP-Coil according to claim 3, characterized in that, When performing the blanking step, the thickness of the selected thin copper layer is 2-5 μm.

5. The method for preparing FP-Coil according to claim 3, characterized in that, When performing the aforementioned blanking step, a copper foil with a thickness of 12μm is selected, and then the copper is reduced to the required thickness through a copper reduction process.

6. The method for preparing FP-Coil according to claim 3, characterized in that, The thickness of the intermediate insulating layer is 10-300 μm.

7. The method for preparing FP-Coil according to claim 1, characterized in that, During the blanking step, the core board is drilled with mechanical through holes, laser through holes, die punching, or laser blind holes.

8. The method for preparing FP-Coil according to claim 1, characterized in that, During the material feeding step, a seed layer is deposited on the thin copper layer using chemical deposition or vacuum deposition. The seed layer is made of titanium, copper, nickel, or an alloy of different metals.

9. The method for preparing FP-Coil according to claim 1, characterized in that, When performing the etching step, chemical etching, plasma etching, or two-fluid etching may be used.

10. The method for preparing FP-Coil according to claim 2, characterized in that, The fabricated FP-Coil circuit includes a circuit stack and a lead plating layer covering the circuit stack. The circuit stack includes a bottom thin copper layer, a seed layer formed on the thin copper layer, a flash plating layer formed on the seed layer, and an electroplating layer formed on the flash plating layer.

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